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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 30 66 68.75 30
Automatically Generated Cross Bins 96 30 66 68.75 30
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] * * * * [auto[1]] -- -- 16
[auto[1]] [auto[1]] [auto[0]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 50 1 T39 2 T95 1 T236 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 19 1 T329 1 T330 2 T254 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 61 1 T32 1 T41 1 T235 3
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 31 1 T44 1 T251 1 T225 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 58 1 T32 2 T39 1 T41 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 18 1 T40 1 T104 1 T251 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 41 1 T39 2 T234 1 T236 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 30 1 T40 2 T104 1 T251 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 54 1 T43 1 T236 1 T252 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 7 1 T44 3 T251 1 T254 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 51 1 T32 1 T40 1 T235 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 18 1 T40 1 T43 2 T111 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 52 1 T32 1 T129 1 T135 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 10 1 T44 1 T104 2 T113 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 54 1 T42 1 T39 1 T235 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 21 1 T40 2 T251 1 T111 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 45 1 T32 1 T92 1 T95 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 20 1 T92 2 T40 1 T43 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 51 1 T20 1 T39 1 T234 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 21 1 T43 2 T104 1 T251 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 37 1 T39 1 T235 1 T236 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 23 1 T43 1 T104 1 T251 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 62 1 T32 1 T39 3 T235 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 42 1 T40 1 T44 2 T104 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 48 1 T39 1 T234 2 T129 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 16 1 T44 1 T104 1 T111 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 54 1 T32 1 T92 1 T39 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 21 1 T43 1 T41 3 T232 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 64 1 T20 1 T32 2 T39 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 26 1 T40 1 T44 2 T251 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 68 1 T32 1 T236 1 T233 15
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 72 1 T44 1 T111 1 T129 9
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 44 1 T42 1 T39 1 T44 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 16 1 T43 1 T44 1 T251 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 60 1 T234 1 T237 1 T261 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 18 1 T43 1 T251 1 T329 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 54 1 T32 1 T42 1 T92 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 28 1 T40 1 T43 1 T44 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 43 1 T42 1 T234 1 T236 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 25 1 T44 1 T111 1 T329 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 42 1 T20 1 T92 1 T235 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 18 1 T43 1 T104 1 T111 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 55 1 T32 2 T235 1 T236 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 34 1 T40 1 T44 1 T104 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 43 1 T235 1 T236 1 T133 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 37 1 T40 1 T43 2 T104 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 76 1 T32 1 T42 9 T39 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 48 1 T111 2 T224 7 T254 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 51 1 T32 1 T232 1 T133 3
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 26 1 T40 3 T104 1 T111 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 35 1 T20 1 T236 1 T252 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 25 1 T43 1 T104 1 T111 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 43 1 T41 1 T234 1 T236 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 34 1 T92 3 T40 2 T43 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 58 1 T32 1 T235 1 T234 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 56 1 T44 1 T104 2 T251 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 41 1 T32 1 T39 1 T235 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 27 1 T104 1 T254 1 T113 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 78 1 T32 1 T235 1 T112 5
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 64 1 T92 5 T40 1 T232 4
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 89 1 T20 9 T32 1 T39 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 61 1 T40 1 T44 2 T223 9
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 162 1 T32 3 T40 2 T39 10
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 110 1 T40 1 T43 10 T104 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 1 1 T345 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 13 1 T43 3 T330 5 T256 1


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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