Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for lid_openXval

Bins
cp_lid_open   cfg.vif.lid_open   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 60 1 T357 3 T127 4 T219 3
auto[0] auto[1] 70 1 T357 3 T127 9 T219 10
auto[1] auto[0] 68 1 T357 8 T127 5 T219 1
auto[1] auto[1] 62 1 T357 6 T127 2 T219 6


Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for z3_wakeupXval

Bins
cp_z3_wakeup   cfg.vif.z3_wakeup   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 134 1 T357 13 T127 12 T219 9
auto[1] auto[1] 126 1 T357 7 T127 8 T219 11


User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins
NAME   COUNT   STATUS   
invalid0 0 Excluded
invalid1 0 Excluded