Summary for Variable cfg.vif.ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.ac_present

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 53 1 T357 7 T249 9 T171 10
auto[1] 67 1 T357 13 T249 11 T171 10


Summary for Variable cfg.vif.bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.bat_disable

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 63 1 T357 11 T249 11 T171 10
auto[1] 57 1 T357 9 T249 9 T171 10


Summary for Variable cfg.vif.key0_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key0_in

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 51 1 T357 9 T249 7 T171 6
auto[1] 69 1 T357 11 T249 13 T171 14


Summary for Variable cfg.vif.key0_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key0_out

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 59 1 T357 8 T249 9 T171 7
auto[1] 61 1 T357 12 T249 11 T171 13


Summary for Variable cfg.vif.key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key1_in

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 56 1 T357 10 T249 9 T171 9
auto[1] 64 1 T357 10 T249 11 T171 11


Summary for Variable cfg.vif.key1_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key1_out

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 63 1 T357 8 T249 10 T171 9
auto[1] 57 1 T357 12 T249 10 T171 11


Summary for Variable cfg.vif.key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key2_in

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 60 1 T357 11 T249 9 T171 12
auto[1] 60 1 T357 9 T249 11 T171 8


Summary for Variable cfg.vif.key2_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key2_out

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 60 1 T357 9 T249 11 T171 13
auto[1] 60 1 T357 11 T249 9 T171 7


Summary for Variable cfg.vif.lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.lid_open

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 65 1 T357 13 T249 14 T171 8
auto[1] 55 1 T357 7 T249 6 T171 12


Summary for Variable cfg.vif.pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.pwrb_in

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 62 1 T357 10 T249 11 T171 9
auto[1] 58 1 T357 10 T249 9 T171 11


Summary for Variable cfg.vif.pwrb_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.pwrb_out

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 53 1 T357 12 T249 9 T171 7
auto[1] 67 1 T357 8 T249 11 T171 13


Summary for Variable cfg.vif.z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.z3_wakeup

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 54 1 T357 7 T249 11 T171 10
auto[1] 66 1 T357 13 T249 9 T171 10


Summary for Variable cp_ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 62 1 T357 8 T249 11 T171 10
auto[1] 58 1 T357 12 T249 9 T171 10


Summary for Variable cp_bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_bat_disable

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 63 1 T357 11 T249 11 T171 10
auto[1] 57 1 T357 9 T249 9 T171 10


Summary for Variable cp_key0_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 54 1 T357 6 T249 11 T171 9
auto[1] 66 1 T357 14 T249 9 T171 11


Summary for Variable cp_key0_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 60 1 T357 11 T249 9 T171 8
auto[1] 60 1 T357 9 T249 11 T171 12


Summary for Variable cp_key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 58 1 T357 6 T249 12 T171 13
auto[1] 62 1 T357 14 T249 8 T171 7


Summary for Variable cp_key1_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 65 1 T357 8 T249 9 T171 13
auto[1] 55 1 T357 12 T249 11 T171 7


Summary for Variable cp_key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 59 1 T357 8 T249 13 T171 8
auto[1] 61 1 T357 12 T249 7 T171 12


Summary for Variable cp_key2_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 61 1 T357 10 T249 11 T171 13
auto[1] 59 1 T357 10 T249 9 T171 7


Summary for Variable cp_lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_lid_open

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 62 1 T357 6 T249 10 T171 10
auto[1] 58 1 T357 14 T249 10 T171 10


Summary for Variable cp_pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 65 1 T357 13 T249 9 T171 12
auto[1] 55 1 T357 7 T249 11 T171 8


Summary for Variable cp_pwrb_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_out

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 54 1 T357 7 T249 11 T171 14
auto[1] 66 1 T357 13 T249 9 T171 6


Summary for Variable cp_z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_z3_wakeup

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 54 1 T357 7 T249 11 T171 10
auto[1] 66 1 T357 13 T249 9 T171 10


Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_inXval

Bins
cp_key0_in   cfg.vif.key0_in   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 23 1 T357 2 T249 3 T171 3
auto[0] auto[1] 31 1 T357 4 T249 8 T171 6
auto[1] auto[0] 28 1 T357 7 T249 4 T171 3
auto[1] auto[1] 38 1 T357 7 T249 5 T171 8


Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_outXval

Bins
cp_key0_out   cfg.vif.key0_out   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 30 1 T357 4 T249 3 T171 3
auto[0] auto[1] 30 1 T357 7 T249 6 T171 5
auto[1] auto[0] 29 1 T357 4 T249 6 T171 4
auto[1] auto[1] 31 1 T357 5 T249 5 T171 8


Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_inXval

Bins
cp_key1_in   cfg.vif.key1_in   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 29 1 T357 4 T249 3 T171 6
auto[0] auto[1] 29 1 T357 2 T249 9 T171 7
auto[1] auto[0] 27 1 T357 6 T249 6 T171 3
auto[1] auto[1] 35 1 T357 8 T249 2 T171 4


Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_outXval

Bins
cp_key1_out   cfg.vif.key1_out   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 36 1 T357 4 T249 2 T171 6
auto[0] auto[1] 29 1 T357 4 T249 7 T171 7
auto[1] auto[0] 27 1 T357 4 T249 8 T171 3
auto[1] auto[1] 28 1 T357 8 T249 3 T171 4


Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_inXval

Bins
cp_key2_in   cfg.vif.key2_in   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 28 1 T357 5 T249 6 T171 6
auto[0] auto[1] 31 1 T357 3 T249 7 T171 2
auto[1] auto[0] 32 1 T357 6 T249 3 T171 6
auto[1] auto[1] 29 1 T357 6 T249 4 T171 6


Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_outXval

Bins
cp_key2_out   cfg.vif.key2_out   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 29 1 T357 5 T249 6 T171 9
auto[0] auto[1] 32 1 T357 5 T249 5 T171 4
auto[1] auto[0] 31 1 T357 4 T249 5 T171 4
auto[1] auto[1] 28 1 T357 6 T249 4 T171 3


Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_inXval

Bins
cp_pwrb_in   cfg.vif.pwrb_in   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 36 1 T357 7 T249 4 T171 6
auto[0] auto[1] 29 1 T357 6 T249 5 T171 6
auto[1] auto[0] 26 1 T357 3 T249 7 T171 3
auto[1] auto[1] 29 1 T357 4 T249 4 T171 5


Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_outXval

Bins
cp_pwrb_out   cfg.vif.pwrb_out   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 26 1 T357 5 T249 4 T171 6
auto[0] auto[1] 28 1 T357 2 T249 7 T171 8
auto[1] auto[0] 27 1 T357 7 T249 5 T171 1
auto[1] auto[1] 39 1 T357 6 T249 4 T171 5


Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for ac_presentXval

Bins
cp_ac_present   cfg.vif.ac_present   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 28 1 T357 2 T249 5 T171 5
auto[0] auto[1] 34 1 T357 6 T249 6 T171 5
auto[1] auto[0] 25 1 T357 5 T249 4 T171 5
auto[1] auto[1] 33 1 T357 7 T249 5 T171 5


Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for bat_disableXval

Bins
cp_bat_disable   cfg.vif.bat_disable   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 63 1 T357 11 T249 11 T171 10
auto[1] auto[1] 57 1 T357 9 T249 9 T171 10


User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins
NAME   COUNT   STATUS   
invalid0 0 Excluded
invalid1 0 Excluded


Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for lid_openXval

Bins
cp_lid_open   cfg.vif.lid_open   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 29 1 T357 4 T249 6 T171 3
auto[0] auto[1] 33 1 T357 2 T249 4 T171 7
auto[1] auto[0] 36 1 T357 9 T249 8 T171 5
auto[1] auto[1] 22 1 T357 5 T249 2 T171 5


Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for z3_wakeupXval

Bins
cp_z3_wakeup   cfg.vif.z3_wakeup   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 54 1 T357 7 T249 11 T171 10
auto[1] auto[1] 66 1 T357 13 T249 9 T171 10


User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins
NAME   COUNT   STATUS   
invalid0 0 Excluded
invalid1 0 Excluded