UART Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	58.440s	10.569ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	15.857us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.630s	15.381us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.560s	3.553ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	31.693us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.260s	24.473us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.630s	15.381us	20	20	100.00
		uart_csr_aliasing	0.770s	31.693us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.733m	135.981ms	50	50	100.00
V2	parity	uart_smoke	58.440s	10.569ms	50	50	100.00
		uart_tx_rx	3.733m	135.981ms	50	50	100.00
V2	parity_error	uart_intr	54.581m	2.728s	45	50	90.00
		uart_rx_parity_err	4.905m	216.131ms	50	50	100.00
V2	watermark	uart_tx_rx	3.733m	135.981ms	50	50	100.00
		uart_intr	54.581m	2.728s	45	50	90.00
V2	fifo_full	uart_fifo_full	7.690m	183.115ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.361m	258.055ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.495m	121.769ms	300	300	100.00
V2	rx_frame_err	uart_intr	54.581m	2.728s	45	50	90.00
V2	rx_break_err	uart_intr	54.581m	2.728s	45	50	90.00
V2	rx_timeout	uart_intr	54.581m	2.728s	45	50	90.00
V2	perf	uart_perf	27.014m	32.302ms	50	50	100.00
V2	sys_loopback	uart_loopback	16.400s	8.701ms	50	50	100.00
V2	line_loopback	uart_loopback	16.400s	8.701ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	8.021m	102.352ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	56.870s	73.533ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	56.550s	6.521ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	38.750s	3.783ms	46	50	92.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	16.964m	110.188ms	49	50	98.00
V2	stress_all	uart_stress_all	1.178h	5.040s	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	26.822m	59.761ms	99	100	99.00
V2	alert_test	uart_alert_test	0.670s	11.737us	50	50	100.00
V2	intr_test	uart_intr_test	0.610s	90.305us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.450s	49.700us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.450s	49.700us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	15.857us	5	5	100.00
		uart_csr_rw	0.630s	15.381us	20	20	100.00
		uart_csr_aliasing	0.770s	31.693us	5	5	100.00
		uart_same_csr_outstanding	0.780s	69.630us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	15.857us	5	5	100.00
		uart_csr_rw	0.630s	15.381us	20	20	100.00
		uart_csr_aliasing	0.770s	31.693us	5	5	100.00
		uart_same_csr_outstanding	0.780s	69.630us	20	20	100.00
V2		TOTAL			1179	1190	99.08
V2S	tl_intg_err	uart_sec_cm	0.900s	483.521us	5	5	100.00
		uart_tl_intg_err	1.380s	84.699us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.380s	84.699us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1309	1320	99.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	15	78.95
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.80	98.45	100.00	--	99.76	100.00	97.59

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:

Test uart_intr has 4 failures.

3.uart_intr.2899264447
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_intr/latest/run.log

  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.uart_intr.1123549775
Line 287, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_intr/latest/run.log

  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 4 failures:

Test uart_rx_oversample has 4 failures.

19.uart_rx_oversample.288103966
Line 215, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/19.uart_rx_oversample/latest/run.log

  UVM_ERROR @  17666484 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (35927 [0x8c57] vs 6318 [0x18ae]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @  26380822 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (14377 [0x3829] vs 28754 [0x7052]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  34880822 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 1/6
  UVM_ERROR @  35023731 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (17835 [0x45ab] vs 35670 [0x8b56]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  53377060 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/6

20.uart_rx_oversample.1900444874
Line 215, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_rx_oversample/latest/run.log

  UVM_ERROR @  24074568 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (63853 [0xf96d] vs 63849 [0xf969]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  32620933 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 1/15
  UVM_INFO @  49469989 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/15
  UVM_ERROR @  49604184 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (32211 [0x7dd3] vs 47543 [0xb9b7]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 265642592 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/15

... and 2 more failures.

UVM_ERROR (uart_scoreboard.sv:420) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark has 1 failures:

Test uart_long_xfer_wo_dly has 1 failures.

0.uart_long_xfer_wo_dly.1084368511
Line 215, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @   1255545 ps: (uart_scoreboard.sv:420) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: TxWatermark
  UVM_INFO @ 8252391244 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/6
  UVM_INFO @ 14387816916 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/6
  UVM_INFO @ 18135383898 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/6
  UVM_INFO @ 25463108871 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/6

Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test uart_intr has 1 failures.
  - 45.uart_intr.4283619965
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/45.uart_intr/latest/run.log
```
  Job ID: smart:610c33b6-e1f2-4630-82b7-a68f657a837a
```

UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

88.uart_stress_all_with_rand_reset.2639426851
Line 1277, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1407057069514 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 1407303070006 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 1407545737158 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 1407787737642 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 1408029571459 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])