UART Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: `a9c19f09f3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	39.490s	11.616ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	17.107us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.630s	15.746us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.470s	3.124ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	57.065us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.150s	93.681us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.630s	15.746us	20	20	100.00
		uart_csr_aliasing	0.770s	57.065us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	6.003m	131.956ms	50	50	100.00
V2	parity	uart_smoke	39.490s	11.616ms	50	50	100.00
		uart_tx_rx	6.003m	131.956ms	50	50	100.00
V2	parity_error	uart_intr	50.083m	2.183s	47	50	94.00
		uart_rx_parity_err	9.129m	262.153ms	50	50	100.00
V2	watermark	uart_tx_rx	6.003m	131.956ms	50	50	100.00
		uart_intr	50.083m	2.183s	47	50	94.00
V2	fifo_full	uart_fifo_full	7.191m	287.212ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	10.873m	243.752ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	10.482m	216.069ms	300	300	100.00
V2	rx_frame_err	uart_intr	50.083m	2.183s	47	50	94.00
V2	rx_break_err	uart_intr	50.083m	2.183s	47	50	94.00
V2	rx_timeout	uart_intr	50.083m	2.183s	47	50	94.00
V2	perf	uart_perf	20.996m	24.169ms	50	50	100.00
V2	sys_loopback	uart_loopback	22.100s	8.043ms	48	50	96.00
V2	line_loopback	uart_loopback	22.100s	8.043ms	48	50	96.00
V2	rx_noise_filter	uart_noise_filter	4.710m	135.440ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.177m	44.906ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	25.440s	6.948ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	46.190s	4.688ms	42	50	84.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	26.138m	167.764ms	50	50	100.00
V2	stress_all	uart_stress_all	43.141m	1.539s	47	50	94.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	30.926m	261.941ms	95	100	95.00
V2	alert_test	uart_alert_test	0.630s	35.884us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	27.547us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.220s	89.396us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.220s	89.396us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	17.107us	5	5	100.00
		uart_csr_rw	0.630s	15.746us	20	20	100.00
		uart_csr_aliasing	0.770s	57.065us	5	5	100.00
		uart_same_csr_outstanding	0.760s	110.519us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	17.107us	5	5	100.00
		uart_csr_rw	0.630s	15.746us	20	20	100.00
		uart_csr_aliasing	0.770s	57.065us	5	5	100.00
		uart_same_csr_outstanding	0.760s	110.519us	20	20	100.00
V2		TOTAL			1169	1190	98.24
V2S	tl_intg_err	uart_sec_cm	0.840s	205.968us	5	5	100.00
		uart_tl_intg_err	1.510s	654.902us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.510s	654.902us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1299	1320	98.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	14	73.68
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.31	99.79	98.45	100.00	--	99.76	100.00	97.86

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 8 failures:

Test uart_rx_oversample has 8 failures.

4.uart_rx_oversample.16157925169315690499595602876037714904225039232144322613027781038169258119002
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 372885992 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (52087 [0xcb77] vs 35703 [0x8b77]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 389644686 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/5
  UVM_ERROR @ 390260992 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (16238 [0x3f6e] vs 15946 [0x3e4a]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 811115175 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/5
  UVM_INFO @ 1026156831 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/5

16.uart_rx_oversample.107588241704370397432201301001858638076726596741929281892167105866714842419581
Line 252, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/16.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 580417613 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (59013 [0xe685] vs 58058 [0xe2ca]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 598588007 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/20
  UVM_ERROR @ 598872343 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (351 [0x15f] vs 4439 [0x1157]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 614554318 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (49278 [0xc07e] vs 49390 [0xc0ee]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 622995997 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/20

... and 6 more failures.

UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 6 failures:

Test uart_loopback has 2 failures.

15.uart_loopback.83401758026877803843189549954431510748635089488347881445343054409899822304901
Line 262, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_loopback/latest/run.log

  UVM_ERROR @ 9615288128 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (234 [0xea] vs 169 [0xa9]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 9615288128 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (169 [0xa9] vs 234 [0xea]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_ERROR @ 9615808128 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (28 [0x1c] vs 60 [0x3c]) Regname: uart_reg_block.status reset value: 0x3c
  UVM_INFO @ 9615888128 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 15/16
  UVM_INFO @ 10743648128 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 16/16

23.uart_loopback.38504619176400766996234050063431622384430896088527906407399649348640352193257
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/23.uart_loopback/latest/run.log

  UVM_ERROR @ 3198588581 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (23 [0x17] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 3198588581 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 23 [0x17]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 3199546922 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 2/6
  UVM_INFO @ 4148054510 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/6
  UVM_INFO @ 4194596549 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/6

Test uart_stress_all_with_rand_reset has 4 failures.

41.uart_stress_all_with_rand_reset.106266495187757314121092765501356567334814489554066936702317975238791091318042
Line 1077, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 152550349296 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (29 [0x1d] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 152550349296 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (255 [0xff] vs 29 [0x1d]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 152550469296 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 10/15
  UVM_INFO @ 152691069296 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 70/539
  UVM_INFO @ 152752009296 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 11/15

86.uart_stress_all_with_rand_reset.68125682258927199078477878920783932580937209336619103007291698601444818816247
Line 1053, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 182495482613 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (42 [0x2a] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 182495482613 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 42 [0x2a]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 182495732615 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/15
  UVM_INFO @ 182732567843 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 266/276
  UVM_INFO @ 183143071127 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 267/276

... and 2 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test uart_intr has 3 failures.
  - 0.uart_intr.100113390995099824316705644551238165636328800770704152841093948355404350403038
    Line 315, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.uart_intr.64580649414523059255525797423107832115789357751116158855593351160030858036351
    Line 279, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 2 failures:

Test uart_stress_all has 1 failures.

17.uart_stress_all.110532422874186328146033663786206561996396087697359593430525124420318166546875
Line 257, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_stress_all/latest/run.log

  UVM_ERROR @ 6487743978 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 7165541826 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 1/20
  UVM_INFO @ 7206093834 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 2/20
  UVM_INFO @ 8539241097 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/20
  UVM_INFO @ 9649731629 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/20

Test uart_stress_all_with_rand_reset has 1 failures.

59.uart_stress_all_with_rand_reset.96761749973856819982153195124824401220418203684308976789140480243225027563540
Line 753, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 112464199025 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 112464199025 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_INFO @ 112464740696 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 112532616239 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 54/534

Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test uart_stress_all has 1 failures.
  - 15.uart_stress_all.81273618583983537102787122275465197602886126684337095956455012203311749211776
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_stress_all/latest/run.log
```
  Job ID: smart:8669ebfc-b7a0-4fc5-982d-297619ecb2e2
```

UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all has 1 failures.

31.uart_stress_all.31739196223819276954034365613204770259650688277783236809300611357301558804808
Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/31.uart_stress_all/latest/run.log

  UVM_ERROR @ 9185322211 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 9410322211 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 9636522211 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 9860522211 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 10086122211 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])