UART Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	26.020s	5.469ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	16.500us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	15.854us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.560s	137.718us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.790s	311.975us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.300s	49.521us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	15.854us	20	20	100.00
		uart_csr_aliasing	0.790s	311.975us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.920m	111.240ms	50	50	100.00
V2	parity	uart_smoke	26.020s	5.469ms	50	50	100.00
		uart_tx_rx	3.920m	111.240ms	50	50	100.00
V2	parity_error	uart_intr	6.134m	112.771ms	49	50	98.00
		uart_rx_parity_err	6.565m	169.050ms	49	50	98.00
V2	watermark	uart_tx_rx	3.920m	111.240ms	50	50	100.00
		uart_intr	6.134m	112.771ms	49	50	98.00
V2	fifo_full	uart_fifo_full	21.862m	245.329ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	3.699m	126.652ms	49	50	98.00
V2	fifo_reset	uart_fifo_reset	8.910m	206.266ms	299	300	99.67
V2	rx_frame_err	uart_intr	6.134m	112.771ms	49	50	98.00
V2	rx_break_err	uart_intr	6.134m	112.771ms	49	50	98.00
V2	rx_timeout	uart_intr	6.134m	112.771ms	49	50	98.00
V2	perf	uart_perf	23.718m	25.097ms	50	50	100.00
V2	sys_loopback	uart_loopback	24.820s	9.061ms	50	50	100.00
V2	line_loopback	uart_loopback	24.820s	9.061ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.115m	71.425ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.212m	51.621ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	53.960s	12.047ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	55.760s	6.238ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	27.617m	168.712ms	50	50	100.00
V2	stress_all	uart_stress_all	35.019m	236.686ms	50	50	100.00
V2	alert_test	uart_alert_test	0.600s	13.422us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	57.580us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.760s	249.991us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.760s	249.991us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	16.500us	5	5	100.00
		uart_csr_rw	0.640s	15.854us	20	20	100.00
		uart_csr_aliasing	0.790s	311.975us	5	5	100.00
		uart_same_csr_outstanding	0.790s	57.302us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	16.500us	5	5	100.00
		uart_csr_rw	0.640s	15.854us	20	20	100.00
		uart_csr_aliasing	0.790s	311.975us	5	5	100.00
		uart_same_csr_outstanding	0.790s	57.302us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	0.900s	221.930us	5	5	100.00
		uart_tl_intg_err	1.390s	85.241us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.390s	85.241us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	33.274m	103.227ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1314	1320	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	14	77.78
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.57

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 3 failures:

Test uart_intr has 1 failures.

4.uart_intr.42370403843700622411091403997436739662571182460168993711780020608303349864185
Line 319, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_intr/latest/run.log

  UVM_ERROR @ 41970575752 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 42018051895 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr
  UVM_INFO @ 42066813751 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark

Test uart_stress_all_with_rand_reset has 1 failures.

6.uart_stress_all_with_rand_reset.112972688056234867197530888163876187087066275321855373537316022517150966676533
Line 1087, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 70789636111 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 70848120901 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/790
  UVM_INFO @ 70879211779 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/790
  UVM_INFO @ 70947373327 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/7
  UVM_INFO @ 70991575303 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/790

Test uart_rx_parity_err has 1 failures.

13.uart_rx_parity_err.24404228002103637214444882637457941686568064275976175696005594715905132303791
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_rx_parity_err/latest/run.log

  UVM_ERROR @    751157 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @    751157 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 10541177037 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 1/5
  UVM_INFO @ 10763797705 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 2/5
  UVM_INFO @ 23387890589 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 3/5

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test uart_fifo_overflow has 1 failures.
  - 23.uart_fifo_overflow.7799186964430708037801340815569123714649978771597478372126782549513326746611
    Line 257, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/23.uart_fifo_overflow/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test uart_fifo_reset has 1 failures.
  - 133.uart_fifo_reset.43731112324273373323658872560694239503725297909832127493960253664332453532464
    Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/133.uart_fifo_reset/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:825) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

19.uart_stress_all_with_rand_reset.34194299343736338612998945945580734935229797805469447170305829857672823541891
Line 631, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 127331750580 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 127331768536 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 127331768536 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 7/10
  UVM_INFO @ 127331770580 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2