| T1053 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/194.uart_fifo_reset.3976538874 |
|
|
Sep 18 06:50:59 PM UTC 24 |
Sep 18 06:51:30 PM UTC 24 |
38262199998 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/187.uart_fifo_reset.1682547727 |
|
|
Sep 18 06:50:48 PM UTC 24 |
Sep 18 06:51:31 PM UTC 24 |
75835998615 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/171.uart_fifo_reset.2933540238 |
|
|
Sep 18 06:50:23 PM UTC 24 |
Sep 18 06:51:31 PM UTC 24 |
40224758189 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/216.uart_fifo_reset.3133243766 |
|
|
Sep 18 06:51:49 PM UTC 24 |
Sep 18 06:53:23 PM UTC 24 |
65462327152 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/181.uart_fifo_reset.219887681 |
|
|
Sep 18 06:50:40 PM UTC 24 |
Sep 18 06:51:33 PM UTC 24 |
22007655611 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/182.uart_fifo_reset.1214692869 |
|
|
Sep 18 06:50:40 PM UTC 24 |
Sep 18 06:51:38 PM UTC 24 |
205207356835 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/168.uart_fifo_reset.2381308012 |
|
|
Sep 18 06:50:20 PM UTC 24 |
Sep 18 06:51:41 PM UTC 24 |
124195959743 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/166.uart_fifo_reset.1197182508 |
|
|
Sep 18 06:50:18 PM UTC 24 |
Sep 18 06:51:41 PM UTC 24 |
112605554380 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/174.uart_fifo_reset.630516995 |
|
|
Sep 18 06:50:30 PM UTC 24 |
Sep 18 06:51:42 PM UTC 24 |
62147867100 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/198.uart_fifo_reset.3941181274 |
|
|
Sep 18 06:51:03 PM UTC 24 |
Sep 18 06:51:42 PM UTC 24 |
12678969046 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/193.uart_fifo_reset.1102988329 |
|
|
Sep 18 06:50:58 PM UTC 24 |
Sep 18 06:51:44 PM UTC 24 |
54683903571 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/180.uart_fifo_reset.2352553172 |
|
|
Sep 18 06:50:38 PM UTC 24 |
Sep 18 06:51:48 PM UTC 24 |
107366232944 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/186.uart_fifo_reset.3643064762 |
|
|
Sep 18 06:50:48 PM UTC 24 |
Sep 18 06:51:50 PM UTC 24 |
33008751998 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/201.uart_fifo_reset.3604726319 |
|
|
Sep 18 06:51:07 PM UTC 24 |
Sep 18 06:51:50 PM UTC 24 |
62147691189 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/205.uart_fifo_reset.327445472 |
|
|
Sep 18 06:51:27 PM UTC 24 |
Sep 18 06:51:54 PM UTC 24 |
65825834272 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/211.uart_fifo_reset.4031293878 |
|
|
Sep 18 06:51:42 PM UTC 24 |
Sep 18 06:51:57 PM UTC 24 |
14065811146 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/176.uart_fifo_reset.2860177016 |
|
|
Sep 18 06:50:32 PM UTC 24 |
Sep 18 06:51:58 PM UTC 24 |
61189101764 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/82.uart_fifo_reset.3718288326 |
|
|
Sep 18 06:46:33 PM UTC 24 |
Sep 18 06:52:00 PM UTC 24 |
226227344727 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/197.uart_fifo_reset.3000153699 |
|
|
Sep 18 06:51:02 PM UTC 24 |
Sep 18 06:52:03 PM UTC 24 |
55586749358 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/202.uart_fifo_reset.4007428967 |
|
|
Sep 18 06:51:15 PM UTC 24 |
Sep 18 06:52:06 PM UTC 24 |
50422145890 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/206.uart_fifo_reset.4050717799 |
|
|
Sep 18 06:51:31 PM UTC 24 |
Sep 18 06:52:06 PM UTC 24 |
15861481500 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/209.uart_fifo_reset.804456189 |
|
|
Sep 18 06:51:34 PM UTC 24 |
Sep 18 06:52:09 PM UTC 24 |
31546667902 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_fifo_reset.2607904262 |
|
|
Sep 18 06:37:27 PM UTC 24 |
Sep 18 06:52:24 PM UTC 24 |
138108702143 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/207.uart_fifo_reset.776525215 |
|
|
Sep 18 06:51:32 PM UTC 24 |
Sep 18 06:52:27 PM UTC 24 |
42855134333 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/196.uart_fifo_reset.3907127699 |
|
|
Sep 18 06:51:01 PM UTC 24 |
Sep 18 06:52:31 PM UTC 24 |
74486304037 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/218.uart_fifo_reset.2160411585 |
|
|
Sep 18 06:51:52 PM UTC 24 |
Sep 18 06:52:34 PM UTC 24 |
26245691858 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/152.uart_fifo_reset.2089616135 |
|
|
Sep 18 06:49:45 PM UTC 24 |
Sep 18 06:52:41 PM UTC 24 |
68232391279 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/223.uart_fifo_reset.2895372047 |
|
|
Sep 18 06:52:04 PM UTC 24 |
Sep 18 06:52:46 PM UTC 24 |
62376085450 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_perf.2756268006 |
|
|
Sep 18 06:43:08 PM UTC 24 |
Sep 18 06:52:47 PM UTC 24 |
22733441800 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/213.uart_fifo_reset.2154832816 |
|
|
Sep 18 06:51:42 PM UTC 24 |
Sep 18 06:52:49 PM UTC 24 |
22022836822 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/225.uart_fifo_reset.960263691 |
|
|
Sep 18 06:52:06 PM UTC 24 |
Sep 18 06:52:55 PM UTC 24 |
107347880418 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/228.uart_fifo_reset.911171338 |
|
|
Sep 18 06:52:27 PM UTC 24 |
Sep 18 06:52:58 PM UTC 24 |
38441772493 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/224.uart_fifo_reset.2864876013 |
|
|
Sep 18 06:52:06 PM UTC 24 |
Sep 18 06:52:59 PM UTC 24 |
21698295675 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/139.uart_fifo_reset.4191051284 |
|
|
Sep 18 06:49:15 PM UTC 24 |
Sep 18 06:53:00 PM UTC 24 |
88691824459 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/231.uart_fifo_reset.2589976309 |
|
|
Sep 18 06:52:42 PM UTC 24 |
Sep 18 06:53:08 PM UTC 24 |
10166573139 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/94.uart_fifo_reset.3798347503 |
|
|
Sep 18 06:47:37 PM UTC 24 |
Sep 18 06:53:10 PM UTC 24 |
141535177219 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/210.uart_fifo_reset.1065095521 |
|
|
Sep 18 06:51:39 PM UTC 24 |
Sep 18 06:53:18 PM UTC 24 |
155437535262 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/221.uart_fifo_reset.628264779 |
|
|
Sep 18 06:51:59 PM UTC 24 |
Sep 18 06:53:18 PM UTC 24 |
28643197509 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/227.uart_fifo_reset.3695414103 |
|
|
Sep 18 06:52:24 PM UTC 24 |
Sep 18 06:53:20 PM UTC 24 |
31031470728 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/113.uart_fifo_reset.1035797252 |
|
|
Sep 18 06:48:20 PM UTC 24 |
Sep 18 06:53:21 PM UTC 24 |
94989106008 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/169.uart_fifo_reset.1296951769 |
|
|
Sep 18 06:50:20 PM UTC 24 |
Sep 18 06:53:24 PM UTC 24 |
92886260749 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/232.uart_fifo_reset.731694908 |
|
|
Sep 18 06:52:47 PM UTC 24 |
Sep 18 06:53:25 PM UTC 24 |
92520397478 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_stress_all.1189515805 |
|
|
Sep 18 06:43:30 PM UTC 24 |
Sep 18 06:53:28 PM UTC 24 |
227378744277 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/237.uart_fifo_reset.989883442 |
|
|
Sep 18 06:52:59 PM UTC 24 |
Sep 18 06:53:28 PM UTC 24 |
16544213808 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/240.uart_fifo_reset.4171284557 |
|
|
Sep 18 06:53:11 PM UTC 24 |
Sep 18 06:53:28 PM UTC 24 |
9680956022 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/185.uart_fifo_reset.1749922782 |
|
|
Sep 18 06:50:48 PM UTC 24 |
Sep 18 06:53:29 PM UTC 24 |
292143243183 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/188.uart_fifo_reset.378438767 |
|
|
Sep 18 06:50:49 PM UTC 24 |
Sep 18 06:53:36 PM UTC 24 |
214247953997 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/75.uart_fifo_reset.422521168 |
|
|
Sep 18 06:46:05 PM UTC 24 |
Sep 18 06:53:40 PM UTC 24 |
100735636775 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/230.uart_fifo_reset.435264056 |
|
|
Sep 18 06:52:36 PM UTC 24 |
Sep 18 06:53:40 PM UTC 24 |
85880274739 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/265.uart_fifo_reset.700645659 |
|
|
Sep 18 06:53:54 PM UTC 24 |
Sep 18 06:56:17 PM UTC 24 |
105236249438 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/142.uart_fifo_reset.3111329932 |
|
|
Sep 18 06:49:28 PM UTC 24 |
Sep 18 06:53:40 PM UTC 24 |
109221126278 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/236.uart_fifo_reset.555797193 |
|
|
Sep 18 06:52:59 PM UTC 24 |
Sep 18 06:53:42 PM UTC 24 |
82048199620 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/150.uart_fifo_reset.616541442 |
|
|
Sep 18 06:49:42 PM UTC 24 |
Sep 18 06:53:44 PM UTC 24 |
125005793381 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/238.uart_fifo_reset.2661555284 |
|
|
Sep 18 06:53:01 PM UTC 24 |
Sep 18 06:53:48 PM UTC 24 |
24549503339 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/234.uart_fifo_reset.1685273482 |
|
|
Sep 18 06:52:50 PM UTC 24 |
Sep 18 06:53:51 PM UTC 24 |
37519241094 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/233.uart_fifo_reset.3275284302 |
|
|
Sep 18 06:52:48 PM UTC 24 |
Sep 18 06:53:52 PM UTC 24 |
102146533702 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/214.uart_fifo_reset.3793209727 |
|
|
Sep 18 06:51:43 PM UTC 24 |
Sep 18 06:53:53 PM UTC 24 |
39502430383 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/249.uart_fifo_reset.2800097831 |
|
|
Sep 18 06:53:28 PM UTC 24 |
Sep 18 06:53:54 PM UTC 24 |
37603897450 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/242.uart_fifo_reset.1805629210 |
|
|
Sep 18 06:53:20 PM UTC 24 |
Sep 18 06:53:54 PM UTC 24 |
28146870519 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/243.uart_fifo_reset.701824854 |
|
|
Sep 18 06:53:22 PM UTC 24 |
Sep 18 06:53:55 PM UTC 24 |
16408485761 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/192.uart_fifo_reset.2571426845 |
|
|
Sep 18 06:50:54 PM UTC 24 |
Sep 18 06:53:55 PM UTC 24 |
94567946426 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/219.uart_fifo_reset.1358681625 |
|
|
Sep 18 06:51:55 PM UTC 24 |
Sep 18 06:53:55 PM UTC 24 |
175180212685 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/250.uart_fifo_reset.2251215857 |
|
|
Sep 18 06:53:29 PM UTC 24 |
Sep 18 06:53:56 PM UTC 24 |
16057526332 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/212.uart_fifo_reset.1042771093 |
|
|
Sep 18 06:51:42 PM UTC 24 |
Sep 18 06:54:00 PM UTC 24 |
84991031511 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/195.uart_fifo_reset.3920098602 |
|
|
Sep 18 06:51:00 PM UTC 24 |
Sep 18 06:54:01 PM UTC 24 |
75827366248 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/162.uart_fifo_reset.2333730997 |
|
|
Sep 18 06:49:59 PM UTC 24 |
Sep 18 06:54:02 PM UTC 24 |
147310535230 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/217.uart_fifo_reset.3337399550 |
|
|
Sep 18 06:51:50 PM UTC 24 |
Sep 18 06:54:06 PM UTC 24 |
137410974494 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/56.uart_fifo_reset.2864095778 |
|
|
Sep 18 06:44:20 PM UTC 24 |
Sep 18 06:54:08 PM UTC 24 |
153968470674 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/255.uart_fifo_reset.350865679 |
|
|
Sep 18 06:53:40 PM UTC 24 |
Sep 18 06:54:10 PM UTC 24 |
19050992708 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/252.uart_fifo_reset.1636413246 |
|
|
Sep 18 06:53:30 PM UTC 24 |
Sep 18 06:54:15 PM UTC 24 |
22465917642 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/253.uart_fifo_reset.3326346558 |
|
|
Sep 18 06:53:37 PM UTC 24 |
Sep 18 06:54:17 PM UTC 24 |
49195294105 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/229.uart_fifo_reset.397782800 |
|
|
Sep 18 06:52:31 PM UTC 24 |
Sep 18 06:54:18 PM UTC 24 |
245165451380 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_perf.1743168317 |
|
|
Sep 18 06:39:21 PM UTC 24 |
Sep 18 06:54:18 PM UTC 24 |
19480365654 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/244.uart_fifo_reset.1891423150 |
|
|
Sep 18 06:53:23 PM UTC 24 |
Sep 18 06:54:20 PM UTC 24 |
24107911841 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1514873372 |
|
|
Sep 18 06:53:09 PM UTC 24 |
Sep 18 06:54:21 PM UTC 24 |
51660992082 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/260.uart_fifo_reset.4093114923 |
|
|
Sep 18 06:53:45 PM UTC 24 |
Sep 18 06:54:22 PM UTC 24 |
45093962850 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/258.uart_fifo_reset.1479246675 |
|
|
Sep 18 06:53:42 PM UTC 24 |
Sep 18 06:54:22 PM UTC 24 |
47934374758 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/269.uart_fifo_reset.626823971 |
|
|
Sep 18 06:53:56 PM UTC 24 |
Sep 18 06:54:24 PM UTC 24 |
18656241954 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/246.uart_fifo_reset.1455744130 |
|
|
Sep 18 06:53:24 PM UTC 24 |
Sep 18 06:54:26 PM UTC 24 |
162126693425 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/262.uart_fifo_reset.4078722711 |
|
|
Sep 18 06:53:52 PM UTC 24 |
Sep 18 06:54:27 PM UTC 24 |
48362364715 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/247.uart_fifo_reset.2733558084 |
|
|
Sep 18 06:53:25 PM UTC 24 |
Sep 18 06:54:28 PM UTC 24 |
137703977634 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/251.uart_fifo_reset.1461734139 |
|
|
Sep 18 06:53:29 PM UTC 24 |
Sep 18 06:54:31 PM UTC 24 |
142472281738 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/272.uart_fifo_reset.1576019206 |
|
|
Sep 18 06:54:03 PM UTC 24 |
Sep 18 06:54:31 PM UTC 24 |
205236487168 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/191.uart_fifo_reset.2401996043 |
|
|
Sep 18 06:50:52 PM UTC 24 |
Sep 18 06:54:33 PM UTC 24 |
139956296648 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/274.uart_fifo_reset.324081374 |
|
|
Sep 18 06:54:07 PM UTC 24 |
Sep 18 06:54:35 PM UTC 24 |
12427677200 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/271.uart_fifo_reset.477257611 |
|
|
Sep 18 06:54:01 PM UTC 24 |
Sep 18 06:54:35 PM UTC 24 |
13017936925 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/284.uart_fifo_reset.2224275994 |
|
|
Sep 18 06:54:22 PM UTC 24 |
Sep 18 06:54:39 PM UTC 24 |
7339259843 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/267.uart_fifo_reset.1954730681 |
|
|
Sep 18 06:53:55 PM UTC 24 |
Sep 18 06:54:40 PM UTC 24 |
75994242487 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/257.uart_fifo_reset.2438268536 |
|
|
Sep 18 06:53:41 PM UTC 24 |
Sep 18 06:54:42 PM UTC 24 |
177808818538 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/268.uart_fifo_reset.273146947 |
|
|
Sep 18 06:53:55 PM UTC 24 |
Sep 18 06:54:48 PM UTC 24 |
82305069788 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.3983559113 |
|
|
Sep 18 06:40:08 PM UTC 24 |
Sep 18 06:54:50 PM UTC 24 |
94904006115 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/184.uart_fifo_reset.2234451709 |
|
|
Sep 18 06:50:45 PM UTC 24 |
Sep 18 06:54:54 PM UTC 24 |
113311301751 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/273.uart_fifo_reset.2461790297 |
|
|
Sep 18 06:54:03 PM UTC 24 |
Sep 18 06:54:56 PM UTC 24 |
195270825400 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2855709852 |
|
|
Sep 18 06:54:32 PM UTC 24 |
Sep 18 06:54:58 PM UTC 24 |
11044014239 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3794746034 |
|
|
Sep 18 06:53:26 PM UTC 24 |
Sep 18 06:55:00 PM UTC 24 |
27412043442 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/117.uart_fifo_reset.742209049 |
|
|
Sep 18 06:48:30 PM UTC 24 |
Sep 18 06:55:05 PM UTC 24 |
262205793307 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/261.uart_fifo_reset.2373154933 |
|
|
Sep 18 06:53:49 PM UTC 24 |
Sep 18 06:55:06 PM UTC 24 |
225889587576 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/199.uart_fifo_reset.3517985372 |
|
|
Sep 18 06:51:03 PM UTC 24 |
Sep 18 06:55:06 PM UTC 24 |
80988935965 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/281.uart_fifo_reset.2628272389 |
|
|
Sep 18 06:54:21 PM UTC 24 |
Sep 18 06:55:08 PM UTC 24 |
17915659127 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/200.uart_fifo_reset.1166693865 |
|
|
Sep 18 06:51:04 PM UTC 24 |
Sep 18 06:55:11 PM UTC 24 |
90433973280 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/235.uart_fifo_reset.1460906217 |
|
|
Sep 18 06:52:56 PM UTC 24 |
Sep 18 06:55:13 PM UTC 24 |
309495724238 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/286.uart_fifo_reset.2953197944 |
|
|
Sep 18 06:54:28 PM UTC 24 |
Sep 18 06:55:14 PM UTC 24 |
47712962407 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/294.uart_fifo_reset.2314979979 |
|
|
Sep 18 06:54:40 PM UTC 24 |
Sep 18 06:55:14 PM UTC 24 |
98697935937 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/280.uart_fifo_reset.4003515674 |
|
|
Sep 18 06:54:19 PM UTC 24 |
Sep 18 06:55:14 PM UTC 24 |
18404516871 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2726900629 |
|
|
Sep 18 06:51:32 PM UTC 24 |
Sep 18 06:55:17 PM UTC 24 |
147870191264 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/291.uart_fifo_reset.3762968133 |
|
|
Sep 18 06:54:34 PM UTC 24 |
Sep 18 06:55:24 PM UTC 24 |
65465829768 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/256.uart_fifo_reset.1536830178 |
|
|
Sep 18 06:53:40 PM UTC 24 |
Sep 18 06:55:28 PM UTC 24 |
129484866575 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/259.uart_fifo_reset.3648885214 |
|
|
Sep 18 06:53:43 PM UTC 24 |
Sep 18 06:55:29 PM UTC 24 |
102677883992 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/293.uart_fifo_reset.77126830 |
|
|
Sep 18 06:54:36 PM UTC 24 |
Sep 18 06:55:30 PM UTC 24 |
26398361064 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/287.uart_fifo_reset.3149938910 |
|
|
Sep 18 06:54:28 PM UTC 24 |
Sep 18 06:55:30 PM UTC 24 |
219928444065 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/289.uart_fifo_reset.1545653884 |
|
|
Sep 18 06:54:32 PM UTC 24 |
Sep 18 06:55:31 PM UTC 24 |
57832068663 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/297.uart_fifo_reset.299732367 |
|
|
Sep 18 06:54:48 PM UTC 24 |
Sep 18 06:55:31 PM UTC 24 |
96717345801 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/299.uart_fifo_reset.3939913387 |
|
|
Sep 18 06:54:56 PM UTC 24 |
Sep 18 06:55:42 PM UTC 24 |
103407835160 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/285.uart_fifo_reset.2708548089 |
|
|
Sep 18 06:54:25 PM UTC 24 |
Sep 18 06:55:45 PM UTC 24 |
128428789394 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_stress_all.830169929 |
|
|
Sep 18 06:34:02 PM UTC 24 |
Sep 18 06:55:45 PM UTC 24 |
159090126343 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/275.uart_fifo_reset.3846428539 |
|
|
Sep 18 06:54:09 PM UTC 24 |
Sep 18 06:55:47 PM UTC 24 |
59910985375 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_perf.160010626 |
|
|
Sep 18 06:40:04 PM UTC 24 |
Sep 18 06:55:51 PM UTC 24 |
15443650250 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/288.uart_fifo_reset.3380245249 |
|
|
Sep 18 06:54:29 PM UTC 24 |
Sep 18 06:55:52 PM UTC 24 |
29920719783 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/277.uart_fifo_reset.687459990 |
|
|
Sep 18 06:54:16 PM UTC 24 |
Sep 18 06:55:56 PM UTC 24 |
52950635732 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_stress_all.1633792014 |
|
|
Sep 18 06:40:52 PM UTC 24 |
Sep 18 06:55:57 PM UTC 24 |
527177903172 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/241.uart_fifo_reset.3449191215 |
|
|
Sep 18 06:53:19 PM UTC 24 |
Sep 18 06:55:59 PM UTC 24 |
70637519622 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2132638427 |
|
|
Sep 18 06:51:21 PM UTC 24 |
Sep 18 06:56:02 PM UTC 24 |
225104324727 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/215.uart_fifo_reset.3496859413 |
|
|
Sep 18 06:51:45 PM UTC 24 |
Sep 18 06:56:06 PM UTC 24 |
106153658768 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/298.uart_fifo_reset.643129233 |
|
|
Sep 18 06:54:51 PM UTC 24 |
Sep 18 06:56:16 PM UTC 24 |
198821480727 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/295.uart_fifo_reset.391402977 |
|
|
Sep 18 06:54:40 PM UTC 24 |
Sep 18 06:56:34 PM UTC 24 |
134626707992 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/263.uart_fifo_reset.1128457636 |
|
|
Sep 18 06:53:53 PM UTC 24 |
Sep 18 06:56:38 PM UTC 24 |
99699955742 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2197739796 |
|
|
Sep 18 06:51:17 PM UTC 24 |
Sep 18 06:56:38 PM UTC 24 |
127898848804 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/264.uart_fifo_reset.4114889885 |
|
|
Sep 18 06:53:53 PM UTC 24 |
Sep 18 06:56:46 PM UTC 24 |
83630927962 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/292.uart_fifo_reset.4204768301 |
|
|
Sep 18 06:54:35 PM UTC 24 |
Sep 18 06:57:03 PM UTC 24 |
107580154122 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/278.uart_fifo_reset.3693446514 |
|
|
Sep 18 06:54:18 PM UTC 24 |
Sep 18 06:57:03 PM UTC 24 |
92280712704 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_perf.723987369 |
|
|
Sep 18 06:37:45 PM UTC 24 |
Sep 18 06:57:05 PM UTC 24 |
17861795946 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3371903395 |
|
|
Sep 18 06:53:23 PM UTC 24 |
Sep 18 06:57:15 PM UTC 24 |
135047458841 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_stress_all.3801881557 |
|
|
Sep 18 06:42:16 PM UTC 24 |
Sep 18 06:57:20 PM UTC 24 |
38224784431 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/179.uart_fifo_reset.526076917 |
|
|
Sep 18 06:50:34 PM UTC 24 |
Sep 18 06:57:25 PM UTC 24 |
99502543477 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/270.uart_fifo_reset.602474017 |
|
|
Sep 18 06:53:56 PM UTC 24 |
Sep 18 06:57:27 PM UTC 24 |
138884309270 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/220.uart_fifo_reset.2866778740 |
|
|
Sep 18 06:51:58 PM UTC 24 |
Sep 18 06:57:28 PM UTC 24 |
101421435056 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.197588312 |
|
|
Sep 18 06:36:53 PM UTC 24 |
Sep 18 06:57:31 PM UTC 24 |
188431270895 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/276.uart_fifo_reset.2867296656 |
|
|
Sep 18 06:54:10 PM UTC 24 |
Sep 18 06:57:39 PM UTC 24 |
128586673538 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/222.uart_fifo_reset.356076398 |
|
|
Sep 18 06:52:01 PM UTC 24 |
Sep 18 06:57:41 PM UTC 24 |
202404103408 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/283.uart_fifo_reset.3930388469 |
|
|
Sep 18 06:54:22 PM UTC 24 |
Sep 18 06:58:01 PM UTC 24 |
230122904231 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/282.uart_fifo_reset.1632883549 |
|
|
Sep 18 06:54:21 PM UTC 24 |
Sep 18 06:58:10 PM UTC 24 |
123604034300 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/254.uart_fifo_reset.2742194870 |
|
|
Sep 18 06:53:39 PM UTC 24 |
Sep 18 06:58:16 PM UTC 24 |
104088025936 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_perf.583137297 |
|
|
Sep 18 06:43:28 PM UTC 24 |
Sep 18 06:58:37 PM UTC 24 |
15407516658 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/266.uart_fifo_reset.1224251898 |
|
|
Sep 18 06:53:55 PM UTC 24 |
Sep 18 06:59:25 PM UTC 24 |
209900510154 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/296.uart_fifo_reset.420540998 |
|
|
Sep 18 06:54:43 PM UTC 24 |
Sep 18 07:00:07 PM UTC 24 |
150840855605 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_perf.3153943580 |
|
|
Sep 18 06:34:45 PM UTC 24 |
Sep 18 07:00:23 PM UTC 24 |
26306580965 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.157994157 |
|
|
Sep 18 06:40:48 PM UTC 24 |
Sep 18 07:00:37 PM UTC 24 |
121107403611 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_stress_all.2256220346 |
|
|
Sep 18 06:36:12 PM UTC 24 |
Sep 18 07:01:38 PM UTC 24 |
300091106817 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_stress_all.864734192 |
|
|
Sep 18 06:41:27 PM UTC 24 |
Sep 18 07:01:55 PM UTC 24 |
336313284758 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.1170871776 |
|
|
Sep 18 06:43:08 PM UTC 24 |
Sep 18 07:09:14 PM UTC 24 |
173523908168 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_stress_all.2219323458 |
|
|
Sep 18 06:42:48 PM UTC 24 |
Sep 18 07:12:30 PM UTC 24 |
385860101880 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.944891375 |
|
|
Sep 18 06:54:57 PM UTC 24 |
Sep 18 06:55:02 PM UTC 24 |
120132052 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.2420017495 |
|
|
Sep 18 06:55:01 PM UTC 24 |
Sep 18 06:55:03 PM UTC 24 |
108311864 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.129741515 |
|
|
Sep 18 06:55:00 PM UTC 24 |
Sep 18 06:55:03 PM UTC 24 |
79674192 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.2517338649 |
|
|
Sep 18 06:55:02 PM UTC 24 |
Sep 18 06:55:04 PM UTC 24 |
171525766 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.1131812967 |
|
|
Sep 18 06:55:04 PM UTC 24 |
Sep 18 06:55:06 PM UTC 24 |
49841373 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.2155189681 |
|
|
Sep 18 06:55:05 PM UTC 24 |
Sep 18 06:55:07 PM UTC 24 |
138805748 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.706228864 |
|
|
Sep 18 06:55:04 PM UTC 24 |
Sep 18 06:55:08 PM UTC 24 |
220201258 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1334002764 |
|
|
Sep 18 06:55:06 PM UTC 24 |
Sep 18 06:55:08 PM UTC 24 |
18890622 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.4195361692 |
|
|
Sep 18 06:55:06 PM UTC 24 |
Sep 18 06:55:09 PM UTC 24 |
31021060 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.3466606944 |
|
|
Sep 18 06:55:08 PM UTC 24 |
Sep 18 06:55:11 PM UTC 24 |
220585034 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.3352387910 |
|
|
Sep 18 06:55:09 PM UTC 24 |
Sep 18 06:55:11 PM UTC 24 |
22077381 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.925658699 |
|
|
Sep 18 06:55:08 PM UTC 24 |
Sep 18 06:55:11 PM UTC 24 |
91705857 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.1447122208 |
|
|
Sep 18 06:55:09 PM UTC 24 |
Sep 18 06:55:11 PM UTC 24 |
42826351 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3938116979 |
|
|
Sep 18 06:55:09 PM UTC 24 |
Sep 18 06:55:11 PM UTC 24 |
11944510 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.1239203589 |
|
|
Sep 18 06:55:10 PM UTC 24 |
Sep 18 06:55:13 PM UTC 24 |
15029602 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.1584722525 |
|
|
Sep 18 06:55:12 PM UTC 24 |
Sep 18 06:55:14 PM UTC 24 |
15480220 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.1037596472 |
|
|
Sep 18 06:55:12 PM UTC 24 |
Sep 18 06:55:15 PM UTC 24 |
15688602 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.297495937 |
|
|
Sep 18 06:55:12 PM UTC 24 |
Sep 18 06:55:15 PM UTC 24 |
29878844 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.4053352242 |
|
|
Sep 18 06:55:12 PM UTC 24 |
Sep 18 06:55:15 PM UTC 24 |
99620568 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.3369840301 |
|
|
Sep 18 06:55:12 PM UTC 24 |
Sep 18 06:55:15 PM UTC 24 |
146034414 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3840646482 |
|
|
Sep 18 06:55:10 PM UTC 24 |
Sep 18 06:55:15 PM UTC 24 |
867317444 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.4053370858 |
|
|
Sep 18 06:55:12 PM UTC 24 |
Sep 18 06:55:15 PM UTC 24 |
82666021 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3659815008 |
|
|
Sep 18 06:55:14 PM UTC 24 |
Sep 18 06:55:16 PM UTC 24 |
13767356 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.4079340818 |
|
|
Sep 18 06:55:15 PM UTC 24 |
Sep 18 06:55:17 PM UTC 24 |
14924260 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.1629022302 |
|
|
Sep 18 06:55:15 PM UTC 24 |
Sep 18 06:55:17 PM UTC 24 |
75932117 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.833078066 |
|
|
Sep 18 06:55:15 PM UTC 24 |
Sep 18 06:55:18 PM UTC 24 |
43116660 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.73997356 |
|
|
Sep 18 06:55:15 PM UTC 24 |
Sep 18 06:55:18 PM UTC 24 |
344573566 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.2140042695 |
|
|
Sep 18 06:55:16 PM UTC 24 |
Sep 18 06:55:19 PM UTC 24 |
22686623 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.3286789226 |
|
|
Sep 18 06:55:16 PM UTC 24 |
Sep 18 06:55:19 PM UTC 24 |
23220959 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.1986964591 |
|
|
Sep 18 06:55:16 PM UTC 24 |
Sep 18 06:55:19 PM UTC 24 |
35050075 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.1545268563 |
|
|
Sep 18 06:55:17 PM UTC 24 |
Sep 18 06:55:19 PM UTC 24 |
14403400 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.3300109976 |
|
|
Sep 18 06:55:16 PM UTC 24 |
Sep 18 06:55:19 PM UTC 24 |
93274287 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.227831410 |
|
|
Sep 18 06:55:17 PM UTC 24 |
Sep 18 06:55:19 PM UTC 24 |
55032561 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.1729707487 |
|
|
Sep 18 06:55:18 PM UTC 24 |
Sep 18 06:55:20 PM UTC 24 |
327317887 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.554613617 |
|
|
Sep 18 06:55:18 PM UTC 24 |
Sep 18 06:55:20 PM UTC 24 |
34842427 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.1130558104 |
|
|
Sep 18 06:55:17 PM UTC 24 |
Sep 18 06:55:21 PM UTC 24 |
260782440 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.3812871101 |
|
|
Sep 18 06:55:18 PM UTC 24 |
Sep 18 06:55:21 PM UTC 24 |
147526563 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.4234494672 |
|
|
Sep 18 06:55:16 PM UTC 24 |
Sep 18 06:55:21 PM UTC 24 |
363055626 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.1882747329 |
|
|
Sep 18 06:55:19 PM UTC 24 |
Sep 18 06:55:21 PM UTC 24 |
38257694 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.4023212868 |
|
|
Sep 18 06:55:19 PM UTC 24 |
Sep 18 06:55:21 PM UTC 24 |
39757797 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.3458296773 |
|
|
Sep 18 06:55:19 PM UTC 24 |
Sep 18 06:55:21 PM UTC 24 |
12817815 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.2107238679 |
|
|
Sep 18 06:55:20 PM UTC 24 |
Sep 18 06:55:22 PM UTC 24 |
32844645 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2871754979 |
|
|
Sep 18 06:55:20 PM UTC 24 |
Sep 18 06:55:22 PM UTC 24 |
91226976 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3126935674 |
|
|
Sep 18 06:55:21 PM UTC 24 |
Sep 18 06:55:23 PM UTC 24 |
23272449 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3934117887 |
|
|
Sep 18 06:55:21 PM UTC 24 |
Sep 18 06:55:23 PM UTC 24 |
71254288 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.3851340678 |
|
|
Sep 18 06:55:21 PM UTC 24 |
Sep 18 06:55:23 PM UTC 24 |
428167316 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.2068258584 |
|
|
Sep 18 06:55:19 PM UTC 24 |
Sep 18 06:55:24 PM UTC 24 |
252352762 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.1800433228 |
|
|
Sep 18 06:55:21 PM UTC 24 |
Sep 18 06:55:24 PM UTC 24 |
91900532 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.513756224 |
|
|
Sep 18 06:55:23 PM UTC 24 |
Sep 18 06:55:24 PM UTC 24 |
33358619 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.720329704 |
|
|
Sep 18 06:55:23 PM UTC 24 |
Sep 18 06:55:25 PM UTC 24 |
99022551 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.2624684163 |
|
|
Sep 18 06:55:23 PM UTC 24 |
Sep 18 06:55:25 PM UTC 24 |
52553209 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.603586977 |
|
|
Sep 18 06:55:23 PM UTC 24 |
Sep 18 06:55:25 PM UTC 24 |
11424202 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.890192742 |
|
|
Sep 18 06:55:23 PM UTC 24 |
Sep 18 06:55:25 PM UTC 24 |
27112238 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.414037045 |
|
|
Sep 18 06:55:23 PM UTC 24 |
Sep 18 06:55:25 PM UTC 24 |
71411724 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.4085025695 |
|
|
Sep 18 06:55:23 PM UTC 24 |
Sep 18 06:55:26 PM UTC 24 |
88315191 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3820713800 |
|
|
Sep 18 06:55:23 PM UTC 24 |
Sep 18 06:55:26 PM UTC 24 |
186012807 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.353469851 |
|
|
Sep 18 06:55:24 PM UTC 24 |
Sep 18 06:55:26 PM UTC 24 |
55918846 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.3928801744 |
|
|
Sep 18 06:55:24 PM UTC 24 |
Sep 18 06:55:26 PM UTC 24 |
12636427 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.1226480965 |
|
|
Sep 18 06:55:24 PM UTC 24 |
Sep 18 06:55:27 PM UTC 24 |
700049073 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.1464813167 |
|
|
Sep 18 06:55:24 PM UTC 24 |
Sep 18 06:55:28 PM UTC 24 |
157227994 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2730556086 |
|
|
Sep 18 06:55:30 PM UTC 24 |
Sep 18 06:55:33 PM UTC 24 |
42447851 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.682072763 |
|
|
Sep 18 06:55:26 PM UTC 24 |
Sep 18 06:55:28 PM UTC 24 |
46995505 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.3690078444 |
|
|
Sep 18 06:55:26 PM UTC 24 |
Sep 18 06:55:28 PM UTC 24 |
130472398 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.2069231510 |
|
|
Sep 18 06:55:26 PM UTC 24 |
Sep 18 06:55:28 PM UTC 24 |
15985616 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.612982282 |
|
|
Sep 18 06:55:26 PM UTC 24 |
Sep 18 06:55:28 PM UTC 24 |
31484067 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.2709016306 |
|
|
Sep 18 06:55:27 PM UTC 24 |
Sep 18 06:55:28 PM UTC 24 |
59617890 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.4280011037 |
|
|
Sep 18 06:55:26 PM UTC 24 |
Sep 18 06:55:29 PM UTC 24 |
175983510 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.3814349874 |
|
|
Sep 18 06:55:26 PM UTC 24 |
Sep 18 06:55:29 PM UTC 24 |
102313905 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3453405843 |
|
|
Sep 18 06:55:26 PM UTC 24 |
Sep 18 06:55:29 PM UTC 24 |
97976652 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1199629552 |
|
|
Sep 18 06:55:27 PM UTC 24 |
Sep 18 06:55:29 PM UTC 24 |
39317173 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.1076827222 |
|
|
Sep 18 06:55:28 PM UTC 24 |
Sep 18 06:55:30 PM UTC 24 |
40511820 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.2710636099 |
|
|
Sep 18 06:55:28 PM UTC 24 |
Sep 18 06:55:30 PM UTC 24 |
41442951 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.1378484698 |
|
|
Sep 18 06:55:28 PM UTC 24 |
Sep 18 06:55:30 PM UTC 24 |
22374892 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.3119432281 |
|
|
Sep 18 06:55:28 PM UTC 24 |
Sep 18 06:55:31 PM UTC 24 |
87413750 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.2963053130 |
|
|
Sep 18 06:55:28 PM UTC 24 |
Sep 18 06:55:32 PM UTC 24 |
109997086 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.3329512845 |
|
|
Sep 18 06:55:30 PM UTC 24 |
Sep 18 06:55:32 PM UTC 24 |
37402222 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.2960425732 |
|
|
Sep 18 06:55:31 PM UTC 24 |
Sep 18 06:55:32 PM UTC 24 |
25146358 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.4238575788 |
|
|
Sep 18 06:55:30 PM UTC 24 |
Sep 18 06:55:32 PM UTC 24 |
76836510 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.270426857 |
|
|
Sep 18 06:55:30 PM UTC 24 |
Sep 18 06:55:32 PM UTC 24 |
74770556 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.527921212 |
|
|
Sep 18 06:55:30 PM UTC 24 |
Sep 18 06:55:32 PM UTC 24 |
76034820 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.2872817490 |
|
|
Sep 18 06:55:32 PM UTC 24 |
Sep 18 06:55:34 PM UTC 24 |
12118983 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.2506549999 |
|
|
Sep 18 06:55:30 PM UTC 24 |
Sep 18 06:55:33 PM UTC 24 |
26753910 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.874250524 |
|
|
Sep 18 06:55:31 PM UTC 24 |
Sep 18 06:55:33 PM UTC 24 |
22523341 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.3446110571 |
|
|
Sep 18 06:55:31 PM UTC 24 |
Sep 18 06:55:33 PM UTC 24 |
49941110 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.3420922616 |
|
|
Sep 18 06:55:30 PM UTC 24 |
Sep 18 06:55:33 PM UTC 24 |
47115318 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1028771804 |
|
|
Sep 18 06:55:30 PM UTC 24 |
Sep 18 06:55:33 PM UTC 24 |
510732137 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.3875406728 |
|
|
Sep 18 06:55:32 PM UTC 24 |
Sep 18 06:55:34 PM UTC 24 |
147226227 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.2660537555 |
|
|
Sep 18 06:55:33 PM UTC 24 |
Sep 18 06:55:35 PM UTC 24 |
12377988 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.865777039 |
|
|
Sep 18 06:55:33 PM UTC 24 |
Sep 18 06:55:35 PM UTC 24 |
85658698 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3914923066 |
|
|
Sep 18 06:55:32 PM UTC 24 |
Sep 18 06:55:35 PM UTC 24 |
50419577 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.337017116 |
|
|
Sep 18 06:55:33 PM UTC 24 |
Sep 18 06:55:35 PM UTC 24 |
37339176 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.2355073675 |
|
|
Sep 18 06:55:32 PM UTC 24 |
Sep 18 06:55:35 PM UTC 24 |
303719857 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1307203992 |
|
|
Sep 18 06:55:33 PM UTC 24 |
Sep 18 06:55:36 PM UTC 24 |
155088105 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.540498374 |
|
|
Sep 18 06:55:32 PM UTC 24 |
Sep 18 06:55:36 PM UTC 24 |
76714680 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.2270699000 |
|
|
Sep 18 06:55:35 PM UTC 24 |
Sep 18 06:55:37 PM UTC 24 |
52989848 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.3554364377 |
|
|
Sep 18 06:55:35 PM UTC 24 |
Sep 18 06:55:37 PM UTC 24 |
40851474 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1514490689 |
|
|
Sep 18 06:55:35 PM UTC 24 |
Sep 18 06:55:37 PM UTC 24 |
63014694 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.1731534073 |
|
|
Sep 18 06:55:35 PM UTC 24 |
Sep 18 06:55:37 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.1140469159 |
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