| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.09 | 99.08 | 97.65 | 100.00 | 98.35 | 100.00 | 99.46 |
| T62 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.4097227049 | Sep 18 06:55:35 PM UTC 24 | Sep 18 06:55:37 PM UTC 24 | 18995748 ps | ||
| T1255 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3055417899 | Sep 18 06:55:35 PM UTC 24 | Sep 18 06:55:37 PM UTC 24 | 147854368 ps | ||
| T1256 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2042898893 | Sep 18 06:55:36 PM UTC 24 | Sep 18 06:55:38 PM UTC 24 | 59896455 ps | ||
| T1257 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1983919616 | Sep 18 06:55:36 PM UTC 24 | Sep 18 06:55:38 PM UTC 24 | 60058866 ps | ||
| T1258 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.2159578420 | Sep 18 06:55:35 PM UTC 24 | Sep 18 06:55:38 PM UTC 24 | 39443148 ps | ||
| T1259 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.2685188836 | Sep 18 06:55:35 PM UTC 24 | Sep 18 06:55:38 PM UTC 24 | 38920548 ps | ||
| T1260 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.1555516217 | Sep 18 06:55:36 PM UTC 24 | Sep 18 06:55:38 PM UTC 24 | 42324687 ps | ||
| T1261 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.3022323457 | Sep 18 06:55:36 PM UTC 24 | Sep 18 06:55:38 PM UTC 24 | 72035957 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.1442200251 | Sep 18 06:55:36 PM UTC 24 | Sep 18 06:55:38 PM UTC 24 | 754766531 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.3825843549 | Sep 18 06:55:36 PM UTC 24 | Sep 18 06:55:38 PM UTC 24 | 40119316 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.1140632336 | Sep 18 06:55:35 PM UTC 24 | Sep 18 06:55:39 PM UTC 24 | 170997657 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.4078545141 | Sep 18 06:55:38 PM UTC 24 | Sep 18 06:55:39 PM UTC 24 | 32453835 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.2025137877 | Sep 18 06:55:37 PM UTC 24 | Sep 18 06:55:39 PM UTC 24 | 121282572 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3139904455 | Sep 18 06:55:37 PM UTC 24 | Sep 18 06:55:39 PM UTC 24 | 25130039 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2906349353 | Sep 18 06:55:37 PM UTC 24 | Sep 18 06:55:40 PM UTC 24 | 19618252 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.443626196 | Sep 18 06:55:37 PM UTC 24 | Sep 18 06:55:40 PM UTC 24 | 510218596 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.2465002419 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:43 PM UTC 24 | 29253977 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2846741054 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:43 PM UTC 24 | 23771346 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.796193340 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:43 PM UTC 24 | 20341276 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2386420991 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:43 PM UTC 24 | 84008836 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.126441075 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:43 PM UTC 24 | 75670984 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.112415363 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:43 PM UTC 24 | 92055153 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3647956212 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:43 PM UTC 24 | 50922015 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4175505853 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:43 PM UTC 24 | 70005517 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.3766089 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:43 PM UTC 24 | 16773833 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.2769576 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:43 PM UTC 24 | 42749740 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.3249756741 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:43 PM UTC 24 | 74060594 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.741107630 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:43 PM UTC 24 | 13358603 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.1974143638 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:43 PM UTC 24 | 157432326 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2659357423 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:44 PM UTC 24 | 56280041 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3076008544 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:44 PM UTC 24 | 62049367 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.2712797734 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:44 PM UTC 24 | 105101201 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2822975620 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:44 PM UTC 24 | 24469434 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.454243175 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:44 PM UTC 24 | 74725516 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.1053487078 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:44 PM UTC 24 | 244769649 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.1921638175 | Sep 18 06:55:43 PM UTC 24 | Sep 18 06:55:44 PM UTC 24 | 58823055 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.1103380823 | Sep 18 06:55:41 PM UTC 24 | Sep 18 06:55:44 PM UTC 24 | 473004766 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.805701754 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 26464238 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.3394127146 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 56902374 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3829564019 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 25990206 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.2227639489 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 144111894 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.3053099474 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 34296770 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.2470577797 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 12444085 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.2938107583 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 52882588 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1420102681 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 22830444 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.899795203 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 15272626 ps | ||
| T1297 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.1639296344 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 13368443 ps | ||
| T1298 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.547803219 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 43492840 ps | ||
| T1299 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.2743354390 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 38755005 ps | ||
| T1300 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.1240552857 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 14571548 ps | ||
| T1301 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3228378849 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 13544510 ps | ||
| T1302 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.4072981405 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 17554386 ps | ||
| T1303 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.3793070790 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 44516366 ps | ||
| T1304 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.937114735 | Sep 18 06:55:48 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 12903292 ps | ||
| T1305 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.3869713856 | Sep 18 06:55:48 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 12073437 ps | ||
| T1306 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.2193680873 | Sep 18 06:55:48 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 13663658 ps | ||
| T1307 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.827842523 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 235466344 ps | ||
| T1308 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.2215823488 | Sep 18 06:55:47 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 12340488 ps | ||
| T1309 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.1610363697 | Sep 18 06:55:48 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 24445165 ps | ||
| T1310 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3096325158 | Sep 18 06:55:48 PM UTC 24 | Sep 18 06:55:49 PM UTC 24 | 75652557 ps | ||
| T1311 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1611427288 | Sep 18 06:55:54 PM UTC 24 | Sep 18 06:55:56 PM UTC 24 | 12689352 ps | ||
| T1312 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.1769168618 | Sep 18 06:55:54 PM UTC 24 | Sep 18 06:55:56 PM UTC 24 | 38826323 ps | ||
| T1313 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2636990372 | Sep 18 06:55:54 PM UTC 24 | Sep 18 06:55:56 PM UTC 24 | 45651185 ps | ||
| T1314 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.2749038841 | Sep 18 06:55:54 PM UTC 24 | Sep 18 06:55:56 PM UTC 24 | 109961940 ps | ||
| T1315 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.617101702 | Sep 18 06:55:54 PM UTC 24 | Sep 18 06:55:56 PM UTC 24 | 56950339 ps | ||
| T1316 | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.798830457 | Sep 18 06:55:54 PM UTC 24 | Sep 18 06:55:56 PM UTC 24 | 65162582 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_rx_oversample.339495694 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 2221836741 ps |
| CPU time | 13.69 seconds |
| Started | Sep 18 06:14:27 PM UTC 24 |
| Finished | Sep 18 06:14:42 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339495694 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.339495694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.219052225 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10752345553 ps |
| CPU time | 31.6 seconds |
| Started | Sep 18 06:15:34 PM UTC 24 |
| Finished | Sep 18 06:16:06 PM UTC 24 |
| Peak memory | 226324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=219052225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_w ith_rand_reset.219052225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_tx_rx.1762367888 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 24763154771 ps |
| CPU time | 28.38 seconds |
| Started | Sep 18 06:14:53 PM UTC 24 |
| Finished | Sep 18 06:15:23 PM UTC 24 |
| Peak memory | 204120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762367888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1762367888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_stress_all.1910485464 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 618835458338 ps |
| CPU time | 216.22 seconds |
| Started | Sep 18 06:15:35 PM UTC 24 |
| Finished | Sep 18 06:19:14 PM UTC 24 |
| Peak memory | 205892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910485464 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1910485464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_stress_all.4087343083 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 310994045532 ps |
| CPU time | 241.77 seconds |
| Started | Sep 18 06:16:47 PM UTC 24 |
| Finished | Sep 18 06:20:52 PM UTC 24 |
| Peak memory | 218440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087343083 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.4087343083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_stress_all.4008828830 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 180697239881 ps |
| CPU time | 127.76 seconds |
| Started | Sep 18 06:18:51 PM UTC 24 |
| Finished | Sep 18 06:21:01 PM UTC 24 |
| Peak memory | 205904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008828830 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.4008828830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_stress_all.3328967035 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 129153632096 ps |
| CPU time | 151.86 seconds |
| Started | Sep 18 06:17:26 PM UTC 24 |
| Finished | Sep 18 06:20:00 PM UTC 24 |
| Peak memory | 205756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328967035 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3328967035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.3398998043 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 66285698685 ps |
| CPU time | 160.53 seconds |
| Started | Sep 18 06:16:23 PM UTC 24 |
| Finished | Sep 18 06:19:07 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398998043 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3398998043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_intr.144838197 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 53153533031 ps |
| CPU time | 32.29 seconds |
| Started | Sep 18 06:15:15 PM UTC 24 |
| Finished | Sep 18 06:15:49 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144838197 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.144838197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.2875076143 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 160718061208 ps |
| CPU time | 299.01 seconds |
| Started | Sep 18 06:14:47 PM UTC 24 |
| Finished | Sep 18 06:19:50 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875076143 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2875076143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_stress_all.422891510 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 73326090314 ps |
| CPU time | 37.54 seconds |
| Started | Sep 18 06:16:26 PM UTC 24 |
| Finished | Sep 18 06:17:05 PM UTC 24 |
| Peak memory | 203900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422891510 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.422891510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_sec_cm.3630491988 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 178250249 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 06:14:49 PM UTC 24 |
| Finished | Sep 18 06:14:51 PM UTC 24 |
| Peak memory | 235520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630491988 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3630491988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_fifo_full.1657851870 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 152119892828 ps |
| CPU time | 85.06 seconds |
| Started | Sep 18 06:15:38 PM UTC 24 |
| Finished | Sep 18 06:17:05 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657851870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1657851870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_fifo_full.3008246922 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 201555752569 ps |
| CPU time | 129.62 seconds |
| Started | Sep 18 06:18:22 PM UTC 24 |
| Finished | Sep 18 06:20:34 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008246922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3008246922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.3742711648 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 48533234385 ps |
| CPU time | 43.96 seconds |
| Started | Sep 18 06:18:13 PM UTC 24 |
| Finished | Sep 18 06:18:59 PM UTC 24 |
| Peak memory | 218240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3742711648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_ with_rand_reset.3742711648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.2517338649 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 171525766 ps |
| CPU time | 0.86 seconds |
| Started | Sep 18 06:55:02 PM UTC 24 |
| Finished | Sep 18 06:55:04 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517338649 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2517338649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_stress_all.1041866629 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 357779618755 ps |
| CPU time | 420.04 seconds |
| Started | Sep 18 06:21:59 PM UTC 24 |
| Finished | Sep 18 06:29:05 PM UTC 24 |
| Peak memory | 218756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041866629 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1041866629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.1352684321 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 234314778007 ps |
| CPU time | 222.35 seconds |
| Started | Sep 18 06:21:26 PM UTC 24 |
| Finished | Sep 18 06:25:11 PM UTC 24 |
| Peak memory | 209352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352684321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1352684321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.4091967506 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 46382157009 ps |
| CPU time | 147.13 seconds |
| Started | Sep 18 06:17:19 PM UTC 24 |
| Finished | Sep 18 06:19:49 PM UTC 24 |
| Peak memory | 209056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091967506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.4091967506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.4278553535 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 75883491825 ps |
| CPU time | 167.18 seconds |
| Started | Sep 18 06:15:04 PM UTC 24 |
| Finished | Sep 18 06:17:53 PM UTC 24 |
| Peak memory | 209544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278553535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.4278553535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_fifo_reset.831072784 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 40952564336 ps |
| CPU time | 23.43 seconds |
| Started | Sep 18 06:19:28 PM UTC 24 |
| Finished | Sep 18 06:19:53 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831072784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.831072784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.3466606944 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 220585034 ps |
| CPU time | 1.94 seconds |
| Started | Sep 18 06:55:08 PM UTC 24 |
| Finished | Sep 18 06:55:11 PM UTC 24 |
| Peak memory | 201780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466606944 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3466606944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.926607408 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 293173836438 ps |
| CPU time | 102.37 seconds |
| Started | Sep 18 06:14:37 PM UTC 24 |
| Finished | Sep 18 06:16:22 PM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926607408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.926607408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_stress_all.1529261129 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 63424161294 ps |
| CPU time | 229.57 seconds |
| Started | Sep 18 06:14:48 PM UTC 24 |
| Finished | Sep 18 06:18:41 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529261129 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1529261129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_stress_all.536166162 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 261596851878 ps |
| CPU time | 277.28 seconds |
| Started | Sep 18 06:20:22 PM UTC 24 |
| Finished | Sep 18 06:25:04 PM UTC 24 |
| Peak memory | 206024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536166162 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.536166162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_alert_test.2907270591 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 12603187 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:14:52 PM UTC 24 |
| Finished | Sep 18 06:14:54 PM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907270591 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2907270591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_fifo_reset.1810905461 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 123576517387 ps |
| CPU time | 99.63 seconds |
| Started | Sep 18 06:20:27 PM UTC 24 |
| Finished | Sep 18 06:22:08 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810905461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1810905461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.3535623767 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 245182593736 ps |
| CPU time | 134.2 seconds |
| Started | Sep 18 06:14:26 PM UTC 24 |
| Finished | Sep 18 06:16:42 PM UTC 24 |
| Peak memory | 203912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535623767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3535623767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_stress_all.425216729 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 611877188314 ps |
| CPU time | 506.61 seconds |
| Started | Sep 18 06:19:44 PM UTC 24 |
| Finished | Sep 18 06:28:18 PM UTC 24 |
| Peak memory | 208952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425216729 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.425216729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_stress_all.312083275 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 100345231750 ps |
| CPU time | 244.57 seconds |
| Started | Sep 18 06:17:42 PM UTC 24 |
| Finished | Sep 18 06:21:50 PM UTC 24 |
| Peak memory | 205832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312083275 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.312083275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_fifo_full.2399543414 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 91914887938 ps |
| CPU time | 78.75 seconds |
| Started | Sep 18 06:25:17 PM UTC 24 |
| Finished | Sep 18 06:26:38 PM UTC 24 |
| Peak memory | 209520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399543414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2399543414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.4213548695 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 31316690114 ps |
| CPU time | 31.11 seconds |
| Started | Sep 18 06:17:04 PM UTC 24 |
| Finished | Sep 18 06:17:37 PM UTC 24 |
| Peak memory | 220996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4213548695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_ with_rand_reset.4213548695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_fifo_reset.711340190 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 21711270156 ps |
| CPU time | 54.04 seconds |
| Started | Sep 18 06:15:04 PM UTC 24 |
| Finished | Sep 18 06:15:59 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711340190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.711340190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.4224213963 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 82779592902 ps |
| CPU time | 184.35 seconds |
| Started | Sep 18 06:19:36 PM UTC 24 |
| Finished | Sep 18 06:22:43 PM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224213963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4224213963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.4195361692 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 31021060 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 06:55:06 PM UTC 24 |
| Finished | Sep 18 06:55:09 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195361692 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.4195361692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_stress_all.275105262 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 291592422706 ps |
| CPU time | 690.37 seconds |
| Started | Sep 18 06:20:41 PM UTC 24 |
| Finished | Sep 18 06:32:18 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275105262 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.275105262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.1037519793 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 143071085368 ps |
| CPU time | 98.37 seconds |
| Started | Sep 18 06:22:51 PM UTC 24 |
| Finished | Sep 18 06:24:32 PM UTC 24 |
| Peak memory | 209352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037519793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1037519793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.2726822169 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 40662260360 ps |
| CPU time | 51.83 seconds |
| Started | Sep 18 06:16:15 PM UTC 24 |
| Finished | Sep 18 06:17:08 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726822169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2726822169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.3256827812 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 19541615917 ps |
| CPU time | 43.91 seconds |
| Started | Sep 18 06:20:22 PM UTC 24 |
| Finished | Sep 18 06:21:08 PM UTC 24 |
| Peak memory | 220604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3256827812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all _with_rand_reset.3256827812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_fifo_full.3621388392 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 92168861937 ps |
| CPU time | 27.1 seconds |
| Started | Sep 18 06:22:07 PM UTC 24 |
| Finished | Sep 18 06:22:35 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621388392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3621388392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_fifo_reset.1037275865 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 51068786678 ps |
| CPU time | 85.01 seconds |
| Started | Sep 18 06:23:55 PM UTC 24 |
| Finished | Sep 18 06:25:21 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037275865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1037275865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.2091334748 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10809286338 ps |
| CPU time | 39.57 seconds |
| Started | Sep 18 06:16:47 PM UTC 24 |
| Finished | Sep 18 06:17:28 PM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2091334748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_ with_rand_reset.2091334748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.453395409 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 132345766843 ps |
| CPU time | 122.84 seconds |
| Started | Sep 18 06:19:13 PM UTC 24 |
| Finished | Sep 18 06:21:18 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453395409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.453395409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.1997400505 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 95795822250 ps |
| CPU time | 216.99 seconds |
| Started | Sep 18 06:19:28 PM UTC 24 |
| Finished | Sep 18 06:23:09 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997400505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1997400505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_noise_filter.2887908352 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 313835041583 ps |
| CPU time | 78.49 seconds |
| Started | Sep 18 06:16:51 PM UTC 24 |
| Finished | Sep 18 06:18:12 PM UTC 24 |
| Peak memory | 218444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887908352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2887908352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.1442200251 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 754766531 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 06:55:36 PM UTC 24 |
| Finished | Sep 18 06:55:38 PM UTC 24 |
| Peak memory | 201720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442200251 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1442200251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.2226333148 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 53847503199 ps |
| CPU time | 96.56 seconds |
| Started | Sep 18 06:23:16 PM UTC 24 |
| Finished | Sep 18 06:24:55 PM UTC 24 |
| Peak memory | 209112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226333148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2226333148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/278.uart_fifo_reset.3693446514 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 92280712704 ps |
| CPU time | 162.78 seconds |
| Started | Sep 18 06:54:18 PM UTC 24 |
| Finished | Sep 18 06:57:03 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693446514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3693446514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/278.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.2485585939 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 24177582247 ps |
| CPU time | 112.04 seconds |
| Started | Sep 18 06:17:41 PM UTC 24 |
| Finished | Sep 18 06:19:35 PM UTC 24 |
| Peak memory | 220680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2485585939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_ with_rand_reset.2485585939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.1869255297 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 65491963636 ps |
| CPU time | 76.8 seconds |
| Started | Sep 18 06:19:02 PM UTC 24 |
| Finished | Sep 18 06:20:21 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869255297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1869255297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/151.uart_fifo_reset.3426124228 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 28825353562 ps |
| CPU time | 74.61 seconds |
| Started | Sep 18 06:49:43 PM UTC 24 |
| Finished | Sep 18 06:51:00 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426124228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3426124228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/151.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/238.uart_fifo_reset.2661555284 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 24549503339 ps |
| CPU time | 45.11 seconds |
| Started | Sep 18 06:53:01 PM UTC 24 |
| Finished | Sep 18 06:53:48 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661555284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2661555284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/238.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_stress_all.4293059917 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 399549834556 ps |
| CPU time | 549.25 seconds |
| Started | Sep 18 06:26:21 PM UTC 24 |
| Finished | Sep 18 06:35:37 PM UTC 24 |
| Peak memory | 208240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293059917 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.4293059917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/252.uart_fifo_reset.1636413246 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 22465917642 ps |
| CPU time | 43.37 seconds |
| Started | Sep 18 06:53:30 PM UTC 24 |
| Finished | Sep 18 06:54:15 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636413246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1636413246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/252.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_fifo_reset.151036674 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 192296156272 ps |
| CPU time | 184.79 seconds |
| Started | Sep 18 06:28:35 PM UTC 24 |
| Finished | Sep 18 06:31:43 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151036674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.151036674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/275.uart_fifo_reset.3846428539 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 59910985375 ps |
| CPU time | 96.36 seconds |
| Started | Sep 18 06:54:09 PM UTC 24 |
| Finished | Sep 18 06:55:47 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846428539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3846428539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/275.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/113.uart_fifo_reset.1035797252 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 94989106008 ps |
| CPU time | 297.16 seconds |
| Started | Sep 18 06:48:20 PM UTC 24 |
| Finished | Sep 18 06:53:21 PM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035797252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1035797252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/113.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_fifo_full.3172321467 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 28579672552 ps |
| CPU time | 67.29 seconds |
| Started | Sep 18 06:21:25 PM UTC 24 |
| Finished | Sep 18 06:22:34 PM UTC 24 |
| Peak memory | 209596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172321467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3172321467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/161.uart_fifo_reset.2535305860 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 20121954588 ps |
| CPU time | 46.92 seconds |
| Started | Sep 18 06:49:58 PM UTC 24 |
| Finished | Sep 18 06:50:47 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535305860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2535305860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/161.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.3282378403 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 106284020890 ps |
| CPU time | 44.45 seconds |
| Started | Sep 18 06:23:32 PM UTC 24 |
| Finished | Sep 18 06:24:18 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282378403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3282378403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.2764326574 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 91121174442 ps |
| CPU time | 188.02 seconds |
| Started | Sep 18 06:32:40 PM UTC 24 |
| Finished | Sep 18 06:35:50 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764326574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2764326574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_tx_rx.1821398399 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 66465911001 ps |
| CPU time | 105.58 seconds |
| Started | Sep 18 06:17:28 PM UTC 24 |
| Finished | Sep 18 06:19:15 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821398399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1821398399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/154.uart_fifo_reset.2652572178 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 41116965445 ps |
| CPU time | 27.65 seconds |
| Started | Sep 18 06:49:48 PM UTC 24 |
| Finished | Sep 18 06:50:17 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652572178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2652572178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/154.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/155.uart_fifo_reset.91910982 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 27589332773 ps |
| CPU time | 51.51 seconds |
| Started | Sep 18 06:49:50 PM UTC 24 |
| Finished | Sep 18 06:50:43 PM UTC 24 |
| Peak memory | 209352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91910982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.91910982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/155.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/179.uart_fifo_reset.526076917 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 99502543477 ps |
| CPU time | 405.26 seconds |
| Started | Sep 18 06:50:34 PM UTC 24 |
| Finished | Sep 18 06:57:25 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526076917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.526076917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/179.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/180.uart_fifo_reset.2352553172 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 107366232944 ps |
| CPU time | 68.27 seconds |
| Started | Sep 18 06:50:38 PM UTC 24 |
| Finished | Sep 18 06:51:48 PM UTC 24 |
| Peak memory | 204096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352553172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2352553172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/180.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/181.uart_fifo_reset.219887681 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 22007655611 ps |
| CPU time | 51.75 seconds |
| Started | Sep 18 06:50:40 PM UTC 24 |
| Finished | Sep 18 06:51:33 PM UTC 24 |
| Peak memory | 209396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219887681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.219887681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/181.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/260.uart_fifo_reset.4093114923 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 45093962850 ps |
| CPU time | 35.55 seconds |
| Started | Sep 18 06:53:45 PM UTC 24 |
| Finished | Sep 18 06:54:22 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093114923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.4093114923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/260.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/60.uart_fifo_reset.4065607823 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 31486546657 ps |
| CPU time | 30.73 seconds |
| Started | Sep 18 06:44:53 PM UTC 24 |
| Finished | Sep 18 06:45:26 PM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065607823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.4065607823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/60.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/103.uart_fifo_reset.3688690739 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 39879414526 ps |
| CPU time | 32.86 seconds |
| Started | Sep 18 06:47:59 PM UTC 24 |
| Finished | Sep 18 06:48:34 PM UTC 24 |
| Peak memory | 203908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688690739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3688690739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/103.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/124.uart_fifo_reset.1453058982 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 91667914174 ps |
| CPU time | 58.76 seconds |
| Started | Sep 18 06:48:47 PM UTC 24 |
| Finished | Sep 18 06:49:47 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453058982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1453058982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/124.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_fifo_full.3597725495 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 238709501714 ps |
| CPU time | 509.19 seconds |
| Started | Sep 18 06:20:46 PM UTC 24 |
| Finished | Sep 18 06:29:21 PM UTC 24 |
| Peak memory | 206152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597725495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3597725495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_fifo_reset.1102818897 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 147216355634 ps |
| CPU time | 258.37 seconds |
| Started | Sep 18 06:20:53 PM UTC 24 |
| Finished | Sep 18 06:25:15 PM UTC 24 |
| Peak memory | 203716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102818897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1102818897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_intr.1952829797 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 61673185927 ps |
| CPU time | 40.37 seconds |
| Started | Sep 18 06:21:02 PM UTC 24 |
| Finished | Sep 18 06:21:44 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952829797 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1952829797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.2513513302 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 138908856647 ps |
| CPU time | 134.08 seconds |
| Started | Sep 18 06:22:39 PM UTC 24 |
| Finished | Sep 18 06:24:55 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513513302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2513513302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/172.uart_fifo_reset.2734283368 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 26556080405 ps |
| CPU time | 28.73 seconds |
| Started | Sep 18 06:50:24 PM UTC 24 |
| Finished | Sep 18 06:50:54 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734283368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2734283368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/172.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/175.uart_fifo_reset.2272786463 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 87447478448 ps |
| CPU time | 45.4 seconds |
| Started | Sep 18 06:50:30 PM UTC 24 |
| Finished | Sep 18 06:51:17 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272786463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2272786463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/175.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_fifo_reset.1327125412 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 281766108631 ps |
| CPU time | 88.49 seconds |
| Started | Sep 18 06:23:17 PM UTC 24 |
| Finished | Sep 18 06:24:48 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327125412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1327125412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_noise_filter.2408201371 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 64434283993 ps |
| CPU time | 155.06 seconds |
| Started | Sep 18 06:24:05 PM UTC 24 |
| Finished | Sep 18 06:26:42 PM UTC 24 |
| Peak memory | 220636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408201371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2408201371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/193.uart_fifo_reset.1102988329 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 54683903571 ps |
| CPU time | 44.44 seconds |
| Started | Sep 18 06:50:58 PM UTC 24 |
| Finished | Sep 18 06:51:44 PM UTC 24 |
| Peak memory | 209180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102988329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1102988329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/193.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/195.uart_fifo_reset.3920098602 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 75827366248 ps |
| CPU time | 179.1 seconds |
| Started | Sep 18 06:51:00 PM UTC 24 |
| Finished | Sep 18 06:54:01 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920098602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3920098602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/195.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/197.uart_fifo_reset.3000153699 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 55586749358 ps |
| CPU time | 60.01 seconds |
| Started | Sep 18 06:51:02 PM UTC 24 |
| Finished | Sep 18 06:52:03 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000153699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3000153699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/197.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_fifo_reset.2903338697 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 16970479173 ps |
| CPU time | 48.85 seconds |
| Started | Sep 18 06:15:41 PM UTC 24 |
| Finished | Sep 18 06:16:32 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903338697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2903338697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/201.uart_fifo_reset.3604726319 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 62147691189 ps |
| CPU time | 41.92 seconds |
| Started | Sep 18 06:51:07 PM UTC 24 |
| Finished | Sep 18 06:51:50 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604726319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3604726319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/201.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/210.uart_fifo_reset.1065095521 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 155437535262 ps |
| CPU time | 97.26 seconds |
| Started | Sep 18 06:51:39 PM UTC 24 |
| Finished | Sep 18 06:53:18 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065095521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1065095521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/210.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/223.uart_fifo_reset.2895372047 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 62376085450 ps |
| CPU time | 41.04 seconds |
| Started | Sep 18 06:52:04 PM UTC 24 |
| Finished | Sep 18 06:52:46 PM UTC 24 |
| Peak memory | 209156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895372047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2895372047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/223.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/242.uart_fifo_reset.1805629210 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 28146870519 ps |
| CPU time | 32.98 seconds |
| Started | Sep 18 06:53:20 PM UTC 24 |
| Finished | Sep 18 06:53:54 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805629210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1805629210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/242.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_fifo_reset.1197355786 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 134346742099 ps |
| CPU time | 274.99 seconds |
| Started | Sep 18 06:29:19 PM UTC 24 |
| Finished | Sep 18 06:33:58 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197355786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1197355786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/66.uart_fifo_reset.171586694 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 272719221551 ps |
| CPU time | 57.78 seconds |
| Started | Sep 18 06:45:25 PM UTC 24 |
| Finished | Sep 18 06:46:24 PM UTC 24 |
| Peak memory | 209468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171586694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.171586694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/66.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/98.uart_fifo_reset.2375457831 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 36618342021 ps |
| CPU time | 104.56 seconds |
| Started | Sep 18 06:47:51 PM UTC 24 |
| Finished | Sep 18 06:49:38 PM UTC 24 |
| Peak memory | 203712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375457831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2375457831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/98.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.2155189681 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 138805748 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 06:55:05 PM UTC 24 |
| Finished | Sep 18 06:55:07 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155189681 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2155189681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.706228864 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 220201258 ps |
| CPU time | 2.74 seconds |
| Started | Sep 18 06:55:04 PM UTC 24 |
| Finished | Sep 18 06:55:08 PM UTC 24 |
| Peak memory | 202640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706228864 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.706228864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1334002764 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 18890622 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:55:06 PM UTC 24 |
| Finished | Sep 18 06:55:08 PM UTC 24 |
| Peak memory | 201708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1334002764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_r eset.1334002764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.1131812967 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 49841373 ps |
| CPU time | 0.92 seconds |
| Started | Sep 18 06:55:04 PM UTC 24 |
| Finished | Sep 18 06:55:06 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131812967 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1131812967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.2420017495 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 108311864 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 06:55:01 PM UTC 24 |
| Finished | Sep 18 06:55:03 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420017495 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2420017495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.944891375 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 120132052 ps |
| CPU time | 2.99 seconds |
| Started | Sep 18 06:54:57 PM UTC 24 |
| Finished | Sep 18 06:55:02 PM UTC 24 |
| Peak memory | 204744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944891375 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.944891375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.129741515 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 79674192 ps |
| CPU time | 1.95 seconds |
| Started | Sep 18 06:55:00 PM UTC 24 |
| Finished | Sep 18 06:55:03 PM UTC 24 |
| Peak memory | 201780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129741515 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.129741515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.1239203589 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 15029602 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 06:55:10 PM UTC 24 |
| Finished | Sep 18 06:55:13 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239203589 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1239203589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3840646482 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 867317444 ps |
| CPU time | 3.66 seconds |
| Started | Sep 18 06:55:10 PM UTC 24 |
| Finished | Sep 18 06:55:15 PM UTC 24 |
| Peak memory | 202704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840646482 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3840646482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3938116979 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 11944510 ps |
| CPU time | 0.89 seconds |
| Started | Sep 18 06:55:09 PM UTC 24 |
| Finished | Sep 18 06:55:11 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938116979 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3938116979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.4053352242 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 99620568 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 06:55:12 PM UTC 24 |
| Finished | Sep 18 06:55:15 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4053352242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_r eset.4053352242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.1447122208 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 42826351 ps |
| CPU time | 0.78 seconds |
| Started | Sep 18 06:55:09 PM UTC 24 |
| Finished | Sep 18 06:55:11 PM UTC 24 |
| Peak memory | 201608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447122208 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1447122208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.3352387910 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 22077381 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 06:55:09 PM UTC 24 |
| Finished | Sep 18 06:55:11 PM UTC 24 |
| Peak memory | 201588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352387910 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3352387910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.1584722525 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 15480220 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 06:55:12 PM UTC 24 |
| Finished | Sep 18 06:55:14 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584722525 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.1584722525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.925658699 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 91705857 ps |
| CPU time | 2.33 seconds |
| Started | Sep 18 06:55:08 PM UTC 24 |
| Finished | Sep 18 06:55:11 PM UTC 24 |
| Peak memory | 202612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925658699 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.925658699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.270426857 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 74770556 ps |
| CPU time | 0.77 seconds |
| Started | Sep 18 06:55:30 PM UTC 24 |
| Finished | Sep 18 06:55:32 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=270426857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_r eset.270426857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.4238575788 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 76836510 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 06:55:30 PM UTC 24 |
| Finished | Sep 18 06:55:32 PM UTC 24 |
| Peak memory | 201640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238575788 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.4238575788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.3329512845 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 37402222 ps |
| CPU time | 0.7 seconds |
| Started | Sep 18 06:55:30 PM UTC 24 |
| Finished | Sep 18 06:55:32 PM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329512845 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3329512845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.2506549999 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 26753910 ps |
| CPU time | 0.92 seconds |
| Started | Sep 18 06:55:30 PM UTC 24 |
| Finished | Sep 18 06:55:33 PM UTC 24 |
| Peak memory | 201656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506549999 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.2506549999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1028771804 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 510732137 ps |
| CPU time | 1.85 seconds |
| Started | Sep 18 06:55:30 PM UTC 24 |
| Finished | Sep 18 06:55:33 PM UTC 24 |
| Peak memory | 201716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028771804 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1028771804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.3420922616 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 47115318 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 06:55:30 PM UTC 24 |
| Finished | Sep 18 06:55:33 PM UTC 24 |
| Peak memory | 201632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420922616 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3420922616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3914923066 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 50419577 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 06:55:32 PM UTC 24 |
| Finished | Sep 18 06:55:35 PM UTC 24 |
| Peak memory | 203448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3914923066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_ reset.3914923066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.874250524 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 22523341 ps |
| CPU time | 0.74 seconds |
| Started | Sep 18 06:55:31 PM UTC 24 |
| Finished | Sep 18 06:55:33 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874250524 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.874250524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.2960425732 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 25146358 ps |
| CPU time | 0.55 seconds |
| Started | Sep 18 06:55:31 PM UTC 24 |
| Finished | Sep 18 06:55:32 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960425732 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2960425732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.3875406728 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 147226227 ps |
| CPU time | 0.92 seconds |
| Started | Sep 18 06:55:32 PM UTC 24 |
| Finished | Sep 18 06:55:34 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875406728 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.3875406728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2730556086 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 42447851 ps |
| CPU time | 1.49 seconds |
| Started | Sep 18 06:55:30 PM UTC 24 |
| Finished | Sep 18 06:55:33 PM UTC 24 |
| Peak memory | 201716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730556086 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2730556086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.3446110571 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 49941110 ps |
| CPU time | 1.02 seconds |
| Started | Sep 18 06:55:31 PM UTC 24 |
| Finished | Sep 18 06:55:33 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446110571 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3446110571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.337017116 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 37339176 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 06:55:33 PM UTC 24 |
| Finished | Sep 18 06:55:35 PM UTC 24 |
| Peak memory | 200896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=337017116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_r eset.337017116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.2660537555 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 12377988 ps |
| CPU time | 0.79 seconds |
| Started | Sep 18 06:55:33 PM UTC 24 |
| Finished | Sep 18 06:55:35 PM UTC 24 |
| Peak memory | 201680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660537555 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2660537555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.2872817490 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 12118983 ps |
| CPU time | 0.68 seconds |
| Started | Sep 18 06:55:32 PM UTC 24 |
| Finished | Sep 18 06:55:34 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872817490 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2872817490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.865777039 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 85658698 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 06:55:33 PM UTC 24 |
| Finished | Sep 18 06:55:35 PM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865777039 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.865777039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.540498374 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 76714680 ps |
| CPU time | 2.69 seconds |
| Started | Sep 18 06:55:32 PM UTC 24 |
| Finished | Sep 18 06:55:36 PM UTC 24 |
| Peak memory | 202484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540498374 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.540498374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.2355073675 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 303719857 ps |
| CPU time | 1.48 seconds |
| Started | Sep 18 06:55:32 PM UTC 24 |
| Finished | Sep 18 06:55:35 PM UTC 24 |
| Peak memory | 201024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355073675 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2355073675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3055417899 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 147854368 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 06:55:35 PM UTC 24 |
| Finished | Sep 18 06:55:37 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3055417899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_ reset.3055417899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.3554364377 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 40851474 ps |
| CPU time | 0.71 seconds |
| Started | Sep 18 06:55:35 PM UTC 24 |
| Finished | Sep 18 06:55:37 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554364377 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3554364377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.2270699000 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 52989848 ps |
| CPU time | 0.62 seconds |
| Started | Sep 18 06:55:35 PM UTC 24 |
| Finished | Sep 18 06:55:37 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270699000 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2270699000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.1731534073 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 21139548 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:55:35 PM UTC 24 |
| Finished | Sep 18 06:55:37 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731534073 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.1731534073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1307203992 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 155088105 ps |
| CPU time | 1.75 seconds |
| Started | Sep 18 06:55:33 PM UTC 24 |
| Finished | Sep 18 06:55:36 PM UTC 24 |
| Peak memory | 201708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307203992 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1307203992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.2159578420 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 39443148 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 06:55:35 PM UTC 24 |
| Finished | Sep 18 06:55:38 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159578420 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2159578420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2042898893 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 59896455 ps |
| CPU time | 0.78 seconds |
| Started | Sep 18 06:55:36 PM UTC 24 |
| Finished | Sep 18 06:55:38 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2042898893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_ reset.2042898893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.4097227049 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 18995748 ps |
| CPU time | 0.72 seconds |
| Started | Sep 18 06:55:35 PM UTC 24 |
| Finished | Sep 18 06:55:37 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097227049 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.4097227049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1514490689 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 63014694 ps |
| CPU time | 0.7 seconds |
| Started | Sep 18 06:55:35 PM UTC 24 |
| Finished | Sep 18 06:55:37 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514490689 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1514490689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1983919616 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 60058866 ps |
| CPU time | 0.94 seconds |
| Started | Sep 18 06:55:36 PM UTC 24 |
| Finished | Sep 18 06:55:38 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983919616 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.1983919616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.1140632336 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 170997657 ps |
| CPU time | 2.29 seconds |
| Started | Sep 18 06:55:35 PM UTC 24 |
| Finished | Sep 18 06:55:39 PM UTC 24 |
| Peak memory | 204680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140632336 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1140632336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.2685188836 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 38920548 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 06:55:35 PM UTC 24 |
| Finished | Sep 18 06:55:38 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685188836 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2685188836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3139904455 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 25130039 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 06:55:37 PM UTC 24 |
| Finished | Sep 18 06:55:39 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3139904455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_ reset.3139904455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.3022323457 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 72035957 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 06:55:36 PM UTC 24 |
| Finished | Sep 18 06:55:38 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022323457 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3022323457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.1140469159 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 12123831 ps |
| CPU time | 0.55 seconds |
| Started | Sep 18 06:55:36 PM UTC 24 |
| Finished | Sep 18 06:55:37 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140469159 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1140469159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.1555516217 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 42324687 ps |
| CPU time | 0.77 seconds |
| Started | Sep 18 06:55:36 PM UTC 24 |
| Finished | Sep 18 06:55:38 PM UTC 24 |
| Peak memory | 201640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555516217 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.1555516217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.3825843549 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 40119316 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 06:55:36 PM UTC 24 |
| Finished | Sep 18 06:55:38 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825843549 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3825843549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2386420991 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 84008836 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:43 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2386420991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_ reset.2386420991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.4078545141 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 32453835 ps |
| CPU time | 0.65 seconds |
| Started | Sep 18 06:55:38 PM UTC 24 |
| Finished | Sep 18 06:55:39 PM UTC 24 |
| Peak memory | 201640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078545141 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.4078545141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.2025137877 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 121282572 ps |
| CPU time | 0.65 seconds |
| Started | Sep 18 06:55:37 PM UTC 24 |
| Finished | Sep 18 06:55:39 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025137877 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2025137877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.2465002419 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 29253977 ps |
| CPU time | 0.9 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:43 PM UTC 24 |
| Peak memory | 205792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465002419 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.2465002419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2906349353 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 19618252 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 06:55:37 PM UTC 24 |
| Finished | Sep 18 06:55:40 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906349353 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2906349353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.443626196 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 510218596 ps |
| CPU time | 1.3 seconds |
| Started | Sep 18 06:55:37 PM UTC 24 |
| Finished | Sep 18 06:55:40 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443626196 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.443626196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4175505853 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 70005517 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:43 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4175505853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_ reset.4175505853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2846741054 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 23771346 ps |
| CPU time | 0.77 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:43 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846741054 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2846741054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.796193340 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 20341276 ps |
| CPU time | 0.65 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:43 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796193340 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.796193340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.126441075 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 75670984 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:43 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126441075 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.126441075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.2712797734 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 105101201 ps |
| CPU time | 1.73 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:44 PM UTC 24 |
| Peak memory | 201716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712797734 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2712797734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3647956212 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 50922015 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:43 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647956212 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3647956212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3076008544 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 62049367 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:44 PM UTC 24 |
| Peak memory | 201764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3076008544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_ reset.3076008544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.3766089 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 16773833 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:43 PM UTC 24 |
| Peak memory | 201632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766089 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3766089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.112415363 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 92055153 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:43 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112415363 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.112415363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.3249756741 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 74060594 ps |
| CPU time | 0.94 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:43 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249756741 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.3249756741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.1053487078 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 244769649 ps |
| CPU time | 2.09 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:44 PM UTC 24 |
| Peak memory | 202560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053487078 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1053487078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.1974143638 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 157432326 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:43 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974143638 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1974143638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2822975620 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 24469434 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:44 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2822975620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_ reset.2822975620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.741107630 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 13358603 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:43 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741107630 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.741107630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.2769576 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 42749740 ps |
| CPU time | 0.75 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:43 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769576 -assert nopostproc +UVM_TESTNAME=uart_base_tes t +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2769576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2659357423 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 56280041 ps |
| CPU time | 0.88 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:44 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659357423 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.2659357423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.1103380823 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 473004766 ps |
| CPU time | 1.92 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:44 PM UTC 24 |
| Peak memory | 203756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103380823 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1103380823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.454243175 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 74725516 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 06:55:41 PM UTC 24 |
| Finished | Sep 18 06:55:44 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454243175 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.454243175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.1629022302 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 75932117 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 06:55:15 PM UTC 24 |
| Finished | Sep 18 06:55:17 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629022302 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1629022302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.73997356 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 344573566 ps |
| CPU time | 2.25 seconds |
| Started | Sep 18 06:55:15 PM UTC 24 |
| Finished | Sep 18 06:55:18 PM UTC 24 |
| Peak memory | 202516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73997356 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.73997356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.297495937 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 29878844 ps |
| CPU time | 0.92 seconds |
| Started | Sep 18 06:55:12 PM UTC 24 |
| Finished | Sep 18 06:55:15 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297495937 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.297495937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.833078066 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 43116660 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 06:55:15 PM UTC 24 |
| Finished | Sep 18 06:55:18 PM UTC 24 |
| Peak memory | 203756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=833078066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_re set.833078066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3659815008 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 13767356 ps |
| CPU time | 0.93 seconds |
| Started | Sep 18 06:55:14 PM UTC 24 |
| Finished | Sep 18 06:55:16 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659815008 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3659815008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.1037596472 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 15688602 ps |
| CPU time | 0.89 seconds |
| Started | Sep 18 06:55:12 PM UTC 24 |
| Finished | Sep 18 06:55:15 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037596472 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1037596472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.4079340818 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 14924260 ps |
| CPU time | 0.89 seconds |
| Started | Sep 18 06:55:15 PM UTC 24 |
| Finished | Sep 18 06:55:17 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079340818 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.4079340818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.4053370858 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 82666021 ps |
| CPU time | 1.55 seconds |
| Started | Sep 18 06:55:12 PM UTC 24 |
| Finished | Sep 18 06:55:15 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053370858 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4053370858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.3369840301 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 146034414 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 06:55:12 PM UTC 24 |
| Finished | Sep 18 06:55:15 PM UTC 24 |
| Peak memory | 201828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369840301 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3369840301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.1921638175 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 58823055 ps |
| CPU time | 0.66 seconds |
| Started | Sep 18 06:55:43 PM UTC 24 |
| Finished | Sep 18 06:55:44 PM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921638175 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1921638175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.3394127146 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 56902374 ps |
| CPU time | 0.66 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394127146 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3394127146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.805701754 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 26464238 ps |
| CPU time | 0.54 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805701754 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.805701754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1420102681 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 22830444 ps |
| CPU time | 0.76 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420102681 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1420102681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3829564019 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 25990206 ps |
| CPU time | 0.64 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829564019 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3829564019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.3053099474 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 34296770 ps |
| CPU time | 0.68 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053099474 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3053099474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.2938107583 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 52882588 ps |
| CPU time | 0.65 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938107583 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2938107583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.899795203 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 15272626 ps |
| CPU time | 0.68 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899795203 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.899795203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.2227639489 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 144111894 ps |
| CPU time | 0.6 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227639489 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2227639489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.1639296344 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 13368443 ps |
| CPU time | 0.68 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639296344 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1639296344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.227831410 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 55032561 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 06:55:17 PM UTC 24 |
| Finished | Sep 18 06:55:19 PM UTC 24 |
| Peak memory | 201640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227831410 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.227831410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.1130558104 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 260782440 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 06:55:17 PM UTC 24 |
| Finished | Sep 18 06:55:21 PM UTC 24 |
| Peak memory | 202716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130558104 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1130558104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.2140042695 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 22686623 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:55:16 PM UTC 24 |
| Finished | Sep 18 06:55:19 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140042695 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2140042695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.554613617 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 34842427 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 06:55:18 PM UTC 24 |
| Finished | Sep 18 06:55:20 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=554613617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_re set.554613617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.1986964591 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 35050075 ps |
| CPU time | 0.88 seconds |
| Started | Sep 18 06:55:16 PM UTC 24 |
| Finished | Sep 18 06:55:19 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986964591 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1986964591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.3286789226 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 23220959 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:55:16 PM UTC 24 |
| Finished | Sep 18 06:55:19 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286789226 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3286789226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.1545268563 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 14403400 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 06:55:17 PM UTC 24 |
| Finished | Sep 18 06:55:19 PM UTC 24 |
| Peak memory | 201640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545268563 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.1545268563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.4234494672 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 363055626 ps |
| CPU time | 3.3 seconds |
| Started | Sep 18 06:55:16 PM UTC 24 |
| Finished | Sep 18 06:55:21 PM UTC 24 |
| Peak memory | 204680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234494672 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.4234494672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.3300109976 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 93274287 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 06:55:16 PM UTC 24 |
| Finished | Sep 18 06:55:19 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300109976 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3300109976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.547803219 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 43492840 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547803219 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.547803219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.2470577797 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 12444085 ps |
| CPU time | 0.62 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470577797 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2470577797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.4072981405 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 17554386 ps |
| CPU time | 0.74 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072981405 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4072981405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.1240552857 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 14571548 ps |
| CPU time | 0.64 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240552857 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1240552857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3228378849 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 13544510 ps |
| CPU time | 0.72 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228378849 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3228378849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.2743354390 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 38755005 ps |
| CPU time | 0.62 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743354390 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2743354390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.827842523 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 235466344 ps |
| CPU time | 0.75 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827842523 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.827842523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.3793070790 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 44516366 ps |
| CPU time | 0.6 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793070790 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3793070790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.2215823488 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 12340488 ps |
| CPU time | 0.63 seconds |
| Started | Sep 18 06:55:47 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215823488 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2215823488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.2193680873 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 13663658 ps |
| CPU time | 0.73 seconds |
| Started | Sep 18 06:55:48 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193680873 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2193680873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.2107238679 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 32844645 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 06:55:20 PM UTC 24 |
| Finished | Sep 18 06:55:22 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107238679 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2107238679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.2068258584 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 252352762 ps |
| CPU time | 3.26 seconds |
| Started | Sep 18 06:55:19 PM UTC 24 |
| Finished | Sep 18 06:55:24 PM UTC 24 |
| Peak memory | 202576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068258584 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2068258584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.3458296773 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 12817815 ps |
| CPU time | 0.92 seconds |
| Started | Sep 18 06:55:19 PM UTC 24 |
| Finished | Sep 18 06:55:21 PM UTC 24 |
| Peak memory | 201592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458296773 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3458296773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3934117887 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 71254288 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 06:55:21 PM UTC 24 |
| Finished | Sep 18 06:55:23 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3934117887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_r eset.3934117887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.1882747329 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 38257694 ps |
| CPU time | 0.77 seconds |
| Started | Sep 18 06:55:19 PM UTC 24 |
| Finished | Sep 18 06:55:21 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882747329 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1882747329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.4023212868 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 39757797 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 06:55:19 PM UTC 24 |
| Finished | Sep 18 06:55:21 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023212868 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4023212868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2871754979 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 91226976 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 06:55:20 PM UTC 24 |
| Finished | Sep 18 06:55:22 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871754979 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.2871754979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.3812871101 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 147526563 ps |
| CPU time | 1.95 seconds |
| Started | Sep 18 06:55:18 PM UTC 24 |
| Finished | Sep 18 06:55:21 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812871101 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3812871101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.1729707487 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 327317887 ps |
| CPU time | 1.32 seconds |
| Started | Sep 18 06:55:18 PM UTC 24 |
| Finished | Sep 18 06:55:20 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729707487 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1729707487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.3869713856 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 12073437 ps |
| CPU time | 0.64 seconds |
| Started | Sep 18 06:55:48 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869713856 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3869713856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3096325158 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 75652557 ps |
| CPU time | 0.62 seconds |
| Started | Sep 18 06:55:48 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096325158 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3096325158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.937114735 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 12903292 ps |
| CPU time | 0.63 seconds |
| Started | Sep 18 06:55:48 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937114735 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.937114735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.1610363697 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 24445165 ps |
| CPU time | 0.52 seconds |
| Started | Sep 18 06:55:48 PM UTC 24 |
| Finished | Sep 18 06:55:49 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610363697 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1610363697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1611427288 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 12689352 ps |
| CPU time | 0.6 seconds |
| Started | Sep 18 06:55:54 PM UTC 24 |
| Finished | Sep 18 06:55:56 PM UTC 24 |
| Peak memory | 200760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611427288 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1611427288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.1769168618 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 38826323 ps |
| CPU time | 0.53 seconds |
| Started | Sep 18 06:55:54 PM UTC 24 |
| Finished | Sep 18 06:55:56 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769168618 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1769168618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.2749038841 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 109961940 ps |
| CPU time | 0.66 seconds |
| Started | Sep 18 06:55:54 PM UTC 24 |
| Finished | Sep 18 06:55:56 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749038841 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2749038841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.798830457 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 65162582 ps |
| CPU time | 0.78 seconds |
| Started | Sep 18 06:55:54 PM UTC 24 |
| Finished | Sep 18 06:55:56 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798830457 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.798830457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2636990372 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 45651185 ps |
| CPU time | 0.6 seconds |
| Started | Sep 18 06:55:54 PM UTC 24 |
| Finished | Sep 18 06:55:56 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636990372 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2636990372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.617101702 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 56950339 ps |
| CPU time | 0.63 seconds |
| Started | Sep 18 06:55:54 PM UTC 24 |
| Finished | Sep 18 06:55:56 PM UTC 24 |
| Peak memory | 201632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617101702 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.617101702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.414037045 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 71411724 ps |
| CPU time | 1.46 seconds |
| Started | Sep 18 06:55:23 PM UTC 24 |
| Finished | Sep 18 06:55:25 PM UTC 24 |
| Peak memory | 203760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=414037045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_re set.414037045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.513756224 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 33358619 ps |
| CPU time | 0.77 seconds |
| Started | Sep 18 06:55:23 PM UTC 24 |
| Finished | Sep 18 06:55:24 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513756224 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.513756224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3126935674 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 23272449 ps |
| CPU time | 0.86 seconds |
| Started | Sep 18 06:55:21 PM UTC 24 |
| Finished | Sep 18 06:55:23 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126935674 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3126935674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.720329704 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 99022551 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 06:55:23 PM UTC 24 |
| Finished | Sep 18 06:55:25 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720329704 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.720329704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.1800433228 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 91900532 ps |
| CPU time | 2.12 seconds |
| Started | Sep 18 06:55:21 PM UTC 24 |
| Finished | Sep 18 06:55:24 PM UTC 24 |
| Peak memory | 202760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800433228 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1800433228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.3851340678 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 428167316 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 06:55:21 PM UTC 24 |
| Finished | Sep 18 06:55:23 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851340678 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3851340678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.353469851 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 55918846 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 06:55:24 PM UTC 24 |
| Finished | Sep 18 06:55:26 PM UTC 24 |
| Peak memory | 201712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=353469851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_re set.353469851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.603586977 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 11424202 ps |
| CPU time | 0.88 seconds |
| Started | Sep 18 06:55:23 PM UTC 24 |
| Finished | Sep 18 06:55:25 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603586977 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.603586977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.2624684163 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 52553209 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 06:55:23 PM UTC 24 |
| Finished | Sep 18 06:55:25 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624684163 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2624684163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.890192742 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 27112238 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 06:55:23 PM UTC 24 |
| Finished | Sep 18 06:55:25 PM UTC 24 |
| Peak memory | 203744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890192742 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.890192742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3820713800 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 186012807 ps |
| CPU time | 2.4 seconds |
| Started | Sep 18 06:55:23 PM UTC 24 |
| Finished | Sep 18 06:55:26 PM UTC 24 |
| Peak memory | 202612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820713800 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3820713800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.4085025695 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 88315191 ps |
| CPU time | 1.88 seconds |
| Started | Sep 18 06:55:23 PM UTC 24 |
| Finished | Sep 18 06:55:26 PM UTC 24 |
| Peak memory | 201828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085025695 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.4085025695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.4280011037 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 175983510 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 06:55:26 PM UTC 24 |
| Finished | Sep 18 06:55:29 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4280011037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_r eset.4280011037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.682072763 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 46995505 ps |
| CPU time | 0.89 seconds |
| Started | Sep 18 06:55:26 PM UTC 24 |
| Finished | Sep 18 06:55:28 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682072763 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.682072763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.3928801744 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 12636427 ps |
| CPU time | 0.86 seconds |
| Started | Sep 18 06:55:24 PM UTC 24 |
| Finished | Sep 18 06:55:26 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928801744 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3928801744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.3690078444 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 130472398 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 06:55:26 PM UTC 24 |
| Finished | Sep 18 06:55:28 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690078444 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.3690078444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.1464813167 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 157227994 ps |
| CPU time | 2.54 seconds |
| Started | Sep 18 06:55:24 PM UTC 24 |
| Finished | Sep 18 06:55:28 PM UTC 24 |
| Peak memory | 204604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464813167 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1464813167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.1226480965 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 700049073 ps |
| CPU time | 1.87 seconds |
| Started | Sep 18 06:55:24 PM UTC 24 |
| Finished | Sep 18 06:55:27 PM UTC 24 |
| Peak memory | 201780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226480965 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1226480965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1199629552 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 39317173 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 06:55:27 PM UTC 24 |
| Finished | Sep 18 06:55:29 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1199629552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_r eset.1199629552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.612982282 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 31484067 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:55:26 PM UTC 24 |
| Finished | Sep 18 06:55:28 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612982282 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.612982282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.2069231510 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 15985616 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 06:55:26 PM UTC 24 |
| Finished | Sep 18 06:55:28 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069231510 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2069231510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.2709016306 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 59617890 ps |
| CPU time | 0.96 seconds |
| Started | Sep 18 06:55:27 PM UTC 24 |
| Finished | Sep 18 06:55:28 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709016306 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.2709016306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.3814349874 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 102313905 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 06:55:26 PM UTC 24 |
| Finished | Sep 18 06:55:29 PM UTC 24 |
| Peak memory | 201736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814349874 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3814349874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3453405843 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 97976652 ps |
| CPU time | 1.39 seconds |
| Started | Sep 18 06:55:26 PM UTC 24 |
| Finished | Sep 18 06:55:29 PM UTC 24 |
| Peak memory | 201712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453405843 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3453405843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.527921212 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 76034820 ps |
| CPU time | 1.05 seconds |
| Started | Sep 18 06:55:30 PM UTC 24 |
| Finished | Sep 18 06:55:32 PM UTC 24 |
| Peak memory | 201712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=527921212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_re set.527921212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.1076827222 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 40511820 ps |
| CPU time | 0.76 seconds |
| Started | Sep 18 06:55:28 PM UTC 24 |
| Finished | Sep 18 06:55:30 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076827222 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1076827222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.2710636099 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 41442951 ps |
| CPU time | 0.86 seconds |
| Started | Sep 18 06:55:28 PM UTC 24 |
| Finished | Sep 18 06:55:30 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710636099 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2710636099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.1378484698 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 22374892 ps |
| CPU time | 0.94 seconds |
| Started | Sep 18 06:55:28 PM UTC 24 |
| Finished | Sep 18 06:55:30 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378484698 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.1378484698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.2963053130 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 109997086 ps |
| CPU time | 2.68 seconds |
| Started | Sep 18 06:55:28 PM UTC 24 |
| Finished | Sep 18 06:55:32 PM UTC 24 |
| Peak memory | 204620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963053130 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2963053130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.3119432281 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 87413750 ps |
| CPU time | 1.94 seconds |
| Started | Sep 18 06:55:28 PM UTC 24 |
| Finished | Sep 18 06:55:31 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119432281 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3119432281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_fifo_full.3193761258 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 30312167894 ps |
| CPU time | 77.89 seconds |
| Started | Sep 18 06:14:26 PM UTC 24 |
| Finished | Sep 18 06:15:45 PM UTC 24 |
| Peak memory | 209608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193761258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3193761258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_fifo_reset.1971767054 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 65012689393 ps |
| CPU time | 138.49 seconds |
| Started | Sep 18 06:14:27 PM UTC 24 |
| Finished | Sep 18 06:16:48 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971767054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1971767054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_intr.1193314352 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 44388968322 ps |
| CPU time | 100.01 seconds |
| Started | Sep 18 06:14:28 PM UTC 24 |
| Finished | Sep 18 06:16:10 PM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193314352 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1193314352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_loopback.1443557216 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4438267206 ps |
| CPU time | 18.52 seconds |
| Started | Sep 18 06:14:43 PM UTC 24 |
| Finished | Sep 18 06:15:02 PM UTC 24 |
| Peak memory | 209152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443557216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1443557216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_noise_filter.4006091383 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 27582355532 ps |
| CPU time | 111.32 seconds |
| Started | Sep 18 06:14:28 PM UTC 24 |
| Finished | Sep 18 06:16:22 PM UTC 24 |
| Peak memory | 220600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006091383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.4006091383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_perf.3275445555 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 19208428925 ps |
| CPU time | 1082.52 seconds |
| Started | Sep 18 06:14:46 PM UTC 24 |
| Finished | Sep 18 06:33:01 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275445555 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3275445555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.1996389823 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5264465672 ps |
| CPU time | 9.32 seconds |
| Started | Sep 18 06:14:35 PM UTC 24 |
| Finished | Sep 18 06:14:46 PM UTC 24 |
| Peak memory | 203840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996389823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1996389823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_smoke.4078803229 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 321921702 ps |
| CPU time | 1.92 seconds |
| Started | Sep 18 06:14:22 PM UTC 24 |
| Finished | Sep 18 06:14:26 PM UTC 24 |
| Peak memory | 207172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078803229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.uart_smoke.4078803229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.1592636072 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6801371016 ps |
| CPU time | 75.07 seconds |
| Started | Sep 18 06:14:47 PM UTC 24 |
| Finished | Sep 18 06:16:04 PM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1592636072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_ with_rand_reset.1592636072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.3466479123 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 742858748 ps |
| CPU time | 5.08 seconds |
| Started | Sep 18 06:14:43 PM UTC 24 |
| Finished | Sep 18 06:14:49 PM UTC 24 |
| Peak memory | 203976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466479123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3466479123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/0.uart_tx_rx.3811866797 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 176543418296 ps |
| CPU time | 68.71 seconds |
| Started | Sep 18 06:14:24 PM UTC 24 |
| Finished | Sep 18 06:15:34 PM UTC 24 |
| Peak memory | 203976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811866797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3811866797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/0.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_alert_test.464585873 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 45303572 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 06:15:36 PM UTC 24 |
| Finished | Sep 18 06:15:38 PM UTC 24 |
| Peak memory | 203120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464585873 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.464585873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_fifo_full.1901935640 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 50106840411 ps |
| CPU time | 38.67 seconds |
| Started | Sep 18 06:14:54 PM UTC 24 |
| Finished | Sep 18 06:15:34 PM UTC 24 |
| Peak memory | 209608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901935640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1901935640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.4099372069 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 61004091170 ps |
| CPU time | 532.66 seconds |
| Started | Sep 18 06:15:32 PM UTC 24 |
| Finished | Sep 18 06:24:32 PM UTC 24 |
| Peak memory | 209468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099372069 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.4099372069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_loopback.1754685175 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 316800396 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 06:15:30 PM UTC 24 |
| Finished | Sep 18 06:15:33 PM UTC 24 |
| Peak memory | 207340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754685175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1754685175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_noise_filter.3334247743 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8360563978 ps |
| CPU time | 23.7 seconds |
| Started | Sep 18 06:15:17 PM UTC 24 |
| Finished | Sep 18 06:15:42 PM UTC 24 |
| Peak memory | 209596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334247743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3334247743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_perf.3182962865 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 13132993095 ps |
| CPU time | 189.67 seconds |
| Started | Sep 18 06:15:31 PM UTC 24 |
| Finished | Sep 18 06:18:44 PM UTC 24 |
| Peak memory | 203964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182962865 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3182962865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_rx_oversample.1054078936 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5268367290 ps |
| CPU time | 11.78 seconds |
| Started | Sep 18 06:15:14 PM UTC 24 |
| Finished | Sep 18 06:15:27 PM UTC 24 |
| Peak memory | 207988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054078936 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1054078936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.3299118603 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 31552973522 ps |
| CPU time | 69.86 seconds |
| Started | Sep 18 06:15:24 PM UTC 24 |
| Finished | Sep 18 06:16:36 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299118603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3299118603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.708045855 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5377187509 ps |
| CPU time | 4.66 seconds |
| Started | Sep 18 06:15:24 PM UTC 24 |
| Finished | Sep 18 06:15:30 PM UTC 24 |
| Peak memory | 203588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708045855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.708045855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_sec_cm.2989262381 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 61577032 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 06:15:35 PM UTC 24 |
| Finished | Sep 18 06:15:37 PM UTC 24 |
| Peak memory | 235464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989262381 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2989262381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_smoke.1548691691 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5437883834 ps |
| CPU time | 29.78 seconds |
| Started | Sep 18 06:14:52 PM UTC 24 |
| Finished | Sep 18 06:15:23 PM UTC 24 |
| Peak memory | 208912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548691691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1548691691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.3616663210 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 871123497 ps |
| CPU time | 5.86 seconds |
| Started | Sep 18 06:15:27 PM UTC 24 |
| Finished | Sep 18 06:15:34 PM UTC 24 |
| Peak memory | 208216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616663210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3616663210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/1.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_alert_test.2087885035 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 15406782 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:19:21 PM UTC 24 |
| Finished | Sep 18 06:19:23 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087885035 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2087885035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_fifo_full.4180907611 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 19940167001 ps |
| CPU time | 24.86 seconds |
| Started | Sep 18 06:18:59 PM UTC 24 |
| Finished | Sep 18 06:19:25 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180907611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.4180907611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_fifo_reset.1885752139 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 40553779620 ps |
| CPU time | 46.2 seconds |
| Started | Sep 18 06:19:02 PM UTC 24 |
| Finished | Sep 18 06:19:50 PM UTC 24 |
| Peak memory | 209176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885752139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1885752139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_intr.791935118 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 67066623684 ps |
| CPU time | 224.07 seconds |
| Started | Sep 18 06:19:07 PM UTC 24 |
| Finished | Sep 18 06:22:55 PM UTC 24 |
| Peak memory | 208936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791935118 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.791935118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.4016862869 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 257290474825 ps |
| CPU time | 307.61 seconds |
| Started | Sep 18 06:19:20 PM UTC 24 |
| Finished | Sep 18 06:24:32 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016862869 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.4016862869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_loopback.3666809240 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 7222276638 ps |
| CPU time | 9.98 seconds |
| Started | Sep 18 06:19:17 PM UTC 24 |
| Finished | Sep 18 06:19:28 PM UTC 24 |
| Peak memory | 208316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666809240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3666809240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_noise_filter.2688333868 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 27857707643 ps |
| CPU time | 25.01 seconds |
| Started | Sep 18 06:19:07 PM UTC 24 |
| Finished | Sep 18 06:19:33 PM UTC 24 |
| Peak memory | 209044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688333868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2688333868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_perf.3171937472 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 16341630171 ps |
| CPU time | 410.33 seconds |
| Started | Sep 18 06:19:19 PM UTC 24 |
| Finished | Sep 18 06:26:14 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171937472 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3171937472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_rx_oversample.182184201 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 5693706845 ps |
| CPU time | 7.94 seconds |
| Started | Sep 18 06:19:04 PM UTC 24 |
| Finished | Sep 18 06:19:13 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182184201 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.182184201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.2815635247 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 37010479913 ps |
| CPU time | 9.39 seconds |
| Started | Sep 18 06:19:08 PM UTC 24 |
| Finished | Sep 18 06:19:19 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815635247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2815635247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_smoke.2390187329 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 273459677 ps |
| CPU time | 1.66 seconds |
| Started | Sep 18 06:18:55 PM UTC 24 |
| Finished | Sep 18 06:18:57 PM UTC 24 |
| Peak memory | 203268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390187329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2390187329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_stress_all.383767872 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 178026712134 ps |
| CPU time | 303.43 seconds |
| Started | Sep 18 06:19:20 PM UTC 24 |
| Finished | Sep 18 06:24:28 PM UTC 24 |
| Peak memory | 205832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383767872 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.383767872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.1169037730 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 12725269419 ps |
| CPU time | 51.75 seconds |
| Started | Sep 18 06:19:20 PM UTC 24 |
| Finished | Sep 18 06:20:13 PM UTC 24 |
| Peak memory | 226488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1169037730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all _with_rand_reset.1169037730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.2391086896 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1500532938 ps |
| CPU time | 3.04 seconds |
| Started | Sep 18 06:19:15 PM UTC 24 |
| Finished | Sep 18 06:19:18 PM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391086896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2391086896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/10.uart_tx_rx.2009581643 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 66482637166 ps |
| CPU time | 42.37 seconds |
| Started | Sep 18 06:18:58 PM UTC 24 |
| Finished | Sep 18 06:19:42 PM UTC 24 |
| Peak memory | 204044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009581643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2009581643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/10.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/100.uart_fifo_reset.2991434762 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 149555022573 ps |
| CPU time | 101.49 seconds |
| Started | Sep 18 06:47:56 PM UTC 24 |
| Finished | Sep 18 06:49:40 PM UTC 24 |
| Peak memory | 208928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991434762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2991434762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/100.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/101.uart_fifo_reset.1950332430 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 15249539833 ps |
| CPU time | 47.7 seconds |
| Started | Sep 18 06:47:56 PM UTC 24 |
| Finished | Sep 18 06:48:45 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950332430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1950332430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/101.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/102.uart_fifo_reset.3340804462 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 62446469755 ps |
| CPU time | 50.52 seconds |
| Started | Sep 18 06:47:57 PM UTC 24 |
| Finished | Sep 18 06:48:49 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340804462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3340804462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/102.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/104.uart_fifo_reset.1813851449 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 70331112624 ps |
| CPU time | 69.31 seconds |
| Started | Sep 18 06:48:02 PM UTC 24 |
| Finished | Sep 18 06:49:13 PM UTC 24 |
| Peak memory | 209660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813851449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1813851449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/104.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/105.uart_fifo_reset.1617345645 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 158193137797 ps |
| CPU time | 55.27 seconds |
| Started | Sep 18 06:48:02 PM UTC 24 |
| Finished | Sep 18 06:48:59 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617345645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1617345645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/105.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/106.uart_fifo_reset.4117687679 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 145246981828 ps |
| CPU time | 41.47 seconds |
| Started | Sep 18 06:48:04 PM UTC 24 |
| Finished | Sep 18 06:48:46 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117687679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.4117687679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/106.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/107.uart_fifo_reset.1268950195 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 93269955512 ps |
| CPU time | 25.65 seconds |
| Started | Sep 18 06:48:06 PM UTC 24 |
| Finished | Sep 18 06:48:33 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268950195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1268950195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/107.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/108.uart_fifo_reset.4203332150 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 69321365805 ps |
| CPU time | 84.7 seconds |
| Started | Sep 18 06:48:07 PM UTC 24 |
| Finished | Sep 18 06:49:33 PM UTC 24 |
| Peak memory | 209576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203332150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.4203332150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/108.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/109.uart_fifo_reset.161058759 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 29913785838 ps |
| CPU time | 48.09 seconds |
| Started | Sep 18 06:48:10 PM UTC 24 |
| Finished | Sep 18 06:49:00 PM UTC 24 |
| Peak memory | 204048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161058759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.161058759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/109.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_alert_test.3792726137 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 28612771 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 06:19:44 PM UTC 24 |
| Finished | Sep 18 06:19:47 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792726137 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3792726137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_fifo_full.721232230 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 42983260692 ps |
| CPU time | 38.48 seconds |
| Started | Sep 18 06:19:26 PM UTC 24 |
| Finished | Sep 18 06:20:06 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721232230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.721232230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_intr.697039976 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 344237385756 ps |
| CPU time | 69.19 seconds |
| Started | Sep 18 06:19:32 PM UTC 24 |
| Finished | Sep 18 06:20:42 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697039976 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.697039976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.2276205482 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 188762153725 ps |
| CPU time | 178.36 seconds |
| Started | Sep 18 06:19:42 PM UTC 24 |
| Finished | Sep 18 06:22:43 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276205482 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2276205482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_loopback.2671432643 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1478362126 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 06:19:39 PM UTC 24 |
| Finished | Sep 18 06:19:43 PM UTC 24 |
| Peak memory | 203712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671432643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2671432643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_noise_filter.1865813420 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 165398757305 ps |
| CPU time | 88.32 seconds |
| Started | Sep 18 06:19:34 PM UTC 24 |
| Finished | Sep 18 06:21:04 PM UTC 24 |
| Peak memory | 209664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865813420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1865813420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_perf.3638067172 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 24504190825 ps |
| CPU time | 454.69 seconds |
| Started | Sep 18 06:19:41 PM UTC 24 |
| Finished | Sep 18 06:27:22 PM UTC 24 |
| Peak memory | 203720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638067172 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3638067172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_rx_oversample.1129046682 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 3118581198 ps |
| CPU time | 3.32 seconds |
| Started | Sep 18 06:19:30 PM UTC 24 |
| Finished | Sep 18 06:19:35 PM UTC 24 |
| Peak memory | 207948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129046682 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1129046682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.341502675 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 3606950605 ps |
| CPU time | 7.08 seconds |
| Started | Sep 18 06:19:35 PM UTC 24 |
| Finished | Sep 18 06:19:43 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341502675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.341502675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_smoke.2686676502 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 730012704 ps |
| CPU time | 2.18 seconds |
| Started | Sep 18 06:19:24 PM UTC 24 |
| Finished | Sep 18 06:19:27 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686676502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2686676502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.358319478 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13756867020 ps |
| CPU time | 15.66 seconds |
| Started | Sep 18 06:19:44 PM UTC 24 |
| Finished | Sep 18 06:20:02 PM UTC 24 |
| Peak memory | 218544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=358319478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all_ with_rand_reset.358319478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.3434556181 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 935121273 ps |
| CPU time | 6.14 seconds |
| Started | Sep 18 06:19:36 PM UTC 24 |
| Finished | Sep 18 06:19:43 PM UTC 24 |
| Peak memory | 203652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434556181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3434556181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/11.uart_tx_rx.444548689 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 14339442563 ps |
| CPU time | 34.44 seconds |
| Started | Sep 18 06:19:25 PM UTC 24 |
| Finished | Sep 18 06:20:01 PM UTC 24 |
| Peak memory | 203912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444548689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.444548689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/11.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/110.uart_fifo_reset.3896782561 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 6492326958 ps |
| CPU time | 22.66 seconds |
| Started | Sep 18 06:48:11 PM UTC 24 |
| Finished | Sep 18 06:48:35 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896782561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3896782561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/110.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/111.uart_fifo_reset.1494118302 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 113878822875 ps |
| CPU time | 94.53 seconds |
| Started | Sep 18 06:48:15 PM UTC 24 |
| Finished | Sep 18 06:49:52 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494118302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1494118302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/111.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/112.uart_fifo_reset.2180134343 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 33546470010 ps |
| CPU time | 18.12 seconds |
| Started | Sep 18 06:48:18 PM UTC 24 |
| Finished | Sep 18 06:48:38 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180134343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2180134343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/112.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/114.uart_fifo_reset.276130764 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 65441227996 ps |
| CPU time | 94.47 seconds |
| Started | Sep 18 06:48:21 PM UTC 24 |
| Finished | Sep 18 06:49:58 PM UTC 24 |
| Peak memory | 203856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276130764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.276130764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/114.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/115.uart_fifo_reset.1198360636 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 489862448383 ps |
| CPU time | 89.36 seconds |
| Started | Sep 18 06:48:24 PM UTC 24 |
| Finished | Sep 18 06:49:55 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198360636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1198360636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/115.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/116.uart_fifo_reset.2694154284 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 46766170973 ps |
| CPU time | 122.83 seconds |
| Started | Sep 18 06:48:27 PM UTC 24 |
| Finished | Sep 18 06:50:33 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694154284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2694154284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/116.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/117.uart_fifo_reset.742209049 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 262205793307 ps |
| CPU time | 390.47 seconds |
| Started | Sep 18 06:48:30 PM UTC 24 |
| Finished | Sep 18 06:55:05 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742209049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.742209049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/117.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/118.uart_fifo_reset.129257724 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 46604929129 ps |
| CPU time | 32.18 seconds |
| Started | Sep 18 06:48:33 PM UTC 24 |
| Finished | Sep 18 06:49:06 PM UTC 24 |
| Peak memory | 208972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129257724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.129257724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/118.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/119.uart_fifo_reset.2973976449 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 27573333950 ps |
| CPU time | 30.18 seconds |
| Started | Sep 18 06:48:34 PM UTC 24 |
| Finished | Sep 18 06:49:06 PM UTC 24 |
| Peak memory | 209324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973976449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2973976449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/119.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_alert_test.4165996438 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 41527955 ps |
| CPU time | 0.88 seconds |
| Started | Sep 18 06:20:22 PM UTC 24 |
| Finished | Sep 18 06:20:24 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165996438 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4165996438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_fifo_full.3621098963 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 76624674614 ps |
| CPU time | 267.39 seconds |
| Started | Sep 18 06:19:51 PM UTC 24 |
| Finished | Sep 18 06:24:22 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621098963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3621098963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.3088430087 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 54343517620 ps |
| CPU time | 91.62 seconds |
| Started | Sep 18 06:19:51 PM UTC 24 |
| Finished | Sep 18 06:21:24 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088430087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3088430087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_fifo_reset.3705623570 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 95886736861 ps |
| CPU time | 160.27 seconds |
| Started | Sep 18 06:19:52 PM UTC 24 |
| Finished | Sep 18 06:22:35 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705623570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3705623570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_intr.1921559131 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 18003483178 ps |
| CPU time | 32.37 seconds |
| Started | Sep 18 06:19:56 PM UTC 24 |
| Finished | Sep 18 06:20:30 PM UTC 24 |
| Peak memory | 203856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921559131 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1921559131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.1786540741 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 36847028869 ps |
| CPU time | 329.25 seconds |
| Started | Sep 18 06:20:12 PM UTC 24 |
| Finished | Sep 18 06:25:46 PM UTC 24 |
| Peak memory | 206140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786540741 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1786540741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_loopback.1533097567 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 9927036937 ps |
| CPU time | 24.22 seconds |
| Started | Sep 18 06:20:05 PM UTC 24 |
| Finished | Sep 18 06:20:31 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533097567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1533097567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_noise_filter.3512223214 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 125498086056 ps |
| CPU time | 84.2 seconds |
| Started | Sep 18 06:20:01 PM UTC 24 |
| Finished | Sep 18 06:21:27 PM UTC 24 |
| Peak memory | 220656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512223214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3512223214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_perf.3279756524 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 8363279621 ps |
| CPU time | 324.98 seconds |
| Started | Sep 18 06:20:07 PM UTC 24 |
| Finished | Sep 18 06:25:36 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279756524 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3279756524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_rx_oversample.3845052525 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 3268937021 ps |
| CPU time | 9.36 seconds |
| Started | Sep 18 06:19:54 PM UTC 24 |
| Finished | Sep 18 06:20:04 PM UTC 24 |
| Peak memory | 208096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845052525 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3845052525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.465483990 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 38950818507 ps |
| CPU time | 88.39 seconds |
| Started | Sep 18 06:20:02 PM UTC 24 |
| Finished | Sep 18 06:21:32 PM UTC 24 |
| Peak memory | 209240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465483990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.465483990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.835168639 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 40580919048 ps |
| CPU time | 37.49 seconds |
| Started | Sep 18 06:20:01 PM UTC 24 |
| Finished | Sep 18 06:20:40 PM UTC 24 |
| Peak memory | 203532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835168639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.835168639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_smoke.1530054898 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 451894143 ps |
| CPU time | 2.38 seconds |
| Started | Sep 18 06:19:47 PM UTC 24 |
| Finished | Sep 18 06:19:51 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530054898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1530054898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.2192670599 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 6406889175 ps |
| CPU time | 20.72 seconds |
| Started | Sep 18 06:20:02 PM UTC 24 |
| Finished | Sep 18 06:20:24 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192670599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2192670599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/12.uart_tx_rx.1225026949 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 92453348871 ps |
| CPU time | 37.81 seconds |
| Started | Sep 18 06:19:49 PM UTC 24 |
| Finished | Sep 18 06:20:29 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225026949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1225026949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/12.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/120.uart_fifo_reset.3817676093 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 251288279846 ps |
| CPU time | 110.68 seconds |
| Started | Sep 18 06:48:35 PM UTC 24 |
| Finished | Sep 18 06:50:28 PM UTC 24 |
| Peak memory | 209396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817676093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3817676093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/120.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/121.uart_fifo_reset.3270382352 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 107880071804 ps |
| CPU time | 34.56 seconds |
| Started | Sep 18 06:48:36 PM UTC 24 |
| Finished | Sep 18 06:49:12 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270382352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3270382352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/121.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/122.uart_fifo_reset.330199642 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 34539624064 ps |
| CPU time | 24.86 seconds |
| Started | Sep 18 06:48:39 PM UTC 24 |
| Finished | Sep 18 06:49:05 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330199642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.330199642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/122.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/123.uart_fifo_reset.2422854104 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 68149579234 ps |
| CPU time | 35.3 seconds |
| Started | Sep 18 06:48:46 PM UTC 24 |
| Finished | Sep 18 06:49:23 PM UTC 24 |
| Peak memory | 209124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422854104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2422854104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/123.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/125.uart_fifo_reset.1838607349 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 93144511283 ps |
| CPU time | 107.32 seconds |
| Started | Sep 18 06:48:49 PM UTC 24 |
| Finished | Sep 18 06:50:39 PM UTC 24 |
| Peak memory | 204028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838607349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1838607349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/125.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/126.uart_fifo_reset.542851536 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 47688409360 ps |
| CPU time | 23.35 seconds |
| Started | Sep 18 06:48:50 PM UTC 24 |
| Finished | Sep 18 06:49:15 PM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542851536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.542851536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/126.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/127.uart_fifo_reset.711749137 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 41029502152 ps |
| CPU time | 46.02 seconds |
| Started | Sep 18 06:48:54 PM UTC 24 |
| Finished | Sep 18 06:49:42 PM UTC 24 |
| Peak memory | 204176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711749137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.711749137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/127.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/128.uart_fifo_reset.3133496240 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 29294206613 ps |
| CPU time | 15.33 seconds |
| Started | Sep 18 06:48:57 PM UTC 24 |
| Finished | Sep 18 06:49:14 PM UTC 24 |
| Peak memory | 204036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133496240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3133496240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/128.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/129.uart_fifo_reset.2926184911 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 51432999068 ps |
| CPU time | 107.09 seconds |
| Started | Sep 18 06:49:00 PM UTC 24 |
| Finished | Sep 18 06:50:50 PM UTC 24 |
| Peak memory | 204096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926184911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2926184911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/129.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_alert_test.711830153 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 14319165 ps |
| CPU time | 0.86 seconds |
| Started | Sep 18 06:20:42 PM UTC 24 |
| Finished | Sep 18 06:20:43 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711830153 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.711830153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_fifo_full.76362230 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 93414301030 ps |
| CPU time | 118.53 seconds |
| Started | Sep 18 06:20:25 PM UTC 24 |
| Finished | Sep 18 06:22:25 PM UTC 24 |
| Peak memory | 203476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76362230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.76362230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.2204377730 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 139430071636 ps |
| CPU time | 74.82 seconds |
| Started | Sep 18 06:20:25 PM UTC 24 |
| Finished | Sep 18 06:21:41 PM UTC 24 |
| Peak memory | 208952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204377730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2204377730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_intr.4141697803 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 36678604026 ps |
| CPU time | 54.37 seconds |
| Started | Sep 18 06:20:30 PM UTC 24 |
| Finished | Sep 18 06:21:26 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141697803 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.4141697803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.3181369213 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 107273460370 ps |
| CPU time | 664.81 seconds |
| Started | Sep 18 06:20:35 PM UTC 24 |
| Finished | Sep 18 06:31:48 PM UTC 24 |
| Peak memory | 205820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181369213 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3181369213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_loopback.1139644714 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2738531133 ps |
| CPU time | 6.15 seconds |
| Started | Sep 18 06:20:34 PM UTC 24 |
| Finished | Sep 18 06:20:41 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139644714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1139644714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_noise_filter.3812114198 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 64942480450 ps |
| CPU time | 53.16 seconds |
| Started | Sep 18 06:20:30 PM UTC 24 |
| Finished | Sep 18 06:21:25 PM UTC 24 |
| Peak memory | 209680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812114198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3812114198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_perf.1337423445 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 12802142901 ps |
| CPU time | 149.33 seconds |
| Started | Sep 18 06:20:35 PM UTC 24 |
| Finished | Sep 18 06:23:07 PM UTC 24 |
| Peak memory | 203972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337423445 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1337423445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_rx_oversample.2226650942 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 6449074283 ps |
| CPU time | 14.58 seconds |
| Started | Sep 18 06:20:29 PM UTC 24 |
| Finished | Sep 18 06:20:45 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226650942 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2226650942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.3590295141 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 18115191848 ps |
| CPU time | 28.17 seconds |
| Started | Sep 18 06:20:31 PM UTC 24 |
| Finished | Sep 18 06:21:00 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590295141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3590295141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.1801828286 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1928041362 ps |
| CPU time | 2.44 seconds |
| Started | Sep 18 06:20:30 PM UTC 24 |
| Finished | Sep 18 06:20:33 PM UTC 24 |
| Peak memory | 203440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801828286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1801828286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_smoke.3236778503 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 804312472 ps |
| CPU time | 2.39 seconds |
| Started | Sep 18 06:20:23 PM UTC 24 |
| Finished | Sep 18 06:20:26 PM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236778503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3236778503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.192886133 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1731680958 ps |
| CPU time | 27.51 seconds |
| Started | Sep 18 06:20:41 PM UTC 24 |
| Finished | Sep 18 06:21:09 PM UTC 24 |
| Peak memory | 209664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=192886133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all_ with_rand_reset.192886133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.2099231048 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 778517698 ps |
| CPU time | 4.39 seconds |
| Started | Sep 18 06:20:34 PM UTC 24 |
| Finished | Sep 18 06:20:40 PM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099231048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2099231048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/13.uart_tx_rx.291214750 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 28567501186 ps |
| CPU time | 55.81 seconds |
| Started | Sep 18 06:20:23 PM UTC 24 |
| Finished | Sep 18 06:21:20 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291214750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.291214750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/13.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/130.uart_fifo_reset.2205529686 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 162159804812 ps |
| CPU time | 87.28 seconds |
| Started | Sep 18 06:49:01 PM UTC 24 |
| Finished | Sep 18 06:50:30 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205529686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2205529686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/130.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/131.uart_fifo_reset.2763303573 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 26016480598 ps |
| CPU time | 20.01 seconds |
| Started | Sep 18 06:49:06 PM UTC 24 |
| Finished | Sep 18 06:49:27 PM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763303573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2763303573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/131.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/132.uart_fifo_reset.922012303 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 35071743470 ps |
| CPU time | 74.22 seconds |
| Started | Sep 18 06:49:07 PM UTC 24 |
| Finished | Sep 18 06:50:23 PM UTC 24 |
| Peak memory | 203708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922012303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.922012303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/132.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/133.uart_fifo_reset.1060534635 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 50593465468 ps |
| CPU time | 88.59 seconds |
| Started | Sep 18 06:49:08 PM UTC 24 |
| Finished | Sep 18 06:50:38 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060534635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1060534635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/133.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/134.uart_fifo_reset.646852218 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 26049748218 ps |
| CPU time | 46.12 seconds |
| Started | Sep 18 06:49:10 PM UTC 24 |
| Finished | Sep 18 06:49:57 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646852218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.646852218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/134.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/135.uart_fifo_reset.3584024149 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 82547194062 ps |
| CPU time | 66.1 seconds |
| Started | Sep 18 06:49:10 PM UTC 24 |
| Finished | Sep 18 06:50:18 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584024149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3584024149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/135.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/136.uart_fifo_reset.2734919370 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 123671959255 ps |
| CPU time | 41.48 seconds |
| Started | Sep 18 06:49:13 PM UTC 24 |
| Finished | Sep 18 06:49:56 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734919370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2734919370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/136.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/137.uart_fifo_reset.710625731 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 221424722297 ps |
| CPU time | 106.21 seconds |
| Started | Sep 18 06:49:14 PM UTC 24 |
| Finished | Sep 18 06:51:02 PM UTC 24 |
| Peak memory | 209596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710625731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.710625731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/137.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/138.uart_fifo_reset.4176447315 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 327441854500 ps |
| CPU time | 76.66 seconds |
| Started | Sep 18 06:49:15 PM UTC 24 |
| Finished | Sep 18 06:50:34 PM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176447315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.4176447315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/138.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/139.uart_fifo_reset.4191051284 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 88691824459 ps |
| CPU time | 221.84 seconds |
| Started | Sep 18 06:49:15 PM UTC 24 |
| Finished | Sep 18 06:53:00 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191051284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4191051284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/139.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_alert_test.2537549493 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 40320921 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 06:21:21 PM UTC 24 |
| Finished | Sep 18 06:21:23 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537549493 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2537549493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.805570866 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 203368074698 ps |
| CPU time | 69.55 seconds |
| Started | Sep 18 06:20:47 PM UTC 24 |
| Finished | Sep 18 06:21:58 PM UTC 24 |
| Peak memory | 209176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805570866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.805570866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.1536387895 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 182182338974 ps |
| CPU time | 234.84 seconds |
| Started | Sep 18 06:21:18 PM UTC 24 |
| Finished | Sep 18 06:25:16 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536387895 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1536387895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_loopback.762140551 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 399117605 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 06:21:15 PM UTC 24 |
| Finished | Sep 18 06:21:17 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762140551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 14.uart_loopback.762140551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_noise_filter.2287958967 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 125044732201 ps |
| CPU time | 56.78 seconds |
| Started | Sep 18 06:21:04 PM UTC 24 |
| Finished | Sep 18 06:22:02 PM UTC 24 |
| Peak memory | 218376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287958967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2287958967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_perf.3165053293 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 9886222982 ps |
| CPU time | 298.43 seconds |
| Started | Sep 18 06:21:16 PM UTC 24 |
| Finished | Sep 18 06:26:19 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165053293 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3165053293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_rx_oversample.1552954186 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 6194791157 ps |
| CPU time | 12.48 seconds |
| Started | Sep 18 06:21:01 PM UTC 24 |
| Finished | Sep 18 06:21:15 PM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552954186 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1552954186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.2849168857 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 106653534128 ps |
| CPU time | 178.46 seconds |
| Started | Sep 18 06:21:08 PM UTC 24 |
| Finished | Sep 18 06:24:09 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849168857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2849168857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.2191779305 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 39016646309 ps |
| CPU time | 145.89 seconds |
| Started | Sep 18 06:21:07 PM UTC 24 |
| Finished | Sep 18 06:23:36 PM UTC 24 |
| Peak memory | 203836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191779305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2191779305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_smoke.3472617607 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 275116019 ps |
| CPU time | 1.7 seconds |
| Started | Sep 18 06:20:44 PM UTC 24 |
| Finished | Sep 18 06:20:46 PM UTC 24 |
| Peak memory | 207136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472617607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3472617607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_stress_all.3960439877 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 69157545149 ps |
| CPU time | 618.95 seconds |
| Started | Sep 18 06:21:19 PM UTC 24 |
| Finished | Sep 18 06:31:45 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960439877 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3960439877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.1852502725 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2587750519 ps |
| CPU time | 47.97 seconds |
| Started | Sep 18 06:21:19 PM UTC 24 |
| Finished | Sep 18 06:22:08 PM UTC 24 |
| Peak memory | 209456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1852502725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all _with_rand_reset.1852502725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.1119218387 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2129208292 ps |
| CPU time | 2.43 seconds |
| Started | Sep 18 06:21:10 PM UTC 24 |
| Finished | Sep 18 06:21:14 PM UTC 24 |
| Peak memory | 203644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119218387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1119218387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/14.uart_tx_rx.1105040211 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 66030397743 ps |
| CPU time | 98.31 seconds |
| Started | Sep 18 06:20:44 PM UTC 24 |
| Finished | Sep 18 06:22:24 PM UTC 24 |
| Peak memory | 205836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105040211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1105040211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/14.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/140.uart_fifo_reset.1660108802 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 10821810571 ps |
| CPU time | 26.87 seconds |
| Started | Sep 18 06:49:16 PM UTC 24 |
| Finished | Sep 18 06:49:44 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660108802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1660108802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/140.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/141.uart_fifo_reset.35968133 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 37325271421 ps |
| CPU time | 31.41 seconds |
| Started | Sep 18 06:49:23 PM UTC 24 |
| Finished | Sep 18 06:49:56 PM UTC 24 |
| Peak memory | 203980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35968133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.35968133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/141.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/142.uart_fifo_reset.3111329932 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 109221126278 ps |
| CPU time | 249.35 seconds |
| Started | Sep 18 06:49:28 PM UTC 24 |
| Finished | Sep 18 06:53:40 PM UTC 24 |
| Peak memory | 209324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111329932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3111329932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/142.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/143.uart_fifo_reset.3053750268 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 18230982262 ps |
| CPU time | 29.11 seconds |
| Started | Sep 18 06:49:32 PM UTC 24 |
| Finished | Sep 18 06:50:02 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053750268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3053750268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/143.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/144.uart_fifo_reset.989394049 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 29859461554 ps |
| CPU time | 18.51 seconds |
| Started | Sep 18 06:49:34 PM UTC 24 |
| Finished | Sep 18 06:49:54 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989394049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.989394049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/144.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/145.uart_fifo_reset.3678027607 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 374736969153 ps |
| CPU time | 54.69 seconds |
| Started | Sep 18 06:49:37 PM UTC 24 |
| Finished | Sep 18 06:50:34 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678027607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3678027607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/145.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/146.uart_fifo_reset.2116455979 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 22195667192 ps |
| CPU time | 41.22 seconds |
| Started | Sep 18 06:49:39 PM UTC 24 |
| Finished | Sep 18 06:50:21 PM UTC 24 |
| Peak memory | 209652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116455979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2116455979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/146.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/147.uart_fifo_reset.2361127530 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 37484905086 ps |
| CPU time | 76.44 seconds |
| Started | Sep 18 06:49:40 PM UTC 24 |
| Finished | Sep 18 06:50:58 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361127530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2361127530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/147.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/148.uart_fifo_reset.3786179476 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 88816625362 ps |
| CPU time | 37.72 seconds |
| Started | Sep 18 06:49:40 PM UTC 24 |
| Finished | Sep 18 06:50:19 PM UTC 24 |
| Peak memory | 209396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786179476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3786179476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/148.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/149.uart_fifo_reset.4145954808 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 71182635494 ps |
| CPU time | 64.37 seconds |
| Started | Sep 18 06:49:41 PM UTC 24 |
| Finished | Sep 18 06:50:47 PM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145954808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.4145954808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/149.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_alert_test.3972877420 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 39810745 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 06:22:01 PM UTC 24 |
| Finished | Sep 18 06:22:03 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972877420 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3972877420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_fifo_reset.3040462945 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 31086159940 ps |
| CPU time | 32.28 seconds |
| Started | Sep 18 06:21:27 PM UTC 24 |
| Finished | Sep 18 06:22:01 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040462945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3040462945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_intr.1545624034 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 184316490947 ps |
| CPU time | 79.65 seconds |
| Started | Sep 18 06:21:32 PM UTC 24 |
| Finished | Sep 18 06:22:54 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545624034 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1545624034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.3707096671 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 83091419665 ps |
| CPU time | 102.58 seconds |
| Started | Sep 18 06:21:52 PM UTC 24 |
| Finished | Sep 18 06:23:37 PM UTC 24 |
| Peak memory | 209320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707096671 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3707096671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_loopback.3126154700 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 8775610964 ps |
| CPU time | 20.05 seconds |
| Started | Sep 18 06:21:49 PM UTC 24 |
| Finished | Sep 18 06:22:10 PM UTC 24 |
| Peak memory | 203928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126154700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3126154700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_noise_filter.1875338765 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 71432097278 ps |
| CPU time | 52.37 seconds |
| Started | Sep 18 06:21:34 PM UTC 24 |
| Finished | Sep 18 06:22:28 PM UTC 24 |
| Peak memory | 209860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875338765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1875338765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_perf.890214055 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 5919371590 ps |
| CPU time | 83.44 seconds |
| Started | Sep 18 06:21:51 PM UTC 24 |
| Finished | Sep 18 06:23:17 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890214055 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.890214055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_rx_oversample.2598949333 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1391858136 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 06:21:28 PM UTC 24 |
| Finished | Sep 18 06:21:32 PM UTC 24 |
| Peak memory | 208204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598949333 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2598949333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.408931713 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 23026647638 ps |
| CPU time | 54.48 seconds |
| Started | Sep 18 06:21:45 PM UTC 24 |
| Finished | Sep 18 06:22:41 PM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408931713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.408931713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.758948855 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 517202459 ps |
| CPU time | 2.72 seconds |
| Started | Sep 18 06:21:42 PM UTC 24 |
| Finished | Sep 18 06:21:45 PM UTC 24 |
| Peak memory | 203512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758948855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.758948855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_smoke.1196007052 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 109186636 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 06:21:24 PM UTC 24 |
| Finished | Sep 18 06:21:26 PM UTC 24 |
| Peak memory | 207220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196007052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1196007052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.481723020 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 4100571225 ps |
| CPU time | 77.08 seconds |
| Started | Sep 18 06:21:59 PM UTC 24 |
| Finished | Sep 18 06:23:18 PM UTC 24 |
| Peak memory | 225884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=481723020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all_ with_rand_reset.481723020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.2364704991 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 3551826829 ps |
| CPU time | 3.21 seconds |
| Started | Sep 18 06:21:47 PM UTC 24 |
| Finished | Sep 18 06:21:51 PM UTC 24 |
| Peak memory | 203912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364704991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2364704991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/15.uart_tx_rx.3096377478 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 23738132346 ps |
| CPU time | 50.06 seconds |
| Started | Sep 18 06:21:25 PM UTC 24 |
| Finished | Sep 18 06:22:17 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096377478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3096377478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/15.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/150.uart_fifo_reset.616541442 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 125005793381 ps |
| CPU time | 238.17 seconds |
| Started | Sep 18 06:49:42 PM UTC 24 |
| Finished | Sep 18 06:53:44 PM UTC 24 |
| Peak memory | 209212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616541442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.616541442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/150.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/152.uart_fifo_reset.2089616135 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 68232391279 ps |
| CPU time | 172.76 seconds |
| Started | Sep 18 06:49:45 PM UTC 24 |
| Finished | Sep 18 06:52:41 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089616135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2089616135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/152.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/153.uart_fifo_reset.3205880141 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 22359616413 ps |
| CPU time | 57.39 seconds |
| Started | Sep 18 06:49:48 PM UTC 24 |
| Finished | Sep 18 06:50:48 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205880141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3205880141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/153.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/156.uart_fifo_reset.3644666146 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 53244797210 ps |
| CPU time | 52.94 seconds |
| Started | Sep 18 06:49:53 PM UTC 24 |
| Finished | Sep 18 06:50:47 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644666146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3644666146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/156.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/157.uart_fifo_reset.3765448689 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 12471290290 ps |
| CPU time | 35.47 seconds |
| Started | Sep 18 06:49:55 PM UTC 24 |
| Finished | Sep 18 06:50:32 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765448689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3765448689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/157.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/158.uart_fifo_reset.2040637642 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 16523359834 ps |
| CPU time | 30.64 seconds |
| Started | Sep 18 06:49:57 PM UTC 24 |
| Finished | Sep 18 06:50:29 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040637642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2040637642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/158.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/159.uart_fifo_reset.2588011837 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 20015796878 ps |
| CPU time | 40.7 seconds |
| Started | Sep 18 06:49:57 PM UTC 24 |
| Finished | Sep 18 06:50:39 PM UTC 24 |
| Peak memory | 204040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588011837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2588011837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/159.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_alert_test.4190935021 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 38904692 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 06:22:35 PM UTC 24 |
| Finished | Sep 18 06:22:36 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190935021 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.4190935021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.772854446 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 55437095175 ps |
| CPU time | 77.52 seconds |
| Started | Sep 18 06:22:09 PM UTC 24 |
| Finished | Sep 18 06:23:28 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772854446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.772854446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_fifo_reset.2115492609 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 20453162778 ps |
| CPU time | 28.18 seconds |
| Started | Sep 18 06:22:10 PM UTC 24 |
| Finished | Sep 18 06:22:39 PM UTC 24 |
| Peak memory | 204168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115492609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2115492609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_intr.1268358211 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 46397792832 ps |
| CPU time | 33.39 seconds |
| Started | Sep 18 06:22:11 PM UTC 24 |
| Finished | Sep 18 06:22:46 PM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268358211 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1268358211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.3838227190 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 86283029876 ps |
| CPU time | 180.25 seconds |
| Started | Sep 18 06:22:32 PM UTC 24 |
| Finished | Sep 18 06:25:35 PM UTC 24 |
| Peak memory | 209184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838227190 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3838227190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_loopback.470626441 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1329585201 ps |
| CPU time | 3.83 seconds |
| Started | Sep 18 06:22:28 PM UTC 24 |
| Finished | Sep 18 06:22:33 PM UTC 24 |
| Peak memory | 207608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470626441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 16.uart_loopback.470626441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_noise_filter.2457930754 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 45021796102 ps |
| CPU time | 85.53 seconds |
| Started | Sep 18 06:22:18 PM UTC 24 |
| Finished | Sep 18 06:23:45 PM UTC 24 |
| Peak memory | 209924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457930754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2457930754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_perf.3907379793 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 17327358841 ps |
| CPU time | 787.96 seconds |
| Started | Sep 18 06:22:32 PM UTC 24 |
| Finished | Sep 18 06:35:50 PM UTC 24 |
| Peak memory | 209184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907379793 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3907379793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_rx_oversample.3283353574 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 4725962112 ps |
| CPU time | 66.9 seconds |
| Started | Sep 18 06:22:10 PM UTC 24 |
| Finished | Sep 18 06:23:18 PM UTC 24 |
| Peak memory | 207976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283353574 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3283353574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.4229825994 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 18554468055 ps |
| CPU time | 28.84 seconds |
| Started | Sep 18 06:22:26 PM UTC 24 |
| Finished | Sep 18 06:22:56 PM UTC 24 |
| Peak memory | 209160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229825994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.4229825994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.857867869 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1833067049 ps |
| CPU time | 5.44 seconds |
| Started | Sep 18 06:22:25 PM UTC 24 |
| Finished | Sep 18 06:22:32 PM UTC 24 |
| Peak memory | 203512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857867869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.857867869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_smoke.2260222077 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 739594706 ps |
| CPU time | 1.65 seconds |
| Started | Sep 18 06:22:03 PM UTC 24 |
| Finished | Sep 18 06:22:06 PM UTC 24 |
| Peak memory | 207236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260222077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2260222077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_stress_all.636957729 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 616007473903 ps |
| CPU time | 566.23 seconds |
| Started | Sep 18 06:22:34 PM UTC 24 |
| Finished | Sep 18 06:32:07 PM UTC 24 |
| Peak memory | 218456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636957729 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.636957729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.3511492441 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2535260342 ps |
| CPU time | 41.85 seconds |
| Started | Sep 18 06:22:32 PM UTC 24 |
| Finished | Sep 18 06:23:16 PM UTC 24 |
| Peak memory | 218392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3511492441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all _with_rand_reset.3511492441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.2061531721 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 628877231 ps |
| CPU time | 1.82 seconds |
| Started | Sep 18 06:22:28 PM UTC 24 |
| Finished | Sep 18 06:22:31 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061531721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2061531721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/16.uart_tx_rx.3684499168 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 2449750916 ps |
| CPU time | 3.17 seconds |
| Started | Sep 18 06:22:04 PM UTC 24 |
| Finished | Sep 18 06:22:09 PM UTC 24 |
| Peak memory | 203708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684499168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3684499168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/16.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/160.uart_fifo_reset.2221129576 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 6307612848 ps |
| CPU time | 13.86 seconds |
| Started | Sep 18 06:49:57 PM UTC 24 |
| Finished | Sep 18 06:50:12 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221129576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2221129576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/160.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/162.uart_fifo_reset.2333730997 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 147310535230 ps |
| CPU time | 239.51 seconds |
| Started | Sep 18 06:49:59 PM UTC 24 |
| Finished | Sep 18 06:54:02 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333730997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2333730997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/162.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/163.uart_fifo_reset.3153626948 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 29967527438 ps |
| CPU time | 61.1 seconds |
| Started | Sep 18 06:50:03 PM UTC 24 |
| Finished | Sep 18 06:51:06 PM UTC 24 |
| Peak memory | 209596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153626948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3153626948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/163.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/164.uart_fifo_reset.4065449779 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 68709102871 ps |
| CPU time | 50.41 seconds |
| Started | Sep 18 06:50:09 PM UTC 24 |
| Finished | Sep 18 06:51:01 PM UTC 24 |
| Peak memory | 208132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065449779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.4065449779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/164.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/165.uart_fifo_reset.3456832049 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 53797004208 ps |
| CPU time | 30.1 seconds |
| Started | Sep 18 06:50:12 PM UTC 24 |
| Finished | Sep 18 06:50:44 PM UTC 24 |
| Peak memory | 203984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456832049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3456832049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/165.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/166.uart_fifo_reset.1197182508 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 112605554380 ps |
| CPU time | 81.3 seconds |
| Started | Sep 18 06:50:18 PM UTC 24 |
| Finished | Sep 18 06:51:41 PM UTC 24 |
| Peak memory | 203856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197182508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1197182508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/166.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/167.uart_fifo_reset.3653890178 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 73293404187 ps |
| CPU time | 31.57 seconds |
| Started | Sep 18 06:50:18 PM UTC 24 |
| Finished | Sep 18 06:50:51 PM UTC 24 |
| Peak memory | 209504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653890178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3653890178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/167.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/168.uart_fifo_reset.2381308012 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 124195959743 ps |
| CPU time | 79.54 seconds |
| Started | Sep 18 06:50:20 PM UTC 24 |
| Finished | Sep 18 06:51:41 PM UTC 24 |
| Peak memory | 208984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381308012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2381308012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/168.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/169.uart_fifo_reset.1296951769 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 92886260749 ps |
| CPU time | 181.56 seconds |
| Started | Sep 18 06:50:20 PM UTC 24 |
| Finished | Sep 18 06:53:24 PM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296951769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1296951769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/169.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_alert_test.1859628081 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 40594894 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 06:23:08 PM UTC 24 |
| Finished | Sep 18 06:23:10 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859628081 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1859628081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_fifo_full.1064482680 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 24583016096 ps |
| CPU time | 49.71 seconds |
| Started | Sep 18 06:22:37 PM UTC 24 |
| Finished | Sep 18 06:23:28 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064482680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1064482680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_fifo_reset.555404522 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 121530713501 ps |
| CPU time | 111.8 seconds |
| Started | Sep 18 06:22:40 PM UTC 24 |
| Finished | Sep 18 06:24:34 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555404522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.555404522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_intr.619476143 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 32077588735 ps |
| CPU time | 51.01 seconds |
| Started | Sep 18 06:22:44 PM UTC 24 |
| Finished | Sep 18 06:23:37 PM UTC 24 |
| Peak memory | 204036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619476143 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.619476143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.3335014922 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 123365831018 ps |
| CPU time | 840.18 seconds |
| Started | Sep 18 06:22:57 PM UTC 24 |
| Finished | Sep 18 06:37:07 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335014922 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3335014922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_loopback.2904061603 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1898705346 ps |
| CPU time | 3.21 seconds |
| Started | Sep 18 06:22:55 PM UTC 24 |
| Finished | Sep 18 06:23:00 PM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904061603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2904061603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_noise_filter.2180767867 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 180122511848 ps |
| CPU time | 123.62 seconds |
| Started | Sep 18 06:22:44 PM UTC 24 |
| Finished | Sep 18 06:24:50 PM UTC 24 |
| Peak memory | 220556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180767867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2180767867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_perf.533101297 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 15917244598 ps |
| CPU time | 228.09 seconds |
| Started | Sep 18 06:22:56 PM UTC 24 |
| Finished | Sep 18 06:26:47 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533101297 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.533101297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_rx_oversample.3814336584 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2434661292 ps |
| CPU time | 11.5 seconds |
| Started | Sep 18 06:22:42 PM UTC 24 |
| Finished | Sep 18 06:22:55 PM UTC 24 |
| Peak memory | 208496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814336584 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3814336584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.3108457973 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3114048942 ps |
| CPU time | 2.95 seconds |
| Started | Sep 18 06:22:46 PM UTC 24 |
| Finished | Sep 18 06:22:50 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108457973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3108457973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_smoke.1919974489 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 306348465 ps |
| CPU time | 1.48 seconds |
| Started | Sep 18 06:22:36 PM UTC 24 |
| Finished | Sep 18 06:22:38 PM UTC 24 |
| Peak memory | 203268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919974489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1919974489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_stress_all.3279616626 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 439246821641 ps |
| CPU time | 804.73 seconds |
| Started | Sep 18 06:23:01 PM UTC 24 |
| Finished | Sep 18 06:36:35 PM UTC 24 |
| Peak memory | 222868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279616626 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3279616626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.3376023362 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 10742634411 ps |
| CPU time | 63.38 seconds |
| Started | Sep 18 06:23:01 PM UTC 24 |
| Finished | Sep 18 06:24:06 PM UTC 24 |
| Peak memory | 222636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3376023362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all _with_rand_reset.3376023362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.2213076901 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2529754130 ps |
| CPU time | 3.3 seconds |
| Started | Sep 18 06:22:55 PM UTC 24 |
| Finished | Sep 18 06:23:00 PM UTC 24 |
| Peak memory | 204116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213076901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2213076901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/17.uart_tx_rx.205422667 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 72535577955 ps |
| CPU time | 153.37 seconds |
| Started | Sep 18 06:22:36 PM UTC 24 |
| Finished | Sep 18 06:25:11 PM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205422667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.205422667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/17.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/170.uart_fifo_reset.744046146 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 19497114787 ps |
| CPU time | 26.84 seconds |
| Started | Sep 18 06:50:21 PM UTC 24 |
| Finished | Sep 18 06:50:49 PM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744046146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.744046146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/170.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/171.uart_fifo_reset.2933540238 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 40224758189 ps |
| CPU time | 66.47 seconds |
| Started | Sep 18 06:50:23 PM UTC 24 |
| Finished | Sep 18 06:51:31 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933540238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2933540238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/171.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/173.uart_fifo_reset.1841156777 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 12699559617 ps |
| CPU time | 27.26 seconds |
| Started | Sep 18 06:50:29 PM UTC 24 |
| Finished | Sep 18 06:50:57 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841156777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1841156777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/173.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/174.uart_fifo_reset.630516995 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 62147867100 ps |
| CPU time | 70 seconds |
| Started | Sep 18 06:50:30 PM UTC 24 |
| Finished | Sep 18 06:51:42 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630516995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.630516995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/174.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/176.uart_fifo_reset.2860177016 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 61189101764 ps |
| CPU time | 84.17 seconds |
| Started | Sep 18 06:50:32 PM UTC 24 |
| Finished | Sep 18 06:51:58 PM UTC 24 |
| Peak memory | 204100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860177016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2860177016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/176.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/177.uart_fifo_reset.3855901846 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 76131059594 ps |
| CPU time | 27.03 seconds |
| Started | Sep 18 06:50:33 PM UTC 24 |
| Finished | Sep 18 06:51:02 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855901846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3855901846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/177.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/178.uart_fifo_reset.810805558 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 25960989435 ps |
| CPU time | 50.36 seconds |
| Started | Sep 18 06:50:34 PM UTC 24 |
| Finished | Sep 18 06:51:26 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810805558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.810805558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/178.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_alert_test.460273631 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 39178056 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:23:45 PM UTC 24 |
| Finished | Sep 18 06:23:47 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460273631 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.460273631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_fifo_full.1569286591 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 162130601764 ps |
| CPU time | 44.95 seconds |
| Started | Sep 18 06:23:13 PM UTC 24 |
| Finished | Sep 18 06:23:59 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569286591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1569286591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_intr.895123821 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 70074220992 ps |
| CPU time | 61.27 seconds |
| Started | Sep 18 06:23:19 PM UTC 24 |
| Finished | Sep 18 06:24:22 PM UTC 24 |
| Peak memory | 203908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895123821 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.895123821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.3976595766 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 101357768652 ps |
| CPU time | 340.42 seconds |
| Started | Sep 18 06:23:38 PM UTC 24 |
| Finished | Sep 18 06:29:23 PM UTC 24 |
| Peak memory | 209320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976595766 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3976595766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_loopback.1622573234 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 5574796876 ps |
| CPU time | 9.1 seconds |
| Started | Sep 18 06:23:37 PM UTC 24 |
| Finished | Sep 18 06:23:47 PM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622573234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1622573234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_noise_filter.4018293497 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 88991184202 ps |
| CPU time | 88.31 seconds |
| Started | Sep 18 06:23:28 PM UTC 24 |
| Finished | Sep 18 06:24:59 PM UTC 24 |
| Peak memory | 209924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018293497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.4018293497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_perf.2952142234 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 4153670643 ps |
| CPU time | 79.89 seconds |
| Started | Sep 18 06:23:37 PM UTC 24 |
| Finished | Sep 18 06:24:59 PM UTC 24 |
| Peak memory | 204112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952142234 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2952142234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_rx_oversample.1084605519 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 5725826110 ps |
| CPU time | 9.9 seconds |
| Started | Sep 18 06:23:19 PM UTC 24 |
| Finished | Sep 18 06:23:30 PM UTC 24 |
| Peak memory | 207948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084605519 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1084605519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.609833774 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 518118337 ps |
| CPU time | 1.6 seconds |
| Started | Sep 18 06:23:28 PM UTC 24 |
| Finished | Sep 18 06:23:31 PM UTC 24 |
| Peak memory | 203248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609833774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.609833774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_smoke.314968853 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 107654813 ps |
| CPU time | 1.67 seconds |
| Started | Sep 18 06:23:10 PM UTC 24 |
| Finished | Sep 18 06:23:13 PM UTC 24 |
| Peak memory | 207284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314968853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 18.uart_smoke.314968853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_stress_all.82755303 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 173096599775 ps |
| CPU time | 108.95 seconds |
| Started | Sep 18 06:23:39 PM UTC 24 |
| Finished | Sep 18 06:25:30 PM UTC 24 |
| Peak memory | 213204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82755303 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.82755303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.725847566 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1882812603 ps |
| CPU time | 43.46 seconds |
| Started | Sep 18 06:23:38 PM UTC 24 |
| Finished | Sep 18 06:24:23 PM UTC 24 |
| Peak memory | 218172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=725847566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all_ with_rand_reset.725847566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.2751101961 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1079927256 ps |
| CPU time | 3.85 seconds |
| Started | Sep 18 06:23:33 PM UTC 24 |
| Finished | Sep 18 06:23:38 PM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751101961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2751101961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/18.uart_tx_rx.238981428 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 47530923034 ps |
| CPU time | 68.89 seconds |
| Started | Sep 18 06:23:11 PM UTC 24 |
| Finished | Sep 18 06:24:22 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238981428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.238981428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/18.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/182.uart_fifo_reset.1214692869 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 205207356835 ps |
| CPU time | 56.95 seconds |
| Started | Sep 18 06:50:40 PM UTC 24 |
| Finished | Sep 18 06:51:38 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214692869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1214692869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/182.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/183.uart_fifo_reset.3192745098 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 39147008589 ps |
| CPU time | 18.38 seconds |
| Started | Sep 18 06:50:44 PM UTC 24 |
| Finished | Sep 18 06:51:03 PM UTC 24 |
| Peak memory | 209388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192745098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3192745098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/183.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/184.uart_fifo_reset.2234451709 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 113311301751 ps |
| CPU time | 246.35 seconds |
| Started | Sep 18 06:50:45 PM UTC 24 |
| Finished | Sep 18 06:54:54 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234451709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2234451709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/184.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/185.uart_fifo_reset.1749922782 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 292143243183 ps |
| CPU time | 158.4 seconds |
| Started | Sep 18 06:50:48 PM UTC 24 |
| Finished | Sep 18 06:53:29 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749922782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1749922782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/185.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/186.uart_fifo_reset.3643064762 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 33008751998 ps |
| CPU time | 60.38 seconds |
| Started | Sep 18 06:50:48 PM UTC 24 |
| Finished | Sep 18 06:51:50 PM UTC 24 |
| Peak memory | 209432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643064762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3643064762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/186.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/187.uart_fifo_reset.1682547727 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 75835998615 ps |
| CPU time | 41.47 seconds |
| Started | Sep 18 06:50:48 PM UTC 24 |
| Finished | Sep 18 06:51:31 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682547727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1682547727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/187.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/188.uart_fifo_reset.378438767 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 214247953997 ps |
| CPU time | 164.62 seconds |
| Started | Sep 18 06:50:49 PM UTC 24 |
| Finished | Sep 18 06:53:36 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378438767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.378438767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/188.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/189.uart_fifo_reset.3707830979 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 16685369960 ps |
| CPU time | 29.18 seconds |
| Started | Sep 18 06:50:50 PM UTC 24 |
| Finished | Sep 18 06:51:20 PM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707830979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3707830979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/189.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_alert_test.879551559 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 19210726 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 06:24:23 PM UTC 24 |
| Finished | Sep 18 06:24:24 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879551559 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.879551559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_fifo_full.2879068314 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 141594432406 ps |
| CPU time | 50.16 seconds |
| Started | Sep 18 06:23:47 PM UTC 24 |
| Finished | Sep 18 06:24:39 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879068314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2879068314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.2635396325 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 9595531119 ps |
| CPU time | 39.13 seconds |
| Started | Sep 18 06:23:49 PM UTC 24 |
| Finished | Sep 18 06:24:29 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635396325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2635396325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_intr.1062807471 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 35494347772 ps |
| CPU time | 14.14 seconds |
| Started | Sep 18 06:24:05 PM UTC 24 |
| Finished | Sep 18 06:24:20 PM UTC 24 |
| Peak memory | 209212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062807471 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1062807471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.3050868395 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 84278568435 ps |
| CPU time | 335.88 seconds |
| Started | Sep 18 06:24:21 PM UTC 24 |
| Finished | Sep 18 06:30:02 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050868395 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3050868395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_loopback.2571392053 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 5665581625 ps |
| CPU time | 9.06 seconds |
| Started | Sep 18 06:24:18 PM UTC 24 |
| Finished | Sep 18 06:24:28 PM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571392053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2571392053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_perf.1257791935 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 8745332611 ps |
| CPU time | 62.18 seconds |
| Started | Sep 18 06:24:19 PM UTC 24 |
| Finished | Sep 18 06:25:23 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257791935 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1257791935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_rx_oversample.214446745 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2494593164 ps |
| CPU time | 2.88 seconds |
| Started | Sep 18 06:24:00 PM UTC 24 |
| Finished | Sep 18 06:24:04 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214446745 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.214446745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.2794487470 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 32685419661 ps |
| CPU time | 38.47 seconds |
| Started | Sep 18 06:24:10 PM UTC 24 |
| Finished | Sep 18 06:24:50 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794487470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2794487470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.3452400440 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 4831433828 ps |
| CPU time | 5.45 seconds |
| Started | Sep 18 06:24:07 PM UTC 24 |
| Finished | Sep 18 06:24:13 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452400440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3452400440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_smoke.4108641924 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 5994617281 ps |
| CPU time | 16.15 seconds |
| Started | Sep 18 06:23:46 PM UTC 24 |
| Finished | Sep 18 06:24:04 PM UTC 24 |
| Peak memory | 208924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108641924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.uart_smoke.4108641924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_stress_all.2598034369 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 158589189140 ps |
| CPU time | 43.93 seconds |
| Started | Sep 18 06:24:23 PM UTC 24 |
| Finished | Sep 18 06:25:08 PM UTC 24 |
| Peak memory | 205888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598034369 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2598034369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.2315927934 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1837383833 ps |
| CPU time | 22.61 seconds |
| Started | Sep 18 06:24:23 PM UTC 24 |
| Finished | Sep 18 06:24:46 PM UTC 24 |
| Peak memory | 209320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2315927934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all _with_rand_reset.2315927934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.1161041328 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 382730052 ps |
| CPU time | 2.32 seconds |
| Started | Sep 18 06:24:14 PM UTC 24 |
| Finished | Sep 18 06:24:17 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161041328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1161041328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/19.uart_tx_rx.1764896905 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 102689802760 ps |
| CPU time | 46.27 seconds |
| Started | Sep 18 06:23:47 PM UTC 24 |
| Finished | Sep 18 06:24:35 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764896905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1764896905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/19.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/190.uart_fifo_reset.1535252819 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 59691756270 ps |
| CPU time | 22.49 seconds |
| Started | Sep 18 06:50:50 PM UTC 24 |
| Finished | Sep 18 06:51:14 PM UTC 24 |
| Peak memory | 209324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535252819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1535252819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/190.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/191.uart_fifo_reset.2401996043 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 139956296648 ps |
| CPU time | 218.23 seconds |
| Started | Sep 18 06:50:52 PM UTC 24 |
| Finished | Sep 18 06:54:33 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401996043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2401996043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/191.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/192.uart_fifo_reset.2571426845 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 94567946426 ps |
| CPU time | 177.78 seconds |
| Started | Sep 18 06:50:54 PM UTC 24 |
| Finished | Sep 18 06:53:55 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571426845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2571426845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/192.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/194.uart_fifo_reset.3976538874 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 38262199998 ps |
| CPU time | 29.65 seconds |
| Started | Sep 18 06:50:59 PM UTC 24 |
| Finished | Sep 18 06:51:30 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976538874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3976538874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/194.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/196.uart_fifo_reset.3907127699 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 74486304037 ps |
| CPU time | 88.31 seconds |
| Started | Sep 18 06:51:01 PM UTC 24 |
| Finished | Sep 18 06:52:31 PM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907127699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3907127699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/196.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/198.uart_fifo_reset.3941181274 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 12678969046 ps |
| CPU time | 38.11 seconds |
| Started | Sep 18 06:51:03 PM UTC 24 |
| Finished | Sep 18 06:51:42 PM UTC 24 |
| Peak memory | 203752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941181274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3941181274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/198.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/199.uart_fifo_reset.3517985372 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 80988935965 ps |
| CPU time | 239.98 seconds |
| Started | Sep 18 06:51:03 PM UTC 24 |
| Finished | Sep 18 06:55:06 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517985372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3517985372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/199.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_alert_test.596874580 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 30411290 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 06:16:08 PM UTC 24 |
| Finished | Sep 18 06:16:10 PM UTC 24 |
| Peak memory | 203120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596874580 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.596874580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.3508094004 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 197847956521 ps |
| CPU time | 119.98 seconds |
| Started | Sep 18 06:15:39 PM UTC 24 |
| Finished | Sep 18 06:17:41 PM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508094004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3508094004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_intr.4110723632 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 34473543350 ps |
| CPU time | 27.22 seconds |
| Started | Sep 18 06:15:45 PM UTC 24 |
| Finished | Sep 18 06:16:14 PM UTC 24 |
| Peak memory | 204036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110723632 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.4110723632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.2073885118 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 96250137266 ps |
| CPU time | 97.83 seconds |
| Started | Sep 18 06:16:00 PM UTC 24 |
| Finished | Sep 18 06:17:40 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073885118 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2073885118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_loopback.318364621 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6662271987 ps |
| CPU time | 20.81 seconds |
| Started | Sep 18 06:15:58 PM UTC 24 |
| Finished | Sep 18 06:16:20 PM UTC 24 |
| Peak memory | 204036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318364621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.uart_loopback.318364621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_noise_filter.1884333171 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 47245056438 ps |
| CPU time | 95.28 seconds |
| Started | Sep 18 06:15:46 PM UTC 24 |
| Finished | Sep 18 06:17:24 PM UTC 24 |
| Peak memory | 218688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884333171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1884333171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_perf.3947091115 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 6757908793 ps |
| CPU time | 383.98 seconds |
| Started | Sep 18 06:15:59 PM UTC 24 |
| Finished | Sep 18 06:22:28 PM UTC 24 |
| Peak memory | 209580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947091115 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3947091115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_rx_oversample.361900817 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2118359000 ps |
| CPU time | 20.82 seconds |
| Started | Sep 18 06:15:42 PM UTC 24 |
| Finished | Sep 18 06:16:04 PM UTC 24 |
| Peak memory | 208136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361900817 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.361900817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.1058383679 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 41679253756 ps |
| CPU time | 29.38 seconds |
| Started | Sep 18 06:15:54 PM UTC 24 |
| Finished | Sep 18 06:16:25 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058383679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1058383679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.1515934907 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1908969459 ps |
| CPU time | 6.95 seconds |
| Started | Sep 18 06:15:50 PM UTC 24 |
| Finished | Sep 18 06:15:58 PM UTC 24 |
| Peak memory | 203456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515934907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1515934907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_sec_cm.4117669413 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 103133644 ps |
| CPU time | 0.96 seconds |
| Started | Sep 18 06:16:07 PM UTC 24 |
| Finished | Sep 18 06:16:09 PM UTC 24 |
| Peak memory | 237808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117669413 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.4117669413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_smoke.3858773912 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 486169762 ps |
| CPU time | 3.36 seconds |
| Started | Sep 18 06:15:36 PM UTC 24 |
| Finished | Sep 18 06:15:40 PM UTC 24 |
| Peak memory | 203728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858773912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3858773912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_stress_all.3844270342 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 179230619435 ps |
| CPU time | 959.51 seconds |
| Started | Sep 18 06:16:05 PM UTC 24 |
| Finished | Sep 18 06:32:15 PM UTC 24 |
| Peak memory | 220488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844270342 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3844270342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.3078696867 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 22126361015 ps |
| CPU time | 103.79 seconds |
| Started | Sep 18 06:16:04 PM UTC 24 |
| Finished | Sep 18 06:17:50 PM UTC 24 |
| Peak memory | 226212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3078696867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_ with_rand_reset.3078696867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.3885895846 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 6353260264 ps |
| CPU time | 26.68 seconds |
| Started | Sep 18 06:15:55 PM UTC 24 |
| Finished | Sep 18 06:16:23 PM UTC 24 |
| Peak memory | 203768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885895846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3885895846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/2.uart_tx_rx.3462288321 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 46785666852 ps |
| CPU time | 76.71 seconds |
| Started | Sep 18 06:15:38 PM UTC 24 |
| Finished | Sep 18 06:16:56 PM UTC 24 |
| Peak memory | 203800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462288321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3462288321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/2.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_alert_test.1196314121 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 69638246 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 06:24:51 PM UTC 24 |
| Finished | Sep 18 06:24:53 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196314121 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1196314121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_fifo_full.93352449 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 43838405639 ps |
| CPU time | 20.68 seconds |
| Started | Sep 18 06:24:28 PM UTC 24 |
| Finished | Sep 18 06:24:50 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93352449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.93352449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.1210969592 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 102031445432 ps |
| CPU time | 26.67 seconds |
| Started | Sep 18 06:24:29 PM UTC 24 |
| Finished | Sep 18 06:24:57 PM UTC 24 |
| Peak memory | 208944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210969592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1210969592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_fifo_reset.4082101320 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 188915790794 ps |
| CPU time | 78.89 seconds |
| Started | Sep 18 06:24:29 PM UTC 24 |
| Finished | Sep 18 06:25:50 PM UTC 24 |
| Peak memory | 208980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082101320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.4082101320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_intr.416230222 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 173583097737 ps |
| CPU time | 90.15 seconds |
| Started | Sep 18 06:24:32 PM UTC 24 |
| Finished | Sep 18 06:26:04 PM UTC 24 |
| Peak memory | 203572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416230222 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.416230222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.1102547332 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 134524779310 ps |
| CPU time | 1079.84 seconds |
| Started | Sep 18 06:24:47 PM UTC 24 |
| Finished | Sep 18 06:42:59 PM UTC 24 |
| Peak memory | 204156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102547332 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1102547332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_loopback.2740991862 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2381377520 ps |
| CPU time | 10.12 seconds |
| Started | Sep 18 06:24:40 PM UTC 24 |
| Finished | Sep 18 06:24:51 PM UTC 24 |
| Peak memory | 208440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740991862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2740991862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_noise_filter.3241697082 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 23166385352 ps |
| CPU time | 43.06 seconds |
| Started | Sep 18 06:24:32 PM UTC 24 |
| Finished | Sep 18 06:25:17 PM UTC 24 |
| Peak memory | 209924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241697082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3241697082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_perf.1277217399 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 18333396317 ps |
| CPU time | 273.73 seconds |
| Started | Sep 18 06:24:41 PM UTC 24 |
| Finished | Sep 18 06:29:18 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277217399 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1277217399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_rx_oversample.2930076064 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 6304729193 ps |
| CPU time | 23.19 seconds |
| Started | Sep 18 06:24:30 PM UTC 24 |
| Finished | Sep 18 06:24:55 PM UTC 24 |
| Peak memory | 208204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930076064 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2930076064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.2971657833 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 39955453887 ps |
| CPU time | 22.79 seconds |
| Started | Sep 18 06:24:34 PM UTC 24 |
| Finished | Sep 18 06:24:59 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971657833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2971657833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.1154942593 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 33191827355 ps |
| CPU time | 47.16 seconds |
| Started | Sep 18 06:24:33 PM UTC 24 |
| Finished | Sep 18 06:25:22 PM UTC 24 |
| Peak memory | 203504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154942593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1154942593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_smoke.1785823548 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 945538348 ps |
| CPU time | 2.61 seconds |
| Started | Sep 18 06:24:24 PM UTC 24 |
| Finished | Sep 18 06:24:27 PM UTC 24 |
| Peak memory | 207892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785823548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1785823548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_stress_all.2852380439 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 85741425211 ps |
| CPU time | 161.63 seconds |
| Started | Sep 18 06:24:51 PM UTC 24 |
| Finished | Sep 18 06:27:35 PM UTC 24 |
| Peak memory | 204096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852380439 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2852380439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.4169920326 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 21250284922 ps |
| CPU time | 63.41 seconds |
| Started | Sep 18 06:24:49 PM UTC 24 |
| Finished | Sep 18 06:25:54 PM UTC 24 |
| Peak memory | 222328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4169920326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all _with_rand_reset.4169920326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.1280482598 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1818754842 ps |
| CPU time | 2.52 seconds |
| Started | Sep 18 06:24:36 PM UTC 24 |
| Finished | Sep 18 06:24:40 PM UTC 24 |
| Peak memory | 204044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280482598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1280482598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/20.uart_tx_rx.1930928595 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 96319981275 ps |
| CPU time | 74.17 seconds |
| Started | Sep 18 06:24:25 PM UTC 24 |
| Finished | Sep 18 06:25:41 PM UTC 24 |
| Peak memory | 209204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930928595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1930928595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/20.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/200.uart_fifo_reset.1166693865 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 90433973280 ps |
| CPU time | 243.99 seconds |
| Started | Sep 18 06:51:04 PM UTC 24 |
| Finished | Sep 18 06:55:11 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166693865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1166693865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/200.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/202.uart_fifo_reset.4007428967 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 50422145890 ps |
| CPU time | 48.7 seconds |
| Started | Sep 18 06:51:15 PM UTC 24 |
| Finished | Sep 18 06:52:06 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007428967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.4007428967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/202.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2197739796 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 127898848804 ps |
| CPU time | 315.96 seconds |
| Started | Sep 18 06:51:17 PM UTC 24 |
| Finished | Sep 18 06:56:38 PM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197739796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2197739796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/203.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2132638427 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 225104324727 ps |
| CPU time | 276.67 seconds |
| Started | Sep 18 06:51:21 PM UTC 24 |
| Finished | Sep 18 06:56:02 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132638427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2132638427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/204.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/205.uart_fifo_reset.327445472 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 65825834272 ps |
| CPU time | 25 seconds |
| Started | Sep 18 06:51:27 PM UTC 24 |
| Finished | Sep 18 06:51:54 PM UTC 24 |
| Peak memory | 204112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327445472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.327445472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/205.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/206.uart_fifo_reset.4050717799 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 15861481500 ps |
| CPU time | 33.23 seconds |
| Started | Sep 18 06:51:31 PM UTC 24 |
| Finished | Sep 18 06:52:06 PM UTC 24 |
| Peak memory | 209288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050717799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.4050717799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/206.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/207.uart_fifo_reset.776525215 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 42855134333 ps |
| CPU time | 53.13 seconds |
| Started | Sep 18 06:51:32 PM UTC 24 |
| Finished | Sep 18 06:52:27 PM UTC 24 |
| Peak memory | 209352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776525215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.776525215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/207.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2726900629 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 147870191264 ps |
| CPU time | 221.41 seconds |
| Started | Sep 18 06:51:32 PM UTC 24 |
| Finished | Sep 18 06:55:17 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726900629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2726900629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/208.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/209.uart_fifo_reset.804456189 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 31546667902 ps |
| CPU time | 33.82 seconds |
| Started | Sep 18 06:51:34 PM UTC 24 |
| Finished | Sep 18 06:52:09 PM UTC 24 |
| Peak memory | 203716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804456189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.804456189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/209.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_alert_test.553702887 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 31835564 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:25:12 PM UTC 24 |
| Finished | Sep 18 06:25:14 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553702887 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.553702887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_fifo_full.935529734 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 104891385933 ps |
| CPU time | 217.26 seconds |
| Started | Sep 18 06:24:54 PM UTC 24 |
| Finished | Sep 18 06:28:35 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935529734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.935529734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.2652563341 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 70491514521 ps |
| CPU time | 77.33 seconds |
| Started | Sep 18 06:24:55 PM UTC 24 |
| Finished | Sep 18 06:26:14 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652563341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2652563341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_fifo_reset.2331668079 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 50591152811 ps |
| CPU time | 21.45 seconds |
| Started | Sep 18 06:24:55 PM UTC 24 |
| Finished | Sep 18 06:25:18 PM UTC 24 |
| Peak memory | 209596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331668079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2331668079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_intr.2690925018 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 56737617219 ps |
| CPU time | 31.84 seconds |
| Started | Sep 18 06:24:56 PM UTC 24 |
| Finished | Sep 18 06:25:30 PM UTC 24 |
| Peak memory | 208628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690925018 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2690925018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.2243037195 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 90721447010 ps |
| CPU time | 1081.49 seconds |
| Started | Sep 18 06:25:07 PM UTC 24 |
| Finished | Sep 18 06:43:21 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243037195 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2243037195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_loopback.3469571648 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 11693984389 ps |
| CPU time | 25.81 seconds |
| Started | Sep 18 06:25:02 PM UTC 24 |
| Finished | Sep 18 06:25:29 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469571648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3469571648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_noise_filter.4068935774 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 74916557921 ps |
| CPU time | 24.75 seconds |
| Started | Sep 18 06:24:58 PM UTC 24 |
| Finished | Sep 18 06:25:24 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068935774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.4068935774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_perf.3136767422 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 10656724886 ps |
| CPU time | 214.8 seconds |
| Started | Sep 18 06:25:04 PM UTC 24 |
| Finished | Sep 18 06:28:42 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136767422 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3136767422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_rx_oversample.998957289 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 3939391442 ps |
| CPU time | 4.45 seconds |
| Started | Sep 18 06:24:55 PM UTC 24 |
| Finished | Sep 18 06:25:01 PM UTC 24 |
| Peak memory | 207948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998957289 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.998957289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.2270899933 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 130522126791 ps |
| CPU time | 294.01 seconds |
| Started | Sep 18 06:25:00 PM UTC 24 |
| Finished | Sep 18 06:29:57 PM UTC 24 |
| Peak memory | 203868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270899933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2270899933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.1323435465 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1606228423 ps |
| CPU time | 5.92 seconds |
| Started | Sep 18 06:25:00 PM UTC 24 |
| Finished | Sep 18 06:25:07 PM UTC 24 |
| Peak memory | 203516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323435465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1323435465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_smoke.2105783416 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 502954102 ps |
| CPU time | 2.5 seconds |
| Started | Sep 18 06:24:51 PM UTC 24 |
| Finished | Sep 18 06:24:55 PM UTC 24 |
| Peak memory | 208076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105783416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2105783416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_stress_all.1086952082 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 256729949079 ps |
| CPU time | 390.03 seconds |
| Started | Sep 18 06:25:12 PM UTC 24 |
| Finished | Sep 18 06:31:47 PM UTC 24 |
| Peak memory | 205956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086952082 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1086952082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.3809535577 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 4341009435 ps |
| CPU time | 23.43 seconds |
| Started | Sep 18 06:25:09 PM UTC 24 |
| Finished | Sep 18 06:25:34 PM UTC 24 |
| Peak memory | 218556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3809535577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all _with_rand_reset.3809535577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.415134385 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 12519537366 ps |
| CPU time | 25.14 seconds |
| Started | Sep 18 06:25:00 PM UTC 24 |
| Finished | Sep 18 06:25:26 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415134385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.415134385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/21.uart_tx_rx.3239692097 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 91056982886 ps |
| CPU time | 177.54 seconds |
| Started | Sep 18 06:24:52 PM UTC 24 |
| Finished | Sep 18 06:27:52 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239692097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3239692097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/21.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/211.uart_fifo_reset.4031293878 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 14065811146 ps |
| CPU time | 13.39 seconds |
| Started | Sep 18 06:51:42 PM UTC 24 |
| Finished | Sep 18 06:51:57 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031293878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.4031293878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/211.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/212.uart_fifo_reset.1042771093 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 84991031511 ps |
| CPU time | 135.63 seconds |
| Started | Sep 18 06:51:42 PM UTC 24 |
| Finished | Sep 18 06:54:00 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042771093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1042771093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/212.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/213.uart_fifo_reset.2154832816 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 22022836822 ps |
| CPU time | 65.28 seconds |
| Started | Sep 18 06:51:42 PM UTC 24 |
| Finished | Sep 18 06:52:49 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154832816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2154832816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/213.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/214.uart_fifo_reset.3793209727 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 39502430383 ps |
| CPU time | 126.72 seconds |
| Started | Sep 18 06:51:43 PM UTC 24 |
| Finished | Sep 18 06:53:53 PM UTC 24 |
| Peak memory | 209324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793209727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3793209727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/214.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/215.uart_fifo_reset.3496859413 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 106153658768 ps |
| CPU time | 256.26 seconds |
| Started | Sep 18 06:51:45 PM UTC 24 |
| Finished | Sep 18 06:56:06 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496859413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3496859413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/215.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/216.uart_fifo_reset.3133243766 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 65462327152 ps |
| CPU time | 91.5 seconds |
| Started | Sep 18 06:51:49 PM UTC 24 |
| Finished | Sep 18 06:53:23 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133243766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3133243766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/216.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/217.uart_fifo_reset.3337399550 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 137410974494 ps |
| CPU time | 133.05 seconds |
| Started | Sep 18 06:51:50 PM UTC 24 |
| Finished | Sep 18 06:54:06 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337399550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3337399550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/217.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/218.uart_fifo_reset.2160411585 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 26245691858 ps |
| CPU time | 41.41 seconds |
| Started | Sep 18 06:51:52 PM UTC 24 |
| Finished | Sep 18 06:52:34 PM UTC 24 |
| Peak memory | 203764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160411585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2160411585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/218.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/219.uart_fifo_reset.1358681625 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 175180212685 ps |
| CPU time | 118.53 seconds |
| Started | Sep 18 06:51:55 PM UTC 24 |
| Finished | Sep 18 06:53:55 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358681625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1358681625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/219.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_alert_test.1116465230 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 27171644 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 06:25:34 PM UTC 24 |
| Finished | Sep 18 06:25:37 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116465230 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1116465230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.2320928403 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 73114910245 ps |
| CPU time | 116.92 seconds |
| Started | Sep 18 06:25:17 PM UTC 24 |
| Finished | Sep 18 06:27:17 PM UTC 24 |
| Peak memory | 204048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320928403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2320928403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_fifo_reset.489959864 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 51346106507 ps |
| CPU time | 246.7 seconds |
| Started | Sep 18 06:25:19 PM UTC 24 |
| Finished | Sep 18 06:29:29 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489959864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.489959864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_intr.2149718722 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 25565962366 ps |
| CPU time | 54.23 seconds |
| Started | Sep 18 06:25:23 PM UTC 24 |
| Finished | Sep 18 06:26:19 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149718722 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2149718722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.699285676 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 138776293217 ps |
| CPU time | 186.88 seconds |
| Started | Sep 18 06:25:30 PM UTC 24 |
| Finished | Sep 18 06:28:40 PM UTC 24 |
| Peak memory | 206140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699285676 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.699285676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_loopback.457703507 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 8130421002 ps |
| CPU time | 17.73 seconds |
| Started | Sep 18 06:25:29 PM UTC 24 |
| Finished | Sep 18 06:25:48 PM UTC 24 |
| Peak memory | 205880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457703507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 22.uart_loopback.457703507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_noise_filter.2251171812 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 55026444679 ps |
| CPU time | 27.69 seconds |
| Started | Sep 18 06:25:23 PM UTC 24 |
| Finished | Sep 18 06:25:52 PM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251171812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2251171812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_perf.1963768361 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 26351362439 ps |
| CPU time | 210.52 seconds |
| Started | Sep 18 06:25:30 PM UTC 24 |
| Finished | Sep 18 06:29:04 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963768361 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1963768361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_rx_oversample.433345922 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 3081158126 ps |
| CPU time | 26.13 seconds |
| Started | Sep 18 06:25:20 PM UTC 24 |
| Finished | Sep 18 06:25:47 PM UTC 24 |
| Peak memory | 208044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433345922 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.433345922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.2129600115 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 129880903321 ps |
| CPU time | 261.01 seconds |
| Started | Sep 18 06:25:25 PM UTC 24 |
| Finished | Sep 18 06:29:50 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129600115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2129600115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.3274720063 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 5171218953 ps |
| CPU time | 2.71 seconds |
| Started | Sep 18 06:25:24 PM UTC 24 |
| Finished | Sep 18 06:25:28 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274720063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3274720063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_smoke.4272456678 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 261726180 ps |
| CPU time | 2.34 seconds |
| Started | Sep 18 06:25:15 PM UTC 24 |
| Finished | Sep 18 06:25:19 PM UTC 24 |
| Peak memory | 203916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272456678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 22.uart_smoke.4272456678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_stress_all.282546921 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 19491945761 ps |
| CPU time | 12.43 seconds |
| Started | Sep 18 06:25:31 PM UTC 24 |
| Finished | Sep 18 06:25:45 PM UTC 24 |
| Peak memory | 208592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282546921 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.282546921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.1966277357 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 8573905254 ps |
| CPU time | 39.02 seconds |
| Started | Sep 18 06:25:30 PM UTC 24 |
| Finished | Sep 18 06:26:11 PM UTC 24 |
| Peak memory | 225148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1966277357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all _with_rand_reset.1966277357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.2072037358 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 464215153 ps |
| CPU time | 1.68 seconds |
| Started | Sep 18 06:25:27 PM UTC 24 |
| Finished | Sep 18 06:25:30 PM UTC 24 |
| Peak memory | 207240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072037358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2072037358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/22.uart_tx_rx.1984011596 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 28008166325 ps |
| CPU time | 58.71 seconds |
| Started | Sep 18 06:25:15 PM UTC 24 |
| Finished | Sep 18 06:26:16 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984011596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1984011596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/22.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/220.uart_fifo_reset.2866778740 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 101421435056 ps |
| CPU time | 325.47 seconds |
| Started | Sep 18 06:51:58 PM UTC 24 |
| Finished | Sep 18 06:57:28 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866778740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2866778740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/220.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/221.uart_fifo_reset.628264779 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 28643197509 ps |
| CPU time | 77.86 seconds |
| Started | Sep 18 06:51:59 PM UTC 24 |
| Finished | Sep 18 06:53:18 PM UTC 24 |
| Peak memory | 209204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628264779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.628264779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/221.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/222.uart_fifo_reset.356076398 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 202404103408 ps |
| CPU time | 335.62 seconds |
| Started | Sep 18 06:52:01 PM UTC 24 |
| Finished | Sep 18 06:57:41 PM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356076398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.356076398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/222.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/224.uart_fifo_reset.2864876013 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 21698295675 ps |
| CPU time | 51.07 seconds |
| Started | Sep 18 06:52:06 PM UTC 24 |
| Finished | Sep 18 06:52:59 PM UTC 24 |
| Peak memory | 209204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864876013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2864876013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/224.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/225.uart_fifo_reset.960263691 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 107347880418 ps |
| CPU time | 47.95 seconds |
| Started | Sep 18 06:52:06 PM UTC 24 |
| Finished | Sep 18 06:52:55 PM UTC 24 |
| Peak memory | 208984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960263691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.960263691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/225.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/226.uart_fifo_reset.423181966 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 31769712485 ps |
| CPU time | 69.91 seconds |
| Started | Sep 18 06:52:10 PM UTC 24 |
| Finished | Sep 18 06:53:22 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423181966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.423181966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/226.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/227.uart_fifo_reset.3695414103 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 31031470728 ps |
| CPU time | 54.55 seconds |
| Started | Sep 18 06:52:24 PM UTC 24 |
| Finished | Sep 18 06:53:20 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695414103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3695414103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/227.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/228.uart_fifo_reset.911171338 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 38441772493 ps |
| CPU time | 29.69 seconds |
| Started | Sep 18 06:52:27 PM UTC 24 |
| Finished | Sep 18 06:52:58 PM UTC 24 |
| Peak memory | 209220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911171338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.911171338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/228.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/229.uart_fifo_reset.397782800 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 245165451380 ps |
| CPU time | 104.71 seconds |
| Started | Sep 18 06:52:31 PM UTC 24 |
| Finished | Sep 18 06:54:18 PM UTC 24 |
| Peak memory | 209284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397782800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.397782800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/229.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_alert_test.397381835 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 28739942 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 06:25:59 PM UTC 24 |
| Finished | Sep 18 06:26:01 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397381835 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.397381835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_fifo_full.40456919 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 8359410776 ps |
| CPU time | 18.54 seconds |
| Started | Sep 18 06:25:38 PM UTC 24 |
| Finished | Sep 18 06:25:57 PM UTC 24 |
| Peak memory | 203652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40456919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.40456919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.3524523764 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 75574383210 ps |
| CPU time | 14.63 seconds |
| Started | Sep 18 06:25:41 PM UTC 24 |
| Finished | Sep 18 06:25:56 PM UTC 24 |
| Peak memory | 208460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524523764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3524523764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_fifo_reset.1726002162 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 15412595142 ps |
| CPU time | 22.46 seconds |
| Started | Sep 18 06:25:42 PM UTC 24 |
| Finished | Sep 18 06:26:06 PM UTC 24 |
| Peak memory | 204100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726002162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1726002162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_intr.2463789188 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 7964501277 ps |
| CPU time | 9.66 seconds |
| Started | Sep 18 06:25:47 PM UTC 24 |
| Finished | Sep 18 06:25:58 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463789188 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2463789188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.1828753032 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 50490075728 ps |
| CPU time | 346.26 seconds |
| Started | Sep 18 06:25:58 PM UTC 24 |
| Finished | Sep 18 06:31:48 PM UTC 24 |
| Peak memory | 203772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828753032 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1828753032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_loopback.2693302759 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 10896115706 ps |
| CPU time | 11.48 seconds |
| Started | Sep 18 06:25:54 PM UTC 24 |
| Finished | Sep 18 06:26:07 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693302759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2693302759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_noise_filter.3665977484 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 21202708384 ps |
| CPU time | 36.65 seconds |
| Started | Sep 18 06:25:48 PM UTC 24 |
| Finished | Sep 18 06:26:26 PM UTC 24 |
| Peak memory | 209608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665977484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3665977484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_perf.2040560083 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 7737520993 ps |
| CPU time | 211.13 seconds |
| Started | Sep 18 06:25:54 PM UTC 24 |
| Finished | Sep 18 06:29:29 PM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040560083 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2040560083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_rx_oversample.3560060304 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 4959976668 ps |
| CPU time | 9.86 seconds |
| Started | Sep 18 06:25:46 PM UTC 24 |
| Finished | Sep 18 06:25:57 PM UTC 24 |
| Peak memory | 208204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560060304 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3560060304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.1222772357 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 17015249712 ps |
| CPU time | 33 seconds |
| Started | Sep 18 06:25:50 PM UTC 24 |
| Finished | Sep 18 06:26:25 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222772357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1222772357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.138793423 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 3001363095 ps |
| CPU time | 3.61 seconds |
| Started | Sep 18 06:25:49 PM UTC 24 |
| Finished | Sep 18 06:25:54 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138793423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.138793423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_smoke.2747298344 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 251607739 ps |
| CPU time | 2.08 seconds |
| Started | Sep 18 06:25:36 PM UTC 24 |
| Finished | Sep 18 06:25:40 PM UTC 24 |
| Peak memory | 203924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747298344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2747298344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_stress_all.3951040045 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 125443831636 ps |
| CPU time | 970.23 seconds |
| Started | Sep 18 06:25:58 PM UTC 24 |
| Finished | Sep 18 06:42:19 PM UTC 24 |
| Peak memory | 205904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951040045 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3951040045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.3497933719 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 9347412573 ps |
| CPU time | 56.34 seconds |
| Started | Sep 18 06:25:58 PM UTC 24 |
| Finished | Sep 18 06:26:55 PM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3497933719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all _with_rand_reset.3497933719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.3230862887 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1955443186 ps |
| CPU time | 3.55 seconds |
| Started | Sep 18 06:25:52 PM UTC 24 |
| Finished | Sep 18 06:25:57 PM UTC 24 |
| Peak memory | 207880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230862887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3230862887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/23.uart_tx_rx.1623025204 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 58164291561 ps |
| CPU time | 26.44 seconds |
| Started | Sep 18 06:25:38 PM UTC 24 |
| Finished | Sep 18 06:26:05 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623025204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1623025204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/23.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/230.uart_fifo_reset.435264056 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 85880274739 ps |
| CPU time | 63.3 seconds |
| Started | Sep 18 06:52:36 PM UTC 24 |
| Finished | Sep 18 06:53:40 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435264056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.435264056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/230.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/231.uart_fifo_reset.2589976309 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 10166573139 ps |
| CPU time | 25.41 seconds |
| Started | Sep 18 06:52:42 PM UTC 24 |
| Finished | Sep 18 06:53:08 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589976309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2589976309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/231.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/232.uart_fifo_reset.731694908 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 92520397478 ps |
| CPU time | 37.4 seconds |
| Started | Sep 18 06:52:47 PM UTC 24 |
| Finished | Sep 18 06:53:25 PM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731694908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.731694908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/232.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/233.uart_fifo_reset.3275284302 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 102146533702 ps |
| CPU time | 63.07 seconds |
| Started | Sep 18 06:52:48 PM UTC 24 |
| Finished | Sep 18 06:53:52 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275284302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3275284302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/233.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/234.uart_fifo_reset.1685273482 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 37519241094 ps |
| CPU time | 59.55 seconds |
| Started | Sep 18 06:52:50 PM UTC 24 |
| Finished | Sep 18 06:53:51 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685273482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1685273482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/234.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/235.uart_fifo_reset.1460906217 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 309495724238 ps |
| CPU time | 135.05 seconds |
| Started | Sep 18 06:52:56 PM UTC 24 |
| Finished | Sep 18 06:55:13 PM UTC 24 |
| Peak memory | 203768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460906217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1460906217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/235.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/236.uart_fifo_reset.555797193 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 82048199620 ps |
| CPU time | 40.6 seconds |
| Started | Sep 18 06:52:59 PM UTC 24 |
| Finished | Sep 18 06:53:42 PM UTC 24 |
| Peak memory | 204048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555797193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.555797193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/236.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/237.uart_fifo_reset.989883442 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 16544213808 ps |
| CPU time | 27.04 seconds |
| Started | Sep 18 06:52:59 PM UTC 24 |
| Finished | Sep 18 06:53:28 PM UTC 24 |
| Peak memory | 209352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989883442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.989883442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/237.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1514873372 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 51660992082 ps |
| CPU time | 69.8 seconds |
| Started | Sep 18 06:53:09 PM UTC 24 |
| Finished | Sep 18 06:54:21 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514873372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1514873372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/239.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_alert_test.688160650 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 16644066 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 06:26:22 PM UTC 24 |
| Finished | Sep 18 06:26:24 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688160650 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.688160650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_fifo_full.3844303887 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 51272312770 ps |
| CPU time | 44.04 seconds |
| Started | Sep 18 06:26:02 PM UTC 24 |
| Finished | Sep 18 06:26:47 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844303887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3844303887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.3227136671 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 213932016190 ps |
| CPU time | 393.13 seconds |
| Started | Sep 18 06:26:05 PM UTC 24 |
| Finished | Sep 18 06:32:43 PM UTC 24 |
| Peak memory | 203868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227136671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3227136671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_fifo_reset.3036459756 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 8244177798 ps |
| CPU time | 13.82 seconds |
| Started | Sep 18 06:26:06 PM UTC 24 |
| Finished | Sep 18 06:26:21 PM UTC 24 |
| Peak memory | 203712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036459756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3036459756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_intr.1241904737 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 123437811695 ps |
| CPU time | 218.09 seconds |
| Started | Sep 18 06:26:07 PM UTC 24 |
| Finished | Sep 18 06:29:48 PM UTC 24 |
| Peak memory | 204036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241904737 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1241904737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.318398338 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 140227756221 ps |
| CPU time | 1004.15 seconds |
| Started | Sep 18 06:26:20 PM UTC 24 |
| Finished | Sep 18 06:43:15 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318398338 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.318398338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_loopback.3144955564 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 4497396129 ps |
| CPU time | 18.27 seconds |
| Started | Sep 18 06:26:17 PM UTC 24 |
| Finished | Sep 18 06:26:36 PM UTC 24 |
| Peak memory | 204120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144955564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3144955564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_noise_filter.1116974895 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 108772561640 ps |
| CPU time | 291.34 seconds |
| Started | Sep 18 06:26:12 PM UTC 24 |
| Finished | Sep 18 06:31:08 PM UTC 24 |
| Peak memory | 218436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116974895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1116974895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_perf.1934590097 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 8930449046 ps |
| CPU time | 232.38 seconds |
| Started | Sep 18 06:26:20 PM UTC 24 |
| Finished | Sep 18 06:30:15 PM UTC 24 |
| Peak memory | 204160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934590097 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1934590097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_rx_oversample.3133934418 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2622021137 ps |
| CPU time | 20.39 seconds |
| Started | Sep 18 06:26:06 PM UTC 24 |
| Finished | Sep 18 06:26:28 PM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133934418 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3133934418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.1906445629 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 90381923556 ps |
| CPU time | 66.31 seconds |
| Started | Sep 18 06:26:15 PM UTC 24 |
| Finished | Sep 18 06:27:23 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906445629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1906445629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.32856592 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 3104673339 ps |
| CPU time | 3.02 seconds |
| Started | Sep 18 06:26:15 PM UTC 24 |
| Finished | Sep 18 06:26:19 PM UTC 24 |
| Peak memory | 203716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32856592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.32856592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_smoke.3437595573 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 96499720 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 06:25:59 PM UTC 24 |
| Finished | Sep 18 06:26:01 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437595573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3437595573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.2550236547 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 13957253492 ps |
| CPU time | 73.43 seconds |
| Started | Sep 18 06:26:21 PM UTC 24 |
| Finished | Sep 18 06:27:36 PM UTC 24 |
| Peak memory | 224676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2550236547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all _with_rand_reset.2550236547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.1083403229 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1622137440 ps |
| CPU time | 3.54 seconds |
| Started | Sep 18 06:26:16 PM UTC 24 |
| Finished | Sep 18 06:26:20 PM UTC 24 |
| Peak memory | 207880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083403229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1083403229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/24.uart_tx_rx.336983128 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 37547483945 ps |
| CPU time | 94.33 seconds |
| Started | Sep 18 06:26:01 PM UTC 24 |
| Finished | Sep 18 06:27:37 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336983128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.336983128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/24.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/240.uart_fifo_reset.4171284557 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 9680956022 ps |
| CPU time | 15.68 seconds |
| Started | Sep 18 06:53:11 PM UTC 24 |
| Finished | Sep 18 06:53:28 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171284557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.4171284557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/240.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/241.uart_fifo_reset.3449191215 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 70637519622 ps |
| CPU time | 156.34 seconds |
| Started | Sep 18 06:53:19 PM UTC 24 |
| Finished | Sep 18 06:55:59 PM UTC 24 |
| Peak memory | 203904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449191215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3449191215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/241.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/243.uart_fifo_reset.701824854 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 16408485761 ps |
| CPU time | 31.64 seconds |
| Started | Sep 18 06:53:22 PM UTC 24 |
| Finished | Sep 18 06:53:55 PM UTC 24 |
| Peak memory | 208080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701824854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.701824854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/243.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/244.uart_fifo_reset.1891423150 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 24107911841 ps |
| CPU time | 55.9 seconds |
| Started | Sep 18 06:53:23 PM UTC 24 |
| Finished | Sep 18 06:54:20 PM UTC 24 |
| Peak memory | 203856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891423150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1891423150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/244.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3371903395 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 135047458841 ps |
| CPU time | 228.63 seconds |
| Started | Sep 18 06:53:23 PM UTC 24 |
| Finished | Sep 18 06:57:15 PM UTC 24 |
| Peak memory | 203704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371903395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3371903395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/245.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/246.uart_fifo_reset.1455744130 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 162126693425 ps |
| CPU time | 61.14 seconds |
| Started | Sep 18 06:53:24 PM UTC 24 |
| Finished | Sep 18 06:54:26 PM UTC 24 |
| Peak memory | 209240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455744130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1455744130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/246.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/247.uart_fifo_reset.2733558084 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 137703977634 ps |
| CPU time | 61.62 seconds |
| Started | Sep 18 06:53:25 PM UTC 24 |
| Finished | Sep 18 06:54:28 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733558084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2733558084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/247.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3794746034 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 27412043442 ps |
| CPU time | 91.8 seconds |
| Started | Sep 18 06:53:26 PM UTC 24 |
| Finished | Sep 18 06:55:00 PM UTC 24 |
| Peak memory | 209508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794746034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3794746034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/248.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/249.uart_fifo_reset.2800097831 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 37603897450 ps |
| CPU time | 24.3 seconds |
| Started | Sep 18 06:53:28 PM UTC 24 |
| Finished | Sep 18 06:53:54 PM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800097831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2800097831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/249.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_alert_test.2531839984 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 17037780 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 06:27:17 PM UTC 24 |
| Finished | Sep 18 06:27:19 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531839984 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2531839984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_fifo_full.276329040 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 177067322620 ps |
| CPU time | 48.1 seconds |
| Started | Sep 18 06:26:27 PM UTC 24 |
| Finished | Sep 18 06:27:17 PM UTC 24 |
| Peak memory | 209472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276329040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.276329040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.346991689 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 48979116809 ps |
| CPU time | 42.14 seconds |
| Started | Sep 18 06:26:28 PM UTC 24 |
| Finished | Sep 18 06:27:12 PM UTC 24 |
| Peak memory | 203868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346991689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.346991689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_fifo_reset.3433158449 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 37066130194 ps |
| CPU time | 81.75 seconds |
| Started | Sep 18 06:26:28 PM UTC 24 |
| Finished | Sep 18 06:27:52 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433158449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3433158449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_intr.3495705287 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 194272621659 ps |
| CPU time | 399.74 seconds |
| Started | Sep 18 06:26:40 PM UTC 24 |
| Finished | Sep 18 06:33:24 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495705287 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3495705287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.2732515271 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 106986239815 ps |
| CPU time | 178.69 seconds |
| Started | Sep 18 06:27:05 PM UTC 24 |
| Finished | Sep 18 06:30:07 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732515271 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2732515271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_loopback.3332179283 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 6708319290 ps |
| CPU time | 6.57 seconds |
| Started | Sep 18 06:26:56 PM UTC 24 |
| Finished | Sep 18 06:27:04 PM UTC 24 |
| Peak memory | 209616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332179283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3332179283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_noise_filter.1667799813 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 51105784345 ps |
| CPU time | 117.44 seconds |
| Started | Sep 18 06:26:44 PM UTC 24 |
| Finished | Sep 18 06:28:43 PM UTC 24 |
| Peak memory | 209608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667799813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1667799813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_perf.3384567512 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 20257872451 ps |
| CPU time | 604.42 seconds |
| Started | Sep 18 06:27:00 PM UTC 24 |
| Finished | Sep 18 06:37:12 PM UTC 24 |
| Peak memory | 203860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384567512 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3384567512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_rx_oversample.4182452538 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 6013376146 ps |
| CPU time | 15.76 seconds |
| Started | Sep 18 06:26:37 PM UTC 24 |
| Finished | Sep 18 06:26:54 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182452538 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.4182452538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.1028076304 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 70743519720 ps |
| CPU time | 104.33 seconds |
| Started | Sep 18 06:26:49 PM UTC 24 |
| Finished | Sep 18 06:28:35 PM UTC 24 |
| Peak memory | 203856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028076304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1028076304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.494778703 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 49006149931 ps |
| CPU time | 48.24 seconds |
| Started | Sep 18 06:26:48 PM UTC 24 |
| Finished | Sep 18 06:27:37 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494778703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.494778703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_smoke.2617902451 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 453829201 ps |
| CPU time | 1.62 seconds |
| Started | Sep 18 06:26:25 PM UTC 24 |
| Finished | Sep 18 06:26:28 PM UTC 24 |
| Peak memory | 203212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617902451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2617902451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_stress_all.1342593984 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 180022221217 ps |
| CPU time | 756.86 seconds |
| Started | Sep 18 06:27:17 PM UTC 24 |
| Finished | Sep 18 06:40:03 PM UTC 24 |
| Peak memory | 209916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342593984 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1342593984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.590861975 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1494573174 ps |
| CPU time | 54.47 seconds |
| Started | Sep 18 06:27:13 PM UTC 24 |
| Finished | Sep 18 06:28:10 PM UTC 24 |
| Peak memory | 218480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=590861975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all_ with_rand_reset.590861975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.1040207883 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 2441706378 ps |
| CPU time | 3.02 seconds |
| Started | Sep 18 06:26:55 PM UTC 24 |
| Finished | Sep 18 06:26:59 PM UTC 24 |
| Peak memory | 207992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040207883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1040207883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/25.uart_tx_rx.2912925487 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 68403089617 ps |
| CPU time | 122.89 seconds |
| Started | Sep 18 06:26:26 PM UTC 24 |
| Finished | Sep 18 06:28:31 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912925487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2912925487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/25.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/250.uart_fifo_reset.2251215857 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 16057526332 ps |
| CPU time | 25.56 seconds |
| Started | Sep 18 06:53:29 PM UTC 24 |
| Finished | Sep 18 06:53:56 PM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251215857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2251215857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/250.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/251.uart_fifo_reset.1461734139 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 142472281738 ps |
| CPU time | 60.44 seconds |
| Started | Sep 18 06:53:29 PM UTC 24 |
| Finished | Sep 18 06:54:31 PM UTC 24 |
| Peak memory | 209016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461734139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1461734139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/251.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/253.uart_fifo_reset.3326346558 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 49195294105 ps |
| CPU time | 38.72 seconds |
| Started | Sep 18 06:53:37 PM UTC 24 |
| Finished | Sep 18 06:54:17 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326346558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3326346558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/253.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/254.uart_fifo_reset.2742194870 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 104088025936 ps |
| CPU time | 273.63 seconds |
| Started | Sep 18 06:53:39 PM UTC 24 |
| Finished | Sep 18 06:58:16 PM UTC 24 |
| Peak memory | 209616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742194870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2742194870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/254.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/255.uart_fifo_reset.350865679 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 19050992708 ps |
| CPU time | 27.87 seconds |
| Started | Sep 18 06:53:40 PM UTC 24 |
| Finished | Sep 18 06:54:10 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350865679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.350865679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/255.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/256.uart_fifo_reset.1536830178 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 129484866575 ps |
| CPU time | 105.37 seconds |
| Started | Sep 18 06:53:40 PM UTC 24 |
| Finished | Sep 18 06:55:28 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536830178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1536830178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/256.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/257.uart_fifo_reset.2438268536 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 177808818538 ps |
| CPU time | 59.25 seconds |
| Started | Sep 18 06:53:41 PM UTC 24 |
| Finished | Sep 18 06:54:42 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438268536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2438268536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/257.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/258.uart_fifo_reset.1479246675 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 47934374758 ps |
| CPU time | 38.77 seconds |
| Started | Sep 18 06:53:42 PM UTC 24 |
| Finished | Sep 18 06:54:22 PM UTC 24 |
| Peak memory | 203908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479246675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1479246675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/258.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/259.uart_fifo_reset.3648885214 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 102677883992 ps |
| CPU time | 104.64 seconds |
| Started | Sep 18 06:53:43 PM UTC 24 |
| Finished | Sep 18 06:55:29 PM UTC 24 |
| Peak memory | 209580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648885214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3648885214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/259.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_alert_test.2382517635 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 91342350 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 06:28:19 PM UTC 24 |
| Finished | Sep 18 06:28:21 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382517635 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2382517635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_fifo_full.3816793804 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 304945485790 ps |
| CPU time | 172.21 seconds |
| Started | Sep 18 06:27:25 PM UTC 24 |
| Finished | Sep 18 06:30:20 PM UTC 24 |
| Peak memory | 209508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816793804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3816793804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.3707403400 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 87519644718 ps |
| CPU time | 61.83 seconds |
| Started | Sep 18 06:27:32 PM UTC 24 |
| Finished | Sep 18 06:28:35 PM UTC 24 |
| Peak memory | 209356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707403400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3707403400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_fifo_reset.4109547546 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 41231065864 ps |
| CPU time | 41.2 seconds |
| Started | Sep 18 06:27:36 PM UTC 24 |
| Finished | Sep 18 06:28:18 PM UTC 24 |
| Peak memory | 203984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109547546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.4109547546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_intr.1755079832 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 73974531907 ps |
| CPU time | 55.01 seconds |
| Started | Sep 18 06:27:38 PM UTC 24 |
| Finished | Sep 18 06:28:34 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755079832 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1755079832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.1925891546 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 148916027281 ps |
| CPU time | 1287.6 seconds |
| Started | Sep 18 06:27:57 PM UTC 24 |
| Finished | Sep 18 06:49:39 PM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925891546 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1925891546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_loopback.3805242147 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 2039197303 ps |
| CPU time | 3.33 seconds |
| Started | Sep 18 06:27:52 PM UTC 24 |
| Finished | Sep 18 06:27:57 PM UTC 24 |
| Peak memory | 203800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805242147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3805242147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_noise_filter.4249656609 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 208919399157 ps |
| CPU time | 103.61 seconds |
| Started | Sep 18 06:27:38 PM UTC 24 |
| Finished | Sep 18 06:29:24 PM UTC 24 |
| Peak memory | 209924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249656609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.4249656609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_perf.168970994 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 17116276507 ps |
| CPU time | 201.02 seconds |
| Started | Sep 18 06:27:53 PM UTC 24 |
| Finished | Sep 18 06:31:18 PM UTC 24 |
| Peak memory | 209468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168970994 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.168970994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_rx_oversample.1327529807 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 5067391089 ps |
| CPU time | 10.06 seconds |
| Started | Sep 18 06:27:37 PM UTC 24 |
| Finished | Sep 18 06:27:48 PM UTC 24 |
| Peak memory | 208320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327529807 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1327529807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.1139116186 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 82737272776 ps |
| CPU time | 165.95 seconds |
| Started | Sep 18 06:27:49 PM UTC 24 |
| Finished | Sep 18 06:30:38 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139116186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1139116186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.1541752487 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1770329197 ps |
| CPU time | 6.37 seconds |
| Started | Sep 18 06:27:43 PM UTC 24 |
| Finished | Sep 18 06:27:50 PM UTC 24 |
| Peak memory | 203516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541752487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1541752487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_smoke.912725052 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 5738393929 ps |
| CPU time | 8.93 seconds |
| Started | Sep 18 06:27:20 PM UTC 24 |
| Finished | Sep 18 06:27:31 PM UTC 24 |
| Peak memory | 204116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912725052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 26.uart_smoke.912725052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_stress_all.968821201 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 343295672844 ps |
| CPU time | 400.08 seconds |
| Started | Sep 18 06:28:15 PM UTC 24 |
| Finished | Sep 18 06:34:59 PM UTC 24 |
| Peak memory | 218768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968821201 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.968821201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.2735079301 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 9895934738 ps |
| CPU time | 67.31 seconds |
| Started | Sep 18 06:28:11 PM UTC 24 |
| Finished | Sep 18 06:29:20 PM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2735079301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all _with_rand_reset.2735079301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.2639831508 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 6781894142 ps |
| CPU time | 20.92 seconds |
| Started | Sep 18 06:27:51 PM UTC 24 |
| Finished | Sep 18 06:28:13 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639831508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2639831508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/26.uart_tx_rx.1006016896 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 26863240196 ps |
| CPU time | 18.21 seconds |
| Started | Sep 18 06:27:22 PM UTC 24 |
| Finished | Sep 18 06:27:42 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006016896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1006016896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/26.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/261.uart_fifo_reset.2373154933 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 225889587576 ps |
| CPU time | 75.31 seconds |
| Started | Sep 18 06:53:49 PM UTC 24 |
| Finished | Sep 18 06:55:06 PM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373154933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2373154933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/261.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/262.uart_fifo_reset.4078722711 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 48362364715 ps |
| CPU time | 34.2 seconds |
| Started | Sep 18 06:53:52 PM UTC 24 |
| Finished | Sep 18 06:54:27 PM UTC 24 |
| Peak memory | 207672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078722711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.4078722711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/262.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/263.uart_fifo_reset.1128457636 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 99699955742 ps |
| CPU time | 162.1 seconds |
| Started | Sep 18 06:53:53 PM UTC 24 |
| Finished | Sep 18 06:56:38 PM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128457636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1128457636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/263.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/264.uart_fifo_reset.4114889885 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 83630927962 ps |
| CPU time | 169.96 seconds |
| Started | Sep 18 06:53:53 PM UTC 24 |
| Finished | Sep 18 06:56:46 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114889885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.4114889885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/264.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/265.uart_fifo_reset.700645659 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 105236249438 ps |
| CPU time | 140.4 seconds |
| Started | Sep 18 06:53:54 PM UTC 24 |
| Finished | Sep 18 06:56:17 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700645659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.700645659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/265.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/266.uart_fifo_reset.1224251898 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 209900510154 ps |
| CPU time | 325.24 seconds |
| Started | Sep 18 06:53:55 PM UTC 24 |
| Finished | Sep 18 06:59:25 PM UTC 24 |
| Peak memory | 210592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224251898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1224251898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/266.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/267.uart_fifo_reset.1954730681 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 75994242487 ps |
| CPU time | 43.24 seconds |
| Started | Sep 18 06:53:55 PM UTC 24 |
| Finished | Sep 18 06:54:40 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954730681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1954730681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/267.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/268.uart_fifo_reset.273146947 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 82305069788 ps |
| CPU time | 50.96 seconds |
| Started | Sep 18 06:53:55 PM UTC 24 |
| Finished | Sep 18 06:54:48 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273146947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.273146947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/268.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/269.uart_fifo_reset.626823971 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 18656241954 ps |
| CPU time | 26.38 seconds |
| Started | Sep 18 06:53:56 PM UTC 24 |
| Finished | Sep 18 06:54:24 PM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626823971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.626823971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/269.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_alert_test.1383768457 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 12212457 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 06:29:05 PM UTC 24 |
| Finished | Sep 18 06:29:07 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383768457 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1383768457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_fifo_full.4045707630 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 180814722600 ps |
| CPU time | 872.11 seconds |
| Started | Sep 18 06:28:24 PM UTC 24 |
| Finished | Sep 18 06:43:06 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045707630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.4045707630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.2858091206 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 286674159487 ps |
| CPU time | 89.12 seconds |
| Started | Sep 18 06:28:32 PM UTC 24 |
| Finished | Sep 18 06:30:04 PM UTC 24 |
| Peak memory | 204060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858091206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2858091206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_intr.929790499 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 32471603157 ps |
| CPU time | 91.81 seconds |
| Started | Sep 18 06:28:35 PM UTC 24 |
| Finished | Sep 18 06:30:09 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929790499 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.929790499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.848295876 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 97010765010 ps |
| CPU time | 722.5 seconds |
| Started | Sep 18 06:28:50 PM UTC 24 |
| Finished | Sep 18 06:41:01 PM UTC 24 |
| Peak memory | 206144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848295876 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.848295876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_loopback.622240576 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1702483704 ps |
| CPU time | 6.07 seconds |
| Started | Sep 18 06:28:45 PM UTC 24 |
| Finished | Sep 18 06:28:52 PM UTC 24 |
| Peak memory | 207864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622240576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 27.uart_loopback.622240576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_noise_filter.3094350317 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 133556677776 ps |
| CPU time | 114.89 seconds |
| Started | Sep 18 06:28:36 PM UTC 24 |
| Finished | Sep 18 06:30:34 PM UTC 24 |
| Peak memory | 220492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094350317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3094350317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_perf.1656144468 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 17276201573 ps |
| CPU time | 401.18 seconds |
| Started | Sep 18 06:28:49 PM UTC 24 |
| Finished | Sep 18 06:35:35 PM UTC 24 |
| Peak memory | 204036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656144468 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1656144468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_rx_oversample.4260612943 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 2970092540 ps |
| CPU time | 24.24 seconds |
| Started | Sep 18 06:28:35 PM UTC 24 |
| Finished | Sep 18 06:29:01 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260612943 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4260612943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.3646109796 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 78123994618 ps |
| CPU time | 34.06 seconds |
| Started | Sep 18 06:28:43 PM UTC 24 |
| Finished | Sep 18 06:29:18 PM UTC 24 |
| Peak memory | 209456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646109796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3646109796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.1286946449 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 5633227057 ps |
| CPU time | 1.9 seconds |
| Started | Sep 18 06:28:40 PM UTC 24 |
| Finished | Sep 18 06:28:44 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286946449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1286946449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_smoke.1217890267 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 864397684 ps |
| CPU time | 2.8 seconds |
| Started | Sep 18 06:28:19 PM UTC 24 |
| Finished | Sep 18 06:28:23 PM UTC 24 |
| Peak memory | 203660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217890267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1217890267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_stress_all.1467720703 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 215459957207 ps |
| CPU time | 674.22 seconds |
| Started | Sep 18 06:29:02 PM UTC 24 |
| Finished | Sep 18 06:40:24 PM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467720703 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1467720703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.463219855 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 18558428490 ps |
| CPU time | 79.26 seconds |
| Started | Sep 18 06:28:53 PM UTC 24 |
| Finished | Sep 18 06:30:14 PM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=463219855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all_ with_rand_reset.463219855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.3901802299 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1697661395 ps |
| CPU time | 3.15 seconds |
| Started | Sep 18 06:28:44 PM UTC 24 |
| Finished | Sep 18 06:28:48 PM UTC 24 |
| Peak memory | 207928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901802299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3901802299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/27.uart_tx_rx.3388089140 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 17092326345 ps |
| CPU time | 25.89 seconds |
| Started | Sep 18 06:28:22 PM UTC 24 |
| Finished | Sep 18 06:28:49 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388089140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3388089140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/27.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/270.uart_fifo_reset.602474017 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 138884309270 ps |
| CPU time | 207.64 seconds |
| Started | Sep 18 06:53:56 PM UTC 24 |
| Finished | Sep 18 06:57:27 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602474017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.602474017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/270.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/271.uart_fifo_reset.477257611 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 13017936925 ps |
| CPU time | 32.01 seconds |
| Started | Sep 18 06:54:01 PM UTC 24 |
| Finished | Sep 18 06:54:35 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477257611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.477257611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/271.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/272.uart_fifo_reset.1576019206 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 205236487168 ps |
| CPU time | 27.37 seconds |
| Started | Sep 18 06:54:03 PM UTC 24 |
| Finished | Sep 18 06:54:31 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576019206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1576019206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/272.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/273.uart_fifo_reset.2461790297 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 195270825400 ps |
| CPU time | 51.37 seconds |
| Started | Sep 18 06:54:03 PM UTC 24 |
| Finished | Sep 18 06:54:56 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461790297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2461790297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/273.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/274.uart_fifo_reset.324081374 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 12427677200 ps |
| CPU time | 26.51 seconds |
| Started | Sep 18 06:54:07 PM UTC 24 |
| Finished | Sep 18 06:54:35 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324081374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.324081374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/274.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/276.uart_fifo_reset.2867296656 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 128586673538 ps |
| CPU time | 206.01 seconds |
| Started | Sep 18 06:54:10 PM UTC 24 |
| Finished | Sep 18 06:57:39 PM UTC 24 |
| Peak memory | 209156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867296656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2867296656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/276.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/277.uart_fifo_reset.687459990 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 52950635732 ps |
| CPU time | 97.72 seconds |
| Started | Sep 18 06:54:16 PM UTC 24 |
| Finished | Sep 18 06:55:56 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687459990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.687459990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/277.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_alert_test.3909533596 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 16066403 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 06:29:49 PM UTC 24 |
| Finished | Sep 18 06:29:51 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909533596 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3909533596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_fifo_full.1130968598 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 12099888354 ps |
| CPU time | 17.26 seconds |
| Started | Sep 18 06:29:08 PM UTC 24 |
| Finished | Sep 18 06:29:28 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130968598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1130968598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.3948704413 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 66111142409 ps |
| CPU time | 83.03 seconds |
| Started | Sep 18 06:29:19 PM UTC 24 |
| Finished | Sep 18 06:30:44 PM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948704413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3948704413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_intr.1726956911 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 43329126836 ps |
| CPU time | 22.92 seconds |
| Started | Sep 18 06:29:22 PM UTC 24 |
| Finished | Sep 18 06:29:46 PM UTC 24 |
| Peak memory | 208136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726956911 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1726956911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.1764445350 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 119596300960 ps |
| CPU time | 370.9 seconds |
| Started | Sep 18 06:29:34 PM UTC 24 |
| Finished | Sep 18 06:35:50 PM UTC 24 |
| Peak memory | 204088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764445350 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1764445350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_loopback.61220626 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 11994624353 ps |
| CPU time | 15.81 seconds |
| Started | Sep 18 06:29:30 PM UTC 24 |
| Finished | Sep 18 06:29:47 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61220626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 28.uart_loopback.61220626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_noise_filter.325157061 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 217195675859 ps |
| CPU time | 50.69 seconds |
| Started | Sep 18 06:29:24 PM UTC 24 |
| Finished | Sep 18 06:30:16 PM UTC 24 |
| Peak memory | 220828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325157061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.325157061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_perf.1702339578 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 9065118941 ps |
| CPU time | 610.37 seconds |
| Started | Sep 18 06:29:31 PM UTC 24 |
| Finished | Sep 18 06:39:49 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702339578 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1702339578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_rx_oversample.352320881 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 6829812209 ps |
| CPU time | 47.68 seconds |
| Started | Sep 18 06:29:21 PM UTC 24 |
| Finished | Sep 18 06:30:10 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352320881 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.352320881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.3831584834 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 251582572045 ps |
| CPU time | 49.52 seconds |
| Started | Sep 18 06:29:29 PM UTC 24 |
| Finished | Sep 18 06:30:20 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831584834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3831584834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.1111222292 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 5358809167 ps |
| CPU time | 4.56 seconds |
| Started | Sep 18 06:29:25 PM UTC 24 |
| Finished | Sep 18 06:29:30 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111222292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1111222292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_smoke.3554067830 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 137099537 ps |
| CPU time | 1.43 seconds |
| Started | Sep 18 06:29:05 PM UTC 24 |
| Finished | Sep 18 06:29:08 PM UTC 24 |
| Peak memory | 203268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554067830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3554067830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_stress_all.4045117638 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1146795304711 ps |
| CPU time | 238.04 seconds |
| Started | Sep 18 06:29:47 PM UTC 24 |
| Finished | Sep 18 06:33:49 PM UTC 24 |
| Peak memory | 207876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045117638 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.4045117638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.2154613262 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 21081620649 ps |
| CPU time | 144.82 seconds |
| Started | Sep 18 06:29:46 PM UTC 24 |
| Finished | Sep 18 06:32:14 PM UTC 24 |
| Peak memory | 226096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2154613262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all _with_rand_reset.2154613262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.797363454 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 307933010 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 06:29:30 PM UTC 24 |
| Finished | Sep 18 06:29:33 PM UTC 24 |
| Peak memory | 205292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797363454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.797363454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/28.uart_tx_rx.1793132514 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 101262467376 ps |
| CPU time | 42.23 seconds |
| Started | Sep 18 06:29:08 PM UTC 24 |
| Finished | Sep 18 06:29:52 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793132514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1793132514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/28.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/280.uart_fifo_reset.4003515674 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 18404516871 ps |
| CPU time | 53.46 seconds |
| Started | Sep 18 06:54:19 PM UTC 24 |
| Finished | Sep 18 06:55:14 PM UTC 24 |
| Peak memory | 209444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003515674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.4003515674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/280.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/281.uart_fifo_reset.2628272389 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 17915659127 ps |
| CPU time | 45.35 seconds |
| Started | Sep 18 06:54:21 PM UTC 24 |
| Finished | Sep 18 06:55:08 PM UTC 24 |
| Peak memory | 209064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628272389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2628272389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/281.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/282.uart_fifo_reset.1632883549 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 123604034300 ps |
| CPU time | 225.94 seconds |
| Started | Sep 18 06:54:21 PM UTC 24 |
| Finished | Sep 18 06:58:10 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632883549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1632883549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/282.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/283.uart_fifo_reset.3930388469 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 230122904231 ps |
| CPU time | 215.73 seconds |
| Started | Sep 18 06:54:22 PM UTC 24 |
| Finished | Sep 18 06:58:01 PM UTC 24 |
| Peak memory | 204044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930388469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3930388469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/283.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/284.uart_fifo_reset.2224275994 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 7339259843 ps |
| CPU time | 15.52 seconds |
| Started | Sep 18 06:54:22 PM UTC 24 |
| Finished | Sep 18 06:54:39 PM UTC 24 |
| Peak memory | 209648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224275994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2224275994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/284.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/285.uart_fifo_reset.2708548089 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 128428789394 ps |
| CPU time | 78.37 seconds |
| Started | Sep 18 06:54:25 PM UTC 24 |
| Finished | Sep 18 06:55:45 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708548089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2708548089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/285.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/286.uart_fifo_reset.2953197944 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 47712962407 ps |
| CPU time | 44.22 seconds |
| Started | Sep 18 06:54:28 PM UTC 24 |
| Finished | Sep 18 06:55:14 PM UTC 24 |
| Peak memory | 203856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953197944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2953197944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/286.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/287.uart_fifo_reset.3149938910 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 219928444065 ps |
| CPU time | 60.68 seconds |
| Started | Sep 18 06:54:28 PM UTC 24 |
| Finished | Sep 18 06:55:30 PM UTC 24 |
| Peak memory | 209596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149938910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3149938910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/287.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/288.uart_fifo_reset.3380245249 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 29920719783 ps |
| CPU time | 81.46 seconds |
| Started | Sep 18 06:54:29 PM UTC 24 |
| Finished | Sep 18 06:55:52 PM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380245249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3380245249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/288.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/289.uart_fifo_reset.1545653884 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 57832068663 ps |
| CPU time | 57.19 seconds |
| Started | Sep 18 06:54:32 PM UTC 24 |
| Finished | Sep 18 06:55:31 PM UTC 24 |
| Peak memory | 209052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545653884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1545653884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/289.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_alert_test.1153189377 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 13520186 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:30:27 PM UTC 24 |
| Finished | Sep 18 06:30:29 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153189377 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1153189377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_fifo_full.1694932201 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 59859542086 ps |
| CPU time | 31.95 seconds |
| Started | Sep 18 06:29:53 PM UTC 24 |
| Finished | Sep 18 06:30:26 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694932201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1694932201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.3420030422 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 265628293504 ps |
| CPU time | 251.73 seconds |
| Started | Sep 18 06:29:57 PM UTC 24 |
| Finished | Sep 18 06:34:12 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420030422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3420030422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_fifo_reset.3763527434 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 187690651551 ps |
| CPU time | 225.16 seconds |
| Started | Sep 18 06:29:58 PM UTC 24 |
| Finished | Sep 18 06:33:46 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763527434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3763527434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_intr.2003187341 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 136871899183 ps |
| CPU time | 115.91 seconds |
| Started | Sep 18 06:30:04 PM UTC 24 |
| Finished | Sep 18 06:32:02 PM UTC 24 |
| Peak memory | 207928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003187341 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2003187341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.694820456 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 94852347257 ps |
| CPU time | 776.15 seconds |
| Started | Sep 18 06:30:18 PM UTC 24 |
| Finished | Sep 18 06:43:23 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694820456 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.694820456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_loopback.2193189450 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 9535631650 ps |
| CPU time | 34.63 seconds |
| Started | Sep 18 06:30:16 PM UTC 24 |
| Finished | Sep 18 06:30:53 PM UTC 24 |
| Peak memory | 208376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193189450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2193189450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_noise_filter.2068404111 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 129707385230 ps |
| CPU time | 73.08 seconds |
| Started | Sep 18 06:30:07 PM UTC 24 |
| Finished | Sep 18 06:31:22 PM UTC 24 |
| Peak memory | 220684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068404111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2068404111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_perf.1648276371 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 14764563544 ps |
| CPU time | 442.46 seconds |
| Started | Sep 18 06:30:16 PM UTC 24 |
| Finished | Sep 18 06:37:45 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648276371 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1648276371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_rx_oversample.3127112845 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 4017478922 ps |
| CPU time | 12.76 seconds |
| Started | Sep 18 06:30:03 PM UTC 24 |
| Finished | Sep 18 06:30:17 PM UTC 24 |
| Peak memory | 207948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127112845 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3127112845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.2372249098 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 28935834814 ps |
| CPU time | 45.21 seconds |
| Started | Sep 18 06:30:10 PM UTC 24 |
| Finished | Sep 18 06:30:57 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372249098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2372249098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.2852395405 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 40884489139 ps |
| CPU time | 72 seconds |
| Started | Sep 18 06:30:10 PM UTC 24 |
| Finished | Sep 18 06:31:24 PM UTC 24 |
| Peak memory | 203504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852395405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2852395405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_smoke.258253917 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 534607471 ps |
| CPU time | 4.09 seconds |
| Started | Sep 18 06:29:51 PM UTC 24 |
| Finished | Sep 18 06:29:56 PM UTC 24 |
| Peak memory | 203860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258253917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 29.uart_smoke.258253917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_stress_all.2027065562 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 383867278899 ps |
| CPU time | 798.94 seconds |
| Started | Sep 18 06:30:21 PM UTC 24 |
| Finished | Sep 18 06:43:48 PM UTC 24 |
| Peak memory | 206084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027065562 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2027065562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.4236724080 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 7248186834 ps |
| CPU time | 59.92 seconds |
| Started | Sep 18 06:30:21 PM UTC 24 |
| Finished | Sep 18 06:31:22 PM UTC 24 |
| Peak memory | 218896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4236724080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all _with_rand_reset.4236724080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.3938149712 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 6136489332 ps |
| CPU time | 25.36 seconds |
| Started | Sep 18 06:30:15 PM UTC 24 |
| Finished | Sep 18 06:30:43 PM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938149712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3938149712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/29.uart_tx_rx.4098379986 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 16322693393 ps |
| CPU time | 47.99 seconds |
| Started | Sep 18 06:29:52 PM UTC 24 |
| Finished | Sep 18 06:30:41 PM UTC 24 |
| Peak memory | 204100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098379986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.4098379986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/29.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2855709852 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 11044014239 ps |
| CPU time | 25.06 seconds |
| Started | Sep 18 06:54:32 PM UTC 24 |
| Finished | Sep 18 06:54:58 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855709852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2855709852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/290.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/291.uart_fifo_reset.3762968133 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 65465829768 ps |
| CPU time | 47.93 seconds |
| Started | Sep 18 06:54:34 PM UTC 24 |
| Finished | Sep 18 06:55:24 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762968133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3762968133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/291.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/292.uart_fifo_reset.4204768301 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 107580154122 ps |
| CPU time | 145.24 seconds |
| Started | Sep 18 06:54:35 PM UTC 24 |
| Finished | Sep 18 06:57:03 PM UTC 24 |
| Peak memory | 203828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204768301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4204768301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/292.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/293.uart_fifo_reset.77126830 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 26398361064 ps |
| CPU time | 51.84 seconds |
| Started | Sep 18 06:54:36 PM UTC 24 |
| Finished | Sep 18 06:55:30 PM UTC 24 |
| Peak memory | 204124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77126830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.77126830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/293.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/294.uart_fifo_reset.2314979979 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 98697935937 ps |
| CPU time | 32.4 seconds |
| Started | Sep 18 06:54:40 PM UTC 24 |
| Finished | Sep 18 06:55:14 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314979979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2314979979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/294.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/295.uart_fifo_reset.391402977 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 134626707992 ps |
| CPU time | 111.83 seconds |
| Started | Sep 18 06:54:40 PM UTC 24 |
| Finished | Sep 18 06:56:34 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391402977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.391402977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/295.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/296.uart_fifo_reset.420540998 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 150840855605 ps |
| CPU time | 318.88 seconds |
| Started | Sep 18 06:54:43 PM UTC 24 |
| Finished | Sep 18 07:00:07 PM UTC 24 |
| Peak memory | 212716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420540998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.420540998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/296.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/297.uart_fifo_reset.299732367 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 96717345801 ps |
| CPU time | 41.11 seconds |
| Started | Sep 18 06:54:48 PM UTC 24 |
| Finished | Sep 18 06:55:31 PM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299732367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.299732367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/297.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/298.uart_fifo_reset.643129233 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 198821480727 ps |
| CPU time | 83.23 seconds |
| Started | Sep 18 06:54:51 PM UTC 24 |
| Finished | Sep 18 06:56:16 PM UTC 24 |
| Peak memory | 208232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643129233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.643129233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/298.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/299.uart_fifo_reset.3939913387 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 103407835160 ps |
| CPU time | 44.17 seconds |
| Started | Sep 18 06:54:56 PM UTC 24 |
| Finished | Sep 18 06:55:42 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939913387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3939913387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/299.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_alert_test.473621878 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 13802836 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:16:28 PM UTC 24 |
| Finished | Sep 18 06:16:30 PM UTC 24 |
| Peak memory | 203120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473621878 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.473621878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_fifo_full.2236076977 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 51272108386 ps |
| CPU time | 90.37 seconds |
| Started | Sep 18 06:16:12 PM UTC 24 |
| Finished | Sep 18 06:17:44 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236076977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2236076977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_fifo_reset.2713669102 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 106226825930 ps |
| CPU time | 247.6 seconds |
| Started | Sep 18 06:16:18 PM UTC 24 |
| Finished | Sep 18 06:20:29 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713669102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2713669102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_intr.508175843 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 174935099586 ps |
| CPU time | 228.75 seconds |
| Started | Sep 18 06:16:19 PM UTC 24 |
| Finished | Sep 18 06:20:11 PM UTC 24 |
| Peak memory | 203708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508175843 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.508175843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_loopback.3400296445 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 3748487394 ps |
| CPU time | 9.47 seconds |
| Started | Sep 18 06:16:23 PM UTC 24 |
| Finished | Sep 18 06:16:34 PM UTC 24 |
| Peak memory | 208868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400296445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3400296445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_noise_filter.716474254 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 161747176198 ps |
| CPU time | 30.75 seconds |
| Started | Sep 18 06:16:19 PM UTC 24 |
| Finished | Sep 18 06:16:51 PM UTC 24 |
| Peak memory | 209072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716474254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.716474254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_perf.2428802095 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 17594534768 ps |
| CPU time | 872.6 seconds |
| Started | Sep 18 06:16:23 PM UTC 24 |
| Finished | Sep 18 06:31:06 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428802095 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2428802095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_rx_oversample.1956623822 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1383260841 ps |
| CPU time | 2.59 seconds |
| Started | Sep 18 06:16:19 PM UTC 24 |
| Finished | Sep 18 06:16:23 PM UTC 24 |
| Peak memory | 207600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956623822 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1956623822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.1274398085 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 57131236678 ps |
| CPU time | 17.87 seconds |
| Started | Sep 18 06:16:21 PM UTC 24 |
| Finished | Sep 18 06:16:40 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274398085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1274398085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.169738135 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 5161633546 ps |
| CPU time | 5.07 seconds |
| Started | Sep 18 06:16:21 PM UTC 24 |
| Finished | Sep 18 06:16:27 PM UTC 24 |
| Peak memory | 203524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169738135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.169738135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_sec_cm.3398774604 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 185901950 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 06:16:27 PM UTC 24 |
| Finished | Sep 18 06:16:29 PM UTC 24 |
| Peak memory | 237808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398774604 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3398774604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_smoke.1060613033 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 931011566 ps |
| CPU time | 6.03 seconds |
| Started | Sep 18 06:16:10 PM UTC 24 |
| Finished | Sep 18 06:16:18 PM UTC 24 |
| Peak memory | 207824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060613033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1060613033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.317140054 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4923214496 ps |
| CPU time | 50.09 seconds |
| Started | Sep 18 06:16:24 PM UTC 24 |
| Finished | Sep 18 06:17:15 PM UTC 24 |
| Peak memory | 220616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=317140054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_w ith_rand_reset.317140054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.3899647392 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 463927844 ps |
| CPU time | 3.73 seconds |
| Started | Sep 18 06:16:22 PM UTC 24 |
| Finished | Sep 18 06:16:27 PM UTC 24 |
| Peak memory | 203644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899647392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3899647392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/3.uart_tx_rx.574352719 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 48295180848 ps |
| CPU time | 144.2 seconds |
| Started | Sep 18 06:16:11 PM UTC 24 |
| Finished | Sep 18 06:18:38 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574352719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.574352719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/3.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_alert_test.1758563375 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 34986071 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:31:18 PM UTC 24 |
| Finished | Sep 18 06:31:20 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758563375 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1758563375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_fifo_full.2910522431 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 71836897665 ps |
| CPU time | 145.52 seconds |
| Started | Sep 18 06:30:35 PM UTC 24 |
| Finished | Sep 18 06:33:03 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910522431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2910522431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.1092617912 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 28630063208 ps |
| CPU time | 60.81 seconds |
| Started | Sep 18 06:30:38 PM UTC 24 |
| Finished | Sep 18 06:31:41 PM UTC 24 |
| Peak memory | 203984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092617912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1092617912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_fifo_reset.233371077 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 45792998189 ps |
| CPU time | 17.11 seconds |
| Started | Sep 18 06:30:38 PM UTC 24 |
| Finished | Sep 18 06:30:56 PM UTC 24 |
| Peak memory | 204184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233371077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.233371077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_intr.3610401830 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 48292674805 ps |
| CPU time | 48.25 seconds |
| Started | Sep 18 06:30:43 PM UTC 24 |
| Finished | Sep 18 06:31:33 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610401830 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3610401830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.4146017286 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 79598297690 ps |
| CPU time | 461.63 seconds |
| Started | Sep 18 06:31:09 PM UTC 24 |
| Finished | Sep 18 06:38:56 PM UTC 24 |
| Peak memory | 209324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146017286 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.4146017286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_loopback.2552426418 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 3500528925 ps |
| CPU time | 4.9 seconds |
| Started | Sep 18 06:31:05 PM UTC 24 |
| Finished | Sep 18 06:31:11 PM UTC 24 |
| Peak memory | 207604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552426418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2552426418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_noise_filter.1354457330 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 11238152193 ps |
| CPU time | 36.98 seconds |
| Started | Sep 18 06:30:45 PM UTC 24 |
| Finished | Sep 18 06:31:24 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354457330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1354457330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_perf.254362522 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 8206042565 ps |
| CPU time | 609.17 seconds |
| Started | Sep 18 06:31:07 PM UTC 24 |
| Finished | Sep 18 06:41:23 PM UTC 24 |
| Peak memory | 203704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254362522 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.254362522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_rx_oversample.200344465 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 2445292024 ps |
| CPU time | 20.39 seconds |
| Started | Sep 18 06:30:42 PM UTC 24 |
| Finished | Sep 18 06:31:04 PM UTC 24 |
| Peak memory | 208360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200344465 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.200344465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.3306593609 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 80920350080 ps |
| CPU time | 45.55 seconds |
| Started | Sep 18 06:30:58 PM UTC 24 |
| Finished | Sep 18 06:31:44 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306593609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3306593609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.3319299182 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 39440050873 ps |
| CPU time | 41.37 seconds |
| Started | Sep 18 06:30:53 PM UTC 24 |
| Finished | Sep 18 06:31:36 PM UTC 24 |
| Peak memory | 203836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319299182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3319299182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_smoke.1377752881 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 288668803 ps |
| CPU time | 2.37 seconds |
| Started | Sep 18 06:30:30 PM UTC 24 |
| Finished | Sep 18 06:30:33 PM UTC 24 |
| Peak memory | 207816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377752881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1377752881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_stress_all.1026242059 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 186030766423 ps |
| CPU time | 741.77 seconds |
| Started | Sep 18 06:31:11 PM UTC 24 |
| Finished | Sep 18 06:43:41 PM UTC 24 |
| Peak memory | 218496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026242059 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1026242059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.202501143 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 17991336785 ps |
| CPU time | 75.8 seconds |
| Started | Sep 18 06:31:09 PM UTC 24 |
| Finished | Sep 18 06:32:27 PM UTC 24 |
| Peak memory | 225772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=202501143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all_ with_rand_reset.202501143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.827923654 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 7189883905 ps |
| CPU time | 18.67 seconds |
| Started | Sep 18 06:30:58 PM UTC 24 |
| Finished | Sep 18 06:31:17 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827923654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.827923654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/30.uart_tx_rx.180108203 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 12793142165 ps |
| CPU time | 32.49 seconds |
| Started | Sep 18 06:30:34 PM UTC 24 |
| Finished | Sep 18 06:31:08 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180108203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.180108203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/30.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_alert_test.2140018605 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 14382257 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 06:31:46 PM UTC 24 |
| Finished | Sep 18 06:31:48 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140018605 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2140018605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_fifo_full.184854486 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 23087771749 ps |
| CPU time | 43.92 seconds |
| Started | Sep 18 06:31:21 PM UTC 24 |
| Finished | Sep 18 06:32:07 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184854486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.184854486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.2404637967 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 20006666690 ps |
| CPU time | 102.95 seconds |
| Started | Sep 18 06:31:23 PM UTC 24 |
| Finished | Sep 18 06:33:09 PM UTC 24 |
| Peak memory | 203868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404637967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2404637967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_fifo_reset.1413632065 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 33740065683 ps |
| CPU time | 28.01 seconds |
| Started | Sep 18 06:31:24 PM UTC 24 |
| Finished | Sep 18 06:31:53 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413632065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1413632065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_intr.4034831605 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 8952296446 ps |
| CPU time | 20.95 seconds |
| Started | Sep 18 06:31:25 PM UTC 24 |
| Finished | Sep 18 06:31:47 PM UTC 24 |
| Peak memory | 203832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034831605 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.4034831605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.308465394 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 130377994260 ps |
| CPU time | 1058.52 seconds |
| Started | Sep 18 06:31:45 PM UTC 24 |
| Finished | Sep 18 06:49:36 PM UTC 24 |
| Peak memory | 207100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308465394 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.308465394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_loopback.3042310389 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1250014948 ps |
| CPU time | 2.7 seconds |
| Started | Sep 18 06:31:42 PM UTC 24 |
| Finished | Sep 18 06:31:46 PM UTC 24 |
| Peak memory | 207820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042310389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3042310389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_noise_filter.4161304476 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 40364274941 ps |
| CPU time | 25.03 seconds |
| Started | Sep 18 06:31:25 PM UTC 24 |
| Finished | Sep 18 06:31:51 PM UTC 24 |
| Peak memory | 209656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161304476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.4161304476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_perf.1277356116 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 21039842252 ps |
| CPU time | 57.78 seconds |
| Started | Sep 18 06:31:44 PM UTC 24 |
| Finished | Sep 18 06:32:44 PM UTC 24 |
| Peak memory | 203924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277356116 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1277356116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_rx_oversample.4270445828 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 7019392245 ps |
| CPU time | 35.33 seconds |
| Started | Sep 18 06:31:24 PM UTC 24 |
| Finished | Sep 18 06:32:00 PM UTC 24 |
| Peak memory | 208472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270445828 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.4270445828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.1395902277 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 360864039201 ps |
| CPU time | 97.94 seconds |
| Started | Sep 18 06:31:37 PM UTC 24 |
| Finished | Sep 18 06:33:17 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395902277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1395902277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.3678162508 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 4472761326 ps |
| CPU time | 2.62 seconds |
| Started | Sep 18 06:31:34 PM UTC 24 |
| Finished | Sep 18 06:31:38 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678162508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3678162508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_smoke.3184683857 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 606599745 ps |
| CPU time | 1.52 seconds |
| Started | Sep 18 06:31:18 PM UTC 24 |
| Finished | Sep 18 06:31:21 PM UTC 24 |
| Peak memory | 207228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184683857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3184683857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_stress_all.3612711398 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 248810481037 ps |
| CPU time | 781.47 seconds |
| Started | Sep 18 06:31:46 PM UTC 24 |
| Finished | Sep 18 06:44:57 PM UTC 24 |
| Peak memory | 218408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612711398 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3612711398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.2747339861 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 723297651 ps |
| CPU time | 4.35 seconds |
| Started | Sep 18 06:31:39 PM UTC 24 |
| Finished | Sep 18 06:31:45 PM UTC 24 |
| Peak memory | 207884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747339861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2747339861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/31.uart_tx_rx.3062786315 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 58563172711 ps |
| CPU time | 52.4 seconds |
| Started | Sep 18 06:31:20 PM UTC 24 |
| Finished | Sep 18 06:32:14 PM UTC 24 |
| Peak memory | 209412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062786315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3062786315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_alert_test.2689173289 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 11620216 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 06:32:15 PM UTC 24 |
| Finished | Sep 18 06:32:16 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689173289 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2689173289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_fifo_full.3157384203 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 154282755919 ps |
| CPU time | 129.72 seconds |
| Started | Sep 18 06:31:49 PM UTC 24 |
| Finished | Sep 18 06:34:01 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157384203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3157384203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.4043727647 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 52746758379 ps |
| CPU time | 77.79 seconds |
| Started | Sep 18 06:31:49 PM UTC 24 |
| Finished | Sep 18 06:33:08 PM UTC 24 |
| Peak memory | 209456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043727647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.4043727647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_fifo_reset.2417583590 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 15963130806 ps |
| CPU time | 25.48 seconds |
| Started | Sep 18 06:31:50 PM UTC 24 |
| Finished | Sep 18 06:32:16 PM UTC 24 |
| Peak memory | 209108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417583590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2417583590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_intr.1938144014 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 87499889823 ps |
| CPU time | 114.51 seconds |
| Started | Sep 18 06:31:52 PM UTC 24 |
| Finished | Sep 18 06:33:48 PM UTC 24 |
| Peak memory | 208288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938144014 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1938144014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.934369317 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 55545382752 ps |
| CPU time | 201.13 seconds |
| Started | Sep 18 06:32:07 PM UTC 24 |
| Finished | Sep 18 06:35:32 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934369317 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.934369317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_loopback.2108592357 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 262364808 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 06:32:05 PM UTC 24 |
| Finished | Sep 18 06:32:07 PM UTC 24 |
| Peak memory | 205300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108592357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2108592357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_noise_filter.2305078195 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 96817926618 ps |
| CPU time | 69.84 seconds |
| Started | Sep 18 06:31:53 PM UTC 24 |
| Finished | Sep 18 06:33:05 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305078195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2305078195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_perf.2454223170 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 18489030252 ps |
| CPU time | 280.88 seconds |
| Started | Sep 18 06:32:07 PM UTC 24 |
| Finished | Sep 18 06:36:52 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454223170 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2454223170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_rx_oversample.3903682036 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2428498466 ps |
| CPU time | 5.03 seconds |
| Started | Sep 18 06:31:51 PM UTC 24 |
| Finished | Sep 18 06:31:57 PM UTC 24 |
| Peak memory | 208504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903682036 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3903682036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.675070202 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 42227892390 ps |
| CPU time | 33.1 seconds |
| Started | Sep 18 06:32:01 PM UTC 24 |
| Finished | Sep 18 06:32:36 PM UTC 24 |
| Peak memory | 204048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675070202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.675070202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.2161507960 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 42855465144 ps |
| CPU time | 30.13 seconds |
| Started | Sep 18 06:31:58 PM UTC 24 |
| Finished | Sep 18 06:32:30 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161507960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2161507960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_smoke.1303318777 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 747302393 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 06:31:47 PM UTC 24 |
| Finished | Sep 18 06:31:50 PM UTC 24 |
| Peak memory | 203264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303318777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1303318777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_stress_all.3402822241 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 335746647780 ps |
| CPU time | 145.47 seconds |
| Started | Sep 18 06:32:15 PM UTC 24 |
| Finished | Sep 18 06:34:43 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402822241 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3402822241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.2495118125 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 27879013712 ps |
| CPU time | 13.03 seconds |
| Started | Sep 18 06:32:09 PM UTC 24 |
| Finished | Sep 18 06:32:23 PM UTC 24 |
| Peak memory | 226232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2495118125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all _with_rand_reset.2495118125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.269669990 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 520224060 ps |
| CPU time | 1.65 seconds |
| Started | Sep 18 06:32:02 PM UTC 24 |
| Finished | Sep 18 06:32:05 PM UTC 24 |
| Peak memory | 207340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269669990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.269669990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/32.uart_tx_rx.2998079472 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 92569260938 ps |
| CPU time | 85.49 seconds |
| Started | Sep 18 06:31:48 PM UTC 24 |
| Finished | Sep 18 06:33:15 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998079472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2998079472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/32.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_alert_test.3326027976 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 14285407 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 06:32:59 PM UTC 24 |
| Finished | Sep 18 06:33:01 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326027976 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3326027976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_fifo_full.3567290821 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 59824035310 ps |
| CPU time | 21.03 seconds |
| Started | Sep 18 06:32:17 PM UTC 24 |
| Finished | Sep 18 06:32:39 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567290821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3567290821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.1126065797 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 42106534158 ps |
| CPU time | 21.86 seconds |
| Started | Sep 18 06:32:19 PM UTC 24 |
| Finished | Sep 18 06:32:42 PM UTC 24 |
| Peak memory | 209512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126065797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1126065797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_fifo_reset.2420208580 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 72599075036 ps |
| CPU time | 33.87 seconds |
| Started | Sep 18 06:32:23 PM UTC 24 |
| Finished | Sep 18 06:32:58 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420208580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2420208580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_intr.2849714575 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 50150320851 ps |
| CPU time | 129.06 seconds |
| Started | Sep 18 06:32:29 PM UTC 24 |
| Finished | Sep 18 06:34:41 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849714575 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2849714575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.1445068339 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 94455439190 ps |
| CPU time | 465.29 seconds |
| Started | Sep 18 06:32:44 PM UTC 24 |
| Finished | Sep 18 06:40:35 PM UTC 24 |
| Peak memory | 204092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445068339 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1445068339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_loopback.2636326771 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 6294425938 ps |
| CPU time | 18.02 seconds |
| Started | Sep 18 06:32:43 PM UTC 24 |
| Finished | Sep 18 06:33:02 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636326771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2636326771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_noise_filter.549042899 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 66674485942 ps |
| CPU time | 57.28 seconds |
| Started | Sep 18 06:32:30 PM UTC 24 |
| Finished | Sep 18 06:33:29 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549042899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.549042899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_perf.2846198198 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 17823096732 ps |
| CPU time | 162.57 seconds |
| Started | Sep 18 06:32:43 PM UTC 24 |
| Finished | Sep 18 06:35:28 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846198198 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2846198198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_rx_oversample.850889535 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2957205443 ps |
| CPU time | 13.63 seconds |
| Started | Sep 18 06:32:27 PM UTC 24 |
| Finished | Sep 18 06:32:42 PM UTC 24 |
| Peak memory | 208280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850889535 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.850889535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.2885674571 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 2049209555 ps |
| CPU time | 4.31 seconds |
| Started | Sep 18 06:32:36 PM UTC 24 |
| Finished | Sep 18 06:32:42 PM UTC 24 |
| Peak memory | 203772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885674571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2885674571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_smoke.3539967331 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 5441084403 ps |
| CPU time | 11.76 seconds |
| Started | Sep 18 06:32:16 PM UTC 24 |
| Finished | Sep 18 06:32:29 PM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539967331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3539967331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_stress_all.2116309344 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 53759144725 ps |
| CPU time | 46.09 seconds |
| Started | Sep 18 06:32:47 PM UTC 24 |
| Finished | Sep 18 06:33:34 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116309344 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2116309344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.1998059770 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 5092815917 ps |
| CPU time | 52.3 seconds |
| Started | Sep 18 06:32:45 PM UTC 24 |
| Finished | Sep 18 06:33:39 PM UTC 24 |
| Peak memory | 222332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1998059770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all _with_rand_reset.1998059770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.1998292925 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 3158443720 ps |
| CPU time | 2.97 seconds |
| Started | Sep 18 06:32:43 PM UTC 24 |
| Finished | Sep 18 06:32:47 PM UTC 24 |
| Peak memory | 203916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998292925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1998292925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/33.uart_tx_rx.556084960 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 36570637741 ps |
| CPU time | 111.51 seconds |
| Started | Sep 18 06:32:17 PM UTC 24 |
| Finished | Sep 18 06:34:11 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556084960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.556084960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/33.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_alert_test.942965079 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 42315906 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 06:33:31 PM UTC 24 |
| Finished | Sep 18 06:33:32 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942965079 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.942965079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_fifo_full.60646233 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 212914936933 ps |
| CPU time | 141.66 seconds |
| Started | Sep 18 06:33:03 PM UTC 24 |
| Finished | Sep 18 06:35:27 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60646233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.60646233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.2921467211 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 180289670969 ps |
| CPU time | 523.89 seconds |
| Started | Sep 18 06:33:04 PM UTC 24 |
| Finished | Sep 18 06:41:54 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921467211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2921467211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_fifo_reset.119097483 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 73389931717 ps |
| CPU time | 135.1 seconds |
| Started | Sep 18 06:33:05 PM UTC 24 |
| Finished | Sep 18 06:35:24 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119097483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.119097483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_intr.4204673541 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 28161555824 ps |
| CPU time | 50.55 seconds |
| Started | Sep 18 06:33:08 PM UTC 24 |
| Finished | Sep 18 06:34:00 PM UTC 24 |
| Peak memory | 207900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204673541 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.4204673541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.4173589046 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 160866911685 ps |
| CPU time | 619.69 seconds |
| Started | Sep 18 06:33:18 PM UTC 24 |
| Finished | Sep 18 06:43:45 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173589046 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.4173589046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_loopback.1244694074 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3312814934 ps |
| CPU time | 7.96 seconds |
| Started | Sep 18 06:33:14 PM UTC 24 |
| Finished | Sep 18 06:33:23 PM UTC 24 |
| Peak memory | 208216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244694074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1244694074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_noise_filter.395517208 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 457889378562 ps |
| CPU time | 56.49 seconds |
| Started | Sep 18 06:33:08 PM UTC 24 |
| Finished | Sep 18 06:34:06 PM UTC 24 |
| Peak memory | 226368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395517208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.395517208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_perf.2672589342 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 19500240616 ps |
| CPU time | 316.32 seconds |
| Started | Sep 18 06:33:16 PM UTC 24 |
| Finished | Sep 18 06:38:37 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672589342 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2672589342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_rx_oversample.2001927164 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1514037906 ps |
| CPU time | 3.88 seconds |
| Started | Sep 18 06:33:07 PM UTC 24 |
| Finished | Sep 18 06:33:12 PM UTC 24 |
| Peak memory | 203716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001927164 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2001927164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.1821129024 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 70085808143 ps |
| CPU time | 42.59 seconds |
| Started | Sep 18 06:33:10 PM UTC 24 |
| Finished | Sep 18 06:33:54 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821129024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1821129024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.4130312642 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 6271239920 ps |
| CPU time | 2.88 seconds |
| Started | Sep 18 06:33:09 PM UTC 24 |
| Finished | Sep 18 06:33:13 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130312642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.4130312642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_smoke.1005497798 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 468710181 ps |
| CPU time | 3.39 seconds |
| Started | Sep 18 06:33:01 PM UTC 24 |
| Finished | Sep 18 06:33:06 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005497798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1005497798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_stress_all.2387454775 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 162876079083 ps |
| CPU time | 274.37 seconds |
| Started | Sep 18 06:33:25 PM UTC 24 |
| Finished | Sep 18 06:38:04 PM UTC 24 |
| Peak memory | 203856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387454775 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2387454775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.369491954 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 3245411885 ps |
| CPU time | 109.9 seconds |
| Started | Sep 18 06:33:24 PM UTC 24 |
| Finished | Sep 18 06:35:17 PM UTC 24 |
| Peak memory | 218172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=369491954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all_ with_rand_reset.369491954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.3060045255 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 6583822724 ps |
| CPU time | 27.79 seconds |
| Started | Sep 18 06:33:13 PM UTC 24 |
| Finished | Sep 18 06:33:42 PM UTC 24 |
| Peak memory | 208552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060045255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3060045255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/34.uart_tx_rx.2242646804 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 43348459414 ps |
| CPU time | 124.2 seconds |
| Started | Sep 18 06:33:02 PM UTC 24 |
| Finished | Sep 18 06:35:09 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242646804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2242646804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/34.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_alert_test.900223351 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 12935072 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 06:34:07 PM UTC 24 |
| Finished | Sep 18 06:34:09 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900223351 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.900223351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_fifo_full.2382159087 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 94805115838 ps |
| CPU time | 109.8 seconds |
| Started | Sep 18 06:33:35 PM UTC 24 |
| Finished | Sep 18 06:35:28 PM UTC 24 |
| Peak memory | 209460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382159087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2382159087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.2731148929 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 105711638249 ps |
| CPU time | 90.97 seconds |
| Started | Sep 18 06:33:38 PM UTC 24 |
| Finished | Sep 18 06:35:11 PM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731148929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2731148929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_fifo_reset.2717817863 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 109690496669 ps |
| CPU time | 63.7 seconds |
| Started | Sep 18 06:33:39 PM UTC 24 |
| Finished | Sep 18 06:34:44 PM UTC 24 |
| Peak memory | 209408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717817863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2717817863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_intr.262393569 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 35473977814 ps |
| CPU time | 50.08 seconds |
| Started | Sep 18 06:33:47 PM UTC 24 |
| Finished | Sep 18 06:34:39 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262393569 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.262393569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.1374006052 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 88385898134 ps |
| CPU time | 153.53 seconds |
| Started | Sep 18 06:34:01 PM UTC 24 |
| Finished | Sep 18 06:36:37 PM UTC 24 |
| Peak memory | 209516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374006052 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1374006052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_loopback.2140220655 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2398803192 ps |
| CPU time | 9.45 seconds |
| Started | Sep 18 06:33:59 PM UTC 24 |
| Finished | Sep 18 06:34:09 PM UTC 24 |
| Peak memory | 208216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140220655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2140220655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_noise_filter.665368872 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 56880514772 ps |
| CPU time | 35.31 seconds |
| Started | Sep 18 06:33:49 PM UTC 24 |
| Finished | Sep 18 06:34:26 PM UTC 24 |
| Peak memory | 209596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665368872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.665368872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_perf.2205195061 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 14321574689 ps |
| CPU time | 513.86 seconds |
| Started | Sep 18 06:34:01 PM UTC 24 |
| Finished | Sep 18 06:42:41 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205195061 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2205195061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_rx_oversample.945875937 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 5693028084 ps |
| CPU time | 31.78 seconds |
| Started | Sep 18 06:33:43 PM UTC 24 |
| Finished | Sep 18 06:34:16 PM UTC 24 |
| Peak memory | 208400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945875937 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.945875937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.440576787 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 188605030754 ps |
| CPU time | 110.77 seconds |
| Started | Sep 18 06:33:54 PM UTC 24 |
| Finished | Sep 18 06:35:47 PM UTC 24 |
| Peak memory | 209352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440576787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.440576787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.2529525858 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 3547279226 ps |
| CPU time | 9.9 seconds |
| Started | Sep 18 06:33:50 PM UTC 24 |
| Finished | Sep 18 06:34:01 PM UTC 24 |
| Peak memory | 203508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529525858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2529525858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_smoke.3487296568 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 685101565 ps |
| CPU time | 5 seconds |
| Started | Sep 18 06:33:31 PM UTC 24 |
| Finished | Sep 18 06:33:37 PM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487296568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3487296568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_stress_all.830169929 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 159090126343 ps |
| CPU time | 1289.05 seconds |
| Started | Sep 18 06:34:02 PM UTC 24 |
| Finished | Sep 18 06:55:45 PM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830169929 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.830169929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.762685528 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 9131217425 ps |
| CPU time | 50.51 seconds |
| Started | Sep 18 06:34:02 PM UTC 24 |
| Finished | Sep 18 06:34:54 PM UTC 24 |
| Peak memory | 218548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=762685528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all_ with_rand_reset.762685528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.3163040372 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 2135141863 ps |
| CPU time | 4.66 seconds |
| Started | Sep 18 06:33:55 PM UTC 24 |
| Finished | Sep 18 06:34:00 PM UTC 24 |
| Peak memory | 203988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163040372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3163040372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/35.uart_tx_rx.220459426 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 77947678978 ps |
| CPU time | 18.62 seconds |
| Started | Sep 18 06:33:34 PM UTC 24 |
| Finished | Sep 18 06:33:54 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220459426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.220459426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/35.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_alert_test.284594790 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 11325307 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 06:35:05 PM UTC 24 |
| Finished | Sep 18 06:35:07 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284594790 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.284594790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_fifo_full.327785829 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 85261689917 ps |
| CPU time | 87.24 seconds |
| Started | Sep 18 06:34:11 PM UTC 24 |
| Finished | Sep 18 06:35:40 PM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327785829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.327785829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.2787792086 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 58641028612 ps |
| CPU time | 56.29 seconds |
| Started | Sep 18 06:34:12 PM UTC 24 |
| Finished | Sep 18 06:35:10 PM UTC 24 |
| Peak memory | 203920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787792086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2787792086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_fifo_reset.153800676 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 13734020075 ps |
| CPU time | 50.67 seconds |
| Started | Sep 18 06:34:12 PM UTC 24 |
| Finished | Sep 18 06:35:05 PM UTC 24 |
| Peak memory | 208316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153800676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.153800676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_intr.3977819967 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 43736935970 ps |
| CPU time | 70.3 seconds |
| Started | Sep 18 06:34:27 PM UTC 24 |
| Finished | Sep 18 06:35:39 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977819967 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3977819967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.3477962206 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 208042745818 ps |
| CPU time | 310.28 seconds |
| Started | Sep 18 06:34:47 PM UTC 24 |
| Finished | Sep 18 06:40:02 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477962206 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3477962206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_loopback.3041298489 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 5900924451 ps |
| CPU time | 25.41 seconds |
| Started | Sep 18 06:34:44 PM UTC 24 |
| Finished | Sep 18 06:35:11 PM UTC 24 |
| Peak memory | 207884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041298489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3041298489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_noise_filter.2364245728 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 193841728373 ps |
| CPU time | 202.52 seconds |
| Started | Sep 18 06:34:29 PM UTC 24 |
| Finished | Sep 18 06:37:54 PM UTC 24 |
| Peak memory | 218700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364245728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2364245728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_perf.3153943580 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 26306580965 ps |
| CPU time | 1520.51 seconds |
| Started | Sep 18 06:34:45 PM UTC 24 |
| Finished | Sep 18 07:00:23 PM UTC 24 |
| Peak memory | 212600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153943580 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3153943580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_rx_oversample.442970351 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 1483163428 ps |
| CPU time | 8.7 seconds |
| Started | Sep 18 06:34:17 PM UTC 24 |
| Finished | Sep 18 06:34:27 PM UTC 24 |
| Peak memory | 208140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442970351 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.442970351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.1290456424 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 92196319828 ps |
| CPU time | 168.16 seconds |
| Started | Sep 18 06:34:42 PM UTC 24 |
| Finished | Sep 18 06:37:33 PM UTC 24 |
| Peak memory | 209416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290456424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1290456424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.1882374789 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3451948383 ps |
| CPU time | 2.79 seconds |
| Started | Sep 18 06:34:40 PM UTC 24 |
| Finished | Sep 18 06:34:44 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882374789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1882374789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_smoke.177431295 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 144792518 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 06:34:10 PM UTC 24 |
| Finished | Sep 18 06:34:12 PM UTC 24 |
| Peak memory | 207220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177431295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 36.uart_smoke.177431295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_stress_all.2226684395 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 183473809926 ps |
| CPU time | 322.64 seconds |
| Started | Sep 18 06:35:00 PM UTC 24 |
| Finished | Sep 18 06:40:27 PM UTC 24 |
| Peak memory | 203856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226684395 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2226684395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.3874881583 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 21647043636 ps |
| CPU time | 102.94 seconds |
| Started | Sep 18 06:34:55 PM UTC 24 |
| Finished | Sep 18 06:36:40 PM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3874881583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all _with_rand_reset.3874881583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.643533818 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 452035833 ps |
| CPU time | 2.63 seconds |
| Started | Sep 18 06:34:43 PM UTC 24 |
| Finished | Sep 18 06:34:47 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643533818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.643533818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/36.uart_tx_rx.3422546215 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 116784993159 ps |
| CPU time | 68.52 seconds |
| Started | Sep 18 06:34:10 PM UTC 24 |
| Finished | Sep 18 06:35:20 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422546215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3422546215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/36.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_alert_test.3680821542 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 30788980 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 06:35:40 PM UTC 24 |
| Finished | Sep 18 06:35:42 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680821542 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3680821542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_fifo_full.4138261445 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 54741016492 ps |
| CPU time | 58.52 seconds |
| Started | Sep 18 06:35:11 PM UTC 24 |
| Finished | Sep 18 06:36:11 PM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138261445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.4138261445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.1018917372 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 168950407333 ps |
| CPU time | 75.99 seconds |
| Started | Sep 18 06:35:12 PM UTC 24 |
| Finished | Sep 18 06:36:29 PM UTC 24 |
| Peak memory | 209284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018917372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1018917372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_fifo_reset.3018043662 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 171913123595 ps |
| CPU time | 84.73 seconds |
| Started | Sep 18 06:35:12 PM UTC 24 |
| Finished | Sep 18 06:36:38 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018043662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3018043662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_intr.2871419969 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 81703615757 ps |
| CPU time | 85.06 seconds |
| Started | Sep 18 06:35:21 PM UTC 24 |
| Finished | Sep 18 06:36:48 PM UTC 24 |
| Peak memory | 203512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871419969 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2871419969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.1750929057 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 96902699313 ps |
| CPU time | 330.63 seconds |
| Started | Sep 18 06:35:36 PM UTC 24 |
| Finished | Sep 18 06:41:11 PM UTC 24 |
| Peak memory | 209320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750929057 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1750929057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_loopback.1293619809 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 6603478110 ps |
| CPU time | 15.63 seconds |
| Started | Sep 18 06:35:32 PM UTC 24 |
| Finished | Sep 18 06:35:49 PM UTC 24 |
| Peak memory | 209216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293619809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1293619809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_noise_filter.1415871026 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 91458092729 ps |
| CPU time | 304.06 seconds |
| Started | Sep 18 06:35:24 PM UTC 24 |
| Finished | Sep 18 06:40:32 PM UTC 24 |
| Peak memory | 220808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415871026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1415871026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_perf.3645884867 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 22265815972 ps |
| CPU time | 185.7 seconds |
| Started | Sep 18 06:35:32 PM UTC 24 |
| Finished | Sep 18 06:38:41 PM UTC 24 |
| Peak memory | 204040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645884867 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3645884867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_rx_oversample.3683508546 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 5394960230 ps |
| CPU time | 50.21 seconds |
| Started | Sep 18 06:35:17 PM UTC 24 |
| Finished | Sep 18 06:36:09 PM UTC 24 |
| Peak memory | 207948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683508546 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3683508546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.3364996827 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 53898859695 ps |
| CPU time | 27.9 seconds |
| Started | Sep 18 06:35:29 PM UTC 24 |
| Finished | Sep 18 06:35:58 PM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364996827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3364996827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.4030560753 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2313497232 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 06:35:28 PM UTC 24 |
| Finished | Sep 18 06:35:32 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030560753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.4030560753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_smoke.2856012317 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 5545585615 ps |
| CPU time | 52.12 seconds |
| Started | Sep 18 06:35:08 PM UTC 24 |
| Finished | Sep 18 06:36:02 PM UTC 24 |
| Peak memory | 208928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856012317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2856012317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_stress_all.3936763316 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 203161119167 ps |
| CPU time | 629.82 seconds |
| Started | Sep 18 06:35:38 PM UTC 24 |
| Finished | Sep 18 06:46:15 PM UTC 24 |
| Peak memory | 205956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936763316 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3936763316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.1241397294 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3492140668 ps |
| CPU time | 39.38 seconds |
| Started | Sep 18 06:35:37 PM UTC 24 |
| Finished | Sep 18 06:36:17 PM UTC 24 |
| Peak memory | 218540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1241397294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all _with_rand_reset.1241397294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.1347379419 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 995264532 ps |
| CPU time | 5.93 seconds |
| Started | Sep 18 06:35:29 PM UTC 24 |
| Finished | Sep 18 06:35:36 PM UTC 24 |
| Peak memory | 208376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347379419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1347379419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/37.uart_tx_rx.2287351470 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 24645447033 ps |
| CPU time | 42.98 seconds |
| Started | Sep 18 06:35:10 PM UTC 24 |
| Finished | Sep 18 06:35:54 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287351470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2287351470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/37.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_alert_test.1802341413 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 13691483 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:36:18 PM UTC 24 |
| Finished | Sep 18 06:36:20 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802341413 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1802341413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_fifo_full.2070336097 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 55012006264 ps |
| CPU time | 24.67 seconds |
| Started | Sep 18 06:35:45 PM UTC 24 |
| Finished | Sep 18 06:36:11 PM UTC 24 |
| Peak memory | 209596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070336097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2070336097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.2533642568 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 79180292012 ps |
| CPU time | 35.38 seconds |
| Started | Sep 18 06:35:48 PM UTC 24 |
| Finished | Sep 18 06:36:25 PM UTC 24 |
| Peak memory | 204124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533642568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2533642568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_fifo_reset.416258293 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 50286595224 ps |
| CPU time | 107.62 seconds |
| Started | Sep 18 06:35:50 PM UTC 24 |
| Finished | Sep 18 06:37:40 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416258293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.416258293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_intr.2416440431 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 47298708519 ps |
| CPU time | 108.17 seconds |
| Started | Sep 18 06:35:51 PM UTC 24 |
| Finished | Sep 18 06:37:42 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416440431 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2416440431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.1299156069 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 89228129106 ps |
| CPU time | 677.31 seconds |
| Started | Sep 18 06:36:10 PM UTC 24 |
| Finished | Sep 18 06:47:36 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299156069 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1299156069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_loopback.3380830345 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 7601776025 ps |
| CPU time | 14.71 seconds |
| Started | Sep 18 06:36:06 PM UTC 24 |
| Finished | Sep 18 06:36:22 PM UTC 24 |
| Peak memory | 208860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380830345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3380830345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_noise_filter.1276841043 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 67200152980 ps |
| CPU time | 153.95 seconds |
| Started | Sep 18 06:35:51 PM UTC 24 |
| Finished | Sep 18 06:38:28 PM UTC 24 |
| Peak memory | 209608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276841043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1276841043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_perf.1930546137 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 11712756892 ps |
| CPU time | 129.13 seconds |
| Started | Sep 18 06:36:09 PM UTC 24 |
| Finished | Sep 18 06:38:20 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930546137 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1930546137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_rx_oversample.235209994 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 2007908134 ps |
| CPU time | 13.14 seconds |
| Started | Sep 18 06:35:50 PM UTC 24 |
| Finished | Sep 18 06:36:05 PM UTC 24 |
| Peak memory | 207904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235209994 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.235209994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.3546824789 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 124855062372 ps |
| CPU time | 276.79 seconds |
| Started | Sep 18 06:36:00 PM UTC 24 |
| Finished | Sep 18 06:40:41 PM UTC 24 |
| Peak memory | 204188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546824789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3546824789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.1056371343 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 35386485112 ps |
| CPU time | 42.37 seconds |
| Started | Sep 18 06:35:55 PM UTC 24 |
| Finished | Sep 18 06:36:38 PM UTC 24 |
| Peak memory | 203836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056371343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1056371343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_smoke.1141007319 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 688522653 ps |
| CPU time | 2.72 seconds |
| Started | Sep 18 06:35:41 PM UTC 24 |
| Finished | Sep 18 06:35:45 PM UTC 24 |
| Peak memory | 203660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141007319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1141007319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_stress_all.2256220346 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 300091106817 ps |
| CPU time | 1508.85 seconds |
| Started | Sep 18 06:36:12 PM UTC 24 |
| Finished | Sep 18 07:01:38 PM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256220346 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2256220346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.77644095 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 12220800370 ps |
| CPU time | 86.75 seconds |
| Started | Sep 18 06:36:12 PM UTC 24 |
| Finished | Sep 18 06:37:41 PM UTC 24 |
| Peak memory | 222660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=77644095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all_w ith_rand_reset.77644095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.4282067996 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 839380522 ps |
| CPU time | 4.65 seconds |
| Started | Sep 18 06:36:03 PM UTC 24 |
| Finished | Sep 18 06:36:09 PM UTC 24 |
| Peak memory | 207820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282067996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.4282067996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/38.uart_tx_rx.3776327417 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 144272068475 ps |
| CPU time | 117.76 seconds |
| Started | Sep 18 06:35:42 PM UTC 24 |
| Finished | Sep 18 06:37:42 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776327417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3776327417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/38.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_alert_test.2780066555 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 11245293 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 06:37:08 PM UTC 24 |
| Finished | Sep 18 06:37:09 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780066555 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2780066555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_fifo_full.1920483106 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 158006732523 ps |
| CPU time | 165.18 seconds |
| Started | Sep 18 06:36:25 PM UTC 24 |
| Finished | Sep 18 06:39:13 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920483106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1920483106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.291910387 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 43166674924 ps |
| CPU time | 45.99 seconds |
| Started | Sep 18 06:36:25 PM UTC 24 |
| Finished | Sep 18 06:37:13 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291910387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.291910387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_fifo_reset.825789009 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 117363462142 ps |
| CPU time | 159.94 seconds |
| Started | Sep 18 06:36:31 PM UTC 24 |
| Finished | Sep 18 06:39:13 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825789009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.825789009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_intr.1583308337 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 52501746742 ps |
| CPU time | 89.49 seconds |
| Started | Sep 18 06:36:38 PM UTC 24 |
| Finished | Sep 18 06:38:09 PM UTC 24 |
| Peak memory | 209240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583308337 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1583308337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.197588312 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 188431270895 ps |
| CPU time | 1222.76 seconds |
| Started | Sep 18 06:36:53 PM UTC 24 |
| Finished | Sep 18 06:57:31 PM UTC 24 |
| Peak memory | 209144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197588312 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.197588312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_loopback.1784539520 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 3721009168 ps |
| CPU time | 15.38 seconds |
| Started | Sep 18 06:36:48 PM UTC 24 |
| Finished | Sep 18 06:37:05 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784539520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1784539520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_noise_filter.277495796 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 185375651610 ps |
| CPU time | 85.99 seconds |
| Started | Sep 18 06:36:39 PM UTC 24 |
| Finished | Sep 18 06:38:07 PM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277495796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.277495796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_perf.1899076504 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 19330831096 ps |
| CPU time | 385.29 seconds |
| Started | Sep 18 06:36:53 PM UTC 24 |
| Finished | Sep 18 06:43:24 PM UTC 24 |
| Peak memory | 203856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899076504 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1899076504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_rx_oversample.337876701 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 3090098581 ps |
| CPU time | 15.15 seconds |
| Started | Sep 18 06:36:36 PM UTC 24 |
| Finished | Sep 18 06:36:52 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337876701 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.337876701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.2174640160 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 39772821304 ps |
| CPU time | 32.96 seconds |
| Started | Sep 18 06:36:41 PM UTC 24 |
| Finished | Sep 18 06:37:15 PM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174640160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2174640160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.2225292046 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1732339741 ps |
| CPU time | 2.07 seconds |
| Started | Sep 18 06:36:39 PM UTC 24 |
| Finished | Sep 18 06:36:42 PM UTC 24 |
| Peak memory | 203420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225292046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2225292046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_smoke.4168930482 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 461332962 ps |
| CPU time | 2.5 seconds |
| Started | Sep 18 06:36:21 PM UTC 24 |
| Finished | Sep 18 06:36:25 PM UTC 24 |
| Peak memory | 208036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168930482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.uart_smoke.4168930482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_stress_all.4270397092 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 232824269139 ps |
| CPU time | 502.76 seconds |
| Started | Sep 18 06:37:05 PM UTC 24 |
| Finished | Sep 18 06:45:34 PM UTC 24 |
| Peak memory | 215060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270397092 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.4270397092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.885997934 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 2216623285 ps |
| CPU time | 40.05 seconds |
| Started | Sep 18 06:37:02 PM UTC 24 |
| Finished | Sep 18 06:37:44 PM UTC 24 |
| Peak memory | 218240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=885997934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all_ with_rand_reset.885997934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.3294885103 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 8391376489 ps |
| CPU time | 17.87 seconds |
| Started | Sep 18 06:36:43 PM UTC 24 |
| Finished | Sep 18 06:37:02 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294885103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3294885103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/39.uart_tx_rx.2190535068 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 28725872740 ps |
| CPU time | 77.23 seconds |
| Started | Sep 18 06:36:22 PM UTC 24 |
| Finished | Sep 18 06:37:41 PM UTC 24 |
| Peak memory | 203860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190535068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2190535068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/39.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_alert_test.1127750304 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 98401230 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 06:16:47 PM UTC 24 |
| Finished | Sep 18 06:16:49 PM UTC 24 |
| Peak memory | 203076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127750304 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1127750304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_fifo_full.3563783497 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 29500809275 ps |
| CPU time | 56.15 seconds |
| Started | Sep 18 06:16:29 PM UTC 24 |
| Finished | Sep 18 06:17:27 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563783497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3563783497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.2064897125 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 302293456192 ps |
| CPU time | 49.02 seconds |
| Started | Sep 18 06:16:30 PM UTC 24 |
| Finished | Sep 18 06:17:21 PM UTC 24 |
| Peak memory | 204032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064897125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2064897125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_fifo_reset.2607564006 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 14566964798 ps |
| CPU time | 23.53 seconds |
| Started | Sep 18 06:16:30 PM UTC 24 |
| Finished | Sep 18 06:16:55 PM UTC 24 |
| Peak memory | 208280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607564006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2607564006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_intr.1189807040 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 44848880379 ps |
| CPU time | 52.4 seconds |
| Started | Sep 18 06:16:32 PM UTC 24 |
| Finished | Sep 18 06:17:26 PM UTC 24 |
| Peak memory | 203916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189807040 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1189807040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.649853185 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 99473345455 ps |
| CPU time | 307.13 seconds |
| Started | Sep 18 06:16:47 PM UTC 24 |
| Finished | Sep 18 06:21:58 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649853185 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.649853185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_loopback.3619571139 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 11254473347 ps |
| CPU time | 4.38 seconds |
| Started | Sep 18 06:16:41 PM UTC 24 |
| Finished | Sep 18 06:16:46 PM UTC 24 |
| Peak memory | 207860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619571139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3619571139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_noise_filter.4016611437 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 67446885783 ps |
| CPU time | 35.95 seconds |
| Started | Sep 18 06:16:32 PM UTC 24 |
| Finished | Sep 18 06:17:10 PM UTC 24 |
| Peak memory | 218504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016611437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.4016611437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_perf.1489719772 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 25595731715 ps |
| CPU time | 1516.55 seconds |
| Started | Sep 18 06:16:41 PM UTC 24 |
| Finished | Sep 18 06:42:14 PM UTC 24 |
| Peak memory | 203764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489719772 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1489719772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_rx_oversample.2080549949 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 4911256963 ps |
| CPU time | 10.71 seconds |
| Started | Sep 18 06:16:30 PM UTC 24 |
| Finished | Sep 18 06:16:42 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080549949 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2080549949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.537791000 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 28533816335 ps |
| CPU time | 60.74 seconds |
| Started | Sep 18 06:16:35 PM UTC 24 |
| Finished | Sep 18 06:17:37 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537791000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.537791000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.717451574 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 5323586235 ps |
| CPU time | 7.48 seconds |
| Started | Sep 18 06:16:35 PM UTC 24 |
| Finished | Sep 18 06:16:43 PM UTC 24 |
| Peak memory | 203520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717451574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.717451574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_sec_cm.3688808593 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 119830080 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 06:16:47 PM UTC 24 |
| Finished | Sep 18 06:16:49 PM UTC 24 |
| Peak memory | 238104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688808593 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3688808593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_smoke.3427626075 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5361050128 ps |
| CPU time | 19.11 seconds |
| Started | Sep 18 06:16:28 PM UTC 24 |
| Finished | Sep 18 06:16:48 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427626075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3427626075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.660959038 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 806460233 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 06:16:37 PM UTC 24 |
| Finished | Sep 18 06:16:41 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660959038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.660959038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/4.uart_tx_rx.599031875 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 94862518045 ps |
| CPU time | 187.35 seconds |
| Started | Sep 18 06:16:28 PM UTC 24 |
| Finished | Sep 18 06:19:38 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599031875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.599031875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/4.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_alert_test.2760065316 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 53566380 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 06:37:55 PM UTC 24 |
| Finished | Sep 18 06:37:57 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760065316 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2760065316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_fifo_full.2348133596 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 246917234302 ps |
| CPU time | 187.97 seconds |
| Started | Sep 18 06:37:14 PM UTC 24 |
| Finished | Sep 18 06:40:25 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348133596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2348133596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.1158334632 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 9166606093 ps |
| CPU time | 31.32 seconds |
| Started | Sep 18 06:37:16 PM UTC 24 |
| Finished | Sep 18 06:37:49 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158334632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1158334632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_fifo_reset.2607904262 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 138108702143 ps |
| CPU time | 886.42 seconds |
| Started | Sep 18 06:37:27 PM UTC 24 |
| Finished | Sep 18 06:52:24 PM UTC 24 |
| Peak memory | 212852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607904262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2607904262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_intr.4035313136 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 283187713849 ps |
| CPU time | 292.28 seconds |
| Started | Sep 18 06:37:34 PM UTC 24 |
| Finished | Sep 18 06:42:30 PM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035313136 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.4035313136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.516988964 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 222917788640 ps |
| CPU time | 128.66 seconds |
| Started | Sep 18 06:37:46 PM UTC 24 |
| Finished | Sep 18 06:39:57 PM UTC 24 |
| Peak memory | 209648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516988964 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.516988964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_loopback.1539048942 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 2860890405 ps |
| CPU time | 3.22 seconds |
| Started | Sep 18 06:37:43 PM UTC 24 |
| Finished | Sep 18 06:37:47 PM UTC 24 |
| Peak memory | 207996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539048942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1539048942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_noise_filter.2071788088 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 148798476511 ps |
| CPU time | 93.34 seconds |
| Started | Sep 18 06:37:41 PM UTC 24 |
| Finished | Sep 18 06:39:17 PM UTC 24 |
| Peak memory | 209668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071788088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2071788088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_perf.723987369 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 17861795946 ps |
| CPU time | 1147.05 seconds |
| Started | Sep 18 06:37:45 PM UTC 24 |
| Finished | Sep 18 06:57:05 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723987369 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.723987369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_rx_oversample.976727299 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 7262610514 ps |
| CPU time | 62.57 seconds |
| Started | Sep 18 06:37:34 PM UTC 24 |
| Finished | Sep 18 06:38:38 PM UTC 24 |
| Peak memory | 208204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976727299 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.976727299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.1262653460 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 65428592540 ps |
| CPU time | 28.88 seconds |
| Started | Sep 18 06:37:42 PM UTC 24 |
| Finished | Sep 18 06:38:13 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262653460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1262653460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.716707673 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 3770299190 ps |
| CPU time | 14.08 seconds |
| Started | Sep 18 06:37:41 PM UTC 24 |
| Finished | Sep 18 06:37:57 PM UTC 24 |
| Peak memory | 203832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716707673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.716707673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_smoke.2521701484 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 5384402254 ps |
| CPU time | 13.84 seconds |
| Started | Sep 18 06:37:11 PM UTC 24 |
| Finished | Sep 18 06:37:26 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521701484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2521701484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_stress_all.1521431248 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 161749305181 ps |
| CPU time | 88.63 seconds |
| Started | Sep 18 06:37:50 PM UTC 24 |
| Finished | Sep 18 06:39:21 PM UTC 24 |
| Peak memory | 218704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521431248 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1521431248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.1905336014 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 3876393759 ps |
| CPU time | 51.21 seconds |
| Started | Sep 18 06:37:48 PM UTC 24 |
| Finished | Sep 18 06:38:41 PM UTC 24 |
| Peak memory | 218284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1905336014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all _with_rand_reset.1905336014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.2873342830 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 6765520014 ps |
| CPU time | 35.85 seconds |
| Started | Sep 18 06:37:42 PM UTC 24 |
| Finished | Sep 18 06:38:20 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873342830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2873342830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/40.uart_tx_rx.3601432251 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 64840507579 ps |
| CPU time | 18.93 seconds |
| Started | Sep 18 06:37:13 PM UTC 24 |
| Finished | Sep 18 06:37:33 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601432251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3601432251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/40.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_alert_test.4250217061 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 15974092 ps |
| CPU time | 0.89 seconds |
| Started | Sep 18 06:38:49 PM UTC 24 |
| Finished | Sep 18 06:38:52 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250217061 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.4250217061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_fifo_full.324784869 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 32188772952 ps |
| CPU time | 45.87 seconds |
| Started | Sep 18 06:38:01 PM UTC 24 |
| Finished | Sep 18 06:38:48 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324784869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.324784869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.2374543587 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 85609688375 ps |
| CPU time | 53.11 seconds |
| Started | Sep 18 06:38:04 PM UTC 24 |
| Finished | Sep 18 06:38:59 PM UTC 24 |
| Peak memory | 204048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374543587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2374543587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_fifo_reset.3989150614 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 30989446885 ps |
| CPU time | 82.69 seconds |
| Started | Sep 18 06:38:07 PM UTC 24 |
| Finished | Sep 18 06:39:32 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989150614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3989150614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_intr.2498752938 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 139937539604 ps |
| CPU time | 177.38 seconds |
| Started | Sep 18 06:38:14 PM UTC 24 |
| Finished | Sep 18 06:41:14 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498752938 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2498752938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.1493941222 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 68676666808 ps |
| CPU time | 660.89 seconds |
| Started | Sep 18 06:38:39 PM UTC 24 |
| Finished | Sep 18 06:49:48 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493941222 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1493941222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_loopback.3620137144 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 8716957529 ps |
| CPU time | 12.31 seconds |
| Started | Sep 18 06:38:38 PM UTC 24 |
| Finished | Sep 18 06:38:51 PM UTC 24 |
| Peak memory | 207864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620137144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3620137144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_noise_filter.35233627 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 45973755671 ps |
| CPU time | 93.46 seconds |
| Started | Sep 18 06:38:14 PM UTC 24 |
| Finished | Sep 18 06:39:49 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35233627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.35233627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_perf.280030629 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 18111842592 ps |
| CPU time | 443.91 seconds |
| Started | Sep 18 06:38:38 PM UTC 24 |
| Finished | Sep 18 06:46:07 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280030629 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.280030629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_rx_oversample.3980623358 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 4920671069 ps |
| CPU time | 25.99 seconds |
| Started | Sep 18 06:38:09 PM UTC 24 |
| Finished | Sep 18 06:38:37 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980623358 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3980623358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.2822081976 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 25863276705 ps |
| CPU time | 97.13 seconds |
| Started | Sep 18 06:38:21 PM UTC 24 |
| Finished | Sep 18 06:40:00 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822081976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2822081976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.2923737563 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 27372368240 ps |
| CPU time | 45.97 seconds |
| Started | Sep 18 06:38:21 PM UTC 24 |
| Finished | Sep 18 06:39:08 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923737563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2923737563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_smoke.3652051613 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 5530774356 ps |
| CPU time | 14.7 seconds |
| Started | Sep 18 06:37:57 PM UTC 24 |
| Finished | Sep 18 06:38:13 PM UTC 24 |
| Peak memory | 208928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652051613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3652051613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_stress_all.4166619649 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 409125282388 ps |
| CPU time | 238.21 seconds |
| Started | Sep 18 06:38:42 PM UTC 24 |
| Finished | Sep 18 06:42:44 PM UTC 24 |
| Peak memory | 208068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166619649 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.4166619649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.2401372353 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 4351931254 ps |
| CPU time | 136.33 seconds |
| Started | Sep 18 06:38:41 PM UTC 24 |
| Finished | Sep 18 06:41:00 PM UTC 24 |
| Peak memory | 220540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2401372353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all _with_rand_reset.2401372353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.2127787930 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 6320483610 ps |
| CPU time | 32.2 seconds |
| Started | Sep 18 06:38:29 PM UTC 24 |
| Finished | Sep 18 06:39:02 PM UTC 24 |
| Peak memory | 203716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127787930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2127787930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/41.uart_tx_rx.172989692 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4304296634 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 06:37:57 PM UTC 24 |
| Finished | Sep 18 06:38:00 PM UTC 24 |
| Peak memory | 208148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172989692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.172989692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/41.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_alert_test.561471818 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 85339457 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:39:39 PM UTC 24 |
| Finished | Sep 18 06:39:41 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561471818 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.561471818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_fifo_full.643488102 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 13522560620 ps |
| CPU time | 27.8 seconds |
| Started | Sep 18 06:38:58 PM UTC 24 |
| Finished | Sep 18 06:39:27 PM UTC 24 |
| Peak memory | 203984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643488102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.643488102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.3627273939 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 15308496903 ps |
| CPU time | 41.03 seconds |
| Started | Sep 18 06:38:59 PM UTC 24 |
| Finished | Sep 18 06:39:42 PM UTC 24 |
| Peak memory | 203524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627273939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3627273939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_fifo_reset.3066279657 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 175989069082 ps |
| CPU time | 180.49 seconds |
| Started | Sep 18 06:39:01 PM UTC 24 |
| Finished | Sep 18 06:42:04 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066279657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3066279657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_intr.91464549 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 54538826490 ps |
| CPU time | 126.42 seconds |
| Started | Sep 18 06:39:09 PM UTC 24 |
| Finished | Sep 18 06:41:18 PM UTC 24 |
| Peak memory | 204100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91464549 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.91464549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.2513005685 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 38550265538 ps |
| CPU time | 55.86 seconds |
| Started | Sep 18 06:39:28 PM UTC 24 |
| Finished | Sep 18 06:40:26 PM UTC 24 |
| Peak memory | 203832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513005685 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2513005685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_loopback.509585881 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 6253964392 ps |
| CPU time | 5.18 seconds |
| Started | Sep 18 06:39:21 PM UTC 24 |
| Finished | Sep 18 06:39:28 PM UTC 24 |
| Peak memory | 203856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509585881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 42.uart_loopback.509585881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_noise_filter.729090373 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 15276371592 ps |
| CPU time | 42.8 seconds |
| Started | Sep 18 06:39:14 PM UTC 24 |
| Finished | Sep 18 06:39:58 PM UTC 24 |
| Peak memory | 209608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729090373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.729090373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_perf.1743168317 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 19480365654 ps |
| CPU time | 886.29 seconds |
| Started | Sep 18 06:39:21 PM UTC 24 |
| Finished | Sep 18 06:54:18 PM UTC 24 |
| Peak memory | 207176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743168317 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1743168317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_rx_oversample.120585626 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 2008396372 ps |
| CPU time | 12.71 seconds |
| Started | Sep 18 06:39:03 PM UTC 24 |
| Finished | Sep 18 06:39:17 PM UTC 24 |
| Peak memory | 207936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120585626 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.120585626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.4280497592 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 184181707284 ps |
| CPU time | 35.22 seconds |
| Started | Sep 18 06:39:17 PM UTC 24 |
| Finished | Sep 18 06:39:54 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280497592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.4280497592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.3861774723 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 5824444797 ps |
| CPU time | 22.62 seconds |
| Started | Sep 18 06:39:14 PM UTC 24 |
| Finished | Sep 18 06:39:38 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861774723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3861774723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_smoke.4090777243 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 671054905 ps |
| CPU time | 4.79 seconds |
| Started | Sep 18 06:38:52 PM UTC 24 |
| Finished | Sep 18 06:38:58 PM UTC 24 |
| Peak memory | 203980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090777243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.uart_smoke.4090777243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_stress_all.1528416958 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 220800972679 ps |
| CPU time | 640.4 seconds |
| Started | Sep 18 06:39:33 PM UTC 24 |
| Finished | Sep 18 06:50:20 PM UTC 24 |
| Peak memory | 208016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528416958 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1528416958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.4143386947 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 4960344090 ps |
| CPU time | 46.18 seconds |
| Started | Sep 18 06:39:28 PM UTC 24 |
| Finished | Sep 18 06:40:17 PM UTC 24 |
| Peak memory | 225232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4143386947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all _with_rand_reset.4143386947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.2603881536 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 778215975 ps |
| CPU time | 1.84 seconds |
| Started | Sep 18 06:39:17 PM UTC 24 |
| Finished | Sep 18 06:39:20 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603881536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2603881536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/42.uart_tx_rx.3553009406 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 79860279896 ps |
| CPU time | 49.81 seconds |
| Started | Sep 18 06:38:52 PM UTC 24 |
| Finished | Sep 18 06:39:44 PM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553009406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3553009406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/42.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_alert_test.2291852509 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 14192111 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 06:40:17 PM UTC 24 |
| Finished | Sep 18 06:40:19 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291852509 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2291852509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_fifo_full.2366540394 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 62107875594 ps |
| CPU time | 153.04 seconds |
| Started | Sep 18 06:39:45 PM UTC 24 |
| Finished | Sep 18 06:42:21 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366540394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2366540394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.4234073908 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 63002103319 ps |
| CPU time | 60.7 seconds |
| Started | Sep 18 06:39:46 PM UTC 24 |
| Finished | Sep 18 06:40:48 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234073908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.4234073908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_fifo_reset.837967103 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 170233605882 ps |
| CPU time | 73.09 seconds |
| Started | Sep 18 06:39:49 PM UTC 24 |
| Finished | Sep 18 06:41:04 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837967103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.837967103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_intr.1113935241 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 66089758504 ps |
| CPU time | 41.71 seconds |
| Started | Sep 18 06:39:54 PM UTC 24 |
| Finished | Sep 18 06:40:37 PM UTC 24 |
| Peak memory | 209664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113935241 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1113935241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.3983559113 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 94904006115 ps |
| CPU time | 871.65 seconds |
| Started | Sep 18 06:40:08 PM UTC 24 |
| Finished | Sep 18 06:54:50 PM UTC 24 |
| Peak memory | 212728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983559113 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3983559113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_loopback.3296403424 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 6782149745 ps |
| CPU time | 5.64 seconds |
| Started | Sep 18 06:40:03 PM UTC 24 |
| Finished | Sep 18 06:40:09 PM UTC 24 |
| Peak memory | 203716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296403424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3296403424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_noise_filter.1699216145 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 40004134704 ps |
| CPU time | 52.41 seconds |
| Started | Sep 18 06:39:57 PM UTC 24 |
| Finished | Sep 18 06:40:51 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699216145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1699216145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_perf.160010626 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 15443650250 ps |
| CPU time | 937.27 seconds |
| Started | Sep 18 06:40:04 PM UTC 24 |
| Finished | Sep 18 06:55:51 PM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160010626 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.160010626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_rx_oversample.2556277325 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 2118217980 ps |
| CPU time | 10.31 seconds |
| Started | Sep 18 06:39:50 PM UTC 24 |
| Finished | Sep 18 06:40:02 PM UTC 24 |
| Peak memory | 208140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556277325 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2556277325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.4275948115 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 86078741859 ps |
| CPU time | 134.92 seconds |
| Started | Sep 18 06:40:00 PM UTC 24 |
| Finished | Sep 18 06:42:18 PM UTC 24 |
| Peak memory | 209120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275948115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.4275948115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.4019428479 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 6095154380 ps |
| CPU time | 13.48 seconds |
| Started | Sep 18 06:39:59 PM UTC 24 |
| Finished | Sep 18 06:40:14 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019428479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4019428479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_smoke.1316286149 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 518185634 ps |
| CPU time | 2.06 seconds |
| Started | Sep 18 06:39:42 PM UTC 24 |
| Finished | Sep 18 06:39:45 PM UTC 24 |
| Peak memory | 203732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316286149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1316286149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_stress_all.305205599 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 319264708012 ps |
| CPU time | 436.89 seconds |
| Started | Sep 18 06:40:15 PM UTC 24 |
| Finished | Sep 18 06:47:37 PM UTC 24 |
| Peak memory | 207944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305205599 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.305205599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.1365510625 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 10889890065 ps |
| CPU time | 36.13 seconds |
| Started | Sep 18 06:40:10 PM UTC 24 |
| Finished | Sep 18 06:40:47 PM UTC 24 |
| Peak memory | 226172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1365510625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all _with_rand_reset.1365510625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.1439248348 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 2512925045 ps |
| CPU time | 2.95 seconds |
| Started | Sep 18 06:40:03 PM UTC 24 |
| Finished | Sep 18 06:40:07 PM UTC 24 |
| Peak memory | 207932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439248348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1439248348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/43.uart_tx_rx.950640106 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 122718325400 ps |
| CPU time | 112.33 seconds |
| Started | Sep 18 06:39:43 PM UTC 24 |
| Finished | Sep 18 06:41:37 PM UTC 24 |
| Peak memory | 209400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950640106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.950640106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/43.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_alert_test.1384472118 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 80871687 ps |
| CPU time | 0.78 seconds |
| Started | Sep 18 06:40:54 PM UTC 24 |
| Finished | Sep 18 06:40:56 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384472118 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1384472118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_fifo_full.4250728272 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 22950323788 ps |
| CPU time | 46.69 seconds |
| Started | Sep 18 06:40:25 PM UTC 24 |
| Finished | Sep 18 06:41:14 PM UTC 24 |
| Peak memory | 209124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250728272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4250728272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.1373096521 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 16671307564 ps |
| CPU time | 25.82 seconds |
| Started | Sep 18 06:40:25 PM UTC 24 |
| Finished | Sep 18 06:40:53 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373096521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1373096521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_fifo_reset.3750411540 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 158161880572 ps |
| CPU time | 247.97 seconds |
| Started | Sep 18 06:40:26 PM UTC 24 |
| Finished | Sep 18 06:44:37 PM UTC 24 |
| Peak memory | 203992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750411540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3750411540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.157994157 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 121107403611 ps |
| CPU time | 1175.45 seconds |
| Started | Sep 18 06:40:48 PM UTC 24 |
| Finished | Sep 18 07:00:37 PM UTC 24 |
| Peak memory | 212716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157994157 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.157994157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_loopback.513933853 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 789010770 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 06:40:41 PM UTC 24 |
| Finished | Sep 18 06:40:43 PM UTC 24 |
| Peak memory | 205296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513933853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 44.uart_loopback.513933853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_noise_filter.1250109350 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 75108894096 ps |
| CPU time | 112.21 seconds |
| Started | Sep 18 06:40:36 PM UTC 24 |
| Finished | Sep 18 06:42:30 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250109350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1250109350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_perf.3444645647 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 4877515511 ps |
| CPU time | 38.07 seconds |
| Started | Sep 18 06:40:44 PM UTC 24 |
| Finished | Sep 18 06:41:24 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444645647 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3444645647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_rx_oversample.1572139894 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 4337458733 ps |
| CPU time | 7.02 seconds |
| Started | Sep 18 06:40:28 PM UTC 24 |
| Finished | Sep 18 06:40:36 PM UTC 24 |
| Peak memory | 208140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572139894 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1572139894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.101865006 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 319052651296 ps |
| CPU time | 313.25 seconds |
| Started | Sep 18 06:40:38 PM UTC 24 |
| Finished | Sep 18 06:45:55 PM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101865006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.101865006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.456860965 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 41574864893 ps |
| CPU time | 14.82 seconds |
| Started | Sep 18 06:40:37 PM UTC 24 |
| Finished | Sep 18 06:40:53 PM UTC 24 |
| Peak memory | 203832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456860965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.456860965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_smoke.841393215 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 633489210 ps |
| CPU time | 2.78 seconds |
| Started | Sep 18 06:40:20 PM UTC 24 |
| Finished | Sep 18 06:40:24 PM UTC 24 |
| Peak memory | 208360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841393215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 44.uart_smoke.841393215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_stress_all.1633792014 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 527177903172 ps |
| CPU time | 894.32 seconds |
| Started | Sep 18 06:40:52 PM UTC 24 |
| Finished | Sep 18 06:55:57 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633792014 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1633792014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.2479051802 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 2819583757 ps |
| CPU time | 45.99 seconds |
| Started | Sep 18 06:40:49 PM UTC 24 |
| Finished | Sep 18 06:41:38 PM UTC 24 |
| Peak memory | 220668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2479051802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all _with_rand_reset.2479051802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.2415792767 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 6408012077 ps |
| CPU time | 18.02 seconds |
| Started | Sep 18 06:40:40 PM UTC 24 |
| Finished | Sep 18 06:40:59 PM UTC 24 |
| Peak memory | 203772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415792767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2415792767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/44.uart_tx_rx.2336950999 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 3706140670 ps |
| CPU time | 13.67 seconds |
| Started | Sep 18 06:40:24 PM UTC 24 |
| Finished | Sep 18 06:40:39 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336950999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2336950999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_alert_test.1711564237 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 19649997 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 06:41:28 PM UTC 24 |
| Finished | Sep 18 06:41:30 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711564237 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1711564237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_fifo_full.2016467266 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 25223538001 ps |
| CPU time | 35.9 seconds |
| Started | Sep 18 06:41:00 PM UTC 24 |
| Finished | Sep 18 06:41:37 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016467266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2016467266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.3327220419 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 161643598646 ps |
| CPU time | 326.97 seconds |
| Started | Sep 18 06:41:01 PM UTC 24 |
| Finished | Sep 18 06:46:32 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327220419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3327220419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_fifo_reset.2919369393 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 134845031266 ps |
| CPU time | 22.37 seconds |
| Started | Sep 18 06:41:02 PM UTC 24 |
| Finished | Sep 18 06:41:26 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919369393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2919369393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_intr.988522179 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 58933318142 ps |
| CPU time | 114.4 seconds |
| Started | Sep 18 06:41:10 PM UTC 24 |
| Finished | Sep 18 06:43:07 PM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988522179 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.988522179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.1677156468 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 62084458952 ps |
| CPU time | 121.6 seconds |
| Started | Sep 18 06:41:24 PM UTC 24 |
| Finished | Sep 18 06:43:28 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677156468 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1677156468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_loopback.3656972861 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 6809031342 ps |
| CPU time | 17.75 seconds |
| Started | Sep 18 06:41:21 PM UTC 24 |
| Finished | Sep 18 06:41:40 PM UTC 24 |
| Peak memory | 204120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656972861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3656972861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_noise_filter.3085169287 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 51925124602 ps |
| CPU time | 24.29 seconds |
| Started | Sep 18 06:41:11 PM UTC 24 |
| Finished | Sep 18 06:41:37 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085169287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3085169287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_perf.1169252591 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 9147928025 ps |
| CPU time | 482.32 seconds |
| Started | Sep 18 06:41:23 PM UTC 24 |
| Finished | Sep 18 06:49:30 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169252591 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1169252591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_rx_oversample.4025676932 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 4018488559 ps |
| CPU time | 14.28 seconds |
| Started | Sep 18 06:41:05 PM UTC 24 |
| Finished | Sep 18 06:41:21 PM UTC 24 |
| Peak memory | 208204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025676932 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.4025676932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.3238031362 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 147564905059 ps |
| CPU time | 22.76 seconds |
| Started | Sep 18 06:41:14 PM UTC 24 |
| Finished | Sep 18 06:41:38 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238031362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3238031362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.3284649428 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 34603659804 ps |
| CPU time | 11.15 seconds |
| Started | Sep 18 06:41:14 PM UTC 24 |
| Finished | Sep 18 06:41:27 PM UTC 24 |
| Peak memory | 203900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284649428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3284649428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_smoke.3238213064 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 6315685719 ps |
| CPU time | 14.63 seconds |
| Started | Sep 18 06:40:54 PM UTC 24 |
| Finished | Sep 18 06:41:10 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238213064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3238213064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_stress_all.864734192 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 336313284758 ps |
| CPU time | 1214.98 seconds |
| Started | Sep 18 06:41:27 PM UTC 24 |
| Finished | Sep 18 07:01:55 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864734192 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.864734192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.2876093259 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 3232688209 ps |
| CPU time | 91.96 seconds |
| Started | Sep 18 06:41:25 PM UTC 24 |
| Finished | Sep 18 06:42:59 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2876093259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all _with_rand_reset.2876093259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.3345279052 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 1699818187 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 06:41:18 PM UTC 24 |
| Finished | Sep 18 06:41:22 PM UTC 24 |
| Peak memory | 203716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345279052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3345279052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/45.uart_tx_rx.924978936 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 112030852687 ps |
| CPU time | 48.92 seconds |
| Started | Sep 18 06:40:57 PM UTC 24 |
| Finished | Sep 18 06:41:47 PM UTC 24 |
| Peak memory | 209668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924978936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.924978936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/45.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_alert_test.3234136306 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 22948769 ps |
| CPU time | 0.86 seconds |
| Started | Sep 18 06:42:19 PM UTC 24 |
| Finished | Sep 18 06:42:21 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234136306 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3234136306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_fifo_full.1428727829 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 52680958875 ps |
| CPU time | 46.25 seconds |
| Started | Sep 18 06:41:37 PM UTC 24 |
| Finished | Sep 18 06:42:25 PM UTC 24 |
| Peak memory | 209284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428727829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1428727829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.2410591159 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 43282955801 ps |
| CPU time | 42.17 seconds |
| Started | Sep 18 06:41:38 PM UTC 24 |
| Finished | Sep 18 06:42:22 PM UTC 24 |
| Peak memory | 203828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410591159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2410591159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_fifo_reset.4042708165 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 70728438126 ps |
| CPU time | 45.42 seconds |
| Started | Sep 18 06:41:38 PM UTC 24 |
| Finished | Sep 18 06:42:25 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042708165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.4042708165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_intr.3887752283 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 65335043040 ps |
| CPU time | 55.97 seconds |
| Started | Sep 18 06:41:40 PM UTC 24 |
| Finished | Sep 18 06:42:37 PM UTC 24 |
| Peak memory | 209208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887752283 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3887752283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.1884834424 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 112265799494 ps |
| CPU time | 417.86 seconds |
| Started | Sep 18 06:42:11 PM UTC 24 |
| Finished | Sep 18 06:49:14 PM UTC 24 |
| Peak memory | 209580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884834424 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1884834424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_loopback.4284899724 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 183371691 ps |
| CPU time | 1 seconds |
| Started | Sep 18 06:42:05 PM UTC 24 |
| Finished | Sep 18 06:42:07 PM UTC 24 |
| Peak memory | 205300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284899724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 46.uart_loopback.4284899724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_noise_filter.950682922 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 20219693097 ps |
| CPU time | 51.19 seconds |
| Started | Sep 18 06:41:42 PM UTC 24 |
| Finished | Sep 18 06:42:34 PM UTC 24 |
| Peak memory | 209684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950682922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.950682922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_perf.1948640057 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 15509700925 ps |
| CPU time | 179.35 seconds |
| Started | Sep 18 06:42:08 PM UTC 24 |
| Finished | Sep 18 06:45:10 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948640057 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1948640057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_rx_oversample.3046515232 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2832370348 ps |
| CPU time | 30.7 seconds |
| Started | Sep 18 06:41:38 PM UTC 24 |
| Finished | Sep 18 06:42:10 PM UTC 24 |
| Peak memory | 208024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046515232 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3046515232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.538063053 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 21564389020 ps |
| CPU time | 54.93 seconds |
| Started | Sep 18 06:41:55 PM UTC 24 |
| Finished | Sep 18 06:42:51 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538063053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.538063053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.3368205125 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 5450066079 ps |
| CPU time | 9.54 seconds |
| Started | Sep 18 06:41:48 PM UTC 24 |
| Finished | Sep 18 06:41:58 PM UTC 24 |
| Peak memory | 203836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368205125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3368205125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_smoke.3092047588 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 275141189 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 06:41:30 PM UTC 24 |
| Finished | Sep 18 06:41:33 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092047588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3092047588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_stress_all.3801881557 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 38224784431 ps |
| CPU time | 893.19 seconds |
| Started | Sep 18 06:42:16 PM UTC 24 |
| Finished | Sep 18 06:57:20 PM UTC 24 |
| Peak memory | 207396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801881557 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3801881557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.969058150 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2170489123 ps |
| CPU time | 50.03 seconds |
| Started | Sep 18 06:42:16 PM UTC 24 |
| Finished | Sep 18 06:43:07 PM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=969058150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all_ with_rand_reset.969058150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.2075387731 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 6339846532 ps |
| CPU time | 40.09 seconds |
| Started | Sep 18 06:41:59 PM UTC 24 |
| Finished | Sep 18 06:42:40 PM UTC 24 |
| Peak memory | 208376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075387731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2075387731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/46.uart_tx_rx.3739905577 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 82941330093 ps |
| CPU time | 185.98 seconds |
| Started | Sep 18 06:41:34 PM UTC 24 |
| Finished | Sep 18 06:44:43 PM UTC 24 |
| Peak memory | 209388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739905577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3739905577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/46.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_alert_test.3188969432 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 12060270 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 06:42:49 PM UTC 24 |
| Finished | Sep 18 06:42:51 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188969432 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3188969432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_fifo_full.2859609456 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 33131420893 ps |
| CPU time | 60.32 seconds |
| Started | Sep 18 06:42:22 PM UTC 24 |
| Finished | Sep 18 06:43:24 PM UTC 24 |
| Peak memory | 204100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859609456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2859609456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.644691724 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 36197559781 ps |
| CPU time | 26.67 seconds |
| Started | Sep 18 06:42:23 PM UTC 24 |
| Finished | Sep 18 06:42:51 PM UTC 24 |
| Peak memory | 208996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644691724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.644691724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_fifo_reset.3818828180 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 70045574831 ps |
| CPU time | 41.69 seconds |
| Started | Sep 18 06:42:24 PM UTC 24 |
| Finished | Sep 18 06:43:07 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818828180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3818828180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_intr.1114947718 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 20493361397 ps |
| CPU time | 18.58 seconds |
| Started | Sep 18 06:42:26 PM UTC 24 |
| Finished | Sep 18 06:42:47 PM UTC 24 |
| Peak memory | 207672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114947718 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1114947718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.2952547944 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 109873015490 ps |
| CPU time | 220.18 seconds |
| Started | Sep 18 06:42:45 PM UTC 24 |
| Finished | Sep 18 06:46:29 PM UTC 24 |
| Peak memory | 205824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952547944 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2952547944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_loopback.3430689959 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 7557224629 ps |
| CPU time | 9.86 seconds |
| Started | Sep 18 06:42:42 PM UTC 24 |
| Finished | Sep 18 06:42:53 PM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430689959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3430689959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_noise_filter.3748590543 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 145420392711 ps |
| CPU time | 119.01 seconds |
| Started | Sep 18 06:42:30 PM UTC 24 |
| Finished | Sep 18 06:44:32 PM UTC 24 |
| Peak memory | 209384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748590543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3748590543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_perf.1565952200 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 11068328915 ps |
| CPU time | 184.56 seconds |
| Started | Sep 18 06:42:42 PM UTC 24 |
| Finished | Sep 18 06:45:49 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565952200 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1565952200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_rx_oversample.3814797833 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 5203279125 ps |
| CPU time | 51.73 seconds |
| Started | Sep 18 06:42:26 PM UTC 24 |
| Finished | Sep 18 06:43:20 PM UTC 24 |
| Peak memory | 203980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814797833 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3814797833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.3782537135 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 3878786493 ps |
| CPU time | 7.36 seconds |
| Started | Sep 18 06:42:35 PM UTC 24 |
| Finished | Sep 18 06:42:44 PM UTC 24 |
| Peak memory | 209220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782537135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3782537135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.4002439364 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 6241654466 ps |
| CPU time | 14.94 seconds |
| Started | Sep 18 06:42:31 PM UTC 24 |
| Finished | Sep 18 06:42:48 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002439364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4002439364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_smoke.1514895414 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 719850545 ps |
| CPU time | 2.24 seconds |
| Started | Sep 18 06:42:20 PM UTC 24 |
| Finished | Sep 18 06:42:23 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514895414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1514895414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_stress_all.2219323458 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 385860101880 ps |
| CPU time | 1763.03 seconds |
| Started | Sep 18 06:42:48 PM UTC 24 |
| Finished | Sep 18 07:12:30 PM UTC 24 |
| Peak memory | 227288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219323458 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2219323458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.4070094157 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 6212439488 ps |
| CPU time | 57.49 seconds |
| Started | Sep 18 06:42:45 PM UTC 24 |
| Finished | Sep 18 06:43:44 PM UTC 24 |
| Peak memory | 220672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4070094157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all _with_rand_reset.4070094157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.445237573 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 7600340825 ps |
| CPU time | 17.55 seconds |
| Started | Sep 18 06:42:38 PM UTC 24 |
| Finished | Sep 18 06:42:57 PM UTC 24 |
| Peak memory | 209016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445237573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.445237573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/47.uart_tx_rx.1447154553 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 14242601341 ps |
| CPU time | 36.5 seconds |
| Started | Sep 18 06:42:22 PM UTC 24 |
| Finished | Sep 18 06:43:00 PM UTC 24 |
| Peak memory | 204040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447154553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1447154553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/47.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_alert_test.1013581049 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 38607539 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 06:43:15 PM UTC 24 |
| Finished | Sep 18 06:43:17 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013581049 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1013581049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_fifo_full.4025571785 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 6381054728 ps |
| CPU time | 22.24 seconds |
| Started | Sep 18 06:42:52 PM UTC 24 |
| Finished | Sep 18 06:43:16 PM UTC 24 |
| Peak memory | 204100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025571785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.4025571785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.1204209572 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 44474505032 ps |
| CPU time | 44.94 seconds |
| Started | Sep 18 06:42:53 PM UTC 24 |
| Finished | Sep 18 06:43:40 PM UTC 24 |
| Peak memory | 209540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204209572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1204209572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_fifo_reset.332041475 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 10964806307 ps |
| CPU time | 24.08 seconds |
| Started | Sep 18 06:42:56 PM UTC 24 |
| Finished | Sep 18 06:43:22 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332041475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.332041475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_intr.2781214047 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 25524225205 ps |
| CPU time | 59.5 seconds |
| Started | Sep 18 06:43:00 PM UTC 24 |
| Finished | Sep 18 06:44:01 PM UTC 24 |
| Peak memory | 208656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781214047 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2781214047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.1170871776 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 173523908168 ps |
| CPU time | 1549.52 seconds |
| Started | Sep 18 06:43:08 PM UTC 24 |
| Finished | Sep 18 07:09:14 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170871776 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1170871776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_loopback.2653755881 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 4305102204 ps |
| CPU time | 13.6 seconds |
| Started | Sep 18 06:43:08 PM UTC 24 |
| Finished | Sep 18 06:43:23 PM UTC 24 |
| Peak memory | 207944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653755881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2653755881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_noise_filter.1744971163 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 120118984662 ps |
| CPU time | 75.89 seconds |
| Started | Sep 18 06:43:00 PM UTC 24 |
| Finished | Sep 18 06:44:17 PM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744971163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1744971163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_perf.2756268006 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 22733441800 ps |
| CPU time | 572.1 seconds |
| Started | Sep 18 06:43:08 PM UTC 24 |
| Finished | Sep 18 06:52:47 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756268006 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2756268006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_rx_oversample.3731075378 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 1913622955 ps |
| CPU time | 3.23 seconds |
| Started | Sep 18 06:42:57 PM UTC 24 |
| Finished | Sep 18 06:43:02 PM UTC 24 |
| Peak memory | 208012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731075378 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3731075378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.3953751321 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 10242824499 ps |
| CPU time | 8.98 seconds |
| Started | Sep 18 06:43:03 PM UTC 24 |
| Finished | Sep 18 06:43:13 PM UTC 24 |
| Peak memory | 203588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953751321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3953751321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.1347267671 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 3724835891 ps |
| CPU time | 13.07 seconds |
| Started | Sep 18 06:43:01 PM UTC 24 |
| Finished | Sep 18 06:43:15 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347267671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1347267671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_smoke.1285878135 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 296470266 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 06:42:52 PM UTC 24 |
| Finished | Sep 18 06:42:55 PM UTC 24 |
| Peak memory | 207820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285878135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1285878135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_stress_all.1288174828 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 527922771559 ps |
| CPU time | 390.38 seconds |
| Started | Sep 18 06:43:13 PM UTC 24 |
| Finished | Sep 18 06:49:48 PM UTC 24 |
| Peak memory | 206488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288174828 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1288174828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.1038208737 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 7254908609 ps |
| CPU time | 66.97 seconds |
| Started | Sep 18 06:43:10 PM UTC 24 |
| Finished | Sep 18 06:44:19 PM UTC 24 |
| Peak memory | 220348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1038208737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all _with_rand_reset.1038208737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.2350330146 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 3448491808 ps |
| CPU time | 1.95 seconds |
| Started | Sep 18 06:43:07 PM UTC 24 |
| Finished | Sep 18 06:43:10 PM UTC 24 |
| Peak memory | 208036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350330146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2350330146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/48.uart_tx_rx.381754575 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 39733748620 ps |
| CPU time | 94.65 seconds |
| Started | Sep 18 06:42:52 PM UTC 24 |
| Finished | Sep 18 06:44:29 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381754575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.381754575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/48.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_alert_test.321367583 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 12831879 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:43:41 PM UTC 24 |
| Finished | Sep 18 06:43:43 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321367583 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.321367583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_fifo_full.363570752 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 223482768486 ps |
| CPU time | 251.42 seconds |
| Started | Sep 18 06:43:18 PM UTC 24 |
| Finished | Sep 18 06:47:32 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363570752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.363570752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.1377869462 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 133060495976 ps |
| CPU time | 49.4 seconds |
| Started | Sep 18 06:43:21 PM UTC 24 |
| Finished | Sep 18 06:44:11 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377869462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1377869462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_fifo_reset.1509551976 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 31098314705 ps |
| CPU time | 41.58 seconds |
| Started | Sep 18 06:43:21 PM UTC 24 |
| Finished | Sep 18 06:44:04 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509551976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1509551976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_intr.601629503 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 9711716920 ps |
| CPU time | 33.24 seconds |
| Started | Sep 18 06:43:23 PM UTC 24 |
| Finished | Sep 18 06:43:57 PM UTC 24 |
| Peak memory | 208856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601629503 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.601629503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.1685666530 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 248328857911 ps |
| CPU time | 405.21 seconds |
| Started | Sep 18 06:43:28 PM UTC 24 |
| Finished | Sep 18 06:50:19 PM UTC 24 |
| Peak memory | 205896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685666530 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1685666530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_loopback.3554796213 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 627219071 ps |
| CPU time | 1.34 seconds |
| Started | Sep 18 06:43:25 PM UTC 24 |
| Finished | Sep 18 06:43:28 PM UTC 24 |
| Peak memory | 203316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554796213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3554796213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_noise_filter.798074023 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 281678076948 ps |
| CPU time | 182.82 seconds |
| Started | Sep 18 06:43:24 PM UTC 24 |
| Finished | Sep 18 06:46:31 PM UTC 24 |
| Peak memory | 218500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798074023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.798074023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_perf.583137297 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 15407516658 ps |
| CPU time | 897.58 seconds |
| Started | Sep 18 06:43:28 PM UTC 24 |
| Finished | Sep 18 06:58:37 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583137297 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.583137297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_rx_oversample.453015858 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 1601107594 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 06:43:22 PM UTC 24 |
| Finished | Sep 18 06:43:24 PM UTC 24 |
| Peak memory | 207272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453015858 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.453015858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.2335861408 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 90941682730 ps |
| CPU time | 91.71 seconds |
| Started | Sep 18 06:43:24 PM UTC 24 |
| Finished | Sep 18 06:44:58 PM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335861408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2335861408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.1748098469 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 457479828 ps |
| CPU time | 2.28 seconds |
| Started | Sep 18 06:43:24 PM UTC 24 |
| Finished | Sep 18 06:43:27 PM UTC 24 |
| Peak memory | 203772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748098469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1748098469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_smoke.2773113540 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 688391258 ps |
| CPU time | 2.97 seconds |
| Started | Sep 18 06:43:16 PM UTC 24 |
| Finished | Sep 18 06:43:20 PM UTC 24 |
| Peak memory | 207832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773113540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2773113540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_stress_all.1189515805 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 227378744277 ps |
| CPU time | 591.3 seconds |
| Started | Sep 18 06:43:30 PM UTC 24 |
| Finished | Sep 18 06:53:28 PM UTC 24 |
| Peak memory | 215124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189515805 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1189515805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.3854342788 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 54103760193 ps |
| CPU time | 90.2 seconds |
| Started | Sep 18 06:43:28 PM UTC 24 |
| Finished | Sep 18 06:45:01 PM UTC 24 |
| Peak memory | 226440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3854342788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all _with_rand_reset.3854342788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.3791784519 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 1189053932 ps |
| CPU time | 2.68 seconds |
| Started | Sep 18 06:43:25 PM UTC 24 |
| Finished | Sep 18 06:43:29 PM UTC 24 |
| Peak memory | 203976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791784519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3791784519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/49.uart_tx_rx.192347654 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 69890101067 ps |
| CPU time | 33.3 seconds |
| Started | Sep 18 06:43:17 PM UTC 24 |
| Finished | Sep 18 06:43:51 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192347654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.192347654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/49.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_alert_test.2814872995 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 64891198 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 06:17:06 PM UTC 24 |
| Finished | Sep 18 06:17:08 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814872995 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2814872995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_fifo_full.3901724065 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 109309756629 ps |
| CPU time | 221.75 seconds |
| Started | Sep 18 06:16:48 PM UTC 24 |
| Finished | Sep 18 06:20:33 PM UTC 24 |
| Peak memory | 209664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901724065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3901724065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.877977346 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 98625191582 ps |
| CPU time | 217.11 seconds |
| Started | Sep 18 06:16:48 PM UTC 24 |
| Finished | Sep 18 06:20:28 PM UTC 24 |
| Peak memory | 204048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877977346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.877977346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_fifo_reset.1410110923 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 17670239325 ps |
| CPU time | 33.46 seconds |
| Started | Sep 18 06:16:49 PM UTC 24 |
| Finished | Sep 18 06:17:24 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410110923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1410110923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.900928234 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 242523502356 ps |
| CPU time | 401.03 seconds |
| Started | Sep 18 06:17:00 PM UTC 24 |
| Finished | Sep 18 06:23:46 PM UTC 24 |
| Peak memory | 205828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900928234 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.900928234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_loopback.2330631865 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 11271090561 ps |
| CPU time | 21.13 seconds |
| Started | Sep 18 06:16:56 PM UTC 24 |
| Finished | Sep 18 06:17:18 PM UTC 24 |
| Peak memory | 208480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330631865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2330631865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_perf.378027832 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 6023016326 ps |
| CPU time | 330.08 seconds |
| Started | Sep 18 06:16:57 PM UTC 24 |
| Finished | Sep 18 06:22:32 PM UTC 24 |
| Peak memory | 203772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378027832 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.378027832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_rx_oversample.1542769838 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 5709258819 ps |
| CPU time | 12.39 seconds |
| Started | Sep 18 06:16:49 PM UTC 24 |
| Finished | Sep 18 06:17:03 PM UTC 24 |
| Peak memory | 208540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542769838 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1542769838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.830538058 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 28628874183 ps |
| CPU time | 24.09 seconds |
| Started | Sep 18 06:16:54 PM UTC 24 |
| Finished | Sep 18 06:17:19 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830538058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.830538058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.3069834037 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1336349121 ps |
| CPU time | 5.97 seconds |
| Started | Sep 18 06:16:53 PM UTC 24 |
| Finished | Sep 18 06:17:00 PM UTC 24 |
| Peak memory | 203520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069834037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3069834037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_smoke.1129008957 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 5904949964 ps |
| CPU time | 33.91 seconds |
| Started | Sep 18 06:16:47 PM UTC 24 |
| Finished | Sep 18 06:17:22 PM UTC 24 |
| Peak memory | 208508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129008957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1129008957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_stress_all.3572553941 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 29296961787 ps |
| CPU time | 55.43 seconds |
| Started | Sep 18 06:17:05 PM UTC 24 |
| Finished | Sep 18 06:18:02 PM UTC 24 |
| Peak memory | 209664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572553941 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3572553941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.2178673062 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 8606482408 ps |
| CPU time | 13.84 seconds |
| Started | Sep 18 06:16:55 PM UTC 24 |
| Finished | Sep 18 06:17:10 PM UTC 24 |
| Peak memory | 209044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178673062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2178673062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/5.uart_tx_rx.3197375869 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 55104993074 ps |
| CPU time | 107.19 seconds |
| Started | Sep 18 06:16:47 PM UTC 24 |
| Finished | Sep 18 06:18:36 PM UTC 24 |
| Peak memory | 209208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197375869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3197375869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/50.uart_fifo_reset.1481189130 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 60705543102 ps |
| CPU time | 147.83 seconds |
| Started | Sep 18 06:43:42 PM UTC 24 |
| Finished | Sep 18 06:46:12 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481189130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1481189130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/50.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.2408407849 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 5581306588 ps |
| CPU time | 21.84 seconds |
| Started | Sep 18 06:43:43 PM UTC 24 |
| Finished | Sep 18 06:44:06 PM UTC 24 |
| Peak memory | 218564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2408407849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all _with_rand_reset.2408407849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/51.uart_fifo_reset.1504603204 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 61895916120 ps |
| CPU time | 82.56 seconds |
| Started | Sep 18 06:43:45 PM UTC 24 |
| Finished | Sep 18 06:45:09 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504603204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1504603204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/51.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.4186439510 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 10557904654 ps |
| CPU time | 66.55 seconds |
| Started | Sep 18 06:43:46 PM UTC 24 |
| Finished | Sep 18 06:44:54 PM UTC 24 |
| Peak memory | 218364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4186439510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all _with_rand_reset.4186439510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/52.uart_fifo_reset.2350405969 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 37193523895 ps |
| CPU time | 82.29 seconds |
| Started | Sep 18 06:43:49 PM UTC 24 |
| Finished | Sep 18 06:45:13 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350405969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2350405969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/52.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.1788621049 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 4558427200 ps |
| CPU time | 58.44 seconds |
| Started | Sep 18 06:43:52 PM UTC 24 |
| Finished | Sep 18 06:44:53 PM UTC 24 |
| Peak memory | 226068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1788621049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all _with_rand_reset.1788621049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/53.uart_fifo_reset.2709371347 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 92952221060 ps |
| CPU time | 37.81 seconds |
| Started | Sep 18 06:43:58 PM UTC 24 |
| Finished | Sep 18 06:44:38 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709371347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2709371347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/53.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.2377937564 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 19166695277 ps |
| CPU time | 79.54 seconds |
| Started | Sep 18 06:44:01 PM UTC 24 |
| Finished | Sep 18 06:45:23 PM UTC 24 |
| Peak memory | 220660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2377937564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all _with_rand_reset.2377937564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/54.uart_fifo_reset.3382316789 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 18501756553 ps |
| CPU time | 65.28 seconds |
| Started | Sep 18 06:44:04 PM UTC 24 |
| Finished | Sep 18 06:45:12 PM UTC 24 |
| Peak memory | 209612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382316789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3382316789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/54.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.620601553 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 3611417690 ps |
| CPU time | 40.38 seconds |
| Started | Sep 18 06:44:06 PM UTC 24 |
| Finished | Sep 18 06:44:48 PM UTC 24 |
| Peak memory | 218616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=620601553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all_ with_rand_reset.620601553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/55.uart_fifo_reset.1636839641 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 123004161518 ps |
| CPU time | 232.89 seconds |
| Started | Sep 18 06:44:13 PM UTC 24 |
| Finished | Sep 18 06:48:09 PM UTC 24 |
| Peak memory | 209580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636839641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1636839641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/55.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.53674432 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 2264701588 ps |
| CPU time | 101.57 seconds |
| Started | Sep 18 06:44:18 PM UTC 24 |
| Finished | Sep 18 06:46:01 PM UTC 24 |
| Peak memory | 218548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=53674432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all_w ith_rand_reset.53674432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/56.uart_fifo_reset.2864095778 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 153968470674 ps |
| CPU time | 581.42 seconds |
| Started | Sep 18 06:44:20 PM UTC 24 |
| Finished | Sep 18 06:54:08 PM UTC 24 |
| Peak memory | 209576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864095778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2864095778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/56.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.839419462 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 4286273393 ps |
| CPU time | 43.85 seconds |
| Started | Sep 18 06:44:30 PM UTC 24 |
| Finished | Sep 18 06:45:15 PM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=839419462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all_ with_rand_reset.839419462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/57.uart_fifo_reset.1337539064 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 160103020155 ps |
| CPU time | 117.33 seconds |
| Started | Sep 18 06:44:33 PM UTC 24 |
| Finished | Sep 18 06:46:32 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337539064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1337539064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/57.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.1278990059 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 1467831217 ps |
| CPU time | 25.31 seconds |
| Started | Sep 18 06:44:38 PM UTC 24 |
| Finished | Sep 18 06:45:05 PM UTC 24 |
| Peak memory | 220280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1278990059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all _with_rand_reset.1278990059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/58.uart_fifo_reset.2025911584 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 61570358594 ps |
| CPU time | 45.77 seconds |
| Started | Sep 18 06:44:39 PM UTC 24 |
| Finished | Sep 18 06:45:26 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025911584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2025911584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/58.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.1991275994 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 12511847893 ps |
| CPU time | 76.13 seconds |
| Started | Sep 18 06:44:44 PM UTC 24 |
| Finished | Sep 18 06:46:02 PM UTC 24 |
| Peak memory | 218896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1991275994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all _with_rand_reset.1991275994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/59.uart_fifo_reset.1780758744 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 12162534400 ps |
| CPU time | 35.24 seconds |
| Started | Sep 18 06:44:47 PM UTC 24 |
| Finished | Sep 18 06:45:25 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780758744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1780758744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/59.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.1578190981 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 5234317311 ps |
| CPU time | 31.33 seconds |
| Started | Sep 18 06:44:49 PM UTC 24 |
| Finished | Sep 18 06:45:22 PM UTC 24 |
| Peak memory | 218540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1578190981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all _with_rand_reset.1578190981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_alert_test.199935479 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 30948342 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 06:17:26 PM UTC 24 |
| Finished | Sep 18 06:17:27 PM UTC 24 |
| Peak memory | 203120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199935479 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.199935479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_fifo_full.3887178484 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 117020743503 ps |
| CPU time | 73.94 seconds |
| Started | Sep 18 06:17:09 PM UTC 24 |
| Finished | Sep 18 06:18:24 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887178484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3887178484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.4022265437 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 73538174661 ps |
| CPU time | 47.18 seconds |
| Started | Sep 18 06:17:10 PM UTC 24 |
| Finished | Sep 18 06:17:58 PM UTC 24 |
| Peak memory | 208960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022265437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.4022265437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_fifo_reset.1460990605 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 128320572392 ps |
| CPU time | 23.61 seconds |
| Started | Sep 18 06:17:10 PM UTC 24 |
| Finished | Sep 18 06:17:34 PM UTC 24 |
| Peak memory | 203840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460990605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1460990605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_intr.1417111379 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 46210321239 ps |
| CPU time | 131.03 seconds |
| Started | Sep 18 06:17:11 PM UTC 24 |
| Finished | Sep 18 06:19:24 PM UTC 24 |
| Peak memory | 209072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417111379 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1417111379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.346111915 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 31929970966 ps |
| CPU time | 84.76 seconds |
| Started | Sep 18 06:17:24 PM UTC 24 |
| Finished | Sep 18 06:18:51 PM UTC 24 |
| Peak memory | 209180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346111915 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.346111915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_loopback.2652163759 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 9209986873 ps |
| CPU time | 6.83 seconds |
| Started | Sep 18 06:17:21 PM UTC 24 |
| Finished | Sep 18 06:17:29 PM UTC 24 |
| Peak memory | 208224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652163759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2652163759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_noise_filter.2248031073 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 83033471720 ps |
| CPU time | 226.85 seconds |
| Started | Sep 18 06:17:16 PM UTC 24 |
| Finished | Sep 18 06:21:06 PM UTC 24 |
| Peak memory | 208528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248031073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2248031073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_perf.472208475 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 13775049370 ps |
| CPU time | 127 seconds |
| Started | Sep 18 06:17:23 PM UTC 24 |
| Finished | Sep 18 06:19:32 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472208475 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.472208475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_rx_oversample.1453920849 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1181305779 ps |
| CPU time | 2.95 seconds |
| Started | Sep 18 06:17:11 PM UTC 24 |
| Finished | Sep 18 06:17:15 PM UTC 24 |
| Peak memory | 205552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453920849 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1453920849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.107300910 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 6150335611 ps |
| CPU time | 6.06 seconds |
| Started | Sep 18 06:17:16 PM UTC 24 |
| Finished | Sep 18 06:17:23 PM UTC 24 |
| Peak memory | 203588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107300910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.107300910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_smoke.1147250067 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 269463478 ps |
| CPU time | 1.53 seconds |
| Started | Sep 18 06:17:06 PM UTC 24 |
| Finished | Sep 18 06:17:09 PM UTC 24 |
| Peak memory | 203268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147250067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1147250067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.1649392559 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3418146404 ps |
| CPU time | 32.97 seconds |
| Started | Sep 18 06:17:24 PM UTC 24 |
| Finished | Sep 18 06:17:59 PM UTC 24 |
| Peak memory | 218512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1649392559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_ with_rand_reset.1649392559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.2778611713 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1386964599 ps |
| CPU time | 3.86 seconds |
| Started | Sep 18 06:17:20 PM UTC 24 |
| Finished | Sep 18 06:17:25 PM UTC 24 |
| Peak memory | 208252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778611713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2778611713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/6.uart_tx_rx.1144911216 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 20307863225 ps |
| CPU time | 24.18 seconds |
| Started | Sep 18 06:17:08 PM UTC 24 |
| Finished | Sep 18 06:17:34 PM UTC 24 |
| Peak memory | 204044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144911216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1144911216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/6.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.41295914 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 6362004477 ps |
| CPU time | 29.31 seconds |
| Started | Sep 18 06:44:56 PM UTC 24 |
| Finished | Sep 18 06:45:26 PM UTC 24 |
| Peak memory | 220604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=41295914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all_w ith_rand_reset.41295914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/61.uart_fifo_reset.1412731043 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 95257777707 ps |
| CPU time | 24.57 seconds |
| Started | Sep 18 06:44:58 PM UTC 24 |
| Finished | Sep 18 06:45:23 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412731043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1412731043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/61.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.339579534 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 20402928905 ps |
| CPU time | 66.66 seconds |
| Started | Sep 18 06:44:59 PM UTC 24 |
| Finished | Sep 18 06:46:07 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=339579534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all_ with_rand_reset.339579534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/62.uart_fifo_reset.3500921507 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 72655810587 ps |
| CPU time | 107.09 seconds |
| Started | Sep 18 06:45:02 PM UTC 24 |
| Finished | Sep 18 06:46:51 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500921507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3500921507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/62.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.1149428829 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 13151560962 ps |
| CPU time | 48.16 seconds |
| Started | Sep 18 06:45:06 PM UTC 24 |
| Finished | Sep 18 06:45:56 PM UTC 24 |
| Peak memory | 225324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1149428829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all _with_rand_reset.1149428829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/63.uart_fifo_reset.365590433 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 33342686618 ps |
| CPU time | 89.27 seconds |
| Started | Sep 18 06:45:10 PM UTC 24 |
| Finished | Sep 18 06:46:41 PM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365590433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.365590433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/63.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.208857727 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 7822506393 ps |
| CPU time | 52.79 seconds |
| Started | Sep 18 06:45:11 PM UTC 24 |
| Finished | Sep 18 06:46:06 PM UTC 24 |
| Peak memory | 220344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=208857727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all_ with_rand_reset.208857727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/64.uart_fifo_reset.2197953452 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 14070566226 ps |
| CPU time | 34.75 seconds |
| Started | Sep 18 06:45:12 PM UTC 24 |
| Finished | Sep 18 06:45:48 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197953452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2197953452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/64.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.3011586786 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 15783573961 ps |
| CPU time | 19.06 seconds |
| Started | Sep 18 06:45:14 PM UTC 24 |
| Finished | Sep 18 06:45:34 PM UTC 24 |
| Peak memory | 218556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3011586786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all _with_rand_reset.3011586786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/65.uart_fifo_reset.773587159 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 20435714134 ps |
| CPU time | 56.42 seconds |
| Started | Sep 18 06:45:16 PM UTC 24 |
| Finished | Sep 18 06:46:14 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773587159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.773587159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/65.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.35098610 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 11588516756 ps |
| CPU time | 27.86 seconds |
| Started | Sep 18 06:45:22 PM UTC 24 |
| Finished | Sep 18 06:45:52 PM UTC 24 |
| Peak memory | 220360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=35098610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all_w ith_rand_reset.35098610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.2663823549 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 19225383192 ps |
| CPU time | 75.45 seconds |
| Started | Sep 18 06:45:25 PM UTC 24 |
| Finished | Sep 18 06:46:42 PM UTC 24 |
| Peak memory | 222648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2663823549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all _with_rand_reset.2663823549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/67.uart_fifo_reset.3584909006 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 10586546374 ps |
| CPU time | 35.13 seconds |
| Started | Sep 18 06:45:26 PM UTC 24 |
| Finished | Sep 18 06:46:02 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584909006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3584909006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/67.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.4087125922 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 6717821017 ps |
| CPU time | 28.15 seconds |
| Started | Sep 18 06:45:27 PM UTC 24 |
| Finished | Sep 18 06:45:56 PM UTC 24 |
| Peak memory | 218300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4087125922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all _with_rand_reset.4087125922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/68.uart_fifo_reset.2810179900 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 362355359407 ps |
| CPU time | 152.75 seconds |
| Started | Sep 18 06:45:27 PM UTC 24 |
| Finished | Sep 18 06:48:02 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810179900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2810179900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/68.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.2407324461 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 7593499032 ps |
| CPU time | 70.12 seconds |
| Started | Sep 18 06:45:27 PM UTC 24 |
| Finished | Sep 18 06:46:39 PM UTC 24 |
| Peak memory | 218552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2407324461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all _with_rand_reset.2407324461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/69.uart_fifo_reset.3563340228 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 19522538746 ps |
| CPU time | 25.29 seconds |
| Started | Sep 18 06:45:35 PM UTC 24 |
| Finished | Sep 18 06:46:02 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563340228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3563340228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/69.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.4240832826 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 1303139285 ps |
| CPU time | 27.85 seconds |
| Started | Sep 18 06:45:35 PM UTC 24 |
| Finished | Sep 18 06:46:04 PM UTC 24 |
| Peak memory | 209464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4240832826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all _with_rand_reset.4240832826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_alert_test.3929223925 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 13630870 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 06:17:45 PM UTC 24 |
| Finished | Sep 18 06:17:47 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929223925 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3929223925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_fifo_full.1584747991 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 96632953835 ps |
| CPU time | 97.73 seconds |
| Started | Sep 18 06:17:28 PM UTC 24 |
| Finished | Sep 18 06:19:07 PM UTC 24 |
| Peak memory | 209596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584747991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1584747991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.268755490 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 55451701712 ps |
| CPU time | 42.06 seconds |
| Started | Sep 18 06:17:28 PM UTC 24 |
| Finished | Sep 18 06:18:11 PM UTC 24 |
| Peak memory | 209184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268755490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.268755490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2497164783 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 14695747083 ps |
| CPU time | 37.16 seconds |
| Started | Sep 18 06:17:29 PM UTC 24 |
| Finished | Sep 18 06:18:07 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497164783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2497164783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_intr.334059391 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 56002525437 ps |
| CPU time | 91.49 seconds |
| Started | Sep 18 06:17:33 PM UTC 24 |
| Finished | Sep 18 06:19:07 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334059391 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.334059391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.2920809489 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 90024686429 ps |
| CPU time | 813.34 seconds |
| Started | Sep 18 06:17:40 PM UTC 24 |
| Finished | Sep 18 06:31:23 PM UTC 24 |
| Peak memory | 209456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920809489 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2920809489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_loopback.407543797 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 15936014988 ps |
| CPU time | 36.69 seconds |
| Started | Sep 18 06:17:37 PM UTC 24 |
| Finished | Sep 18 06:18:16 PM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407543797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 7.uart_loopback.407543797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_noise_filter.2034983271 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 49279271789 ps |
| CPU time | 124.2 seconds |
| Started | Sep 18 06:17:34 PM UTC 24 |
| Finished | Sep 18 06:19:41 PM UTC 24 |
| Peak memory | 209736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034983271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2034983271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_perf.3026096157 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 16838916621 ps |
| CPU time | 246.75 seconds |
| Started | Sep 18 06:17:37 PM UTC 24 |
| Finished | Sep 18 06:21:48 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026096157 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3026096157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_rx_oversample.1325270574 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1905726500 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 06:17:30 PM UTC 24 |
| Finished | Sep 18 06:17:33 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325270574 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1325270574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.1939472800 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 279585922008 ps |
| CPU time | 30.98 seconds |
| Started | Sep 18 06:17:35 PM UTC 24 |
| Finished | Sep 18 06:18:07 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939472800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1939472800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.104106676 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 5102249784 ps |
| CPU time | 19.43 seconds |
| Started | Sep 18 06:17:35 PM UTC 24 |
| Finished | Sep 18 06:17:56 PM UTC 24 |
| Peak memory | 203588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104106676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.104106676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_smoke.3247516157 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 845443505 ps |
| CPU time | 3.63 seconds |
| Started | Sep 18 06:17:28 PM UTC 24 |
| Finished | Sep 18 06:17:32 PM UTC 24 |
| Peak memory | 207812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247516157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3247516157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.1525506433 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 805790725 ps |
| CPU time | 2.19 seconds |
| Started | Sep 18 06:17:35 PM UTC 24 |
| Finished | Sep 18 06:17:39 PM UTC 24 |
| Peak memory | 207972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525506433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1525506433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/7.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/70.uart_fifo_reset.860134875 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 135140059215 ps |
| CPU time | 226.6 seconds |
| Started | Sep 18 06:45:49 PM UTC 24 |
| Finished | Sep 18 06:49:39 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860134875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.860134875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/70.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.1477623447 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 8946265520 ps |
| CPU time | 121.63 seconds |
| Started | Sep 18 06:45:50 PM UTC 24 |
| Finished | Sep 18 06:47:55 PM UTC 24 |
| Peak memory | 218296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1477623447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all _with_rand_reset.1477623447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/71.uart_fifo_reset.3904157764 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 39641657594 ps |
| CPU time | 72.07 seconds |
| Started | Sep 18 06:45:52 PM UTC 24 |
| Finished | Sep 18 06:47:06 PM UTC 24 |
| Peak memory | 209608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904157764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3904157764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/71.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.2021209305 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 9413133876 ps |
| CPU time | 48.02 seconds |
| Started | Sep 18 06:45:56 PM UTC 24 |
| Finished | Sep 18 06:46:46 PM UTC 24 |
| Peak memory | 218612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2021209305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all _with_rand_reset.2021209305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/72.uart_fifo_reset.1026276059 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 308206403999 ps |
| CPU time | 105.64 seconds |
| Started | Sep 18 06:45:57 PM UTC 24 |
| Finished | Sep 18 06:47:44 PM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026276059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1026276059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/72.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.3497475643 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 5510297254 ps |
| CPU time | 53.36 seconds |
| Started | Sep 18 06:45:58 PM UTC 24 |
| Finished | Sep 18 06:46:53 PM UTC 24 |
| Peak memory | 226168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3497475643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all _with_rand_reset.3497475643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/73.uart_fifo_reset.627045574 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 23341469967 ps |
| CPU time | 26.64 seconds |
| Started | Sep 18 06:46:03 PM UTC 24 |
| Finished | Sep 18 06:46:31 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627045574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.627045574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/73.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.345680764 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 16192992128 ps |
| CPU time | 35.31 seconds |
| Started | Sep 18 06:46:03 PM UTC 24 |
| Finished | Sep 18 06:46:39 PM UTC 24 |
| Peak memory | 226140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=345680764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all_ with_rand_reset.345680764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/74.uart_fifo_reset.2948253997 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 27369211044 ps |
| CPU time | 26.62 seconds |
| Started | Sep 18 06:46:03 PM UTC 24 |
| Finished | Sep 18 06:46:31 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948253997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2948253997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/74.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.3812865190 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 4396495490 ps |
| CPU time | 162.58 seconds |
| Started | Sep 18 06:46:03 PM UTC 24 |
| Finished | Sep 18 06:48:48 PM UTC 24 |
| Peak memory | 218540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3812865190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all _with_rand_reset.3812865190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/75.uart_fifo_reset.422521168 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 100735636775 ps |
| CPU time | 449.57 seconds |
| Started | Sep 18 06:46:05 PM UTC 24 |
| Finished | Sep 18 06:53:40 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422521168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.422521168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/75.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.2320269000 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 3850570045 ps |
| CPU time | 66.32 seconds |
| Started | Sep 18 06:46:06 PM UTC 24 |
| Finished | Sep 18 06:47:14 PM UTC 24 |
| Peak memory | 220348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2320269000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all _with_rand_reset.2320269000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/76.uart_fifo_reset.2931685951 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 34687512893 ps |
| CPU time | 82.42 seconds |
| Started | Sep 18 06:46:08 PM UTC 24 |
| Finished | Sep 18 06:47:32 PM UTC 24 |
| Peak memory | 209124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931685951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2931685951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/76.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.3034201801 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 1690824495 ps |
| CPU time | 27.35 seconds |
| Started | Sep 18 06:46:08 PM UTC 24 |
| Finished | Sep 18 06:46:37 PM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3034201801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all _with_rand_reset.3034201801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/77.uart_fifo_reset.766497306 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 135214719717 ps |
| CPU time | 87.82 seconds |
| Started | Sep 18 06:46:13 PM UTC 24 |
| Finished | Sep 18 06:47:43 PM UTC 24 |
| Peak memory | 204168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766497306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.766497306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/77.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.2496537794 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 5500810435 ps |
| CPU time | 37.91 seconds |
| Started | Sep 18 06:46:15 PM UTC 24 |
| Finished | Sep 18 06:46:55 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2496537794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all _with_rand_reset.2496537794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/78.uart_fifo_reset.3697966114 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 24859599448 ps |
| CPU time | 68.5 seconds |
| Started | Sep 18 06:46:16 PM UTC 24 |
| Finished | Sep 18 06:47:27 PM UTC 24 |
| Peak memory | 203772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697966114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3697966114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/78.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.1957586850 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 13461886892 ps |
| CPU time | 76.83 seconds |
| Started | Sep 18 06:46:25 PM UTC 24 |
| Finished | Sep 18 06:47:43 PM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1957586850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all _with_rand_reset.1957586850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/79.uart_fifo_reset.907259379 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 30554213093 ps |
| CPU time | 18.65 seconds |
| Started | Sep 18 06:46:30 PM UTC 24 |
| Finished | Sep 18 06:46:49 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907259379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.907259379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/79.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.726809068 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 3548743818 ps |
| CPU time | 31.32 seconds |
| Started | Sep 18 06:46:31 PM UTC 24 |
| Finished | Sep 18 06:47:03 PM UTC 24 |
| Peak memory | 218616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=726809068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all_ with_rand_reset.726809068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_alert_test.1286147210 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 37999093 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 06:18:18 PM UTC 24 |
| Finished | Sep 18 06:18:20 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286147210 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1286147210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_fifo_full.613939008 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 33139297462 ps |
| CPU time | 96.99 seconds |
| Started | Sep 18 06:17:51 PM UTC 24 |
| Finished | Sep 18 06:19:30 PM UTC 24 |
| Peak memory | 209632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613939008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.613939008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.789864680 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 195492161496 ps |
| CPU time | 123.83 seconds |
| Started | Sep 18 06:17:54 PM UTC 24 |
| Finished | Sep 18 06:20:00 PM UTC 24 |
| Peak memory | 208284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789864680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.789864680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_fifo_reset.314354491 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 88595950939 ps |
| CPU time | 137.73 seconds |
| Started | Sep 18 06:17:55 PM UTC 24 |
| Finished | Sep 18 06:20:15 PM UTC 24 |
| Peak memory | 209576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314354491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.314354491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_intr.561601711 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 44981703164 ps |
| CPU time | 19.63 seconds |
| Started | Sep 18 06:17:56 PM UTC 24 |
| Finished | Sep 18 06:18:17 PM UTC 24 |
| Peak memory | 208280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561601711 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.561601711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.2837449426 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 119558797541 ps |
| CPU time | 883.2 seconds |
| Started | Sep 18 06:18:13 PM UTC 24 |
| Finished | Sep 18 06:33:07 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837449426 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2837449426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_loopback.313682256 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 6332194493 ps |
| CPU time | 15.71 seconds |
| Started | Sep 18 06:18:09 PM UTC 24 |
| Finished | Sep 18 06:18:26 PM UTC 24 |
| Peak memory | 208476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313682256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 8.uart_loopback.313682256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_noise_filter.3443882838 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 128931065963 ps |
| CPU time | 331.9 seconds |
| Started | Sep 18 06:17:59 PM UTC 24 |
| Finished | Sep 18 06:23:36 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443882838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3443882838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_perf.1969729484 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 12041216998 ps |
| CPU time | 736.95 seconds |
| Started | Sep 18 06:18:12 PM UTC 24 |
| Finished | Sep 18 06:30:37 PM UTC 24 |
| Peak memory | 203836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969729484 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1969729484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_rx_oversample.1215734301 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 4601538398 ps |
| CPU time | 20.77 seconds |
| Started | Sep 18 06:17:56 PM UTC 24 |
| Finished | Sep 18 06:18:18 PM UTC 24 |
| Peak memory | 207944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215734301 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1215734301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.2651035080 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 51703701108 ps |
| CPU time | 109.64 seconds |
| Started | Sep 18 06:18:03 PM UTC 24 |
| Finished | Sep 18 06:19:55 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651035080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2651035080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.4009135639 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 39923244084 ps |
| CPU time | 22.85 seconds |
| Started | Sep 18 06:18:00 PM UTC 24 |
| Finished | Sep 18 06:18:24 PM UTC 24 |
| Peak memory | 203584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009135639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.4009135639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_smoke.4078516036 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 670870142 ps |
| CPU time | 5.11 seconds |
| Started | Sep 18 06:17:48 PM UTC 24 |
| Finished | Sep 18 06:17:55 PM UTC 24 |
| Peak memory | 208572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078516036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4078516036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_stress_all.2640504451 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 115990592711 ps |
| CPU time | 333.46 seconds |
| Started | Sep 18 06:18:16 PM UTC 24 |
| Finished | Sep 18 06:23:54 PM UTC 24 |
| Peak memory | 218416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640504451 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2640504451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.63615975 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 325786910 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 06:18:09 PM UTC 24 |
| Finished | Sep 18 06:18:12 PM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63615975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.63615975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/8.uart_tx_rx.2139983093 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 76459819772 ps |
| CPU time | 57.81 seconds |
| Started | Sep 18 06:17:50 PM UTC 24 |
| Finished | Sep 18 06:18:50 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139983093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2139983093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/8.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/80.uart_fifo_reset.2166126814 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 14548629235 ps |
| CPU time | 12.92 seconds |
| Started | Sep 18 06:46:32 PM UTC 24 |
| Finished | Sep 18 06:46:46 PM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166126814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2166126814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/80.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.2500640789 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 3400369531 ps |
| CPU time | 67.08 seconds |
| Started | Sep 18 06:46:32 PM UTC 24 |
| Finished | Sep 18 06:47:41 PM UTC 24 |
| Peak memory | 218704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2500640789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all _with_rand_reset.2500640789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/81.uart_fifo_reset.1112615021 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 14880656722 ps |
| CPU time | 22.03 seconds |
| Started | Sep 18 06:46:32 PM UTC 24 |
| Finished | Sep 18 06:46:55 PM UTC 24 |
| Peak memory | 203980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112615021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1112615021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/81.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.1702288702 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 2507865044 ps |
| CPU time | 37.18 seconds |
| Started | Sep 18 06:46:33 PM UTC 24 |
| Finished | Sep 18 06:47:12 PM UTC 24 |
| Peak memory | 218492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1702288702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all _with_rand_reset.1702288702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/82.uart_fifo_reset.3718288326 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 226227344727 ps |
| CPU time | 322.66 seconds |
| Started | Sep 18 06:46:33 PM UTC 24 |
| Finished | Sep 18 06:52:00 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718288326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3718288326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/82.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.3741324889 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 12207946544 ps |
| CPU time | 90.46 seconds |
| Started | Sep 18 06:46:37 PM UTC 24 |
| Finished | Sep 18 06:48:10 PM UTC 24 |
| Peak memory | 220528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3741324889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all _with_rand_reset.3741324889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/83.uart_fifo_reset.3286389266 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 54999596319 ps |
| CPU time | 51.33 seconds |
| Started | Sep 18 06:46:39 PM UTC 24 |
| Finished | Sep 18 06:47:32 PM UTC 24 |
| Peak memory | 204044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286389266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3286389266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/83.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.1739595079 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 1792257599 ps |
| CPU time | 16.04 seconds |
| Started | Sep 18 06:46:40 PM UTC 24 |
| Finished | Sep 18 06:46:57 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1739595079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all _with_rand_reset.1739595079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/84.uart_fifo_reset.3738628360 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 85485088022 ps |
| CPU time | 252.51 seconds |
| Started | Sep 18 06:46:42 PM UTC 24 |
| Finished | Sep 18 06:50:59 PM UTC 24 |
| Peak memory | 204048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738628360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3738628360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/84.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.883236900 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 4598555298 ps |
| CPU time | 99.11 seconds |
| Started | Sep 18 06:46:42 PM UTC 24 |
| Finished | Sep 18 06:48:24 PM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=883236900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all_ with_rand_reset.883236900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/85.uart_fifo_reset.2756851676 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 11612679846 ps |
| CPU time | 35.87 seconds |
| Started | Sep 18 06:46:47 PM UTC 24 |
| Finished | Sep 18 06:47:24 PM UTC 24 |
| Peak memory | 203452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756851676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2756851676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/85.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.4140299058 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 27783020109 ps |
| CPU time | 62.7 seconds |
| Started | Sep 18 06:46:47 PM UTC 24 |
| Finished | Sep 18 06:47:51 PM UTC 24 |
| Peak memory | 217944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4140299058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all _with_rand_reset.4140299058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/86.uart_fifo_reset.977590079 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 129166054417 ps |
| CPU time | 80.75 seconds |
| Started | Sep 18 06:46:51 PM UTC 24 |
| Finished | Sep 18 06:48:14 PM UTC 24 |
| Peak memory | 209036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977590079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.977590079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/86.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.1493717767 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 4585481332 ps |
| CPU time | 61.13 seconds |
| Started | Sep 18 06:46:52 PM UTC 24 |
| Finished | Sep 18 06:47:55 PM UTC 24 |
| Peak memory | 226096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1493717767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all _with_rand_reset.1493717767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/87.uart_fifo_reset.384113703 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 134737375706 ps |
| CPU time | 132.57 seconds |
| Started | Sep 18 06:46:54 PM UTC 24 |
| Finished | Sep 18 06:49:09 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384113703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.384113703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/87.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.2433050262 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 3164453443 ps |
| CPU time | 57.62 seconds |
| Started | Sep 18 06:46:56 PM UTC 24 |
| Finished | Sep 18 06:47:55 PM UTC 24 |
| Peak memory | 220812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2433050262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all _with_rand_reset.2433050262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/88.uart_fifo_reset.660224136 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 79619908983 ps |
| CPU time | 52.3 seconds |
| Started | Sep 18 06:46:56 PM UTC 24 |
| Finished | Sep 18 06:47:50 PM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660224136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.660224136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/88.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.1292362870 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 13277857955 ps |
| CPU time | 41.04 seconds |
| Started | Sep 18 06:46:58 PM UTC 24 |
| Finished | Sep 18 06:47:41 PM UTC 24 |
| Peak memory | 226172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1292362870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all _with_rand_reset.1292362870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/89.uart_fifo_reset.2752336913 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 105239416918 ps |
| CPU time | 55.7 seconds |
| Started | Sep 18 06:47:04 PM UTC 24 |
| Finished | Sep 18 06:48:02 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752336913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2752336913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/89.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.518887485 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 8470973577 ps |
| CPU time | 70.94 seconds |
| Started | Sep 18 06:47:07 PM UTC 24 |
| Finished | Sep 18 06:48:20 PM UTC 24 |
| Peak memory | 218636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=518887485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all_ with_rand_reset.518887485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_alert_test.2956939008 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 42277333 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 06:18:52 PM UTC 24 |
| Finished | Sep 18 06:18:53 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956939008 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2956939008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.447145361 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 57030893264 ps |
| CPU time | 53.35 seconds |
| Started | Sep 18 06:18:24 PM UTC 24 |
| Finished | Sep 18 06:19:19 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447145361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.447145361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_fifo_reset.2126068629 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 26961388328 ps |
| CPU time | 62.42 seconds |
| Started | Sep 18 06:18:26 PM UTC 24 |
| Finished | Sep 18 06:19:30 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126068629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2126068629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_intr.525440372 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 29295608109 ps |
| CPU time | 20.94 seconds |
| Started | Sep 18 06:18:28 PM UTC 24 |
| Finished | Sep 18 06:18:50 PM UTC 24 |
| Peak memory | 203708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525440372 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.525440372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.280880507 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 77113454510 ps |
| CPU time | 441.13 seconds |
| Started | Sep 18 06:18:47 PM UTC 24 |
| Finished | Sep 18 06:26:14 PM UTC 24 |
| Peak memory | 209284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280880507 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.280880507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_loopback.4196507628 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 7432674628 ps |
| CPU time | 18.02 seconds |
| Started | Sep 18 06:18:42 PM UTC 24 |
| Finished | Sep 18 06:19:02 PM UTC 24 |
| Peak memory | 208916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196507628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4196507628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_noise_filter.2995090641 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 27138831500 ps |
| CPU time | 28.97 seconds |
| Started | Sep 18 06:18:31 PM UTC 24 |
| Finished | Sep 18 06:19:01 PM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995090641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2995090641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_perf.2715390250 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 26534219021 ps |
| CPU time | 1646.84 seconds |
| Started | Sep 18 06:18:44 PM UTC 24 |
| Finished | Sep 18 06:46:30 PM UTC 24 |
| Peak memory | 207164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715390250 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2715390250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_rx_oversample.1825182345 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 4437216424 ps |
| CPU time | 35.43 seconds |
| Started | Sep 18 06:18:27 PM UTC 24 |
| Finished | Sep 18 06:19:03 PM UTC 24 |
| Peak memory | 207944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825182345 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1825182345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.1186391174 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 37586196245 ps |
| CPU time | 39.62 seconds |
| Started | Sep 18 06:18:39 PM UTC 24 |
| Finished | Sep 18 06:19:20 PM UTC 24 |
| Peak memory | 209596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186391174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1186391174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.1857846212 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1227407824 ps |
| CPU time | 2.35 seconds |
| Started | Sep 18 06:18:37 PM UTC 24 |
| Finished | Sep 18 06:18:40 PM UTC 24 |
| Peak memory | 203520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857846212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1857846212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_smoke.527247030 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 676377319 ps |
| CPU time | 1.72 seconds |
| Started | Sep 18 06:18:19 PM UTC 24 |
| Finished | Sep 18 06:18:22 PM UTC 24 |
| Peak memory | 203268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527247030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 9.uart_smoke.527247030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.3809156288 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 29089723174 ps |
| CPU time | 144.48 seconds |
| Started | Sep 18 06:18:51 PM UTC 24 |
| Finished | Sep 18 06:21:18 PM UTC 24 |
| Peak memory | 226168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3809156288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_ with_rand_reset.3809156288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.1153271061 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 742139175 ps |
| CPU time | 4.39 seconds |
| Started | Sep 18 06:18:41 PM UTC 24 |
| Finished | Sep 18 06:18:47 PM UTC 24 |
| Peak memory | 207984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153271061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1153271061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/9.uart_tx_rx.2294235661 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 59459712377 ps |
| CPU time | 132.13 seconds |
| Started | Sep 18 06:18:20 PM UTC 24 |
| Finished | Sep 18 06:20:35 PM UTC 24 |
| Peak memory | 203720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294235661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2294235661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/9.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/90.uart_fifo_reset.1997871200 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 11382602469 ps |
| CPU time | 20.78 seconds |
| Started | Sep 18 06:47:12 PM UTC 24 |
| Finished | Sep 18 06:47:35 PM UTC 24 |
| Peak memory | 208676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997871200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1997871200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/90.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.2819503548 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 3334908152 ps |
| CPU time | 24.65 seconds |
| Started | Sep 18 06:47:15 PM UTC 24 |
| Finished | Sep 18 06:47:41 PM UTC 24 |
| Peak memory | 209716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2819503548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all _with_rand_reset.2819503548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/91.uart_fifo_reset.39810267 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 50550430427 ps |
| CPU time | 134.12 seconds |
| Started | Sep 18 06:47:26 PM UTC 24 |
| Finished | Sep 18 06:49:42 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39810267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.39810267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/91.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.3109603037 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 8383793569 ps |
| CPU time | 47.93 seconds |
| Started | Sep 18 06:47:28 PM UTC 24 |
| Finished | Sep 18 06:48:17 PM UTC 24 |
| Peak memory | 218692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3109603037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all _with_rand_reset.3109603037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/92.uart_fifo_reset.2135637898 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 30626838994 ps |
| CPU time | 81.96 seconds |
| Started | Sep 18 06:47:33 PM UTC 24 |
| Finished | Sep 18 06:48:57 PM UTC 24 |
| Peak memory | 203712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135637898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2135637898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/92.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.581332285 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 15038051211 ps |
| CPU time | 24.72 seconds |
| Started | Sep 18 06:47:33 PM UTC 24 |
| Finished | Sep 18 06:47:59 PM UTC 24 |
| Peak memory | 218640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=581332285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all_ with_rand_reset.581332285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/93.uart_fifo_reset.388524206 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 39958707388 ps |
| CPU time | 20.98 seconds |
| Started | Sep 18 06:47:34 PM UTC 24 |
| Finished | Sep 18 06:47:56 PM UTC 24 |
| Peak memory | 207936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388524206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.388524206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/93.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.1431763595 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 12047077820 ps |
| CPU time | 54.07 seconds |
| Started | Sep 18 06:47:36 PM UTC 24 |
| Finished | Sep 18 06:48:32 PM UTC 24 |
| Peak memory | 226280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1431763595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all _with_rand_reset.1431763595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/94.uart_fifo_reset.3798347503 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 141535177219 ps |
| CPU time | 328.83 seconds |
| Started | Sep 18 06:47:37 PM UTC 24 |
| Finished | Sep 18 06:53:10 PM UTC 24 |
| Peak memory | 209172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798347503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3798347503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/94.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.3147189003 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 4191054764 ps |
| CPU time | 49.88 seconds |
| Started | Sep 18 06:47:38 PM UTC 24 |
| Finished | Sep 18 06:48:30 PM UTC 24 |
| Peak memory | 218492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3147189003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all _with_rand_reset.3147189003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/95.uart_fifo_reset.1504929812 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 127141477863 ps |
| CPU time | 144.45 seconds |
| Started | Sep 18 06:47:41 PM UTC 24 |
| Finished | Sep 18 06:50:08 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504929812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1504929812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/95.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.83298631 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 11904354795 ps |
| CPU time | 69.99 seconds |
| Started | Sep 18 06:47:41 PM UTC 24 |
| Finished | Sep 18 06:48:53 PM UTC 24 |
| Peak memory | 218296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=83298631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all_w ith_rand_reset.83298631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/96.uart_fifo_reset.3001263876 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 19724998713 ps |
| CPU time | 18.78 seconds |
| Started | Sep 18 06:47:41 PM UTC 24 |
| Finished | Sep 18 06:48:01 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001263876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3001263876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/96.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.1820597854 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 2031951019 ps |
| CPU time | 7.78 seconds |
| Started | Sep 18 06:47:43 PM UTC 24 |
| Finished | Sep 18 06:47:52 PM UTC 24 |
| Peak memory | 218428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1820597854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all _with_rand_reset.1820597854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/97.uart_fifo_reset.1809382829 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 41541954159 ps |
| CPU time | 19.16 seconds |
| Started | Sep 18 06:47:45 PM UTC 24 |
| Finished | Sep 18 06:48:05 PM UTC 24 |
| Peak memory | 209468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809382829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1809382829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/97.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.2723051184 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 2003980853 ps |
| CPU time | 39.83 seconds |
| Started | Sep 18 06:47:46 PM UTC 24 |
| Finished | Sep 18 06:48:27 PM UTC 24 |
| Peak memory | 218428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2723051184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all _with_rand_reset.2723051184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.3151267241 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 9795201724 ps |
| CPU time | 73.91 seconds |
| Started | Sep 18 06:47:53 PM UTC 24 |
| Finished | Sep 18 06:49:09 PM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3151267241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all _with_rand_reset.3151267241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/99.uart_fifo_reset.3658734810 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 19971299023 ps |
| CPU time | 25.35 seconds |
| Started | Sep 18 06:47:53 PM UTC 24 |
| Finished | Sep 18 06:48:20 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658734810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3658734810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/99.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.2577058289 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 377563268 ps |
| CPU time | 9.53 seconds |
| Started | Sep 18 06:47:55 PM UTC 24 |
| Finished | Sep 18 06:48:06 PM UTC 24 |
| Peak memory | 209716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2577058289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all _with_rand_reset.2577058289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest |
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