| T465 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_loopback.103188103 |
|
|
Oct 02 07:12:51 PM UTC 24 |
Oct 02 07:12:58 PM UTC 24 |
1424667132 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_alert_test.3527688569 |
|
|
Oct 02 07:12:59 PM UTC 24 |
Oct 02 07:13:00 PM UTC 24 |
18325266 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.2455173687 |
|
|
Oct 02 07:11:50 PM UTC 24 |
Oct 02 07:13:01 PM UTC 24 |
24400533284 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_intr.3100415873 |
|
|
Oct 02 07:12:47 PM UTC 24 |
Oct 02 07:13:02 PM UTC 24 |
7165504083 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_smoke.3065206560 |
|
|
Oct 02 07:12:59 PM UTC 24 |
Oct 02 07:13:03 PM UTC 24 |
661968236 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.3610847086 |
|
|
Oct 02 07:12:22 PM UTC 24 |
Oct 02 07:13:09 PM UTC 24 |
19152220761 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.4258812193 |
|
|
Oct 02 07:10:14 PM UTC 24 |
Oct 02 07:13:10 PM UTC 24 |
58514722191 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_noise_filter.3758246895 |
|
|
Oct 02 07:12:19 PM UTC 24 |
Oct 02 07:13:12 PM UTC 24 |
69848735673 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.1105968912 |
|
|
Oct 02 07:11:48 PM UTC 24 |
Oct 02 07:13:12 PM UTC 24 |
26058680985 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_noise_filter.4142100923 |
|
|
Oct 02 07:10:07 PM UTC 24 |
Oct 02 07:13:17 PM UTC 24 |
103112006707 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.1802066975 |
|
|
Oct 02 07:13:12 PM UTC 24 |
Oct 02 07:13:18 PM UTC 24 |
3244864392 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_perf.2213217892 |
|
|
Oct 02 07:07:10 PM UTC 24 |
Oct 02 07:13:18 PM UTC 24 |
6343297298 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.1466237050 |
|
|
Oct 02 07:11:31 PM UTC 24 |
Oct 02 07:13:22 PM UTC 24 |
183519805917 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_rx_oversample.3675521585 |
|
|
Oct 02 07:13:03 PM UTC 24 |
Oct 02 07:13:22 PM UTC 24 |
3272194583 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.630479809 |
|
|
Oct 02 07:13:18 PM UTC 24 |
Oct 02 07:13:23 PM UTC 24 |
990810017 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_loopback.1824036427 |
|
|
Oct 02 07:13:18 PM UTC 24 |
Oct 02 07:13:23 PM UTC 24 |
1003044710 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_intr.31448614 |
|
|
Oct 02 07:11:38 PM UTC 24 |
Oct 02 07:13:23 PM UTC 24 |
47902354732 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_alert_test.975103351 |
|
|
Oct 02 07:13:24 PM UTC 24 |
Oct 02 07:13:26 PM UTC 24 |
44378529 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.1253855188 |
|
|
Oct 02 07:12:49 PM UTC 24 |
Oct 02 07:13:28 PM UTC 24 |
36005647836 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_smoke.2968055357 |
|
|
Oct 02 07:13:24 PM UTC 24 |
Oct 02 07:13:28 PM UTC 24 |
427598708 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_intr.2359754023 |
|
|
Oct 02 07:13:10 PM UTC 24 |
Oct 02 07:13:30 PM UTC 24 |
29487001281 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_rx_oversample.498808572 |
|
|
Oct 02 07:12:13 PM UTC 24 |
Oct 02 07:13:35 PM UTC 24 |
7275566558 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_tx_rx.2719938976 |
|
|
Oct 02 07:13:00 PM UTC 24 |
Oct 02 07:13:42 PM UTC 24 |
54654071331 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.307723071 |
|
|
Oct 02 07:13:43 PM UTC 24 |
Oct 02 07:13:46 PM UTC 24 |
4518339421 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.2773003350 |
|
|
Oct 02 07:13:23 PM UTC 24 |
Oct 02 07:13:47 PM UTC 24 |
1604032139 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_intr.2964662367 |
|
|
Oct 02 07:13:31 PM UTC 24 |
Oct 02 07:13:47 PM UTC 24 |
60799383436 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_fifo_reset.1822497473 |
|
|
Oct 02 07:13:03 PM UTC 24 |
Oct 02 07:13:52 PM UTC 24 |
106836711276 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.2130989862 |
|
|
Oct 02 07:13:48 PM UTC 24 |
Oct 02 07:13:53 PM UTC 24 |
1062271076 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_fifo_reset.856498328 |
|
|
Oct 02 07:13:29 PM UTC 24 |
Oct 02 07:13:56 PM UTC 24 |
61797735665 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_rx_oversample.1078771634 |
|
|
Oct 02 07:13:31 PM UTC 24 |
Oct 02 07:13:56 PM UTC 24 |
4433390053 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_noise_filter.673629047 |
|
|
Oct 02 07:13:11 PM UTC 24 |
Oct 02 07:13:59 PM UTC 24 |
139023299242 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_loopback.448056276 |
|
|
Oct 02 07:13:48 PM UTC 24 |
Oct 02 07:13:59 PM UTC 24 |
6592682023 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.3988033846 |
|
|
Oct 02 07:09:57 PM UTC 24 |
Oct 02 07:14:00 PM UTC 24 |
126647035129 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_alert_test.2577385048 |
|
|
Oct 02 07:13:59 PM UTC 24 |
Oct 02 07:14:01 PM UTC 24 |
23623388 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_stress_all.3017590783 |
|
|
Oct 02 07:11:01 PM UTC 24 |
Oct 02 07:14:03 PM UTC 24 |
66203201462 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_perf.3597782623 |
|
|
Oct 02 07:11:48 PM UTC 24 |
Oct 02 07:14:05 PM UTC 24 |
10871350977 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_smoke.2490007980 |
|
|
Oct 02 07:14:01 PM UTC 24 |
Oct 02 07:14:06 PM UTC 24 |
450672313 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_fifo_full.467987885 |
|
|
Oct 02 07:10:40 PM UTC 24 |
Oct 02 07:14:07 PM UTC 24 |
166663283088 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_noise_filter.1799264720 |
|
|
Oct 02 07:12:47 PM UTC 24 |
Oct 02 07:14:12 PM UTC 24 |
138556130214 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_fifo_full.2842037159 |
|
|
Oct 02 07:13:01 PM UTC 24 |
Oct 02 07:14:15 PM UTC 24 |
258438917954 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_tx_rx.4001530304 |
|
|
Oct 02 07:12:44 PM UTC 24 |
Oct 02 07:14:15 PM UTC 24 |
112443499391 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.1007839701 |
|
|
Oct 02 07:13:13 PM UTC 24 |
Oct 02 07:14:19 PM UTC 24 |
28281428233 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.1394743518 |
|
|
Oct 02 07:12:57 PM UTC 24 |
Oct 02 07:14:20 PM UTC 24 |
14685674460 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.1455457655 |
|
|
Oct 02 07:14:16 PM UTC 24 |
Oct 02 07:14:21 PM UTC 24 |
3995393564 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.464381213 |
|
|
Oct 02 07:14:18 PM UTC 24 |
Oct 02 07:14:22 PM UTC 24 |
654966059 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_loopback.2858705456 |
|
|
Oct 02 07:14:19 PM UTC 24 |
Oct 02 07:14:22 PM UTC 24 |
2535329894 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.2186160637 |
|
|
Oct 02 07:13:47 PM UTC 24 |
Oct 02 07:14:27 PM UTC 24 |
73198612862 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_tx_rx.295367047 |
|
|
Oct 02 07:14:02 PM UTC 24 |
Oct 02 07:14:28 PM UTC 24 |
37583963819 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_fifo_full.1652539150 |
|
|
Oct 02 07:14:02 PM UTC 24 |
Oct 02 07:14:29 PM UTC 24 |
49570112747 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.1015263398 |
|
|
Oct 02 07:12:33 PM UTC 24 |
Oct 02 07:14:30 PM UTC 24 |
14053192798 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_alert_test.3934701690 |
|
|
Oct 02 07:14:28 PM UTC 24 |
Oct 02 07:14:30 PM UTC 24 |
14361225 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_stress_all.1016151794 |
|
|
Oct 02 07:13:23 PM UTC 24 |
Oct 02 07:14:31 PM UTC 24 |
383309216599 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.2041441035 |
|
|
Oct 02 07:14:04 PM UTC 24 |
Oct 02 07:14:33 PM UTC 24 |
6194348883 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_intr.2338055291 |
|
|
Oct 02 07:14:08 PM UTC 24 |
Oct 02 07:14:33 PM UTC 24 |
71841860735 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_smoke.3792261576 |
|
|
Oct 02 07:14:29 PM UTC 24 |
Oct 02 07:14:33 PM UTC 24 |
464439493 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.3157563355 |
|
|
Oct 02 07:13:57 PM UTC 24 |
Oct 02 07:14:34 PM UTC 24 |
10772663175 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.2354796395 |
|
|
Oct 02 07:14:35 PM UTC 24 |
Oct 02 07:14:42 PM UTC 24 |
3042315007 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_noise_filter.2464274431 |
|
|
Oct 02 07:14:34 PM UTC 24 |
Oct 02 07:14:42 PM UTC 24 |
17122667337 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.567502819 |
|
|
Oct 02 07:10:54 PM UTC 24 |
Oct 02 07:14:43 PM UTC 24 |
140752106931 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_fifo_reset.784753634 |
|
|
Oct 02 07:14:06 PM UTC 24 |
Oct 02 07:14:47 PM UTC 24 |
69585097381 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_noise_filter.2960849215 |
|
|
Oct 02 07:08:41 PM UTC 24 |
Oct 02 07:14:48 PM UTC 24 |
198033975316 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_rx_oversample.2601198649 |
|
|
Oct 02 07:14:34 PM UTC 24 |
Oct 02 07:14:48 PM UTC 24 |
6414464088 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.334253442 |
|
|
Oct 02 07:14:43 PM UTC 24 |
Oct 02 07:14:49 PM UTC 24 |
978427040 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.159314782 |
|
|
Oct 02 07:13:28 PM UTC 24 |
Oct 02 07:14:51 PM UTC 24 |
31041066225 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_fifo_full.1024540341 |
|
|
Oct 02 07:13:27 PM UTC 24 |
Oct 02 07:14:52 PM UTC 24 |
63859666216 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_perf.3172548209 |
|
|
Oct 02 07:08:53 PM UTC 24 |
Oct 02 07:14:53 PM UTC 24 |
15400172129 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_alert_test.361708935 |
|
|
Oct 02 07:14:52 PM UTC 24 |
Oct 02 07:14:54 PM UTC 24 |
25210221 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_loopback.2688482811 |
|
|
Oct 02 07:14:44 PM UTC 24 |
Oct 02 07:14:55 PM UTC 24 |
5727351853 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_smoke.1413749669 |
|
|
Oct 02 07:14:52 PM UTC 24 |
Oct 02 07:14:56 PM UTC 24 |
709390884 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_perf.2093454404 |
|
|
Oct 02 07:13:19 PM UTC 24 |
Oct 02 07:15:00 PM UTC 24 |
23021768779 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_tx_rx.2056776061 |
|
|
Oct 02 07:13:24 PM UTC 24 |
Oct 02 07:15:00 PM UTC 24 |
93997390170 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_perf.835268162 |
|
|
Oct 02 07:07:23 PM UTC 24 |
Oct 02 07:15:03 PM UTC 24 |
29507197451 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.159353315 |
|
|
Oct 02 07:14:16 PM UTC 24 |
Oct 02 07:15:04 PM UTC 24 |
30008756123 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_perf.3947748031 |
|
|
Oct 02 07:09:41 PM UTC 24 |
Oct 02 07:15:04 PM UTC 24 |
14801469780 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.3597276995 |
|
|
Oct 02 07:15:05 PM UTC 24 |
Oct 02 07:15:07 PM UTC 24 |
4701860194 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_intr.2187124854 |
|
|
Oct 02 07:10:00 PM UTC 24 |
Oct 02 07:15:09 PM UTC 24 |
237870040691 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.1016032629 |
|
|
Oct 02 07:15:06 PM UTC 24 |
Oct 02 07:15:09 PM UTC 24 |
1034001421 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_fifo_full.2456918730 |
|
|
Oct 02 07:14:31 PM UTC 24 |
Oct 02 07:15:10 PM UTC 24 |
55663440170 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_rx_oversample.1291214912 |
|
|
Oct 02 07:14:08 PM UTC 24 |
Oct 02 07:15:11 PM UTC 24 |
5486761559 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_noise_filter.181195682 |
|
|
Oct 02 07:13:36 PM UTC 24 |
Oct 02 07:15:17 PM UTC 24 |
199588226322 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_tx_rx.9424433 |
|
|
Oct 02 07:14:30 PM UTC 24 |
Oct 02 07:15:19 PM UTC 24 |
279314662557 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_alert_test.19093309 |
|
|
Oct 02 07:15:18 PM UTC 24 |
Oct 02 07:15:20 PM UTC 24 |
12972149 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.2845007872 |
|
|
Oct 02 07:14:56 PM UTC 24 |
Oct 02 07:15:22 PM UTC 24 |
152732724552 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.3298606529 |
|
|
Oct 02 07:13:02 PM UTC 24 |
Oct 02 07:15:22 PM UTC 24 |
54136385258 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.834582043 |
|
|
Oct 02 07:15:05 PM UTC 24 |
Oct 02 07:15:23 PM UTC 24 |
38233036492 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_stress_all.3251156051 |
|
|
Oct 02 07:07:17 PM UTC 24 |
Oct 02 07:15:24 PM UTC 24 |
208841875753 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_loopback.1443740565 |
|
|
Oct 02 07:15:08 PM UTC 24 |
Oct 02 07:15:24 PM UTC 24 |
3959256120 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.2945591221 |
|
|
Oct 02 07:14:23 PM UTC 24 |
Oct 02 07:15:28 PM UTC 24 |
59867857866 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_noise_filter.3901021917 |
|
|
Oct 02 07:11:38 PM UTC 24 |
Oct 02 07:15:28 PM UTC 24 |
138469503090 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.2959517534 |
|
|
Oct 02 07:11:24 PM UTC 24 |
Oct 02 07:15:33 PM UTC 24 |
71444701038 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.3024053945 |
|
|
Oct 02 07:14:49 PM UTC 24 |
Oct 02 07:15:43 PM UTC 24 |
3487634496 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_smoke.1778960968 |
|
|
Oct 02 07:15:20 PM UTC 24 |
Oct 02 07:15:45 PM UTC 24 |
6283395815 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.3774764812 |
|
|
Oct 02 07:14:43 PM UTC 24 |
Oct 02 07:15:48 PM UTC 24 |
148521743064 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_perf.2965465721 |
|
|
Oct 02 07:10:33 PM UTC 24 |
Oct 02 07:15:49 PM UTC 24 |
10325418129 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_intr.3704275238 |
|
|
Oct 02 07:15:24 PM UTC 24 |
Oct 02 07:15:51 PM UTC 24 |
13908015078 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_loopback.158879920 |
|
|
Oct 02 07:15:46 PM UTC 24 |
Oct 02 07:15:55 PM UTC 24 |
3200873696 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_tx_rx.217549105 |
|
|
Oct 02 07:14:54 PM UTC 24 |
Oct 02 07:15:56 PM UTC 24 |
133961442722 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_alert_test.2580900865 |
|
|
Oct 02 07:15:57 PM UTC 24 |
Oct 02 07:15:59 PM UTC 24 |
87695922 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_fifo_full.1601561216 |
|
|
Oct 02 07:15:22 PM UTC 24 |
Oct 02 07:16:01 PM UTC 24 |
42221119832 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.3441957850 |
|
|
Oct 02 07:15:30 PM UTC 24 |
Oct 02 07:16:02 PM UTC 24 |
6841433935 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_smoke.1316671712 |
|
|
Oct 02 07:16:00 PM UTC 24 |
Oct 02 07:16:03 PM UTC 24 |
480406096 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.1288113982 |
|
|
Oct 02 07:15:34 PM UTC 24 |
Oct 02 07:16:07 PM UTC 24 |
182647892944 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.722652421 |
|
|
Oct 02 07:12:13 PM UTC 24 |
Oct 02 07:16:08 PM UTC 24 |
197543586720 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_rx_oversample.2727546912 |
|
|
Oct 02 07:15:24 PM UTC 24 |
Oct 02 07:16:08 PM UTC 24 |
5061698694 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_fifo_reset.1536384735 |
|
|
Oct 02 07:14:57 PM UTC 24 |
Oct 02 07:16:08 PM UTC 24 |
174968420422 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.2367701856 |
|
|
Oct 02 07:15:44 PM UTC 24 |
Oct 02 07:16:13 PM UTC 24 |
7016187699 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_perf.331358150 |
|
|
Oct 02 07:07:41 PM UTC 24 |
Oct 02 07:16:15 PM UTC 24 |
9473450857 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_rx_oversample.2357298519 |
|
|
Oct 02 07:15:01 PM UTC 24 |
Oct 02 07:16:16 PM UTC 24 |
6449720290 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_rx_oversample.1765364098 |
|
|
Oct 02 07:16:09 PM UTC 24 |
Oct 02 07:16:20 PM UTC 24 |
1796726925 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.2918310735 |
|
|
Oct 02 07:16:17 PM UTC 24 |
Oct 02 07:16:22 PM UTC 24 |
2146876741 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.2205123407 |
|
|
Oct 02 07:14:31 PM UTC 24 |
Oct 02 07:16:22 PM UTC 24 |
40901324683 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.1175778712 |
|
|
Oct 02 07:19:53 PM UTC 24 |
Oct 02 07:19:57 PM UTC 24 |
1993043011 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.317022576 |
|
|
Oct 02 07:15:51 PM UTC 24 |
Oct 02 07:16:25 PM UTC 24 |
6118078485 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_tx_rx.4275914184 |
|
|
Oct 02 07:15:21 PM UTC 24 |
Oct 02 07:16:30 PM UTC 24 |
117282476821 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_loopback.2669954939 |
|
|
Oct 02 07:16:20 PM UTC 24 |
Oct 02 07:16:31 PM UTC 24 |
4138485681 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_alert_test.3565735852 |
|
|
Oct 02 07:16:32 PM UTC 24 |
Oct 02 07:16:34 PM UTC 24 |
37838939 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_noise_filter.1724719496 |
|
|
Oct 02 07:15:28 PM UTC 24 |
Oct 02 07:16:38 PM UTC 24 |
206208873062 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.2669482541 |
|
|
Oct 02 07:16:05 PM UTC 24 |
Oct 02 07:16:38 PM UTC 24 |
123264633697 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_smoke.1498032191 |
|
|
Oct 02 07:16:35 PM UTC 24 |
Oct 02 07:16:39 PM UTC 24 |
865841247 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.3329699073 |
|
|
Oct 02 07:16:14 PM UTC 24 |
Oct 02 07:16:43 PM UTC 24 |
45048640351 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_intr.262594966 |
|
|
Oct 02 07:16:09 PM UTC 24 |
Oct 02 07:16:44 PM UTC 24 |
45650154383 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_noise_filter.579017259 |
|
|
Oct 02 07:15:04 PM UTC 24 |
Oct 02 07:16:46 PM UTC 24 |
264321478502 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.2682255731 |
|
|
Oct 02 07:15:11 PM UTC 24 |
Oct 02 07:16:49 PM UTC 24 |
18538282152 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.1413597083 |
|
|
Oct 02 07:16:26 PM UTC 24 |
Oct 02 07:16:58 PM UTC 24 |
8419546772 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_perf.2847463192 |
|
|
Oct 02 07:10:12 PM UTC 24 |
Oct 02 07:16:59 PM UTC 24 |
13313417820 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_rx_oversample.1351952992 |
|
|
Oct 02 07:16:45 PM UTC 24 |
Oct 02 07:17:02 PM UTC 24 |
4577016830 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_tx_rx.1604339188 |
|
|
Oct 02 07:16:02 PM UTC 24 |
Oct 02 07:17:04 PM UTC 24 |
131625436145 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.2305305956 |
|
|
Oct 02 07:16:59 PM UTC 24 |
Oct 02 07:17:07 PM UTC 24 |
3275645448 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.1657184470 |
|
|
Oct 02 07:17:03 PM UTC 24 |
Oct 02 07:17:07 PM UTC 24 |
4117113675 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.470068516 |
|
|
Oct 02 07:15:23 PM UTC 24 |
Oct 02 07:17:09 PM UTC 24 |
38335527156 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_stress_all.3458139838 |
|
|
Oct 02 07:12:42 PM UTC 24 |
Oct 02 07:17:13 PM UTC 24 |
150440128954 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_alert_test.1203738905 |
|
|
Oct 02 07:17:17 PM UTC 24 |
Oct 02 07:17:19 PM UTC 24 |
13994574 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_loopback.2853222846 |
|
|
Oct 02 07:17:05 PM UTC 24 |
Oct 02 07:17:21 PM UTC 24 |
6326874867 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.2700390068 |
|
|
Oct 02 07:17:00 PM UTC 24 |
Oct 02 07:17:24 PM UTC 24 |
8260916685 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.3230798314 |
|
|
Oct 02 07:16:16 PM UTC 24 |
Oct 02 07:17:29 PM UTC 24 |
34786551493 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_fifo_full.220637709 |
|
|
Oct 02 07:12:44 PM UTC 24 |
Oct 02 07:17:30 PM UTC 24 |
224812633712 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_stress_all.2225748403 |
|
|
Oct 02 07:14:49 PM UTC 24 |
Oct 02 07:17:39 PM UTC 24 |
318969585712 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_perf.1610481387 |
|
|
Oct 02 07:15:09 PM UTC 24 |
Oct 02 07:17:45 PM UTC 24 |
11659916431 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_tx_rx.3076292563 |
|
|
Oct 02 07:16:39 PM UTC 24 |
Oct 02 07:17:46 PM UTC 24 |
114774823581 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_smoke.3796747127 |
|
|
Oct 02 07:17:21 PM UTC 24 |
Oct 02 07:17:53 PM UTC 24 |
5488442241 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_noise_filter.1002617749 |
|
|
Oct 02 07:16:51 PM UTC 24 |
Oct 02 07:17:53 PM UTC 24 |
89386654368 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_fifo_full.3849707661 |
|
|
Oct 02 07:16:03 PM UTC 24 |
Oct 02 07:17:57 PM UTC 24 |
57331921501 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_stress_all.1212003613 |
|
|
Oct 02 07:17:14 PM UTC 24 |
Oct 02 07:17:58 PM UTC 24 |
48974543694 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_rx_oversample.3814858703 |
|
|
Oct 02 07:17:39 PM UTC 24 |
Oct 02 07:18:00 PM UTC 24 |
7568663611 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.3177739464 |
|
|
Oct 02 07:07:16 PM UTC 24 |
Oct 02 07:18:01 PM UTC 24 |
186562965390 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.987271421 |
|
|
Oct 02 07:17:59 PM UTC 24 |
Oct 02 07:18:05 PM UTC 24 |
762654463 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.3708142544 |
|
|
Oct 02 07:12:44 PM UTC 24 |
Oct 02 07:18:06 PM UTC 24 |
220013051435 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_fifo_reset.670804889 |
|
|
Oct 02 07:17:31 PM UTC 24 |
Oct 02 07:18:07 PM UTC 24 |
122457288117 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_intr.588110777 |
|
|
Oct 02 07:16:47 PM UTC 24 |
Oct 02 07:18:10 PM UTC 24 |
30704262784 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_alert_test.205439000 |
|
|
Oct 02 07:18:08 PM UTC 24 |
Oct 02 07:18:10 PM UTC 24 |
11563765 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_loopback.792039466 |
|
|
Oct 02 07:17:59 PM UTC 24 |
Oct 02 07:18:10 PM UTC 24 |
5450280263 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_stress_all.1062234761 |
|
|
Oct 02 07:10:35 PM UTC 24 |
Oct 02 07:18:11 PM UTC 24 |
160118953281 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_smoke.1766504760 |
|
|
Oct 02 07:18:10 PM UTC 24 |
Oct 02 07:18:12 PM UTC 24 |
135453840 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.1905550537 |
|
|
Oct 02 07:17:54 PM UTC 24 |
Oct 02 07:18:13 PM UTC 24 |
28133166359 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_perf.1616181018 |
|
|
Oct 02 07:14:48 PM UTC 24 |
Oct 02 07:18:17 PM UTC 24 |
10651211591 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.2563711210 |
|
|
Oct 02 07:17:30 PM UTC 24 |
Oct 02 07:18:18 PM UTC 24 |
69393969511 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_stress_all.428272390 |
|
|
Oct 02 07:12:58 PM UTC 24 |
Oct 02 07:18:33 PM UTC 24 |
116194364366 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.455250975 |
|
|
Oct 02 07:18:06 PM UTC 24 |
Oct 02 07:18:34 PM UTC 24 |
8054488546 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_fifo_full.3430591560 |
|
|
Oct 02 07:16:39 PM UTC 24 |
Oct 02 07:18:35 PM UTC 24 |
71581898529 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_rx_oversample.2872031189 |
|
|
Oct 02 07:18:14 PM UTC 24 |
Oct 02 07:18:38 PM UTC 24 |
7347640199 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.441259925 |
|
|
Oct 02 07:17:10 PM UTC 24 |
Oct 02 07:18:39 PM UTC 24 |
4449344518 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.3019394453 |
|
|
Oct 02 07:18:36 PM UTC 24 |
Oct 02 07:18:41 PM UTC 24 |
859642240 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_noise_filter.2540295699 |
|
|
Oct 02 07:17:47 PM UTC 24 |
Oct 02 07:18:47 PM UTC 24 |
14726939385 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_loopback.1637971979 |
|
|
Oct 02 07:18:39 PM UTC 24 |
Oct 02 07:18:48 PM UTC 24 |
3979353486 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_intr.1769295631 |
|
|
Oct 02 07:17:45 PM UTC 24 |
Oct 02 07:18:48 PM UTC 24 |
152460380659 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_fifo_full.3202317613 |
|
|
Oct 02 07:17:26 PM UTC 24 |
Oct 02 07:18:51 PM UTC 24 |
54649684769 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.3576155189 |
|
|
Oct 02 07:18:35 PM UTC 24 |
Oct 02 07:18:51 PM UTC 24 |
24563013915 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_alert_test.618781236 |
|
|
Oct 02 07:18:50 PM UTC 24 |
Oct 02 07:18:51 PM UTC 24 |
12362193 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_tx_rx.4032332987 |
|
|
Oct 02 07:18:10 PM UTC 24 |
Oct 02 07:18:55 PM UTC 24 |
40170804076 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.15090208 |
|
|
Oct 02 07:17:53 PM UTC 24 |
Oct 02 07:18:55 PM UTC 24 |
32389781355 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_fifo_reset.2143626537 |
|
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Oct 02 07:16:08 PM UTC 24 |
Oct 02 07:18:56 PM UTC 24 |
64169047982 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_perf.137027917 |
|
|
Oct 02 07:11:21 PM UTC 24 |
Oct 02 07:18:59 PM UTC 24 |
8272950207 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_smoke.42729557 |
|
|
Oct 02 07:18:52 PM UTC 24 |
Oct 02 07:19:04 PM UTC 24 |
5356321105 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.4060038756 |
|
|
Oct 02 07:14:23 PM UTC 24 |
Oct 02 07:19:05 PM UTC 24 |
82528631947 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_fifo_reset.2370306036 |
|
|
Oct 02 07:14:31 PM UTC 24 |
Oct 02 07:19:09 PM UTC 24 |
182690969776 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_intr.249234378 |
|
|
Oct 02 07:18:18 PM UTC 24 |
Oct 02 07:19:10 PM UTC 24 |
17383339079 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_stress_all.3517912047 |
|
|
Oct 02 07:13:57 PM UTC 24 |
Oct 02 07:19:11 PM UTC 24 |
176134152880 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.1726150515 |
|
|
Oct 02 07:19:06 PM UTC 24 |
Oct 02 07:19:12 PM UTC 24 |
6591974911 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.4020744370 |
|
|
Oct 02 07:19:10 PM UTC 24 |
Oct 02 07:19:14 PM UTC 24 |
1299640845 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.3727357579 |
|
|
Oct 02 07:18:11 PM UTC 24 |
Oct 02 07:19:18 PM UTC 24 |
24528544824 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_fifo_reset.322103110 |
|
|
Oct 02 07:16:44 PM UTC 24 |
Oct 02 07:19:28 PM UTC 24 |
94061894281 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_fifo_reset.2065567626 |
|
|
Oct 02 07:18:56 PM UTC 24 |
Oct 02 07:19:31 PM UTC 24 |
23559569318 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.3497593401 |
|
|
Oct 02 07:18:48 PM UTC 24 |
Oct 02 07:19:34 PM UTC 24 |
5516607334 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_alert_test.1736574619 |
|
|
Oct 02 07:19:32 PM UTC 24 |
Oct 02 07:19:34 PM UTC 24 |
13431105 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_loopback.3609346251 |
|
|
Oct 02 07:19:12 PM UTC 24 |
Oct 02 07:19:36 PM UTC 24 |
6131651756 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_tx_rx.3336416794 |
|
|
Oct 02 07:17:23 PM UTC 24 |
Oct 02 07:19:37 PM UTC 24 |
50612364663 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.1282608820 |
|
|
Oct 02 07:10:33 PM UTC 24 |
Oct 02 07:19:37 PM UTC 24 |
173972592045 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_noise_filter.849122531 |
|
|
Oct 02 07:18:19 PM UTC 24 |
Oct 02 07:19:37 PM UTC 24 |
75543007464 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.3969163368 |
|
|
Oct 02 07:19:09 PM UTC 24 |
Oct 02 07:19:40 PM UTC 24 |
32807018156 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_fifo_reset.1671089245 |
|
|
Oct 02 07:15:24 PM UTC 24 |
Oct 02 07:19:44 PM UTC 24 |
109587585869 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_perf.1724690863 |
|
|
Oct 02 07:13:52 PM UTC 24 |
Oct 02 07:19:45 PM UTC 24 |
8425712261 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_intr.2673703303 |
|
|
Oct 02 07:18:59 PM UTC 24 |
Oct 02 07:19:46 PM UTC 24 |
29545380559 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_rx_oversample.1448544817 |
|
|
Oct 02 07:19:39 PM UTC 24 |
Oct 02 07:19:53 PM UTC 24 |
2005460773 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.2894771711 |
|
|
Oct 02 07:19:37 PM UTC 24 |
Oct 02 07:19:53 PM UTC 24 |
15620602184 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_fifo_reset.1892268389 |
|
|
Oct 02 07:18:13 PM UTC 24 |
Oct 02 07:19:54 PM UTC 24 |
53737143805 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_smoke.4059280761 |
|
|
Oct 02 07:19:35 PM UTC 24 |
Oct 02 07:19:55 PM UTC 24 |
5376209780 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_tx_rx.269700237 |
|
|
Oct 02 07:18:52 PM UTC 24 |
Oct 02 07:19:58 PM UTC 24 |
40283196359 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_fifo_full.3046468813 |
|
|
Oct 02 07:18:11 PM UTC 24 |
Oct 02 07:19:58 PM UTC 24 |
71136318924 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.511857202 |
|
|
Oct 02 07:19:46 PM UTC 24 |
Oct 02 07:20:00 PM UTC 24 |
4124861492 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_alert_test.1389113105 |
|
|
Oct 02 07:19:59 PM UTC 24 |
Oct 02 07:20:01 PM UTC 24 |
11933470 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_loopback.2759155244 |
|
|
Oct 02 07:19:54 PM UTC 24 |
Oct 02 07:20:01 PM UTC 24 |
3563019990 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_smoke.3646272661 |
|
|
Oct 02 07:20:01 PM UTC 24 |
Oct 02 07:20:05 PM UTC 24 |
572358432 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_rx_oversample.2513775328 |
|
|
Oct 02 07:18:57 PM UTC 24 |
Oct 02 07:20:11 PM UTC 24 |
7571891121 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.1506827304 |
|
|
Oct 02 07:19:19 PM UTC 24 |
Oct 02 07:20:14 PM UTC 24 |
6546892963 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_fifo_full.819351341 |
|
|
Oct 02 07:14:55 PM UTC 24 |
Oct 02 07:20:21 PM UTC 24 |
155054900874 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_tx_rx.1871147264 |
|
|
Oct 02 07:19:35 PM UTC 24 |
Oct 02 07:20:28 PM UTC 24 |
56719059473 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_fifo_full.620411026 |
|
|
Oct 02 07:18:53 PM UTC 24 |
Oct 02 07:20:38 PM UTC 24 |
113104029216 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_intr.1108609094 |
|
|
Oct 02 07:19:41 PM UTC 24 |
Oct 02 07:20:43 PM UTC 24 |
41670446526 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.930951345 |
|
|
Oct 02 07:20:39 PM UTC 24 |
Oct 02 07:20:45 PM UTC 24 |
3890539331 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.1056393461 |
|
|
Oct 02 07:19:47 PM UTC 24 |
Oct 02 07:20:46 PM UTC 24 |
117564783649 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_noise_filter.2151162927 |
|
|
Oct 02 07:16:09 PM UTC 24 |
Oct 02 07:20:47 PM UTC 24 |
152338120383 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.3044919155 |
|
|
Oct 02 07:07:11 PM UTC 24 |
Oct 02 07:20:47 PM UTC 24 |
78357678601 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_noise_filter.2957038300 |
|
|
Oct 02 07:19:05 PM UTC 24 |
Oct 02 07:20:50 PM UTC 24 |
117674085140 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.3565102297 |
|
|
Oct 02 07:18:56 PM UTC 24 |
Oct 02 07:20:53 PM UTC 24 |
36342825461 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_perf.1754262040 |
|
|
Oct 02 07:18:39 PM UTC 24 |
Oct 02 07:20:55 PM UTC 24 |
9452269285 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_alert_test.4066106971 |
|
|
Oct 02 07:20:56 PM UTC 24 |
Oct 02 07:20:58 PM UTC 24 |
17643658 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.3172576228 |
|
|
Oct 02 07:18:34 PM UTC 24 |
Oct 02 07:21:03 PM UTC 24 |
76834611019 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_smoke.253207183 |
|
|
Oct 02 07:20:59 PM UTC 24 |
Oct 02 07:21:06 PM UTC 24 |
842879726 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_stress_all.666477841 |
|
|
Oct 02 07:18:48 PM UTC 24 |
Oct 02 07:21:13 PM UTC 24 |
495323048301 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.780873377 |
|
|
Oct 02 07:16:39 PM UTC 24 |
Oct 02 07:21:15 PM UTC 24 |
106383379890 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.3403262600 |
|
|
Oct 02 07:19:58 PM UTC 24 |
Oct 02 07:21:16 PM UTC 24 |
4167985411 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_loopback.1206665759 |
|
|
Oct 02 07:20:47 PM UTC 24 |
Oct 02 07:21:17 PM UTC 24 |
6369115160 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.3040153694 |
|
|
Oct 02 07:20:47 PM UTC 24 |
Oct 02 07:21:20 PM UTC 24 |
6737124554 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_stress_all.439124162 |
|
|
Oct 02 07:15:56 PM UTC 24 |
Oct 02 07:21:20 PM UTC 24 |
135845387634 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_perf.2182669885 |
|
|
Oct 02 07:12:52 PM UTC 24 |
Oct 02 07:21:21 PM UTC 24 |
15765074451 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_intr.3904544735 |
|
|
Oct 02 07:15:01 PM UTC 24 |
Oct 02 07:21:26 PM UTC 24 |
266686887941 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_perf.1799364883 |
|
|
Oct 02 07:17:08 PM UTC 24 |
Oct 02 07:21:33 PM UTC 24 |
21488087173 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_loopback.3574969359 |
|
|
Oct 02 07:21:33 PM UTC 24 |
Oct 02 07:21:35 PM UTC 24 |
332267462 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.146251210 |
|
|
Oct 02 07:20:51 PM UTC 24 |
Oct 02 07:21:37 PM UTC 24 |
5873203298 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_rx_oversample.1054267408 |
|
|
Oct 02 07:20:15 PM UTC 24 |
Oct 02 07:21:42 PM UTC 24 |
6870605951 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.42616556 |
|
|
Oct 02 07:21:26 PM UTC 24 |
Oct 02 07:21:46 PM UTC 24 |
7992447799 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_rx_oversample.3889197969 |
|
|
Oct 02 07:21:17 PM UTC 24 |
Oct 02 07:21:47 PM UTC 24 |
3890567613 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_tx_rx.2743105198 |
|
|
Oct 02 07:20:02 PM UTC 24 |
Oct 02 07:21:48 PM UTC 24 |
47237523026 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_alert_test.871811467 |
|
|
Oct 02 07:21:47 PM UTC 24 |
Oct 02 07:21:49 PM UTC 24 |
31310484 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_intr.2297302273 |
|
|
Oct 02 07:21:19 PM UTC 24 |
Oct 02 07:21:50 PM UTC 24 |
20346625907 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.1628059645 |
|
|
Oct 02 07:21:21 PM UTC 24 |
Oct 02 07:21:54 PM UTC 24 |
49969719520 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_stress_all.2017279505 |
|
|
Oct 02 07:18:07 PM UTC 24 |
Oct 02 07:21:56 PM UTC 24 |
31312923857 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_noise_filter.1669363228 |
|
|
Oct 02 07:20:29 PM UTC 24 |
Oct 02 07:22:12 PM UTC 24 |
37091898385 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.2730597392 |
|
|
Oct 02 07:21:14 PM UTC 24 |
Oct 02 07:22:12 PM UTC 24 |
154252588645 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.127757393 |
|
|
Oct 02 07:06:42 PM UTC 24 |
Oct 02 07:22:18 PM UTC 24 |
109820795979 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_smoke.2155013951 |
|
|
Oct 02 07:21:49 PM UTC 24 |
Oct 02 07:22:21 PM UTC 24 |
5874594818 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_perf.2948655612 |
|
|
Oct 02 07:09:20 PM UTC 24 |
Oct 02 07:22:29 PM UTC 24 |
13908552404 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.2304748537 |
|
|
Oct 02 07:21:51 PM UTC 24 |
Oct 02 07:22:31 PM UTC 24 |
44575109654 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_fifo_reset.103710959 |
|
|
Oct 02 07:19:37 PM UTC 24 |
Oct 02 07:22:31 PM UTC 24 |
65909117810 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_noise_filter.2478616670 |
|
|
Oct 02 07:19:45 PM UTC 24 |
Oct 02 07:22:31 PM UTC 24 |
229093629981 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.3857853018 |
|
|
Oct 02 07:22:30 PM UTC 24 |
Oct 02 07:22:33 PM UTC 24 |
1932552410 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_noise_filter.3935104486 |
|
|
Oct 02 07:21:21 PM UTC 24 |
Oct 02 07:22:33 PM UTC 24 |
25436315760 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_rx_oversample.305616060 |
|
|
Oct 02 07:21:56 PM UTC 24 |
Oct 02 07:22:37 PM UTC 24 |
4140425956 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_alert_test.914043714 |
|
|
Oct 02 07:22:38 PM UTC 24 |
Oct 02 07:22:40 PM UTC 24 |
22481518 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.1931936287 |
|
|
Oct 02 07:15:50 PM UTC 24 |
Oct 02 07:22:47 PM UTC 24 |
42692069291 ps |