| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.12 | 99.08 | 97.65 | 100.00 | 98.35 | 100.00 | 99.62 |
| T57 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.532563477 | Oct 02 07:43:54 PM UTC 24 | Oct 02 07:43:56 PM UTC 24 | 16676037 ps | ||
| T1255 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.629634449 | Oct 02 07:43:54 PM UTC 24 | Oct 02 07:43:56 PM UTC 24 | 12965813 ps | ||
| T1256 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.574718928 | Oct 02 07:43:54 PM UTC 24 | Oct 02 07:43:56 PM UTC 24 | 14933926 ps | ||
| T1257 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.1833239857 | Oct 02 07:43:54 PM UTC 24 | Oct 02 07:43:56 PM UTC 24 | 48846952 ps | ||
| T1258 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.2248420314 | Oct 02 07:43:54 PM UTC 24 | Oct 02 07:43:56 PM UTC 24 | 22072644 ps | ||
| T1259 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.587064177 | Oct 02 07:43:54 PM UTC 24 | Oct 02 07:43:56 PM UTC 24 | 22507352 ps | ||
| T1260 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.2838630648 | Oct 02 07:43:55 PM UTC 24 | Oct 02 07:43:56 PM UTC 24 | 50596437 ps | ||
| T1261 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.2182629465 | Oct 02 07:43:54 PM UTC 24 | Oct 02 07:43:56 PM UTC 24 | 47104525 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2244570509 | Oct 02 07:43:55 PM UTC 24 | Oct 02 07:43:56 PM UTC 24 | 91635785 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2836487796 | Oct 02 07:43:55 PM UTC 24 | Oct 02 07:43:56 PM UTC 24 | 36561443 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2222916724 | Oct 02 07:43:54 PM UTC 24 | Oct 02 07:43:57 PM UTC 24 | 23303534 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.3002961678 | Oct 02 07:43:55 PM UTC 24 | Oct 02 07:43:57 PM UTC 24 | 83139379 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.3329690847 | Oct 02 07:43:54 PM UTC 24 | Oct 02 07:43:57 PM UTC 24 | 539927778 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.358375430 | Oct 02 07:43:55 PM UTC 24 | Oct 02 07:43:57 PM UTC 24 | 76592900 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.2026802172 | Oct 02 07:43:54 PM UTC 24 | Oct 02 07:43:57 PM UTC 24 | 51076756 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.2771867435 | Oct 02 07:43:55 PM UTC 24 | Oct 02 07:43:57 PM UTC 24 | 165773535 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.2102494345 | Oct 02 07:43:54 PM UTC 24 | Oct 02 07:43:57 PM UTC 24 | 72497462 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.2713371727 | Oct 02 07:43:55 PM UTC 24 | Oct 02 07:43:57 PM UTC 24 | 78045381 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.3576051868 | Oct 02 07:43:54 PM UTC 24 | Oct 02 07:43:58 PM UTC 24 | 414693371 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.4271160593 | Oct 02 07:43:55 PM UTC 24 | Oct 02 07:43:58 PM UTC 24 | 184489164 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.2332158302 | Oct 02 07:43:57 PM UTC 24 | Oct 02 07:43:59 PM UTC 24 | 61268149 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.2066347209 | Oct 02 07:43:57 PM UTC 24 | Oct 02 07:43:59 PM UTC 24 | 16207047 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.4251275865 | Oct 02 07:43:57 PM UTC 24 | Oct 02 07:43:59 PM UTC 24 | 13452708 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.42115318 | Oct 02 07:43:58 PM UTC 24 | Oct 02 07:43:59 PM UTC 24 | 46125889 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.4150114471 | Oct 02 07:43:58 PM UTC 24 | Oct 02 07:43:59 PM UTC 24 | 34740431 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.1297646549 | Oct 02 07:43:58 PM UTC 24 | Oct 02 07:43:59 PM UTC 24 | 30524629 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.3200184330 | Oct 02 07:43:57 PM UTC 24 | Oct 02 07:43:59 PM UTC 24 | 44653843 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2749132932 | Oct 02 07:43:58 PM UTC 24 | Oct 02 07:44:00 PM UTC 24 | 26640298 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.597136285 | Oct 02 07:43:58 PM UTC 24 | Oct 02 07:44:00 PM UTC 24 | 19884715 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3109083571 | Oct 02 07:43:58 PM UTC 24 | Oct 02 07:44:00 PM UTC 24 | 54435522 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1188482498 | Oct 02 07:43:58 PM UTC 24 | Oct 02 07:44:00 PM UTC 24 | 39719062 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.464841137 | Oct 02 07:43:58 PM UTC 24 | Oct 02 07:44:00 PM UTC 24 | 21657191 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1209864315 | Oct 02 07:43:58 PM UTC 24 | Oct 02 07:44:00 PM UTC 24 | 32202939 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.1475865011 | Oct 02 07:43:58 PM UTC 24 | Oct 02 07:44:00 PM UTC 24 | 23077203 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.3881477688 | Oct 02 07:43:58 PM UTC 24 | Oct 02 07:44:00 PM UTC 24 | 184050926 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.338010137 | Oct 02 07:43:58 PM UTC 24 | Oct 02 07:44:01 PM UTC 24 | 144784504 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.1714327365 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 50557745 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.2537421755 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 18763730 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.3060798270 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 36147473 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.3036900696 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 18610381 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.4004743692 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 27973531 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.675046879 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 14044236 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.2620117835 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 16938197 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.349160902 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 40652464 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.364413208 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 25308120 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.4145084984 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 130126914 ps | ||
| T1297 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3238559432 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 11010714 ps | ||
| T1298 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.260114977 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 12211157 ps | ||
| T1299 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.1312530610 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 34827626 ps | ||
| T1300 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.658951777 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 37624083 ps | ||
| T1301 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2728330569 | Oct 02 07:44:01 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 17106574 ps | ||
| T1302 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.48666704 | Oct 02 07:44:02 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 49276574 ps | ||
| T1303 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.1004950127 | Oct 02 07:44:02 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 37101962 ps | ||
| T1304 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.3737229037 | Oct 02 07:44:02 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 47300025 ps | ||
| T1305 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.508485931 | Oct 02 07:44:02 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 28435763 ps | ||
| T1306 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.2429152794 | Oct 02 07:44:02 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 41932002 ps | ||
| T1307 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.3205370348 | Oct 02 07:44:02 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 14718380 ps | ||
| T1308 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.37761322 | Oct 02 07:44:02 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 12830737 ps | ||
| T1309 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.2566544471 | Oct 02 07:44:02 PM UTC 24 | Oct 02 07:44:03 PM UTC 24 | 13643106 ps | ||
| T1310 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.1929116828 | Oct 02 07:44:02 PM UTC 24 | Oct 02 07:44:04 PM UTC 24 | 15405243 ps | ||
| T1311 | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.383875207 | Oct 02 07:44:05 PM UTC 24 | Oct 02 07:44:06 PM UTC 24 | 136702121 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_intr.1332171122 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 54968792463 ps |
| CPU time | 21.96 seconds |
| Started | Oct 02 07:06:37 PM UTC 24 |
| Finished | Oct 02 07:07:07 PM UTC 24 |
| Peak memory | 208384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332171122 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1332171122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.2854367425 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3160674105 ps |
| CPU time | 33.33 seconds |
| Started | Oct 02 07:06:42 PM UTC 24 |
| Finished | Oct 02 07:07:33 PM UTC 24 |
| Peak memory | 220356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2854367425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_ with_rand_reset.2854367425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_stress_all.657829758 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 236985442116 ps |
| CPU time | 133.95 seconds |
| Started | Oct 02 07:06:42 PM UTC 24 |
| Finished | Oct 02 07:09:15 PM UTC 24 |
| Peak memory | 205824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657829758 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.657829758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_stress_all.3458701293 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 369676422356 ps |
| CPU time | 146.48 seconds |
| Started | Oct 02 07:07:02 PM UTC 24 |
| Finished | Oct 02 07:09:37 PM UTC 24 |
| Peak memory | 218692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458701293 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3458701293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.2847225789 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 66049347414 ps |
| CPU time | 122.24 seconds |
| Started | Oct 02 07:09:22 PM UTC 24 |
| Finished | Oct 02 07:11:27 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847225789 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2847225789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.4087970073 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 46142395481 ps |
| CPU time | 18.69 seconds |
| Started | Oct 02 07:07:12 PM UTC 24 |
| Finished | Oct 02 07:07:33 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087970073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.4087970073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_tx_rx.78093110 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 132820616447 ps |
| CPU time | 25.26 seconds |
| Started | Oct 02 07:06:36 PM UTC 24 |
| Finished | Oct 02 07:07:10 PM UTC 24 |
| Peak memory | 209056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78093110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.78093110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.103558744 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 78328790830 ps |
| CPU time | 148.01 seconds |
| Started | Oct 02 07:07:01 PM UTC 24 |
| Finished | Oct 02 07:09:34 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103558744 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.103558744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.2798176356 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 41244590302 ps |
| CPU time | 25.93 seconds |
| Started | Oct 02 07:06:37 PM UTC 24 |
| Finished | Oct 02 07:07:11 PM UTC 24 |
| Peak memory | 209396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798176356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2798176356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.1434569667 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5916897287 ps |
| CPU time | 41.98 seconds |
| Started | Oct 02 07:07:26 PM UTC 24 |
| Finished | Oct 02 07:08:10 PM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1434569667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_ with_rand_reset.1434569667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_sec_cm.4222192531 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 63302435 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 07:06:43 PM UTC 24 |
| Finished | Oct 02 07:06:56 PM UTC 24 |
| Peak memory | 235464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222192531 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.4222192531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_stress_all.1899325503 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 143831199772 ps |
| CPU time | 28.95 seconds |
| Started | Oct 02 07:07:11 PM UTC 24 |
| Finished | Oct 02 07:07:44 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899325503 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1899325503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_fifo_full.3060139095 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 169375783035 ps |
| CPU time | 375.03 seconds |
| Started | Oct 02 07:07:06 PM UTC 24 |
| Finished | Oct 02 07:13:29 PM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060139095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3060139095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.1803993116 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 64654526762 ps |
| CPU time | 222.73 seconds |
| Started | Oct 02 07:07:43 PM UTC 24 |
| Finished | Oct 02 07:11:29 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803993116 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1803993116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_fifo_full.2842037159 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 258438917954 ps |
| CPU time | 72.69 seconds |
| Started | Oct 02 07:13:01 PM UTC 24 |
| Finished | Oct 02 07:14:15 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842037159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2842037159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.2722259958 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 122348024 ps |
| CPU time | 0.9 seconds |
| Started | Oct 02 07:43:40 PM UTC 24 |
| Finished | Oct 02 07:43:42 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722259958 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2722259958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_intr.1254635428 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 35946466286 ps |
| CPU time | 44.69 seconds |
| Started | Oct 02 07:07:54 PM UTC 24 |
| Finished | Oct 02 07:08:40 PM UTC 24 |
| Peak memory | 203836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254635428 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1254635428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.2116998677 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 132390264652 ps |
| CPU time | 325.08 seconds |
| Started | Oct 02 07:07:19 PM UTC 24 |
| Finished | Oct 02 07:12:49 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116998677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2116998677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.1392787480 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 212800751240 ps |
| CPU time | 102.1 seconds |
| Started | Oct 02 07:10:41 PM UTC 24 |
| Finished | Oct 02 07:12:25 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392787480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1392787480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.2811220154 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 52192359257 ps |
| CPU time | 49.3 seconds |
| Started | Oct 02 07:09:15 PM UTC 24 |
| Finished | Oct 02 07:10:06 PM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811220154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2811220154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_stress_all.2833504233 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 92655125847 ps |
| CPU time | 27.76 seconds |
| Started | Oct 02 07:11:52 PM UTC 24 |
| Finished | Oct 02 07:12:21 PM UTC 24 |
| Peak memory | 203768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833504233 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2833504233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_fifo_full.4159888123 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 79627634258 ps |
| CPU time | 141.62 seconds |
| Started | Oct 02 07:10:20 PM UTC 24 |
| Finished | Oct 02 07:12:44 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159888123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.4159888123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_tx_rx.2865476687 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 131051249709 ps |
| CPU time | 143.44 seconds |
| Started | Oct 02 07:07:11 PM UTC 24 |
| Finished | Oct 02 07:09:40 PM UTC 24 |
| Peak memory | 203772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865476687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2865476687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_noise_filter.2960849215 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 198033975316 ps |
| CPU time | 361.83 seconds |
| Started | Oct 02 07:08:41 PM UTC 24 |
| Finished | Oct 02 07:14:48 PM UTC 24 |
| Peak memory | 209612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960849215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2960849215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.297909912 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 351554861 ps |
| CPU time | 1.67 seconds |
| Started | Oct 02 07:43:31 PM UTC 24 |
| Finished | Oct 02 07:43:34 PM UTC 24 |
| Peak memory | 201716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297909912 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.297909912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_noise_filter.3639452775 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 407266890080 ps |
| CPU time | 99.37 seconds |
| Started | Oct 02 07:06:37 PM UTC 24 |
| Finished | Oct 02 07:08:35 PM UTC 24 |
| Peak memory | 218508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639452775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3639452775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_alert_test.2734052187 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 45627357 ps |
| CPU time | 0.59 seconds |
| Started | Oct 02 07:06:45 PM UTC 24 |
| Finished | Oct 02 07:07:09 PM UTC 24 |
| Peak memory | 203256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734052187 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2734052187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_noise_filter.3444535727 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 205065890447 ps |
| CPU time | 54.74 seconds |
| Started | Oct 02 07:06:55 PM UTC 24 |
| Finished | Oct 02 07:07:55 PM UTC 24 |
| Peak memory | 218644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444535727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3444535727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_perf.835268162 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 29507197451 ps |
| CPU time | 453.81 seconds |
| Started | Oct 02 07:07:23 PM UTC 24 |
| Finished | Oct 02 07:15:03 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835268162 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.835268162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_fifo_reset.4007880627 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 30541783824 ps |
| CPU time | 72.1 seconds |
| Started | Oct 02 07:06:37 PM UTC 24 |
| Finished | Oct 02 07:07:58 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007880627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.4007880627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.3637646992 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 90590641260 ps |
| CPU time | 220.85 seconds |
| Started | Oct 02 07:09:02 PM UTC 24 |
| Finished | Oct 02 07:12:46 PM UTC 24 |
| Peak memory | 203856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637646992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3637646992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.2007192296 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 101492314243 ps |
| CPU time | 25.51 seconds |
| Started | Oct 02 07:06:52 PM UTC 24 |
| Finished | Oct 02 07:07:36 PM UTC 24 |
| Peak memory | 204044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007192296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2007192296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_fifo_full.467987885 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 166663283088 ps |
| CPU time | 203.98 seconds |
| Started | Oct 02 07:10:40 PM UTC 24 |
| Finished | Oct 02 07:14:07 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467987885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.467987885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_fifo_reset.3121835311 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 22617210908 ps |
| CPU time | 37.74 seconds |
| Started | Oct 02 07:10:41 PM UTC 24 |
| Finished | Oct 02 07:11:20 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121835311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3121835311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_stress_all.1062234761 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 160118953281 ps |
| CPU time | 449.68 seconds |
| Started | Oct 02 07:10:35 PM UTC 24 |
| Finished | Oct 02 07:18:11 PM UTC 24 |
| Peak memory | 213008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062234761 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1062234761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.2682255731 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 18538282152 ps |
| CPU time | 96.53 seconds |
| Started | Oct 02 07:15:11 PM UTC 24 |
| Finished | Oct 02 07:16:49 PM UTC 24 |
| Peak memory | 220664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2682255731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all _with_rand_reset.2682255731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.1100360416 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 160736080 ps |
| CPU time | 1.44 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 201780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100360416 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1100360416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.1466237050 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 183519805917 ps |
| CPU time | 108.77 seconds |
| Started | Oct 02 07:11:31 PM UTC 24 |
| Finished | Oct 02 07:13:22 PM UTC 24 |
| Peak memory | 209448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466237050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1466237050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/188.uart_fifo_reset.1003226171 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 48118541037 ps |
| CPU time | 43.48 seconds |
| Started | Oct 02 07:40:35 PM UTC 24 |
| Finished | Oct 02 07:41:20 PM UTC 24 |
| Peak memory | 204040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003226171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1003226171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/188.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_fifo_reset.2370306036 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 182690969776 ps |
| CPU time | 273.12 seconds |
| Started | Oct 02 07:14:31 PM UTC 24 |
| Finished | Oct 02 07:19:09 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370306036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2370306036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_fifo_full.1094912107 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 85671689263 ps |
| CPU time | 33.48 seconds |
| Started | Oct 02 07:06:36 PM UTC 24 |
| Finished | Oct 02 07:07:19 PM UTC 24 |
| Peak memory | 209160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094912107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1094912107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_noise_filter.1799264720 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 138556130214 ps |
| CPU time | 83.79 seconds |
| Started | Oct 02 07:12:47 PM UTC 24 |
| Finished | Oct 02 07:14:12 PM UTC 24 |
| Peak memory | 218452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799264720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1799264720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.2649053380 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1647776971 ps |
| CPU time | 31.55 seconds |
| Started | Oct 02 07:07:01 PM UTC 24 |
| Finished | Oct 02 07:07:37 PM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2649053380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_ with_rand_reset.2649053380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_fifo_full.4002408390 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 60532789165 ps |
| CPU time | 35.61 seconds |
| Started | Oct 02 07:09:57 PM UTC 24 |
| Finished | Oct 02 07:10:34 PM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002408390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.4002408390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.2205123407 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 40901324683 ps |
| CPU time | 108.78 seconds |
| Started | Oct 02 07:14:31 PM UTC 24 |
| Finished | Oct 02 07:16:22 PM UTC 24 |
| Peak memory | 209120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205123407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2205123407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/102.uart_fifo_reset.4076386131 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 27081394359 ps |
| CPU time | 18.81 seconds |
| Started | Oct 02 07:38:17 PM UTC 24 |
| Finished | Oct 02 07:38:37 PM UTC 24 |
| Peak memory | 209396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076386131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.4076386131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/102.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.1007306390 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 20527694632 ps |
| CPU time | 56.77 seconds |
| Started | Oct 02 07:11:25 PM UTC 24 |
| Finished | Oct 02 07:12:23 PM UTC 24 |
| Peak memory | 222128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1007306390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all _with_rand_reset.1007306390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_stress_all.3517912047 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 176134152880 ps |
| CPU time | 309.53 seconds |
| Started | Oct 02 07:13:57 PM UTC 24 |
| Finished | Oct 02 07:19:11 PM UTC 24 |
| Peak memory | 218424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517912047 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3517912047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_fifo_reset.1536384735 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 174968420422 ps |
| CPU time | 69.5 seconds |
| Started | Oct 02 07:14:57 PM UTC 24 |
| Finished | Oct 02 07:16:08 PM UTC 24 |
| Peak memory | 208996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536384735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1536384735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_noise_filter.4165003395 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 101141171018 ps |
| CPU time | 185.65 seconds |
| Started | Oct 02 07:07:12 PM UTC 24 |
| Finished | Oct 02 07:10:22 PM UTC 24 |
| Peak memory | 209860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165003395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.4165003395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_fifo_reset.1035741244 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 64822875231 ps |
| CPU time | 90.94 seconds |
| Started | Oct 02 07:26:16 PM UTC 24 |
| Finished | Oct 02 07:27:49 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035741244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1035741244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_fifo_reset.373683971 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 26563114839 ps |
| CPU time | 72.9 seconds |
| Started | Oct 02 07:09:36 PM UTC 24 |
| Finished | Oct 02 07:10:51 PM UTC 24 |
| Peak memory | 209152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373683971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.373683971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/149.uart_fifo_reset.573363647 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 32131373922 ps |
| CPU time | 25.92 seconds |
| Started | Oct 02 07:39:31 PM UTC 24 |
| Finished | Oct 02 07:39:59 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573363647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.573363647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/149.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_stress_all.542056553 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 802337784633 ps |
| CPU time | 248.24 seconds |
| Started | Oct 02 07:19:59 PM UTC 24 |
| Finished | Oct 02 07:24:11 PM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542056553 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.542056553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_stress_all.2523307790 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 376269755460 ps |
| CPU time | 324.38 seconds |
| Started | Oct 02 07:25:53 PM UTC 24 |
| Finished | Oct 02 07:31:22 PM UTC 24 |
| Peak memory | 205836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523307790 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2523307790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_stress_all.386508079 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 80830227859 ps |
| CPU time | 138.92 seconds |
| Started | Oct 02 07:07:45 PM UTC 24 |
| Finished | Oct 02 07:10:07 PM UTC 24 |
| Peak memory | 204036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386508079 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.386508079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_perf.535293034 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 8010403513 ps |
| CPU time | 152.53 seconds |
| Started | Oct 02 07:06:41 PM UTC 24 |
| Finished | Oct 02 07:09:19 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535293034 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.535293034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/115.uart_fifo_reset.367462641 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 28537572874 ps |
| CPU time | 64.55 seconds |
| Started | Oct 02 07:38:44 PM UTC 24 |
| Finished | Oct 02 07:39:51 PM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367462641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.367462641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/115.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/145.uart_fifo_reset.959724175 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 66581837249 ps |
| CPU time | 43.97 seconds |
| Started | Oct 02 07:39:26 PM UTC 24 |
| Finished | Oct 02 07:40:11 PM UTC 24 |
| Peak memory | 209548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959724175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.959724175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/145.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/165.uart_fifo_reset.2364284347 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 55643079225 ps |
| CPU time | 24.28 seconds |
| Started | Oct 02 07:39:54 PM UTC 24 |
| Finished | Oct 02 07:40:19 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364284347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2364284347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/165.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/198.uart_fifo_reset.455034521 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 70478091311 ps |
| CPU time | 65.27 seconds |
| Started | Oct 02 07:40:46 PM UTC 24 |
| Finished | Oct 02 07:41:53 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455034521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.455034521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/198.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/297.uart_fifo_reset.2578903504 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 59581850963 ps |
| CPU time | 114.2 seconds |
| Started | Oct 02 07:43:15 PM UTC 24 |
| Finished | Oct 02 07:45:11 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578903504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2578903504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/297.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/298.uart_fifo_reset.1886520598 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 81562056799 ps |
| CPU time | 45.46 seconds |
| Started | Oct 02 07:43:16 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886520598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1886520598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/298.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_perf.550520859 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 10335365262 ps |
| CPU time | 150.56 seconds |
| Started | Oct 02 07:07:59 PM UTC 24 |
| Finished | Oct 02 07:10:32 PM UTC 24 |
| Peak memory | 209580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550520859 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.550520859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/76.uart_fifo_reset.61659427 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 38454971012 ps |
| CPU time | 51.88 seconds |
| Started | Oct 02 07:36:36 PM UTC 24 |
| Finished | Oct 02 07:37:29 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61659427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.61659427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/76.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/97.uart_fifo_reset.3495690131 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 48465967402 ps |
| CPU time | 45.17 seconds |
| Started | Oct 02 07:38:08 PM UTC 24 |
| Finished | Oct 02 07:38:55 PM UTC 24 |
| Peak memory | 209652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495690131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3495690131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/97.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_smoke.316496377 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6206458368 ps |
| CPU time | 9.26 seconds |
| Started | Oct 02 07:06:34 PM UTC 24 |
| Finished | Oct 02 07:07:15 PM UTC 24 |
| Peak memory | 204180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316496377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.uart_smoke.316496377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/108.uart_fifo_reset.895493505 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 17675207583 ps |
| CPU time | 28.21 seconds |
| Started | Oct 02 07:38:26 PM UTC 24 |
| Finished | Oct 02 07:38:55 PM UTC 24 |
| Peak memory | 209320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895493505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.895493505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/108.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/144.uart_fifo_reset.1118761688 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 26514553462 ps |
| CPU time | 33.82 seconds |
| Started | Oct 02 07:39:26 PM UTC 24 |
| Finished | Oct 02 07:40:01 PM UTC 24 |
| Peak memory | 209664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118761688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1118761688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/144.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.2455173687 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 24400533284 ps |
| CPU time | 68.41 seconds |
| Started | Oct 02 07:11:50 PM UTC 24 |
| Finished | Oct 02 07:13:01 PM UTC 24 |
| Peak memory | 226160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2455173687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all _with_rand_reset.2455173687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/203.uart_fifo_reset.3925554206 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 51552766229 ps |
| CPU time | 161.47 seconds |
| Started | Oct 02 07:40:56 PM UTC 24 |
| Finished | Oct 02 07:43:40 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925554206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3925554206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/203.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/218.uart_fifo_reset.3785139145 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 62088566025 ps |
| CPU time | 39.74 seconds |
| Started | Oct 02 07:41:21 PM UTC 24 |
| Finished | Oct 02 07:42:02 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785139145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3785139145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/218.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_fifo_full.1601561216 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 42221119832 ps |
| CPU time | 37.75 seconds |
| Started | Oct 02 07:15:22 PM UTC 24 |
| Finished | Oct 02 07:16:01 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601561216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1601561216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_stress_all.2933447547 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 57445948256 ps |
| CPU time | 241.01 seconds |
| Started | Oct 02 07:31:23 PM UTC 24 |
| Finished | Oct 02 07:35:28 PM UTC 24 |
| Peak memory | 205740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933447547 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2933447547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.4008487693 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 351127557 ps |
| CPU time | 2.05 seconds |
| Started | Oct 02 07:43:21 PM UTC 24 |
| Finished | Oct 02 07:43:25 PM UTC 24 |
| Peak memory | 202568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008487693 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.4008487693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/100.uart_fifo_reset.1088672987 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 83065826276 ps |
| CPU time | 41.9 seconds |
| Started | Oct 02 07:38:16 PM UTC 24 |
| Finished | Oct 02 07:38:59 PM UTC 24 |
| Peak memory | 209464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088672987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1088672987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/100.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.3988033846 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 126647035129 ps |
| CPU time | 239.69 seconds |
| Started | Oct 02 07:09:57 PM UTC 24 |
| Finished | Oct 02 07:14:00 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988033846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3988033846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.3559952421 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 4173664847 ps |
| CPU time | 59.95 seconds |
| Started | Oct 02 07:10:16 PM UTC 24 |
| Finished | Oct 02 07:11:18 PM UTC 24 |
| Peak memory | 218696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3559952421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all _with_rand_reset.3559952421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/110.uart_fifo_reset.533707561 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 32897513528 ps |
| CPU time | 39.56 seconds |
| Started | Oct 02 07:38:26 PM UTC 24 |
| Finished | Oct 02 07:39:07 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533707561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.533707561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/110.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/112.uart_fifo_reset.4111361447 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 29582104730 ps |
| CPU time | 69.13 seconds |
| Started | Oct 02 07:38:32 PM UTC 24 |
| Finished | Oct 02 07:39:43 PM UTC 24 |
| Peak memory | 209320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111361447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.4111361447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/112.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_intr.2593051165 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 14784258952 ps |
| CPU time | 33.95 seconds |
| Started | Oct 02 07:10:23 PM UTC 24 |
| Finished | Oct 02 07:10:58 PM UTC 24 |
| Peak memory | 208940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593051165 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2593051165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.3489183788 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 6827666122 ps |
| CPU time | 21.63 seconds |
| Started | Oct 02 07:10:54 PM UTC 24 |
| Finished | Oct 02 07:11:17 PM UTC 24 |
| Peak memory | 203916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489183788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3489183788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/130.uart_fifo_reset.4085374604 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 64120700190 ps |
| CPU time | 112.1 seconds |
| Started | Oct 02 07:39:03 PM UTC 24 |
| Finished | Oct 02 07:40:57 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085374604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.4085374604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/130.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/146.uart_fifo_reset.3339690497 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 42313267627 ps |
| CPU time | 66.33 seconds |
| Started | Oct 02 07:39:28 PM UTC 24 |
| Finished | Oct 02 07:40:36 PM UTC 24 |
| Peak memory | 204040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339690497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3339690497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/146.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/159.uart_fifo_reset.1742298163 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 80576785259 ps |
| CPU time | 50.36 seconds |
| Started | Oct 02 07:39:46 PM UTC 24 |
| Finished | Oct 02 07:40:38 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742298163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1742298163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/159.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_intr.256308357 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 777551818093 ps |
| CPU time | 1437.63 seconds |
| Started | Oct 02 07:12:15 PM UTC 24 |
| Finished | Oct 02 07:36:29 PM UTC 24 |
| Peak memory | 207220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256308357 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.256308357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/166.uart_fifo_reset.222329998 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 138996921672 ps |
| CPU time | 57.47 seconds |
| Started | Oct 02 07:39:55 PM UTC 24 |
| Finished | Oct 02 07:40:54 PM UTC 24 |
| Peak memory | 209080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222329998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.222329998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/166.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/167.uart_fifo_reset.326291836 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 116160461198 ps |
| CPU time | 29.77 seconds |
| Started | Oct 02 07:39:56 PM UTC 24 |
| Finished | Oct 02 07:40:27 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326291836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.326291836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/167.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/180.uart_fifo_reset.1233701359 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 87065642021 ps |
| CPU time | 64.12 seconds |
| Started | Oct 02 07:40:24 PM UTC 24 |
| Finished | Oct 02 07:41:31 PM UTC 24 |
| Peak memory | 204116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233701359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1233701359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/180.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/181.uart_fifo_reset.2267223454 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 38664724363 ps |
| CPU time | 17.89 seconds |
| Started | Oct 02 07:40:25 PM UTC 24 |
| Finished | Oct 02 07:40:45 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267223454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2267223454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/181.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/205.uart_fifo_reset.2808264805 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 96503943204 ps |
| CPU time | 71.3 seconds |
| Started | Oct 02 07:40:58 PM UTC 24 |
| Finished | Oct 02 07:42:11 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808264805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2808264805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/205.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/207.uart_fifo_reset.3390816050 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 24730925153 ps |
| CPU time | 17.39 seconds |
| Started | Oct 02 07:41:05 PM UTC 24 |
| Finished | Oct 02 07:41:24 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390816050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3390816050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/207.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1427711873 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 63900911270 ps |
| CPU time | 131.45 seconds |
| Started | Oct 02 07:41:55 PM UTC 24 |
| Finished | Oct 02 07:44:09 PM UTC 24 |
| Peak memory | 209444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427711873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1427711873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/243.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/251.uart_fifo_reset.2475084973 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 134065470192 ps |
| CPU time | 66.57 seconds |
| Started | Oct 02 07:42:05 PM UTC 24 |
| Finished | Oct 02 07:43:13 PM UTC 24 |
| Peak memory | 209384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475084973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2475084973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/251.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/255.uart_fifo_reset.3072634782 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 61942664220 ps |
| CPU time | 80.32 seconds |
| Started | Oct 02 07:42:09 PM UTC 24 |
| Finished | Oct 02 07:43:32 PM UTC 24 |
| Peak memory | 204100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072634782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3072634782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/255.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/268.uart_fifo_reset.1414907490 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 97070044384 ps |
| CPU time | 208.62 seconds |
| Started | Oct 02 07:42:26 PM UTC 24 |
| Finished | Oct 02 07:45:58 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414907490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1414907490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/268.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/277.uart_fifo_reset.277005012 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 82706976534 ps |
| CPU time | 157.49 seconds |
| Started | Oct 02 07:42:42 PM UTC 24 |
| Finished | Oct 02 07:45:22 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277005012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.277005012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/277.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.484475078 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 47465706 ps |
| CPU time | 1.02 seconds |
| Started | Oct 02 07:43:26 PM UTC 24 |
| Finished | Oct 02 07:43:28 PM UTC 24 |
| Peak memory | 201640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484475078 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.484475078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.602305350 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 132249496 ps |
| CPU time | 2.36 seconds |
| Started | Oct 02 07:43:26 PM UTC 24 |
| Finished | Oct 02 07:43:29 PM UTC 24 |
| Peak memory | 202580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602305350 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.602305350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.1479233825 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 17348638 ps |
| CPU time | 1 seconds |
| Started | Oct 02 07:43:24 PM UTC 24 |
| Finished | Oct 02 07:43:26 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479233825 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1479233825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.4152384623 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 23702074 ps |
| CPU time | 1.04 seconds |
| Started | Oct 02 07:43:27 PM UTC 24 |
| Finished | Oct 02 07:43:29 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4152384623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_r eset.4152384623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.631816948 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 15295122 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 07:43:26 PM UTC 24 |
| Finished | Oct 02 07:43:28 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631816948 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.631816948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.1579357533 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 48277382 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 07:43:21 PM UTC 24 |
| Finished | Oct 02 07:43:23 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579357533 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1579357533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.2544853548 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 23666250 ps |
| CPU time | 1.1 seconds |
| Started | Oct 02 07:43:26 PM UTC 24 |
| Finished | Oct 02 07:43:28 PM UTC 24 |
| Peak memory | 203748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544853548 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.2544853548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2400589088 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 40607887 ps |
| CPU time | 1.29 seconds |
| Started | Oct 02 07:43:18 PM UTC 24 |
| Finished | Oct 02 07:43:21 PM UTC 24 |
| Peak memory | 202044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400589088 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2400589088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.3592142404 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 17853417 ps |
| CPU time | 1.2 seconds |
| Started | Oct 02 07:43:29 PM UTC 24 |
| Finished | Oct 02 07:43:32 PM UTC 24 |
| Peak memory | 201300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592142404 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3592142404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3790720197 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 217739938 ps |
| CPU time | 2.91 seconds |
| Started | Oct 02 07:43:29 PM UTC 24 |
| Finished | Oct 02 07:43:34 PM UTC 24 |
| Peak memory | 202636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790720197 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3790720197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.4254828196 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 16512448 ps |
| CPU time | 0.92 seconds |
| Started | Oct 02 07:43:28 PM UTC 24 |
| Finished | Oct 02 07:43:30 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254828196 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.4254828196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.297623017 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 26181251 ps |
| CPU time | 1.71 seconds |
| Started | Oct 02 07:43:31 PM UTC 24 |
| Finished | Oct 02 07:43:33 PM UTC 24 |
| Peak memory | 201724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=297623017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_re set.297623017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.2430322344 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 11751372 ps |
| CPU time | 0.99 seconds |
| Started | Oct 02 07:43:29 PM UTC 24 |
| Finished | Oct 02 07:43:32 PM UTC 24 |
| Peak memory | 201264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430322344 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2430322344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.505249717 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 22249471 ps |
| CPU time | 0.87 seconds |
| Started | Oct 02 07:43:28 PM UTC 24 |
| Finished | Oct 02 07:43:30 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505249717 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.505249717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.3158373846 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 103633003 ps |
| CPU time | 1.22 seconds |
| Started | Oct 02 07:43:31 PM UTC 24 |
| Finished | Oct 02 07:43:33 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158373846 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.3158373846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.3277513183 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 58499338 ps |
| CPU time | 1.86 seconds |
| Started | Oct 02 07:43:27 PM UTC 24 |
| Finished | Oct 02 07:43:30 PM UTC 24 |
| Peak memory | 201760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277513183 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3277513183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2399288062 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 370917775 ps |
| CPU time | 1.48 seconds |
| Started | Oct 02 07:43:28 PM UTC 24 |
| Finished | Oct 02 07:43:31 PM UTC 24 |
| Peak memory | 201716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399288062 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2399288062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3046505578 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 239687633 ps |
| CPU time | 1.19 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3046505578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_ reset.3046505578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.880276856 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 14289642 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880276856 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.880276856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.1566594184 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 16994348 ps |
| CPU time | 0.7 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:49 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566594184 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1566594184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.2537705997 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 17674777 ps |
| CPU time | 0.99 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537705997 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.2537705997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1568474041 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 89603560 ps |
| CPU time | 1.9 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 203444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568474041 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1568474041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.3763791950 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 69367230 ps |
| CPU time | 1.78 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763791950 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3763791950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1673512256 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 64892194 ps |
| CPU time | 1.37 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1673512256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_ reset.1673512256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.1459461742 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 52401824 ps |
| CPU time | 0.84 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459461742 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1459461742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.2980513850 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 17764940 ps |
| CPU time | 0.9 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980513850 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2980513850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.4206256903 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 47905453 ps |
| CPU time | 0.85 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206256903 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.4206256903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2033524642 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 65420499 ps |
| CPU time | 1.84 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:51 PM UTC 24 |
| Peak memory | 203764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033524642 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2033524642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2819706504 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 24042122 ps |
| CPU time | 1.23 seconds |
| Started | Oct 02 07:43:51 PM UTC 24 |
| Finished | Oct 02 07:43:53 PM UTC 24 |
| Peak memory | 203704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2819706504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_ reset.2819706504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.1220135425 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 63013693 ps |
| CPU time | 0.71 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 201228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220135425 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1220135425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.474496335 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 39232514 ps |
| CPU time | 0.59 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474496335 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.474496335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.133420467 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 75827888 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 201640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133420467 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.133420467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.3457693435 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 165666985 ps |
| CPU time | 2.2 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:51 PM UTC 24 |
| Peak memory | 204256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457693435 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3457693435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.4011680408 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 725079783 ps |
| CPU time | 1.46 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:51 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011680408 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.4011680408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.240514150 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 53338562 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 07:43:51 PM UTC 24 |
| Finished | Oct 02 07:43:53 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=240514150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_r eset.240514150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.288802578 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 18442175 ps |
| CPU time | 0.67 seconds |
| Started | Oct 02 07:43:51 PM UTC 24 |
| Finished | Oct 02 07:43:52 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288802578 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.288802578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.4063702450 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 13266875 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 07:43:51 PM UTC 24 |
| Finished | Oct 02 07:43:53 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063702450 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.4063702450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2093320271 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 103945911 ps |
| CPU time | 0.84 seconds |
| Started | Oct 02 07:43:51 PM UTC 24 |
| Finished | Oct 02 07:43:53 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093320271 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.2093320271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.3902036944 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 94554124 ps |
| CPU time | 2.08 seconds |
| Started | Oct 02 07:43:51 PM UTC 24 |
| Finished | Oct 02 07:43:54 PM UTC 24 |
| Peak memory | 204684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902036944 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3902036944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.3976618443 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 187653861 ps |
| CPU time | 1.14 seconds |
| Started | Oct 02 07:43:51 PM UTC 24 |
| Finished | Oct 02 07:43:53 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976618443 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3976618443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.574718928 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 14933926 ps |
| CPU time | 0.85 seconds |
| Started | Oct 02 07:43:54 PM UTC 24 |
| Finished | Oct 02 07:43:56 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=574718928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_r eset.574718928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.547482261 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 46602770 ps |
| CPU time | 0.73 seconds |
| Started | Oct 02 07:43:51 PM UTC 24 |
| Finished | Oct 02 07:43:53 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547482261 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.547482261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1005383489 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 24435053 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 07:43:51 PM UTC 24 |
| Finished | Oct 02 07:43:53 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005383489 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1005383489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1607262479 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 27076797 ps |
| CPU time | 1.01 seconds |
| Started | Oct 02 07:43:51 PM UTC 24 |
| Finished | Oct 02 07:43:53 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607262479 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.1607262479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.3616897194 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 91995613 ps |
| CPU time | 1.95 seconds |
| Started | Oct 02 07:43:51 PM UTC 24 |
| Finished | Oct 02 07:43:54 PM UTC 24 |
| Peak memory | 201760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616897194 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3616897194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.1648721462 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 55888516 ps |
| CPU time | 1.03 seconds |
| Started | Oct 02 07:43:51 PM UTC 24 |
| Finished | Oct 02 07:43:53 PM UTC 24 |
| Peak memory | 201820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648721462 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1648721462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2222916724 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 23303534 ps |
| CPU time | 1.23 seconds |
| Started | Oct 02 07:43:54 PM UTC 24 |
| Finished | Oct 02 07:43:57 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2222916724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_ reset.2222916724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.532563477 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 16676037 ps |
| CPU time | 0.59 seconds |
| Started | Oct 02 07:43:54 PM UTC 24 |
| Finished | Oct 02 07:43:56 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532563477 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.532563477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.629634449 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 12965813 ps |
| CPU time | 0.66 seconds |
| Started | Oct 02 07:43:54 PM UTC 24 |
| Finished | Oct 02 07:43:56 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629634449 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.629634449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.1833239857 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 48846952 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 07:43:54 PM UTC 24 |
| Finished | Oct 02 07:43:56 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833239857 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.1833239857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.2102494345 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 72497462 ps |
| CPU time | 1.85 seconds |
| Started | Oct 02 07:43:54 PM UTC 24 |
| Finished | Oct 02 07:43:57 PM UTC 24 |
| Peak memory | 201720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102494345 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2102494345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.3329690847 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 539927778 ps |
| CPU time | 1.52 seconds |
| Started | Oct 02 07:43:54 PM UTC 24 |
| Finished | Oct 02 07:43:57 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329690847 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3329690847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2244570509 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 91635785 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 07:43:55 PM UTC 24 |
| Finished | Oct 02 07:43:56 PM UTC 24 |
| Peak memory | 201736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2244570509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_ reset.2244570509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.2248420314 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 22072644 ps |
| CPU time | 0.83 seconds |
| Started | Oct 02 07:43:54 PM UTC 24 |
| Finished | Oct 02 07:43:56 PM UTC 24 |
| Peak memory | 201604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248420314 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2248420314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.587064177 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 22507352 ps |
| CPU time | 0.81 seconds |
| Started | Oct 02 07:43:54 PM UTC 24 |
| Finished | Oct 02 07:43:56 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587064177 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.587064177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.2182629465 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 47104525 ps |
| CPU time | 0.9 seconds |
| Started | Oct 02 07:43:54 PM UTC 24 |
| Finished | Oct 02 07:43:56 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182629465 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.2182629465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.3576051868 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 414693371 ps |
| CPU time | 2.11 seconds |
| Started | Oct 02 07:43:54 PM UTC 24 |
| Finished | Oct 02 07:43:58 PM UTC 24 |
| Peak memory | 204792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576051868 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3576051868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.2026802172 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 51076756 ps |
| CPU time | 1.36 seconds |
| Started | Oct 02 07:43:54 PM UTC 24 |
| Finished | Oct 02 07:43:57 PM UTC 24 |
| Peak memory | 201824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026802172 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2026802172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.358375430 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 76592900 ps |
| CPU time | 0.84 seconds |
| Started | Oct 02 07:43:55 PM UTC 24 |
| Finished | Oct 02 07:43:57 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=358375430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_r eset.358375430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2836487796 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 36561443 ps |
| CPU time | 0.72 seconds |
| Started | Oct 02 07:43:55 PM UTC 24 |
| Finished | Oct 02 07:43:56 PM UTC 24 |
| Peak memory | 201596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836487796 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2836487796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.2838630648 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 50596437 ps |
| CPU time | 0.76 seconds |
| Started | Oct 02 07:43:55 PM UTC 24 |
| Finished | Oct 02 07:43:56 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838630648 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2838630648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.3002961678 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 83139379 ps |
| CPU time | 0.92 seconds |
| Started | Oct 02 07:43:55 PM UTC 24 |
| Finished | Oct 02 07:43:57 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002961678 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.3002961678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.2713371727 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 78045381 ps |
| CPU time | 1.81 seconds |
| Started | Oct 02 07:43:55 PM UTC 24 |
| Finished | Oct 02 07:43:57 PM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713371727 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2713371727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.2771867435 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 165773535 ps |
| CPU time | 1.17 seconds |
| Started | Oct 02 07:43:55 PM UTC 24 |
| Finished | Oct 02 07:43:57 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771867435 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2771867435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.464841137 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 21657191 ps |
| CPU time | 1.11 seconds |
| Started | Oct 02 07:43:58 PM UTC 24 |
| Finished | Oct 02 07:44:00 PM UTC 24 |
| Peak memory | 203752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=464841137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_r eset.464841137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.2066347209 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 16207047 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 07:43:57 PM UTC 24 |
| Finished | Oct 02 07:43:59 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066347209 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2066347209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.2332158302 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 61268149 ps |
| CPU time | 0.63 seconds |
| Started | Oct 02 07:43:57 PM UTC 24 |
| Finished | Oct 02 07:43:59 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332158302 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2332158302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.4251275865 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 13452708 ps |
| CPU time | 0.76 seconds |
| Started | Oct 02 07:43:57 PM UTC 24 |
| Finished | Oct 02 07:43:59 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251275865 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.4251275865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.4271160593 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 184489164 ps |
| CPU time | 1.84 seconds |
| Started | Oct 02 07:43:55 PM UTC 24 |
| Finished | Oct 02 07:43:58 PM UTC 24 |
| Peak memory | 201716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271160593 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.4271160593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.3200184330 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 44653843 ps |
| CPU time | 1.1 seconds |
| Started | Oct 02 07:43:57 PM UTC 24 |
| Finished | Oct 02 07:43:59 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200184330 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3200184330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3109083571 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 54435522 ps |
| CPU time | 0.83 seconds |
| Started | Oct 02 07:43:58 PM UTC 24 |
| Finished | Oct 02 07:44:00 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3109083571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_ reset.3109083571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.42115318 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 46125889 ps |
| CPU time | 0.76 seconds |
| Started | Oct 02 07:43:58 PM UTC 24 |
| Finished | Oct 02 07:43:59 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42115318 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.42115318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.1297646549 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 30524629 ps |
| CPU time | 0.73 seconds |
| Started | Oct 02 07:43:58 PM UTC 24 |
| Finished | Oct 02 07:43:59 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297646549 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1297646549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2749132932 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 26640298 ps |
| CPU time | 0.79 seconds |
| Started | Oct 02 07:43:58 PM UTC 24 |
| Finished | Oct 02 07:44:00 PM UTC 24 |
| Peak memory | 203748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749132932 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.2749132932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.338010137 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 144784504 ps |
| CPU time | 2.9 seconds |
| Started | Oct 02 07:43:58 PM UTC 24 |
| Finished | Oct 02 07:44:01 PM UTC 24 |
| Peak memory | 202636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338010137 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.338010137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.3881477688 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 184050926 ps |
| CPU time | 1.33 seconds |
| Started | Oct 02 07:43:58 PM UTC 24 |
| Finished | Oct 02 07:44:00 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881477688 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3881477688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3009091423 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 32759808 ps |
| CPU time | 0.94 seconds |
| Started | Oct 02 07:43:33 PM UTC 24 |
| Finished | Oct 02 07:43:35 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009091423 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3009091423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.3887391354 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 116795853 ps |
| CPU time | 1.95 seconds |
| Started | Oct 02 07:43:33 PM UTC 24 |
| Finished | Oct 02 07:43:36 PM UTC 24 |
| Peak memory | 201780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887391354 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3887391354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.1068492018 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 17456041 ps |
| CPU time | 0.9 seconds |
| Started | Oct 02 07:43:32 PM UTC 24 |
| Finished | Oct 02 07:43:34 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068492018 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1068492018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.15112551 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 31062224 ps |
| CPU time | 1.33 seconds |
| Started | Oct 02 07:43:35 PM UTC 24 |
| Finished | Oct 02 07:43:37 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=15112551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.15112551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3417856845 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 18927727 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 07:43:33 PM UTC 24 |
| Finished | Oct 02 07:43:35 PM UTC 24 |
| Peak memory | 201640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417856845 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3417856845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.3714080281 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 18606615 ps |
| CPU time | 0.76 seconds |
| Started | Oct 02 07:43:32 PM UTC 24 |
| Finished | Oct 02 07:43:34 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714080281 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3714080281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.378703131 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 49425326 ps |
| CPU time | 0.96 seconds |
| Started | Oct 02 07:43:33 PM UTC 24 |
| Finished | Oct 02 07:43:35 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378703131 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.378703131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.2523631889 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 131130217 ps |
| CPU time | 2.12 seconds |
| Started | Oct 02 07:43:31 PM UTC 24 |
| Finished | Oct 02 07:43:34 PM UTC 24 |
| Peak memory | 204792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523631889 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2523631889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.4150114471 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 34740431 ps |
| CPU time | 0.58 seconds |
| Started | Oct 02 07:43:58 PM UTC 24 |
| Finished | Oct 02 07:43:59 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150114471 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.4150114471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.597136285 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 19884715 ps |
| CPU time | 0.66 seconds |
| Started | Oct 02 07:43:58 PM UTC 24 |
| Finished | Oct 02 07:44:00 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597136285 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.597136285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1209864315 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 32202939 ps |
| CPU time | 0.7 seconds |
| Started | Oct 02 07:43:58 PM UTC 24 |
| Finished | Oct 02 07:44:00 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209864315 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1209864315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1188482498 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 39719062 ps |
| CPU time | 0.62 seconds |
| Started | Oct 02 07:43:58 PM UTC 24 |
| Finished | Oct 02 07:44:00 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188482498 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1188482498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.1475865011 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 23077203 ps |
| CPU time | 0.66 seconds |
| Started | Oct 02 07:43:58 PM UTC 24 |
| Finished | Oct 02 07:44:00 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475865011 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1475865011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.2537421755 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 18763730 ps |
| CPU time | 0.66 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 200744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537421755 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2537421755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.3036900696 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 18610381 ps |
| CPU time | 0.72 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036900696 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3036900696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.1714327365 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 50557745 ps |
| CPU time | 0.61 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714327365 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1714327365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.2620117835 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 16938197 ps |
| CPU time | 0.73 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620117835 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2620117835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.3060798270 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 36147473 ps |
| CPU time | 0.6 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060798270 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3060798270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.560113934 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 17813779 ps |
| CPU time | 1.01 seconds |
| Started | Oct 02 07:43:35 PM UTC 24 |
| Finished | Oct 02 07:43:37 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560113934 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.560113934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2400439286 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 68189671 ps |
| CPU time | 1.62 seconds |
| Started | Oct 02 07:43:35 PM UTC 24 |
| Finished | Oct 02 07:43:38 PM UTC 24 |
| Peak memory | 201828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400439286 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2400439286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.3320283846 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 48488975 ps |
| CPU time | 0.94 seconds |
| Started | Oct 02 07:43:35 PM UTC 24 |
| Finished | Oct 02 07:43:37 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320283846 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3320283846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.235144026 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 20506093 ps |
| CPU time | 1.41 seconds |
| Started | Oct 02 07:43:36 PM UTC 24 |
| Finished | Oct 02 07:43:39 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=235144026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_re set.235144026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2660085545 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 14733799 ps |
| CPU time | 0.99 seconds |
| Started | Oct 02 07:43:35 PM UTC 24 |
| Finished | Oct 02 07:43:37 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660085545 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2660085545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.645467053 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 23365625 ps |
| CPU time | 0.9 seconds |
| Started | Oct 02 07:43:35 PM UTC 24 |
| Finished | Oct 02 07:43:37 PM UTC 24 |
| Peak memory | 201632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645467053 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.645467053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.268342260 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 288184399 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 07:43:36 PM UTC 24 |
| Finished | Oct 02 07:43:38 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268342260 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.268342260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.874129998 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 85405650 ps |
| CPU time | 1.27 seconds |
| Started | Oct 02 07:43:35 PM UTC 24 |
| Finished | Oct 02 07:43:37 PM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874129998 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.874129998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.1482533811 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 85671438 ps |
| CPU time | 1.98 seconds |
| Started | Oct 02 07:43:35 PM UTC 24 |
| Finished | Oct 02 07:43:38 PM UTC 24 |
| Peak memory | 201716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482533811 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1482533811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.675046879 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 14044236 ps |
| CPU time | 0.73 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675046879 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.675046879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.349160902 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 40652464 ps |
| CPU time | 0.74 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349160902 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.349160902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.4004743692 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 27973531 ps |
| CPU time | 0.6 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004743692 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4004743692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.4145084984 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 130126914 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145084984 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.4145084984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.260114977 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 12211157 ps |
| CPU time | 0.81 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260114977 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.260114977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.364413208 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 25308120 ps |
| CPU time | 0.71 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364413208 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.364413208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.1312530610 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 34827626 ps |
| CPU time | 0.68 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312530610 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1312530610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2728330569 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 17106574 ps |
| CPU time | 0.72 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728330569 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2728330569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.658951777 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 37624083 ps |
| CPU time | 0.61 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658951777 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.658951777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3238559432 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 11010714 ps |
| CPU time | 0.7 seconds |
| Started | Oct 02 07:44:01 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238559432 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3238559432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.3102315915 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 53106846 ps |
| CPU time | 1.11 seconds |
| Started | Oct 02 07:43:38 PM UTC 24 |
| Finished | Oct 02 07:43:40 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102315915 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3102315915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.3674053266 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 1648065062 ps |
| CPU time | 3.54 seconds |
| Started | Oct 02 07:43:38 PM UTC 24 |
| Finished | Oct 02 07:43:43 PM UTC 24 |
| Peak memory | 202764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674053266 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3674053266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.1734450834 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 43634257 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 07:43:38 PM UTC 24 |
| Finished | Oct 02 07:43:40 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734450834 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1734450834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3828119570 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 26211106 ps |
| CPU time | 1.12 seconds |
| Started | Oct 02 07:43:38 PM UTC 24 |
| Finished | Oct 02 07:43:40 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3828119570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_r eset.3828119570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.1557406425 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 28826360 ps |
| CPU time | 0.96 seconds |
| Started | Oct 02 07:43:38 PM UTC 24 |
| Finished | Oct 02 07:43:40 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557406425 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1557406425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.2998437329 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 25708809 ps |
| CPU time | 0.84 seconds |
| Started | Oct 02 07:43:38 PM UTC 24 |
| Finished | Oct 02 07:43:40 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998437329 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2998437329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2635191623 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 37493170 ps |
| CPU time | 0.83 seconds |
| Started | Oct 02 07:43:38 PM UTC 24 |
| Finished | Oct 02 07:43:40 PM UTC 24 |
| Peak memory | 201640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635191623 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.2635191623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.2356431316 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 370211030 ps |
| CPU time | 2.18 seconds |
| Started | Oct 02 07:43:36 PM UTC 24 |
| Finished | Oct 02 07:43:40 PM UTC 24 |
| Peak memory | 202680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356431316 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2356431316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.4021990195 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 162538907 ps |
| CPU time | 1.26 seconds |
| Started | Oct 02 07:43:38 PM UTC 24 |
| Finished | Oct 02 07:43:40 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021990195 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.4021990195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.508485931 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 28435763 ps |
| CPU time | 0.7 seconds |
| Started | Oct 02 07:44:02 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508485931 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.508485931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.1004950127 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 37101962 ps |
| CPU time | 0.79 seconds |
| Started | Oct 02 07:44:02 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004950127 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1004950127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.48666704 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 49276574 ps |
| CPU time | 0.64 seconds |
| Started | Oct 02 07:44:02 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48666704 -assert nopostproc +UVM_TESTNAME=uart_base_te st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.48666704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.3737229037 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 47300025 ps |
| CPU time | 0.61 seconds |
| Started | Oct 02 07:44:02 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737229037 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3737229037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.37761322 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 12830737 ps |
| CPU time | 0.65 seconds |
| Started | Oct 02 07:44:02 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37761322 -assert nopostproc +UVM_TESTNAME=uart_base_te st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.37761322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.3205370348 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 14718380 ps |
| CPU time | 0.76 seconds |
| Started | Oct 02 07:44:02 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205370348 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3205370348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.2566544471 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 13643106 ps |
| CPU time | 0.65 seconds |
| Started | Oct 02 07:44:02 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566544471 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2566544471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.2429152794 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 41932002 ps |
| CPU time | 0.56 seconds |
| Started | Oct 02 07:44:02 PM UTC 24 |
| Finished | Oct 02 07:44:03 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429152794 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2429152794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.1929116828 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 15405243 ps |
| CPU time | 0.64 seconds |
| Started | Oct 02 07:44:02 PM UTC 24 |
| Finished | Oct 02 07:44:04 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929116828 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1929116828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.383875207 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 136702121 ps |
| CPU time | 0.56 seconds |
| Started | Oct 02 07:44:05 PM UTC 24 |
| Finished | Oct 02 07:44:06 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383875207 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.383875207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1360847440 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 38540231 ps |
| CPU time | 1.18 seconds |
| Started | Oct 02 07:43:40 PM UTC 24 |
| Finished | Oct 02 07:43:42 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1360847440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_r eset.1360847440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.1885285135 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 30743790 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 07:43:40 PM UTC 24 |
| Finished | Oct 02 07:43:42 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885285135 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1885285135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.4104040100 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 20134486 ps |
| CPU time | 1.15 seconds |
| Started | Oct 02 07:43:40 PM UTC 24 |
| Finished | Oct 02 07:43:42 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104040100 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.4104040100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.3102844293 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 36151606 ps |
| CPU time | 1.6 seconds |
| Started | Oct 02 07:43:40 PM UTC 24 |
| Finished | Oct 02 07:43:42 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102844293 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3102844293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.4233259663 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 288052414 ps |
| CPU time | 1.72 seconds |
| Started | Oct 02 07:43:40 PM UTC 24 |
| Finished | Oct 02 07:43:43 PM UTC 24 |
| Peak memory | 201720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233259663 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.4233259663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1446905190 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 54976510 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 07:43:42 PM UTC 24 |
| Finished | Oct 02 07:43:44 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1446905190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_r eset.1446905190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.2233617304 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 11005285 ps |
| CPU time | 0.78 seconds |
| Started | Oct 02 07:43:42 PM UTC 24 |
| Finished | Oct 02 07:43:44 PM UTC 24 |
| Peak memory | 201640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233617304 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2233617304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.579242566 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 17057151 ps |
| CPU time | 0.74 seconds |
| Started | Oct 02 07:43:42 PM UTC 24 |
| Finished | Oct 02 07:43:44 PM UTC 24 |
| Peak memory | 201632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579242566 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.579242566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.727410577 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 74350369 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 07:43:42 PM UTC 24 |
| Finished | Oct 02 07:43:44 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727410577 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.727410577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.2733191600 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 54266420 ps |
| CPU time | 1.68 seconds |
| Started | Oct 02 07:43:40 PM UTC 24 |
| Finished | Oct 02 07:43:43 PM UTC 24 |
| Peak memory | 201716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733191600 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2733191600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.357534643 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 52052805 ps |
| CPU time | 1.12 seconds |
| Started | Oct 02 07:43:42 PM UTC 24 |
| Finished | Oct 02 07:43:44 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357534643 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.357534643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2386896376 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 22488283 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 07:43:44 PM UTC 24 |
| Finished | Oct 02 07:43:46 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2386896376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_r eset.2386896376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.1426290486 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 70202019 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 07:43:42 PM UTC 24 |
| Finished | Oct 02 07:43:44 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426290486 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1426290486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.3295028942 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 24547315 ps |
| CPU time | 0.87 seconds |
| Started | Oct 02 07:43:42 PM UTC 24 |
| Finished | Oct 02 07:43:44 PM UTC 24 |
| Peak memory | 201576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295028942 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3295028942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.1578604761 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 22308081 ps |
| CPU time | 0.81 seconds |
| Started | Oct 02 07:43:44 PM UTC 24 |
| Finished | Oct 02 07:43:46 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578604761 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.1578604761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.1628638957 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 39471763 ps |
| CPU time | 1.17 seconds |
| Started | Oct 02 07:43:42 PM UTC 24 |
| Finished | Oct 02 07:43:44 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628638957 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1628638957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.3799349199 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 144022078 ps |
| CPU time | 1.08 seconds |
| Started | Oct 02 07:43:42 PM UTC 24 |
| Finished | Oct 02 07:43:44 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799349199 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3799349199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1347748617 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 31326193 ps |
| CPU time | 1.05 seconds |
| Started | Oct 02 07:43:45 PM UTC 24 |
| Finished | Oct 02 07:43:47 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1347748617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_r eset.1347748617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.475505802 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 45075884 ps |
| CPU time | 0.54 seconds |
| Started | Oct 02 07:43:44 PM UTC 24 |
| Finished | Oct 02 07:43:46 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475505802 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.475505802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.2521714129 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 11507730 ps |
| CPU time | 0.67 seconds |
| Started | Oct 02 07:43:44 PM UTC 24 |
| Finished | Oct 02 07:43:46 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521714129 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2521714129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.4160032370 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 19218846 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 07:43:45 PM UTC 24 |
| Finished | Oct 02 07:43:46 PM UTC 24 |
| Peak memory | 201704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160032370 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.4160032370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.638536883 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 475051956 ps |
| CPU time | 2.33 seconds |
| Started | Oct 02 07:43:44 PM UTC 24 |
| Finished | Oct 02 07:43:48 PM UTC 24 |
| Peak memory | 202628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638536883 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.638536883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3643756064 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 154178590 ps |
| CPU time | 1.31 seconds |
| Started | Oct 02 07:43:44 PM UTC 24 |
| Finished | Oct 02 07:43:47 PM UTC 24 |
| Peak memory | 201760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643756064 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3643756064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3645003228 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 71249226 ps |
| CPU time | 1.03 seconds |
| Started | Oct 02 07:43:48 PM UTC 24 |
| Finished | Oct 02 07:43:50 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3645003228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_r eset.3645003228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.711294423 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 145327772 ps |
| CPU time | 0.65 seconds |
| Started | Oct 02 07:43:45 PM UTC 24 |
| Finished | Oct 02 07:43:47 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711294423 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.711294423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.1347289273 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 19047292 ps |
| CPU time | 0.61 seconds |
| Started | Oct 02 07:43:45 PM UTC 24 |
| Finished | Oct 02 07:43:46 PM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347289273 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1347289273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.2039080064 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 48141777 ps |
| CPU time | 0.74 seconds |
| Started | Oct 02 07:43:47 PM UTC 24 |
| Finished | Oct 02 07:43:49 PM UTC 24 |
| Peak memory | 201424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039080064 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.2039080064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.2984739372 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 106821930 ps |
| CPU time | 2.12 seconds |
| Started | Oct 02 07:43:45 PM UTC 24 |
| Finished | Oct 02 07:43:48 PM UTC 24 |
| Peak memory | 204664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984739372 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2984739372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.2007637220 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 199365247 ps |
| CPU time | 1.29 seconds |
| Started | Oct 02 07:43:45 PM UTC 24 |
| Finished | Oct 02 07:43:47 PM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007637220 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2007637220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.127757393 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 109820795979 ps |
| CPU time | 918.06 seconds |
| Started | Oct 02 07:06:42 PM UTC 24 |
| Finished | Oct 02 07:22:18 PM UTC 24 |
| Peak memory | 212652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127757393 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.127757393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_loopback.3990051366 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 8316054354 ps |
| CPU time | 22.6 seconds |
| Started | Oct 02 07:06:39 PM UTC 24 |
| Finished | Oct 02 07:07:33 PM UTC 24 |
| Peak memory | 203708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990051366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3990051366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_rx_oversample.3123476253 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 2535011596 ps |
| CPU time | 4.63 seconds |
| Started | Oct 02 07:06:37 PM UTC 24 |
| Finished | Oct 02 07:06:50 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123476253 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3123476253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.910431301 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1760513685 ps |
| CPU time | 1.36 seconds |
| Started | Oct 02 07:06:39 PM UTC 24 |
| Finished | Oct 02 07:07:12 PM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910431301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.910431301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_alert_test.317525257 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 16793764 ps |
| CPU time | 0.53 seconds |
| Started | Oct 02 07:07:03 PM UTC 24 |
| Finished | Oct 02 07:07:05 PM UTC 24 |
| Peak memory | 203192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317525257 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.317525257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_fifo_full.1749234130 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 61825943578 ps |
| CPU time | 59.1 seconds |
| Started | Oct 02 07:06:51 PM UTC 24 |
| Finished | Oct 02 07:07:55 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749234130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1749234130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_fifo_reset.1172858517 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 20319159595 ps |
| CPU time | 41.38 seconds |
| Started | Oct 02 07:06:52 PM UTC 24 |
| Finished | Oct 02 07:07:42 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172858517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1172858517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_intr.1772147925 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 21071872619 ps |
| CPU time | 14.95 seconds |
| Started | Oct 02 07:06:53 PM UTC 24 |
| Finished | Oct 02 07:07:09 PM UTC 24 |
| Peak memory | 209132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772147925 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1772147925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_loopback.3840785917 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6871344676 ps |
| CPU time | 15.41 seconds |
| Started | Oct 02 07:07:01 PM UTC 24 |
| Finished | Oct 02 07:07:20 PM UTC 24 |
| Peak memory | 203908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840785917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3840785917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_perf.724546851 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4064577913 ps |
| CPU time | 56.01 seconds |
| Started | Oct 02 07:07:01 PM UTC 24 |
| Finished | Oct 02 07:08:01 PM UTC 24 |
| Peak memory | 203704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724546851 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.724546851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_rx_oversample.3140256285 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1627863276 ps |
| CPU time | 1.7 seconds |
| Started | Oct 02 07:06:52 PM UTC 24 |
| Finished | Oct 02 07:07:02 PM UTC 24 |
| Peak memory | 203328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140256285 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3140256285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.3878246906 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 31918008119 ps |
| CPU time | 9.63 seconds |
| Started | Oct 02 07:07:01 PM UTC 24 |
| Finished | Oct 02 07:07:14 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878246906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3878246906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.1378538608 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4979127967 ps |
| CPU time | 3.74 seconds |
| Started | Oct 02 07:06:56 PM UTC 24 |
| Finished | Oct 02 07:07:08 PM UTC 24 |
| Peak memory | 203516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378538608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1378538608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_sec_cm.100033971 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 216370339 ps |
| CPU time | 0.8 seconds |
| Started | Oct 02 07:07:02 PM UTC 24 |
| Finished | Oct 02 07:07:10 PM UTC 24 |
| Peak memory | 237812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100033971 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.100033971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_smoke.3108871809 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 5539221898 ps |
| CPU time | 11.21 seconds |
| Started | Oct 02 07:06:50 PM UTC 24 |
| Finished | Oct 02 07:07:22 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108871809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3108871809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.1111555119 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 260216922 ps |
| CPU time | 1.24 seconds |
| Started | Oct 02 07:07:01 PM UTC 24 |
| Finished | Oct 02 07:07:06 PM UTC 24 |
| Peak memory | 203440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111555119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1111555119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/1.uart_tx_rx.3726235330 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 93732722334 ps |
| CPU time | 44.41 seconds |
| Started | Oct 02 07:06:51 PM UTC 24 |
| Finished | Oct 02 07:07:40 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726235330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3726235330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/1.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_alert_test.2644208843 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 45438951 ps |
| CPU time | 0.85 seconds |
| Started | Oct 02 07:09:55 PM UTC 24 |
| Finished | Oct 02 07:09:57 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644208843 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2644208843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_fifo_full.1897026368 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 126497080115 ps |
| CPU time | 58.67 seconds |
| Started | Oct 02 07:09:35 PM UTC 24 |
| Finished | Oct 02 07:10:35 PM UTC 24 |
| Peak memory | 204184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897026368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1897026368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.2210376434 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 61301326170 ps |
| CPU time | 45.5 seconds |
| Started | Oct 02 07:09:35 PM UTC 24 |
| Finished | Oct 02 07:10:22 PM UTC 24 |
| Peak memory | 209124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210376434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2210376434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_intr.2287743213 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 28665333421 ps |
| CPU time | 73.48 seconds |
| Started | Oct 02 07:09:37 PM UTC 24 |
| Finished | Oct 02 07:10:52 PM UTC 24 |
| Peak memory | 203980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287743213 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2287743213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.730821191 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 120055124159 ps |
| CPU time | 1054.61 seconds |
| Started | Oct 02 07:09:43 PM UTC 24 |
| Finished | Oct 02 07:27:30 PM UTC 24 |
| Peak memory | 212580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730821191 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.730821191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_loopback.997600501 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 10807661362 ps |
| CPU time | 48.51 seconds |
| Started | Oct 02 07:09:41 PM UTC 24 |
| Finished | Oct 02 07:10:32 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997600501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 10.uart_loopback.997600501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_noise_filter.1704588378 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 195032764579 ps |
| CPU time | 91.42 seconds |
| Started | Oct 02 07:09:38 PM UTC 24 |
| Finished | Oct 02 07:11:12 PM UTC 24 |
| Peak memory | 220488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704588378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1704588378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_perf.3947748031 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 14801469780 ps |
| CPU time | 318.02 seconds |
| Started | Oct 02 07:09:41 PM UTC 24 |
| Finished | Oct 02 07:15:04 PM UTC 24 |
| Peak memory | 203908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947748031 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3947748031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_rx_oversample.563336059 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 6501702470 ps |
| CPU time | 30.5 seconds |
| Started | Oct 02 07:09:36 PM UTC 24 |
| Finished | Oct 02 07:10:08 PM UTC 24 |
| Peak memory | 208412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563336059 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.563336059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.3309145235 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 41745823315 ps |
| CPU time | 18.48 seconds |
| Started | Oct 02 07:09:40 PM UTC 24 |
| Finished | Oct 02 07:10:00 PM UTC 24 |
| Peak memory | 209224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309145235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3309145235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.2476707422 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 37069701100 ps |
| CPU time | 15.78 seconds |
| Started | Oct 02 07:09:39 PM UTC 24 |
| Finished | Oct 02 07:09:56 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476707422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2476707422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_smoke.174534253 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 451584090 ps |
| CPU time | 3.69 seconds |
| Started | Oct 02 07:09:28 PM UTC 24 |
| Finished | Oct 02 07:09:33 PM UTC 24 |
| Peak memory | 203976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174534253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 10.uart_smoke.174534253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_stress_all.3727144329 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 12718365416 ps |
| CPU time | 20.82 seconds |
| Started | Oct 02 07:09:51 PM UTC 24 |
| Finished | Oct 02 07:10:13 PM UTC 24 |
| Peak memory | 204092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727144329 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3727144329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.1337692935 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 12144022718 ps |
| CPU time | 35.05 seconds |
| Started | Oct 02 07:09:41 PM UTC 24 |
| Finished | Oct 02 07:10:18 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337692935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1337692935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_tx_rx.2820397628 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 70917654186 ps |
| CPU time | 60.32 seconds |
| Started | Oct 02 07:09:32 PM UTC 24 |
| Finished | Oct 02 07:10:34 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820397628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2820397628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/101.uart_fifo_reset.462106167 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 18012810112 ps |
| CPU time | 31.31 seconds |
| Started | Oct 02 07:38:17 PM UTC 24 |
| Finished | Oct 02 07:38:50 PM UTC 24 |
| Peak memory | 209240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462106167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.462106167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/101.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/103.uart_fifo_reset.540782423 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 289548450272 ps |
| CPU time | 29.38 seconds |
| Started | Oct 02 07:38:17 PM UTC 24 |
| Finished | Oct 02 07:38:48 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540782423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.540782423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/103.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/104.uart_fifo_reset.1642165654 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 27981256405 ps |
| CPU time | 25.99 seconds |
| Started | Oct 02 07:38:19 PM UTC 24 |
| Finished | Oct 02 07:38:47 PM UTC 24 |
| Peak memory | 208016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642165654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1642165654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/104.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/105.uart_fifo_reset.3445927986 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 67586965888 ps |
| CPU time | 126.77 seconds |
| Started | Oct 02 07:38:21 PM UTC 24 |
| Finished | Oct 02 07:40:31 PM UTC 24 |
| Peak memory | 209172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445927986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3445927986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/105.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/106.uart_fifo_reset.957490690 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 126063339726 ps |
| CPU time | 80.08 seconds |
| Started | Oct 02 07:38:23 PM UTC 24 |
| Finished | Oct 02 07:39:44 PM UTC 24 |
| Peak memory | 203720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957490690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.957490690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/106.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/107.uart_fifo_reset.1678095352 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 32443683543 ps |
| CPU time | 43.53 seconds |
| Started | Oct 02 07:38:24 PM UTC 24 |
| Finished | Oct 02 07:39:09 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678095352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1678095352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/107.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/109.uart_fifo_reset.1272479105 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 7770079481 ps |
| CPU time | 26.94 seconds |
| Started | Oct 02 07:38:26 PM UTC 24 |
| Finished | Oct 02 07:38:54 PM UTC 24 |
| Peak memory | 203840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272479105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1272479105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/109.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_alert_test.1580780157 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 38674606 ps |
| CPU time | 0.9 seconds |
| Started | Oct 02 07:10:16 PM UTC 24 |
| Finished | Oct 02 07:10:18 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580780157 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1580780157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_fifo_reset.4283963924 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 28183990359 ps |
| CPU time | 58.56 seconds |
| Started | Oct 02 07:09:58 PM UTC 24 |
| Finished | Oct 02 07:10:58 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283963924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.4283963924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_intr.2187124854 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 237870040691 ps |
| CPU time | 304.28 seconds |
| Started | Oct 02 07:10:00 PM UTC 24 |
| Finished | Oct 02 07:15:09 PM UTC 24 |
| Peak memory | 203840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187124854 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2187124854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.4258812193 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 58514722191 ps |
| CPU time | 172.85 seconds |
| Started | Oct 02 07:10:14 PM UTC 24 |
| Finished | Oct 02 07:13:10 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258812193 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.4258812193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_loopback.699577437 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3231170899 ps |
| CPU time | 12.96 seconds |
| Started | Oct 02 07:10:12 PM UTC 24 |
| Finished | Oct 02 07:10:26 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699577437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 11.uart_loopback.699577437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_noise_filter.4142100923 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 103112006707 ps |
| CPU time | 187.68 seconds |
| Started | Oct 02 07:10:07 PM UTC 24 |
| Finished | Oct 02 07:13:17 PM UTC 24 |
| Peak memory | 209928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142100923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.4142100923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_perf.2847463192 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 13313417820 ps |
| CPU time | 400.86 seconds |
| Started | Oct 02 07:10:12 PM UTC 24 |
| Finished | Oct 02 07:16:59 PM UTC 24 |
| Peak memory | 203912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847463192 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2847463192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_rx_oversample.851060841 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2516433716 ps |
| CPU time | 9.82 seconds |
| Started | Oct 02 07:10:00 PM UTC 24 |
| Finished | Oct 02 07:10:11 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851060841 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.851060841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.704463249 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 29796371901 ps |
| CPU time | 60.47 seconds |
| Started | Oct 02 07:10:09 PM UTC 24 |
| Finished | Oct 02 07:11:11 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704463249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.704463249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.3850846517 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 4701237347 ps |
| CPU time | 2.42 seconds |
| Started | Oct 02 07:10:08 PM UTC 24 |
| Finished | Oct 02 07:10:11 PM UTC 24 |
| Peak memory | 203640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850846517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3850846517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_smoke.3644943150 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 304360762 ps |
| CPU time | 2.59 seconds |
| Started | Oct 02 07:09:56 PM UTC 24 |
| Finished | Oct 02 07:10:00 PM UTC 24 |
| Peak memory | 203972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644943150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3644943150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_stress_all.3065197609 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 111583170944 ps |
| CPU time | 39.02 seconds |
| Started | Oct 02 07:10:16 PM UTC 24 |
| Finished | Oct 02 07:10:57 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065197609 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3065197609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.2687341224 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 966251335 ps |
| CPU time | 2.16 seconds |
| Started | Oct 02 07:10:12 PM UTC 24 |
| Finished | Oct 02 07:10:15 PM UTC 24 |
| Peak memory | 203712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687341224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2687341224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/11.uart_tx_rx.1700622119 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 53083841704 ps |
| CPU time | 32.55 seconds |
| Started | Oct 02 07:09:56 PM UTC 24 |
| Finished | Oct 02 07:10:30 PM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700622119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1700622119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/11.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/111.uart_fifo_reset.3378068152 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 23685335846 ps |
| CPU time | 48.58 seconds |
| Started | Oct 02 07:38:29 PM UTC 24 |
| Finished | Oct 02 07:39:19 PM UTC 24 |
| Peak memory | 203908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378068152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3378068152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/111.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/113.uart_fifo_reset.2109390626 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 44460884932 ps |
| CPU time | 26.59 seconds |
| Started | Oct 02 07:38:33 PM UTC 24 |
| Finished | Oct 02 07:39:01 PM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109390626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2109390626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/113.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/114.uart_fifo_reset.3567897338 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 8754525950 ps |
| CPU time | 27.07 seconds |
| Started | Oct 02 07:38:38 PM UTC 24 |
| Finished | Oct 02 07:39:07 PM UTC 24 |
| Peak memory | 204048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567897338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3567897338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/114.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/116.uart_fifo_reset.2009202143 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 89022178669 ps |
| CPU time | 65.81 seconds |
| Started | Oct 02 07:38:46 PM UTC 24 |
| Finished | Oct 02 07:39:54 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009202143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2009202143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/116.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/117.uart_fifo_reset.3285347552 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 25384329121 ps |
| CPU time | 63.3 seconds |
| Started | Oct 02 07:38:47 PM UTC 24 |
| Finished | Oct 02 07:39:52 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285347552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3285347552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/117.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/118.uart_fifo_reset.878618639 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 144809344480 ps |
| CPU time | 71.39 seconds |
| Started | Oct 02 07:38:48 PM UTC 24 |
| Finished | Oct 02 07:40:01 PM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878618639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.878618639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/118.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/119.uart_fifo_reset.3109295757 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 54604438516 ps |
| CPU time | 134.07 seconds |
| Started | Oct 02 07:38:48 PM UTC 24 |
| Finished | Oct 02 07:41:04 PM UTC 24 |
| Peak memory | 204040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109295757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3109295757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/119.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_alert_test.2157565766 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 21431153 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 07:10:36 PM UTC 24 |
| Finished | Oct 02 07:10:38 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157565766 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2157565766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.3104030991 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 115786653675 ps |
| CPU time | 72.95 seconds |
| Started | Oct 02 07:10:21 PM UTC 24 |
| Finished | Oct 02 07:11:35 PM UTC 24 |
| Peak memory | 209596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104030991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3104030991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_fifo_reset.328795709 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 35250717921 ps |
| CPU time | 16.75 seconds |
| Started | Oct 02 07:10:22 PM UTC 24 |
| Finished | Oct 02 07:10:40 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328795709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.328795709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.1282608820 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 173972592045 ps |
| CPU time | 536.97 seconds |
| Started | Oct 02 07:10:33 PM UTC 24 |
| Finished | Oct 02 07:19:37 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282608820 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1282608820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_loopback.1880991983 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 6750609203 ps |
| CPU time | 25.24 seconds |
| Started | Oct 02 07:10:32 PM UTC 24 |
| Finished | Oct 02 07:10:59 PM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880991983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1880991983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_noise_filter.1163130598 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 49641668711 ps |
| CPU time | 54.37 seconds |
| Started | Oct 02 07:10:27 PM UTC 24 |
| Finished | Oct 02 07:11:23 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163130598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1163130598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_perf.2965465721 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 10325418129 ps |
| CPU time | 312.02 seconds |
| Started | Oct 02 07:10:33 PM UTC 24 |
| Finished | Oct 02 07:15:49 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965465721 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2965465721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_rx_oversample.2087446242 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 7651595013 ps |
| CPU time | 45.84 seconds |
| Started | Oct 02 07:10:23 PM UTC 24 |
| Finished | Oct 02 07:11:10 PM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087446242 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2087446242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.4245245119 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 293693712739 ps |
| CPU time | 38.61 seconds |
| Started | Oct 02 07:10:29 PM UTC 24 |
| Finished | Oct 02 07:11:09 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245245119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.4245245119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.2675032703 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 45332234902 ps |
| CPU time | 17.67 seconds |
| Started | Oct 02 07:10:29 PM UTC 24 |
| Finished | Oct 02 07:10:48 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675032703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2675032703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_smoke.2972339200 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 6221696742 ps |
| CPU time | 9.81 seconds |
| Started | Oct 02 07:10:17 PM UTC 24 |
| Finished | Oct 02 07:10:28 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972339200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2972339200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.2555912700 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1124964492 ps |
| CPU time | 12.29 seconds |
| Started | Oct 02 07:10:35 PM UTC 24 |
| Finished | Oct 02 07:10:48 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2555912700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all _with_rand_reset.2555912700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.1309465574 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 990020071 ps |
| CPU time | 4.87 seconds |
| Started | Oct 02 07:10:30 PM UTC 24 |
| Finished | Oct 02 07:10:36 PM UTC 24 |
| Peak memory | 203868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309465574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1309465574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/12.uart_tx_rx.3334426957 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 137112965682 ps |
| CPU time | 150.02 seconds |
| Started | Oct 02 07:10:19 PM UTC 24 |
| Finished | Oct 02 07:12:51 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334426957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3334426957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/12.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/120.uart_fifo_reset.3497391002 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 17006927954 ps |
| CPU time | 47.39 seconds |
| Started | Oct 02 07:38:48 PM UTC 24 |
| Finished | Oct 02 07:39:37 PM UTC 24 |
| Peak memory | 203860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497391002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3497391002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/120.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/121.uart_fifo_reset.612924709 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 19019937372 ps |
| CPU time | 50.87 seconds |
| Started | Oct 02 07:38:49 PM UTC 24 |
| Finished | Oct 02 07:39:41 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612924709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.612924709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/121.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/122.uart_fifo_reset.1631940675 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 53378839658 ps |
| CPU time | 21.47 seconds |
| Started | Oct 02 07:38:49 PM UTC 24 |
| Finished | Oct 02 07:39:12 PM UTC 24 |
| Peak memory | 209284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631940675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1631940675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/122.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/123.uart_fifo_reset.3947045025 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 26590516292 ps |
| CPU time | 34.34 seconds |
| Started | Oct 02 07:38:51 PM UTC 24 |
| Finished | Oct 02 07:39:27 PM UTC 24 |
| Peak memory | 203860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947045025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3947045025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/123.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/124.uart_fifo_reset.779902700 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 87290552208 ps |
| CPU time | 48.24 seconds |
| Started | Oct 02 07:38:55 PM UTC 24 |
| Finished | Oct 02 07:39:45 PM UTC 24 |
| Peak memory | 209400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779902700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.779902700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/124.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/125.uart_fifo_reset.3951761312 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 22647063875 ps |
| CPU time | 18.09 seconds |
| Started | Oct 02 07:38:55 PM UTC 24 |
| Finished | Oct 02 07:39:14 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951761312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3951761312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/125.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/126.uart_fifo_reset.2612881826 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 40839706845 ps |
| CPU time | 42.75 seconds |
| Started | Oct 02 07:38:56 PM UTC 24 |
| Finished | Oct 02 07:39:41 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612881826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2612881826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/126.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/127.uart_fifo_reset.2708861770 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 102994256847 ps |
| CPU time | 84.81 seconds |
| Started | Oct 02 07:38:56 PM UTC 24 |
| Finished | Oct 02 07:40:24 PM UTC 24 |
| Peak memory | 209400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708861770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2708861770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/127.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/128.uart_fifo_reset.3948105802 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 13071178299 ps |
| CPU time | 45.16 seconds |
| Started | Oct 02 07:39:00 PM UTC 24 |
| Finished | Oct 02 07:39:47 PM UTC 24 |
| Peak memory | 208940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948105802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3948105802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/128.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/129.uart_fifo_reset.627367854 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 149856139101 ps |
| CPU time | 86.02 seconds |
| Started | Oct 02 07:39:02 PM UTC 24 |
| Finished | Oct 02 07:40:30 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627367854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.627367854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/129.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_alert_test.3069311864 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 78654605 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 07:11:01 PM UTC 24 |
| Finished | Oct 02 07:11:03 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069311864 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3069311864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_intr.2119535427 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 20633655925 ps |
| CPU time | 53.21 seconds |
| Started | Oct 02 07:10:48 PM UTC 24 |
| Finished | Oct 02 07:11:44 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119535427 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2119535427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.4247176566 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 96048114570 ps |
| CPU time | 748.34 seconds |
| Started | Oct 02 07:10:59 PM UTC 24 |
| Finished | Oct 02 07:23:37 PM UTC 24 |
| Peak memory | 212680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247176566 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.4247176566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_loopback.4123073063 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 56173239 ps |
| CPU time | 1.12 seconds |
| Started | Oct 02 07:10:58 PM UTC 24 |
| Finished | Oct 02 07:11:00 PM UTC 24 |
| Peak memory | 205360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123073063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 13.uart_loopback.4123073063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_noise_filter.2826864650 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 13569312440 ps |
| CPU time | 19.19 seconds |
| Started | Oct 02 07:10:49 PM UTC 24 |
| Finished | Oct 02 07:11:11 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826864650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2826864650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_perf.708295332 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 18359620083 ps |
| CPU time | 1001.08 seconds |
| Started | Oct 02 07:10:59 PM UTC 24 |
| Finished | Oct 02 07:27:52 PM UTC 24 |
| Peak memory | 207216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708295332 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.708295332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_rx_oversample.488142915 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 6868901010 ps |
| CPU time | 49.07 seconds |
| Started | Oct 02 07:10:45 PM UTC 24 |
| Finished | Oct 02 07:11:36 PM UTC 24 |
| Peak memory | 208340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488142915 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.488142915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.567502819 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 140752106931 ps |
| CPU time | 226.22 seconds |
| Started | Oct 02 07:10:54 PM UTC 24 |
| Finished | Oct 02 07:14:43 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567502819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.567502819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.4892013 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 3442981700 ps |
| CPU time | 13 seconds |
| Started | Oct 02 07:10:52 PM UTC 24 |
| Finished | Oct 02 07:11:06 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4892013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.4892013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_smoke.1377190690 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 639829224 ps |
| CPU time | 2.51 seconds |
| Started | Oct 02 07:10:37 PM UTC 24 |
| Finished | Oct 02 07:10:41 PM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377190690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1377190690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_stress_all.3017590783 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 66203201462 ps |
| CPU time | 178.72 seconds |
| Started | Oct 02 07:11:01 PM UTC 24 |
| Finished | Oct 02 07:14:03 PM UTC 24 |
| Peak memory | 204032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017590783 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3017590783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.1845750247 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3190794464 ps |
| CPU time | 42.67 seconds |
| Started | Oct 02 07:11:00 PM UTC 24 |
| Finished | Oct 02 07:11:44 PM UTC 24 |
| Peak memory | 220656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1845750247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all _with_rand_reset.1845750247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_tx_rx.1585485535 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 50345390313 ps |
| CPU time | 137.58 seconds |
| Started | Oct 02 07:10:38 PM UTC 24 |
| Finished | Oct 02 07:12:58 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585485535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1585485535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/13.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/131.uart_fifo_reset.860247698 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 116543951201 ps |
| CPU time | 194.98 seconds |
| Started | Oct 02 07:39:04 PM UTC 24 |
| Finished | Oct 02 07:42:21 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860247698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.860247698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/131.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/132.uart_fifo_reset.2639368572 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 71808450475 ps |
| CPU time | 16.69 seconds |
| Started | Oct 02 07:39:07 PM UTC 24 |
| Finished | Oct 02 07:39:25 PM UTC 24 |
| Peak memory | 208952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639368572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2639368572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/132.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/133.uart_fifo_reset.812313669 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 139502613733 ps |
| CPU time | 73.38 seconds |
| Started | Oct 02 07:39:07 PM UTC 24 |
| Finished | Oct 02 07:40:22 PM UTC 24 |
| Peak memory | 203808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812313669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.812313669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/133.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/134.uart_fifo_reset.841037326 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 83872409602 ps |
| CPU time | 172.01 seconds |
| Started | Oct 02 07:39:08 PM UTC 24 |
| Finished | Oct 02 07:42:03 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841037326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.841037326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/134.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/135.uart_fifo_reset.2236432540 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 34088785778 ps |
| CPU time | 43.35 seconds |
| Started | Oct 02 07:39:08 PM UTC 24 |
| Finished | Oct 02 07:39:53 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236432540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2236432540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/135.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/136.uart_fifo_reset.2438700860 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 34905109551 ps |
| CPU time | 103.14 seconds |
| Started | Oct 02 07:39:09 PM UTC 24 |
| Finished | Oct 02 07:40:54 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438700860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2438700860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/136.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/137.uart_fifo_reset.2269443520 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 107564503419 ps |
| CPU time | 84.55 seconds |
| Started | Oct 02 07:39:09 PM UTC 24 |
| Finished | Oct 02 07:40:36 PM UTC 24 |
| Peak memory | 204116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269443520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2269443520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/137.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/138.uart_fifo_reset.14929806 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 73457814911 ps |
| CPU time | 36.44 seconds |
| Started | Oct 02 07:39:12 PM UTC 24 |
| Finished | Oct 02 07:39:50 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14929806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.14929806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/138.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/139.uart_fifo_reset.182647760 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 22107545013 ps |
| CPU time | 26.22 seconds |
| Started | Oct 02 07:39:14 PM UTC 24 |
| Finished | Oct 02 07:39:42 PM UTC 24 |
| Peak memory | 209244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182647760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.182647760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/139.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_alert_test.3432618924 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 26350970 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 07:11:27 PM UTC 24 |
| Finished | Oct 02 07:11:29 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432618924 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3432618924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_fifo_full.2770143609 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 101042053020 ps |
| CPU time | 70.66 seconds |
| Started | Oct 02 07:11:07 PM UTC 24 |
| Finished | Oct 02 07:12:19 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770143609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2770143609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.518594241 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 74707626556 ps |
| CPU time | 63.97 seconds |
| Started | Oct 02 07:11:07 PM UTC 24 |
| Finished | Oct 02 07:12:13 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518594241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.518594241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_fifo_reset.427464820 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 20746917953 ps |
| CPU time | 23.9 seconds |
| Started | Oct 02 07:11:10 PM UTC 24 |
| Finished | Oct 02 07:11:35 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427464820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.427464820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_intr.123165165 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 9390540073 ps |
| CPU time | 32.16 seconds |
| Started | Oct 02 07:11:12 PM UTC 24 |
| Finished | Oct 02 07:11:45 PM UTC 24 |
| Peak memory | 205956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123165165 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.123165165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.2959517534 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 71444701038 ps |
| CPU time | 245.05 seconds |
| Started | Oct 02 07:11:24 PM UTC 24 |
| Finished | Oct 02 07:15:33 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959517534 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2959517534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_loopback.2803470732 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 107856847 ps |
| CPU time | 1.33 seconds |
| Started | Oct 02 07:11:19 PM UTC 24 |
| Finished | Oct 02 07:11:21 PM UTC 24 |
| Peak memory | 205360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803470732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2803470732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_noise_filter.1856938353 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 68111981312 ps |
| CPU time | 57.52 seconds |
| Started | Oct 02 07:11:12 PM UTC 24 |
| Finished | Oct 02 07:12:11 PM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856938353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1856938353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_perf.137027917 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 8272950207 ps |
| CPU time | 451.6 seconds |
| Started | Oct 02 07:11:21 PM UTC 24 |
| Finished | Oct 02 07:18:59 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137027917 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.137027917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_rx_oversample.3361796660 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2612349091 ps |
| CPU time | 13.31 seconds |
| Started | Oct 02 07:11:11 PM UTC 24 |
| Finished | Oct 02 07:11:25 PM UTC 24 |
| Peak memory | 208196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361796660 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3361796660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.3127331327 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 99213545332 ps |
| CPU time | 87.56 seconds |
| Started | Oct 02 07:11:15 PM UTC 24 |
| Finished | Oct 02 07:12:44 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127331327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3127331327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.1350493415 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 6396517274 ps |
| CPU time | 14.69 seconds |
| Started | Oct 02 07:11:13 PM UTC 24 |
| Finished | Oct 02 07:11:29 PM UTC 24 |
| Peak memory | 203504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350493415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1350493415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_smoke.3416564476 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 313690867 ps |
| CPU time | 2.44 seconds |
| Started | Oct 02 07:11:02 PM UTC 24 |
| Finished | Oct 02 07:11:06 PM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416564476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3416564476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.3523350349 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 5511903718 ps |
| CPU time | 2.94 seconds |
| Started | Oct 02 07:11:18 PM UTC 24 |
| Finished | Oct 02 07:11:22 PM UTC 24 |
| Peak memory | 208388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523350349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3523350349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/14.uart_tx_rx.1493498244 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 23333078906 ps |
| CPU time | 39.16 seconds |
| Started | Oct 02 07:11:04 PM UTC 24 |
| Finished | Oct 02 07:11:46 PM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493498244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1493498244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/140.uart_fifo_reset.3494648308 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 137309483123 ps |
| CPU time | 122.5 seconds |
| Started | Oct 02 07:39:15 PM UTC 24 |
| Finished | Oct 02 07:41:20 PM UTC 24 |
| Peak memory | 209664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494648308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3494648308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/140.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/141.uart_fifo_reset.4042413863 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 193431363235 ps |
| CPU time | 146.72 seconds |
| Started | Oct 02 07:39:17 PM UTC 24 |
| Finished | Oct 02 07:41:46 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042413863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.4042413863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/141.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/142.uart_fifo_reset.2432925237 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 16150204583 ps |
| CPU time | 21.53 seconds |
| Started | Oct 02 07:39:19 PM UTC 24 |
| Finished | Oct 02 07:39:41 PM UTC 24 |
| Peak memory | 203836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432925237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2432925237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/142.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/143.uart_fifo_reset.1413428114 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 19300471941 ps |
| CPU time | 17.54 seconds |
| Started | Oct 02 07:39:20 PM UTC 24 |
| Finished | Oct 02 07:39:39 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413428114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1413428114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/143.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/147.uart_fifo_reset.3298376649 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 30466558350 ps |
| CPU time | 79.05 seconds |
| Started | Oct 02 07:39:28 PM UTC 24 |
| Finished | Oct 02 07:40:49 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298376649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3298376649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/147.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/148.uart_fifo_reset.3906898113 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 64669076400 ps |
| CPU time | 119.95 seconds |
| Started | Oct 02 07:39:28 PM UTC 24 |
| Finished | Oct 02 07:41:30 PM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906898113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3906898113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/148.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_alert_test.3870991513 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 16133054 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 07:12:05 PM UTC 24 |
| Finished | Oct 02 07:12:06 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870991513 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3870991513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_fifo_full.4268010751 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 140745953106 ps |
| CPU time | 38.09 seconds |
| Started | Oct 02 07:11:31 PM UTC 24 |
| Finished | Oct 02 07:12:11 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268010751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.4268010751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_fifo_reset.1019843260 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 34975764555 ps |
| CPU time | 43.37 seconds |
| Started | Oct 02 07:11:33 PM UTC 24 |
| Finished | Oct 02 07:12:18 PM UTC 24 |
| Peak memory | 209096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019843260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1019843260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_intr.31448614 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 47902354732 ps |
| CPU time | 103.59 seconds |
| Started | Oct 02 07:11:38 PM UTC 24 |
| Finished | Oct 02 07:13:23 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31448614 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.31448614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.1105968912 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 26058680985 ps |
| CPU time | 81.89 seconds |
| Started | Oct 02 07:11:48 PM UTC 24 |
| Finished | Oct 02 07:13:12 PM UTC 24 |
| Peak memory | 204092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105968912 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1105968912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_loopback.4110664674 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 8823100633 ps |
| CPU time | 16.85 seconds |
| Started | Oct 02 07:11:46 PM UTC 24 |
| Finished | Oct 02 07:12:04 PM UTC 24 |
| Peak memory | 208964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110664674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 15.uart_loopback.4110664674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_noise_filter.3901021917 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 138469503090 ps |
| CPU time | 226.93 seconds |
| Started | Oct 02 07:11:38 PM UTC 24 |
| Finished | Oct 02 07:15:28 PM UTC 24 |
| Peak memory | 218436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901021917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3901021917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_perf.3597782623 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 10871350977 ps |
| CPU time | 134.32 seconds |
| Started | Oct 02 07:11:48 PM UTC 24 |
| Finished | Oct 02 07:14:05 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597782623 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3597782623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_rx_oversample.127332257 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 5724487020 ps |
| CPU time | 13.45 seconds |
| Started | Oct 02 07:11:36 PM UTC 24 |
| Finished | Oct 02 07:11:50 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127332257 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.127332257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.2971503152 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 39938222565 ps |
| CPU time | 57.23 seconds |
| Started | Oct 02 07:11:46 PM UTC 24 |
| Finished | Oct 02 07:12:45 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971503152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2971503152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.916334433 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 2167067454 ps |
| CPU time | 2.85 seconds |
| Started | Oct 02 07:11:42 PM UTC 24 |
| Finished | Oct 02 07:11:46 PM UTC 24 |
| Peak memory | 203712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916334433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.916334433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_smoke.46321653 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 132032758 ps |
| CPU time | 1.26 seconds |
| Started | Oct 02 07:11:29 PM UTC 24 |
| Finished | Oct 02 07:11:31 PM UTC 24 |
| Peak memory | 203384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46321653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 15.uart_smoke.46321653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.1852760838 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1317940876 ps |
| CPU time | 2.83 seconds |
| Started | Oct 02 07:11:46 PM UTC 24 |
| Finished | Oct 02 07:11:50 PM UTC 24 |
| Peak memory | 207808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852760838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1852760838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/15.uart_tx_rx.4278804417 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 21381593185 ps |
| CPU time | 57.93 seconds |
| Started | Oct 02 07:11:31 PM UTC 24 |
| Finished | Oct 02 07:12:31 PM UTC 24 |
| Peak memory | 209652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278804417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.4278804417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/15.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/150.uart_fifo_reset.3552810715 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 73141500485 ps |
| CPU time | 187.6 seconds |
| Started | Oct 02 07:39:31 PM UTC 24 |
| Finished | Oct 02 07:42:42 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552810715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3552810715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/150.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/151.uart_fifo_reset.800261320 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 58273071332 ps |
| CPU time | 63.27 seconds |
| Started | Oct 02 07:39:37 PM UTC 24 |
| Finished | Oct 02 07:40:42 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800261320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.800261320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/151.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/152.uart_fifo_reset.1292343380 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 120542680173 ps |
| CPU time | 60.52 seconds |
| Started | Oct 02 07:39:40 PM UTC 24 |
| Finished | Oct 02 07:40:42 PM UTC 24 |
| Peak memory | 209100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292343380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1292343380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/152.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/153.uart_fifo_reset.3109800015 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 185327036150 ps |
| CPU time | 181.15 seconds |
| Started | Oct 02 07:39:42 PM UTC 24 |
| Finished | Oct 02 07:42:46 PM UTC 24 |
| Peak memory | 209024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109800015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3109800015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/153.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/154.uart_fifo_reset.3034280017 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 116683350806 ps |
| CPU time | 38.66 seconds |
| Started | Oct 02 07:39:43 PM UTC 24 |
| Finished | Oct 02 07:40:23 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034280017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3034280017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/154.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/155.uart_fifo_reset.4214281001 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 86774847337 ps |
| CPU time | 257.02 seconds |
| Started | Oct 02 07:39:43 PM UTC 24 |
| Finished | Oct 02 07:44:04 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214281001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.4214281001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/155.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/156.uart_fifo_reset.2455779154 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 125220751232 ps |
| CPU time | 93.19 seconds |
| Started | Oct 02 07:39:43 PM UTC 24 |
| Finished | Oct 02 07:41:18 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455779154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2455779154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/156.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/157.uart_fifo_reset.2595311276 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 45956219859 ps |
| CPU time | 160.32 seconds |
| Started | Oct 02 07:39:44 PM UTC 24 |
| Finished | Oct 02 07:42:27 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595311276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2595311276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/157.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/158.uart_fifo_reset.3456385421 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 67765451268 ps |
| CPU time | 145.55 seconds |
| Started | Oct 02 07:39:45 PM UTC 24 |
| Finished | Oct 02 07:42:13 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456385421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3456385421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/158.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_alert_test.1625490027 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 13149447 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 07:12:44 PM UTC 24 |
| Finished | Oct 02 07:12:46 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625490027 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1625490027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_fifo_full.2945064504 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 63644322356 ps |
| CPU time | 31.13 seconds |
| Started | Oct 02 07:12:11 PM UTC 24 |
| Finished | Oct 02 07:12:43 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945064504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2945064504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.722652421 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 197543586720 ps |
| CPU time | 231.17 seconds |
| Started | Oct 02 07:12:13 PM UTC 24 |
| Finished | Oct 02 07:16:08 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722652421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.722652421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_fifo_reset.2966061599 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 57392008270 ps |
| CPU time | 31.25 seconds |
| Started | Oct 02 07:12:13 PM UTC 24 |
| Finished | Oct 02 07:12:46 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966061599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2966061599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.2874014692 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 129487445596 ps |
| CPU time | 1412.58 seconds |
| Started | Oct 02 07:12:31 PM UTC 24 |
| Finished | Oct 02 07:36:21 PM UTC 24 |
| Peak memory | 212712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874014692 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2874014692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_loopback.4062291587 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 289938754 ps |
| CPU time | 1.28 seconds |
| Started | Oct 02 07:12:27 PM UTC 24 |
| Finished | Oct 02 07:12:29 PM UTC 24 |
| Peak memory | 207344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062291587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.uart_loopback.4062291587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_noise_filter.3758246895 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 69848735673 ps |
| CPU time | 50.48 seconds |
| Started | Oct 02 07:12:19 PM UTC 24 |
| Finished | Oct 02 07:13:12 PM UTC 24 |
| Peak memory | 220420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758246895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3758246895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_perf.3380604740 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 12662124448 ps |
| CPU time | 677.76 seconds |
| Started | Oct 02 07:12:29 PM UTC 24 |
| Finished | Oct 02 07:23:55 PM UTC 24 |
| Peak memory | 207376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380604740 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3380604740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_rx_oversample.498808572 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 7275566558 ps |
| CPU time | 79.93 seconds |
| Started | Oct 02 07:12:13 PM UTC 24 |
| Finished | Oct 02 07:13:35 PM UTC 24 |
| Peak memory | 207876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498808572 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.498808572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.3610847086 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 19152220761 ps |
| CPU time | 44.61 seconds |
| Started | Oct 02 07:12:22 PM UTC 24 |
| Finished | Oct 02 07:13:09 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610847086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3610847086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.3407608758 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 5922095735 ps |
| CPU time | 20.42 seconds |
| Started | Oct 02 07:12:21 PM UTC 24 |
| Finished | Oct 02 07:12:43 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407608758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3407608758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_smoke.1493729392 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 294413622 ps |
| CPU time | 1.85 seconds |
| Started | Oct 02 07:12:07 PM UTC 24 |
| Finished | Oct 02 07:12:10 PM UTC 24 |
| Peak memory | 203332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493729392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1493729392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_stress_all.3458139838 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 150440128954 ps |
| CPU time | 267.29 seconds |
| Started | Oct 02 07:12:42 PM UTC 24 |
| Finished | Oct 02 07:17:13 PM UTC 24 |
| Peak memory | 203836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458139838 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3458139838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.1015263398 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 14053192798 ps |
| CPU time | 114.34 seconds |
| Started | Oct 02 07:12:33 PM UTC 24 |
| Finished | Oct 02 07:14:30 PM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1015263398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all _with_rand_reset.1015263398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.595177141 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 841646336 ps |
| CPU time | 2.6 seconds |
| Started | Oct 02 07:12:25 PM UTC 24 |
| Finished | Oct 02 07:12:28 PM UTC 24 |
| Peak memory | 203868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595177141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.595177141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_tx_rx.4160859391 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 32379404808 ps |
| CPU time | 33.74 seconds |
| Started | Oct 02 07:12:09 PM UTC 24 |
| Finished | Oct 02 07:12:44 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160859391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.4160859391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/16.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/160.uart_fifo_reset.3266279883 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 90766358986 ps |
| CPU time | 154.95 seconds |
| Started | Oct 02 07:39:48 PM UTC 24 |
| Finished | Oct 02 07:42:26 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266279883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3266279883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/160.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/161.uart_fifo_reset.2576452307 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 111103736850 ps |
| CPU time | 28.82 seconds |
| Started | Oct 02 07:39:51 PM UTC 24 |
| Finished | Oct 02 07:40:21 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576452307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2576452307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/161.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/162.uart_fifo_reset.3351381172 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 40581143744 ps |
| CPU time | 71.21 seconds |
| Started | Oct 02 07:39:51 PM UTC 24 |
| Finished | Oct 02 07:41:04 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351381172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3351381172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/162.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/163.uart_fifo_reset.3176257279 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 83589164966 ps |
| CPU time | 37.1 seconds |
| Started | Oct 02 07:39:52 PM UTC 24 |
| Finished | Oct 02 07:40:31 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176257279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3176257279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/163.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/164.uart_fifo_reset.1390106274 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 61566131312 ps |
| CPU time | 111.48 seconds |
| Started | Oct 02 07:39:54 PM UTC 24 |
| Finished | Oct 02 07:41:47 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390106274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1390106274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/164.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/168.uart_fifo_reset.1634166142 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 28389504532 ps |
| CPU time | 20.31 seconds |
| Started | Oct 02 07:40:00 PM UTC 24 |
| Finished | Oct 02 07:40:21 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634166142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1634166142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/168.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/169.uart_fifo_reset.524665115 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 84159366308 ps |
| CPU time | 67.65 seconds |
| Started | Oct 02 07:40:00 PM UTC 24 |
| Finished | Oct 02 07:41:09 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524665115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.524665115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/169.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_alert_test.3527688569 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 18325266 ps |
| CPU time | 0.9 seconds |
| Started | Oct 02 07:12:59 PM UTC 24 |
| Finished | Oct 02 07:13:00 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527688569 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3527688569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_fifo_full.220637709 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 224812633712 ps |
| CPU time | 281.09 seconds |
| Started | Oct 02 07:12:44 PM UTC 24 |
| Finished | Oct 02 07:17:30 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220637709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.220637709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.3708142544 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 220013051435 ps |
| CPU time | 316.59 seconds |
| Started | Oct 02 07:12:44 PM UTC 24 |
| Finished | Oct 02 07:18:06 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708142544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3708142544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_fifo_reset.1403607201 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 11796537456 ps |
| CPU time | 10.86 seconds |
| Started | Oct 02 07:12:45 PM UTC 24 |
| Finished | Oct 02 07:12:58 PM UTC 24 |
| Peak memory | 209072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403607201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1403607201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_intr.3100415873 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 7165504083 ps |
| CPU time | 13.89 seconds |
| Started | Oct 02 07:12:47 PM UTC 24 |
| Finished | Oct 02 07:13:02 PM UTC 24 |
| Peak memory | 207596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100415873 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3100415873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.3810365716 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 96469820121 ps |
| CPU time | 629.96 seconds |
| Started | Oct 02 07:12:54 PM UTC 24 |
| Finished | Oct 02 07:23:33 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810365716 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3810365716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_loopback.103188103 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1424667132 ps |
| CPU time | 6.09 seconds |
| Started | Oct 02 07:12:51 PM UTC 24 |
| Finished | Oct 02 07:12:58 PM UTC 24 |
| Peak memory | 205560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103188103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 17.uart_loopback.103188103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_perf.2182669885 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 15765074451 ps |
| CPU time | 501.8 seconds |
| Started | Oct 02 07:12:52 PM UTC 24 |
| Finished | Oct 02 07:21:21 PM UTC 24 |
| Peak memory | 203720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182669885 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2182669885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_rx_oversample.3140169802 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2709724990 ps |
| CPU time | 3.7 seconds |
| Started | Oct 02 07:12:46 PM UTC 24 |
| Finished | Oct 02 07:12:50 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140169802 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3140169802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.1253855188 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 36005647836 ps |
| CPU time | 37.49 seconds |
| Started | Oct 02 07:12:49 PM UTC 24 |
| Finished | Oct 02 07:13:28 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253855188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1253855188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.2503282354 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 2466941908 ps |
| CPU time | 5.65 seconds |
| Started | Oct 02 07:12:47 PM UTC 24 |
| Finished | Oct 02 07:12:53 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503282354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2503282354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_smoke.2612545180 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 285706109 ps |
| CPU time | 2.33 seconds |
| Started | Oct 02 07:12:44 PM UTC 24 |
| Finished | Oct 02 07:12:48 PM UTC 24 |
| Peak memory | 203980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612545180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2612545180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_stress_all.428272390 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 116194364366 ps |
| CPU time | 329.57 seconds |
| Started | Oct 02 07:12:58 PM UTC 24 |
| Finished | Oct 02 07:18:33 PM UTC 24 |
| Peak memory | 206148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428272390 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.428272390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.1394743518 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 14685674460 ps |
| CPU time | 80.51 seconds |
| Started | Oct 02 07:12:57 PM UTC 24 |
| Finished | Oct 02 07:14:20 PM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1394743518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all _with_rand_reset.1394743518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.2753795234 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 901895698 ps |
| CPU time | 5.33 seconds |
| Started | Oct 02 07:12:50 PM UTC 24 |
| Finished | Oct 02 07:12:56 PM UTC 24 |
| Peak memory | 207820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753795234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2753795234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_tx_rx.4001530304 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 112443499391 ps |
| CPU time | 88.86 seconds |
| Started | Oct 02 07:12:44 PM UTC 24 |
| Finished | Oct 02 07:14:15 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001530304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.4001530304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/17.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/170.uart_fifo_reset.3886966437 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 63281506355 ps |
| CPU time | 59.32 seconds |
| Started | Oct 02 07:40:01 PM UTC 24 |
| Finished | Oct 02 07:41:02 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886966437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3886966437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/170.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/171.uart_fifo_reset.3882028273 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 237443964950 ps |
| CPU time | 253.48 seconds |
| Started | Oct 02 07:40:02 PM UTC 24 |
| Finished | Oct 02 07:44:19 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882028273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3882028273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/171.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/172.uart_fifo_reset.447547126 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 32749070369 ps |
| CPU time | 27.7 seconds |
| Started | Oct 02 07:40:07 PM UTC 24 |
| Finished | Oct 02 07:40:36 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447547126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.447547126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/172.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/173.uart_fifo_reset.58618960 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 64510164511 ps |
| CPU time | 20.45 seconds |
| Started | Oct 02 07:40:09 PM UTC 24 |
| Finished | Oct 02 07:40:31 PM UTC 24 |
| Peak memory | 203860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58618960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.58618960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/173.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/174.uart_fifo_reset.583810895 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 101286331489 ps |
| CPU time | 19.95 seconds |
| Started | Oct 02 07:40:12 PM UTC 24 |
| Finished | Oct 02 07:40:34 PM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583810895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.583810895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/174.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/175.uart_fifo_reset.4084358970 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 14743555682 ps |
| CPU time | 40.31 seconds |
| Started | Oct 02 07:40:12 PM UTC 24 |
| Finished | Oct 02 07:40:54 PM UTC 24 |
| Peak memory | 209352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084358970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.4084358970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/175.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/176.uart_fifo_reset.1149278603 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 51536002573 ps |
| CPU time | 67.76 seconds |
| Started | Oct 02 07:40:20 PM UTC 24 |
| Finished | Oct 02 07:41:29 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149278603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1149278603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/176.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/177.uart_fifo_reset.705982806 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 57993880283 ps |
| CPU time | 46.87 seconds |
| Started | Oct 02 07:40:23 PM UTC 24 |
| Finished | Oct 02 07:41:12 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705982806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.705982806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/177.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/178.uart_fifo_reset.3540321958 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 27936997805 ps |
| CPU time | 23.54 seconds |
| Started | Oct 02 07:40:23 PM UTC 24 |
| Finished | Oct 02 07:40:49 PM UTC 24 |
| Peak memory | 209204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540321958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3540321958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/178.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/179.uart_fifo_reset.3506890215 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 147278675396 ps |
| CPU time | 185.99 seconds |
| Started | Oct 02 07:40:23 PM UTC 24 |
| Finished | Oct 02 07:43:33 PM UTC 24 |
| Peak memory | 204044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506890215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3506890215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/179.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_alert_test.975103351 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 44378529 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 07:13:24 PM UTC 24 |
| Finished | Oct 02 07:13:26 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975103351 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.975103351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.3298606529 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 54136385258 ps |
| CPU time | 137.5 seconds |
| Started | Oct 02 07:13:02 PM UTC 24 |
| Finished | Oct 02 07:15:22 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298606529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3298606529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_fifo_reset.1822497473 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 106836711276 ps |
| CPU time | 47.17 seconds |
| Started | Oct 02 07:13:03 PM UTC 24 |
| Finished | Oct 02 07:13:52 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822497473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1822497473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_intr.2359754023 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 29487001281 ps |
| CPU time | 18.52 seconds |
| Started | Oct 02 07:13:10 PM UTC 24 |
| Finished | Oct 02 07:13:30 PM UTC 24 |
| Peak memory | 203768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359754023 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2359754023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_loopback.1824036427 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1003044710 ps |
| CPU time | 4.31 seconds |
| Started | Oct 02 07:13:18 PM UTC 24 |
| Finished | Oct 02 07:13:23 PM UTC 24 |
| Peak memory | 205488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824036427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1824036427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_noise_filter.673629047 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 139023299242 ps |
| CPU time | 46.06 seconds |
| Started | Oct 02 07:13:11 PM UTC 24 |
| Finished | Oct 02 07:13:59 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673629047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.673629047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_perf.2093454404 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 23021768779 ps |
| CPU time | 98.92 seconds |
| Started | Oct 02 07:13:19 PM UTC 24 |
| Finished | Oct 02 07:15:00 PM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093454404 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2093454404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_rx_oversample.3675521585 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 3272194583 ps |
| CPU time | 18.24 seconds |
| Started | Oct 02 07:13:03 PM UTC 24 |
| Finished | Oct 02 07:13:22 PM UTC 24 |
| Peak memory | 208364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675521585 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3675521585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.1007839701 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 28281428233 ps |
| CPU time | 63.62 seconds |
| Started | Oct 02 07:13:13 PM UTC 24 |
| Finished | Oct 02 07:14:19 PM UTC 24 |
| Peak memory | 204040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007839701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1007839701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.1802066975 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 3244864392 ps |
| CPU time | 4.31 seconds |
| Started | Oct 02 07:13:12 PM UTC 24 |
| Finished | Oct 02 07:13:18 PM UTC 24 |
| Peak memory | 203512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802066975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1802066975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_smoke.3065206560 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 661968236 ps |
| CPU time | 3.01 seconds |
| Started | Oct 02 07:12:59 PM UTC 24 |
| Finished | Oct 02 07:13:03 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065206560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3065206560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_stress_all.1016151794 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 383309216599 ps |
| CPU time | 65.9 seconds |
| Started | Oct 02 07:13:23 PM UTC 24 |
| Finished | Oct 02 07:14:31 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016151794 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1016151794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.2773003350 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1604032139 ps |
| CPU time | 22.33 seconds |
| Started | Oct 02 07:13:23 PM UTC 24 |
| Finished | Oct 02 07:13:47 PM UTC 24 |
| Peak memory | 209656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2773003350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all _with_rand_reset.2773003350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.630479809 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 990810017 ps |
| CPU time | 4.06 seconds |
| Started | Oct 02 07:13:18 PM UTC 24 |
| Finished | Oct 02 07:13:23 PM UTC 24 |
| Peak memory | 203728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630479809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.630479809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/18.uart_tx_rx.2719938976 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 54654071331 ps |
| CPU time | 40.95 seconds |
| Started | Oct 02 07:13:00 PM UTC 24 |
| Finished | Oct 02 07:13:42 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719938976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2719938976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/182.uart_fifo_reset.1737978532 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 7419257910 ps |
| CPU time | 14.53 seconds |
| Started | Oct 02 07:40:27 PM UTC 24 |
| Finished | Oct 02 07:40:43 PM UTC 24 |
| Peak memory | 209072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737978532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1737978532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/182.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/183.uart_fifo_reset.1825804695 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 20789147753 ps |
| CPU time | 53.7 seconds |
| Started | Oct 02 07:40:28 PM UTC 24 |
| Finished | Oct 02 07:41:24 PM UTC 24 |
| Peak memory | 209652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825804695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1825804695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/183.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/184.uart_fifo_reset.1915997919 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 35769955527 ps |
| CPU time | 60.28 seconds |
| Started | Oct 02 07:40:30 PM UTC 24 |
| Finished | Oct 02 07:41:32 PM UTC 24 |
| Peak memory | 209520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915997919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1915997919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/184.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/185.uart_fifo_reset.111382474 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 189744437709 ps |
| CPU time | 37.35 seconds |
| Started | Oct 02 07:40:31 PM UTC 24 |
| Finished | Oct 02 07:41:10 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111382474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.111382474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/185.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/186.uart_fifo_reset.2734044139 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 51453154069 ps |
| CPU time | 55.43 seconds |
| Started | Oct 02 07:40:31 PM UTC 24 |
| Finished | Oct 02 07:41:28 PM UTC 24 |
| Peak memory | 209508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734044139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2734044139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/186.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/187.uart_fifo_reset.2118804976 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 9232114401 ps |
| CPU time | 5.54 seconds |
| Started | Oct 02 07:40:31 PM UTC 24 |
| Finished | Oct 02 07:40:38 PM UTC 24 |
| Peak memory | 203860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118804976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2118804976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/187.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/189.uart_fifo_reset.1900146922 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 52215187556 ps |
| CPU time | 25.99 seconds |
| Started | Oct 02 07:40:37 PM UTC 24 |
| Finished | Oct 02 07:41:04 PM UTC 24 |
| Peak memory | 209404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900146922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1900146922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/189.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_alert_test.2577385048 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 23623388 ps |
| CPU time | 0.83 seconds |
| Started | Oct 02 07:13:59 PM UTC 24 |
| Finished | Oct 02 07:14:01 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577385048 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2577385048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_fifo_full.1024540341 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 63859666216 ps |
| CPU time | 82.58 seconds |
| Started | Oct 02 07:13:27 PM UTC 24 |
| Finished | Oct 02 07:14:52 PM UTC 24 |
| Peak memory | 204048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024540341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1024540341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.159314782 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 31041066225 ps |
| CPU time | 80.44 seconds |
| Started | Oct 02 07:13:28 PM UTC 24 |
| Finished | Oct 02 07:14:51 PM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159314782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.159314782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_fifo_reset.856498328 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 61797735665 ps |
| CPU time | 25.14 seconds |
| Started | Oct 02 07:13:29 PM UTC 24 |
| Finished | Oct 02 07:13:56 PM UTC 24 |
| Peak memory | 209472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856498328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.856498328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_intr.2964662367 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 60799383436 ps |
| CPU time | 15.47 seconds |
| Started | Oct 02 07:13:31 PM UTC 24 |
| Finished | Oct 02 07:13:47 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964662367 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2964662367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.1103140170 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 67178748765 ps |
| CPU time | 655.6 seconds |
| Started | Oct 02 07:13:54 PM UTC 24 |
| Finished | Oct 02 07:25:00 PM UTC 24 |
| Peak memory | 210652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103140170 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1103140170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_loopback.448056276 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 6592682023 ps |
| CPU time | 10.08 seconds |
| Started | Oct 02 07:13:48 PM UTC 24 |
| Finished | Oct 02 07:13:59 PM UTC 24 |
| Peak memory | 207876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448056276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 19.uart_loopback.448056276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_noise_filter.181195682 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 199588226322 ps |
| CPU time | 98.91 seconds |
| Started | Oct 02 07:13:36 PM UTC 24 |
| Finished | Oct 02 07:15:17 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181195682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.181195682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_perf.1724690863 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 8425712261 ps |
| CPU time | 347.64 seconds |
| Started | Oct 02 07:13:52 PM UTC 24 |
| Finished | Oct 02 07:19:45 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724690863 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1724690863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_rx_oversample.1078771634 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 4433390053 ps |
| CPU time | 24.18 seconds |
| Started | Oct 02 07:13:31 PM UTC 24 |
| Finished | Oct 02 07:13:56 PM UTC 24 |
| Peak memory | 208504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078771634 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1078771634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.2186160637 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 73198612862 ps |
| CPU time | 38.74 seconds |
| Started | Oct 02 07:13:47 PM UTC 24 |
| Finished | Oct 02 07:14:27 PM UTC 24 |
| Peak memory | 208316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186160637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2186160637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.307723071 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 4518339421 ps |
| CPU time | 2.01 seconds |
| Started | Oct 02 07:13:43 PM UTC 24 |
| Finished | Oct 02 07:13:46 PM UTC 24 |
| Peak memory | 203316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307723071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.307723071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_smoke.2968055357 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 427598708 ps |
| CPU time | 3.19 seconds |
| Started | Oct 02 07:13:24 PM UTC 24 |
| Finished | Oct 02 07:13:28 PM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968055357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2968055357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.3157563355 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 10772663175 ps |
| CPU time | 34.88 seconds |
| Started | Oct 02 07:13:57 PM UTC 24 |
| Finished | Oct 02 07:14:34 PM UTC 24 |
| Peak memory | 218304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3157563355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all _with_rand_reset.3157563355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.2130989862 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1062271076 ps |
| CPU time | 4.41 seconds |
| Started | Oct 02 07:13:48 PM UTC 24 |
| Finished | Oct 02 07:13:53 PM UTC 24 |
| Peak memory | 207824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130989862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2130989862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_tx_rx.2056776061 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 93997390170 ps |
| CPU time | 94.08 seconds |
| Started | Oct 02 07:13:24 PM UTC 24 |
| Finished | Oct 02 07:15:00 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056776061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2056776061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/19.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/190.uart_fifo_reset.3795188793 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 73573969252 ps |
| CPU time | 51 seconds |
| Started | Oct 02 07:40:37 PM UTC 24 |
| Finished | Oct 02 07:41:29 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795188793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3795188793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/190.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/191.uart_fifo_reset.4235301549 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 25880883719 ps |
| CPU time | 57.04 seconds |
| Started | Oct 02 07:40:37 PM UTC 24 |
| Finished | Oct 02 07:41:35 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235301549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.4235301549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/191.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/192.uart_fifo_reset.768423795 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 109927948271 ps |
| CPU time | 89.55 seconds |
| Started | Oct 02 07:40:39 PM UTC 24 |
| Finished | Oct 02 07:42:10 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768423795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.768423795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/192.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/193.uart_fifo_reset.1450051327 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 52748351283 ps |
| CPU time | 42.39 seconds |
| Started | Oct 02 07:40:39 PM UTC 24 |
| Finished | Oct 02 07:41:23 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450051327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1450051327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/193.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/194.uart_fifo_reset.818188754 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 236105142954 ps |
| CPU time | 464.82 seconds |
| Started | Oct 02 07:40:39 PM UTC 24 |
| Finished | Oct 02 07:48:30 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818188754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.818188754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/194.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/195.uart_fifo_reset.1323613465 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 27214424983 ps |
| CPU time | 83.75 seconds |
| Started | Oct 02 07:40:42 PM UTC 24 |
| Finished | Oct 02 07:42:08 PM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323613465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1323613465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/195.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/196.uart_fifo_reset.2661560340 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 92584569345 ps |
| CPU time | 82.37 seconds |
| Started | Oct 02 07:40:43 PM UTC 24 |
| Finished | Oct 02 07:42:08 PM UTC 24 |
| Peak memory | 209668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661560340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2661560340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/196.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/197.uart_fifo_reset.2198617285 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 73609992698 ps |
| CPU time | 64.97 seconds |
| Started | Oct 02 07:40:44 PM UTC 24 |
| Finished | Oct 02 07:41:51 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198617285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2198617285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/197.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/199.uart_fifo_reset.2704452513 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 60067121413 ps |
| CPU time | 61.53 seconds |
| Started | Oct 02 07:40:50 PM UTC 24 |
| Finished | Oct 02 07:41:53 PM UTC 24 |
| Peak memory | 203860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704452513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2704452513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/199.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_alert_test.631524620 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 32361408 ps |
| CPU time | 0.72 seconds |
| Started | Oct 02 07:07:11 PM UTC 24 |
| Finished | Oct 02 07:07:16 PM UTC 24 |
| Peak memory | 203192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631524620 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.631524620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.422357399 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 135174078626 ps |
| CPU time | 11.91 seconds |
| Started | Oct 02 07:07:06 PM UTC 24 |
| Finished | Oct 02 07:07:22 PM UTC 24 |
| Peak memory | 208932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422357399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.422357399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_fifo_reset.2528489136 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13930398763 ps |
| CPU time | 28 seconds |
| Started | Oct 02 07:07:07 PM UTC 24 |
| Finished | Oct 02 07:07:38 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528489136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2528489136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_intr.4025033518 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 52769380187 ps |
| CPU time | 80.63 seconds |
| Started | Oct 02 07:07:08 PM UTC 24 |
| Finished | Oct 02 07:08:31 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025033518 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.4025033518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.3044919155 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 78357678601 ps |
| CPU time | 802.61 seconds |
| Started | Oct 02 07:07:11 PM UTC 24 |
| Finished | Oct 02 07:20:47 PM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044919155 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3044919155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_loopback.3101315760 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2220303469 ps |
| CPU time | 6.35 seconds |
| Started | Oct 02 07:07:10 PM UTC 24 |
| Finished | Oct 02 07:07:21 PM UTC 24 |
| Peak memory | 203704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101315760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3101315760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_noise_filter.333241579 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1605321751 ps |
| CPU time | 1.86 seconds |
| Started | Oct 02 07:07:09 PM UTC 24 |
| Finished | Oct 02 07:07:12 PM UTC 24 |
| Peak memory | 208368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333241579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.333241579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_perf.2213217892 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 6343297298 ps |
| CPU time | 358.59 seconds |
| Started | Oct 02 07:07:10 PM UTC 24 |
| Finished | Oct 02 07:13:18 PM UTC 24 |
| Peak memory | 204060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213217892 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2213217892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_rx_oversample.2016436271 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 6654263046 ps |
| CPU time | 59.2 seconds |
| Started | Oct 02 07:07:07 PM UTC 24 |
| Finished | Oct 02 07:08:09 PM UTC 24 |
| Peak memory | 208460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016436271 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2016436271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.1142881736 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 21274546265 ps |
| CPU time | 29.4 seconds |
| Started | Oct 02 07:07:10 PM UTC 24 |
| Finished | Oct 02 07:07:44 PM UTC 24 |
| Peak memory | 209220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142881736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1142881736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.440307882 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 3070446223 ps |
| CPU time | 4.2 seconds |
| Started | Oct 02 07:07:10 PM UTC 24 |
| Finished | Oct 02 07:07:19 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440307882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.440307882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_sec_cm.2280107475 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 36633147 ps |
| CPU time | 1.1 seconds |
| Started | Oct 02 07:07:11 PM UTC 24 |
| Finished | Oct 02 07:07:16 PM UTC 24 |
| Peak memory | 237812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280107475 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2280107475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_smoke.88015850 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5477219904 ps |
| CPU time | 24.41 seconds |
| Started | Oct 02 07:07:03 PM UTC 24 |
| Finished | Oct 02 07:07:30 PM UTC 24 |
| Peak memory | 204120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88015850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.uart_smoke.88015850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.1818254423 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 20900725953 ps |
| CPU time | 97.4 seconds |
| Started | Oct 02 07:07:11 PM UTC 24 |
| Finished | Oct 02 07:08:53 PM UTC 24 |
| Peak memory | 220584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1818254423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_ with_rand_reset.1818254423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.2750619007 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1097206198 ps |
| CPU time | 4.41 seconds |
| Started | Oct 02 07:07:10 PM UTC 24 |
| Finished | Oct 02 07:07:19 PM UTC 24 |
| Peak memory | 203980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750619007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2750619007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/2.uart_tx_rx.4114474386 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 24569070831 ps |
| CPU time | 33.76 seconds |
| Started | Oct 02 07:07:04 PM UTC 24 |
| Finished | Oct 02 07:07:39 PM UTC 24 |
| Peak memory | 203916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114474386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.4114474386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/2.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_alert_test.3934701690 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 14361225 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 07:14:28 PM UTC 24 |
| Finished | Oct 02 07:14:30 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934701690 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3934701690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_fifo_full.1652539150 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 49570112747 ps |
| CPU time | 25.64 seconds |
| Started | Oct 02 07:14:02 PM UTC 24 |
| Finished | Oct 02 07:14:29 PM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652539150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1652539150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.2041441035 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 6194348883 ps |
| CPU time | 25.95 seconds |
| Started | Oct 02 07:14:04 PM UTC 24 |
| Finished | Oct 02 07:14:33 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041441035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2041441035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_fifo_reset.784753634 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 69585097381 ps |
| CPU time | 39.33 seconds |
| Started | Oct 02 07:14:06 PM UTC 24 |
| Finished | Oct 02 07:14:47 PM UTC 24 |
| Peak memory | 203760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784753634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.784753634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_intr.2338055291 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 71841860735 ps |
| CPU time | 22.86 seconds |
| Started | Oct 02 07:14:08 PM UTC 24 |
| Finished | Oct 02 07:14:33 PM UTC 24 |
| Peak memory | 208008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338055291 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2338055291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.4060038756 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 82528631947 ps |
| CPU time | 278.04 seconds |
| Started | Oct 02 07:14:23 PM UTC 24 |
| Finished | Oct 02 07:19:05 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060038756 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.4060038756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_loopback.2858705456 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2535329894 ps |
| CPU time | 1.68 seconds |
| Started | Oct 02 07:14:19 PM UTC 24 |
| Finished | Oct 02 07:14:22 PM UTC 24 |
| Peak memory | 203376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858705456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2858705456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_perf.2344314374 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 19721558737 ps |
| CPU time | 1048.97 seconds |
| Started | Oct 02 07:14:21 PM UTC 24 |
| Finished | Oct 02 07:32:02 PM UTC 24 |
| Peak memory | 212660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344314374 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2344314374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_rx_oversample.1291214912 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 5486761559 ps |
| CPU time | 61.37 seconds |
| Started | Oct 02 07:14:08 PM UTC 24 |
| Finished | Oct 02 07:15:11 PM UTC 24 |
| Peak memory | 208200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291214912 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1291214912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.159353315 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 30008756123 ps |
| CPU time | 45.98 seconds |
| Started | Oct 02 07:14:16 PM UTC 24 |
| Finished | Oct 02 07:15:04 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159353315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.159353315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.1455457655 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 3995393564 ps |
| CPU time | 4.21 seconds |
| Started | Oct 02 07:14:16 PM UTC 24 |
| Finished | Oct 02 07:14:21 PM UTC 24 |
| Peak memory | 203812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455457655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1455457655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_smoke.2490007980 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 450672313 ps |
| CPU time | 4.36 seconds |
| Started | Oct 02 07:14:01 PM UTC 24 |
| Finished | Oct 02 07:14:06 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490007980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2490007980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_stress_all.1621601094 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 194396898597 ps |
| CPU time | 1170.27 seconds |
| Started | Oct 02 07:14:23 PM UTC 24 |
| Finished | Oct 02 07:34:07 PM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621601094 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1621601094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.2945591221 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 59867857866 ps |
| CPU time | 62.74 seconds |
| Started | Oct 02 07:14:23 PM UTC 24 |
| Finished | Oct 02 07:15:28 PM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2945591221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all _with_rand_reset.2945591221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.464381213 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 654966059 ps |
| CPU time | 2.34 seconds |
| Started | Oct 02 07:14:18 PM UTC 24 |
| Finished | Oct 02 07:14:22 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464381213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.464381213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_tx_rx.295367047 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 37583963819 ps |
| CPU time | 24.63 seconds |
| Started | Oct 02 07:14:02 PM UTC 24 |
| Finished | Oct 02 07:14:28 PM UTC 24 |
| Peak memory | 208284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295367047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.295367047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/200.uart_fifo_reset.1997210118 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 67775812125 ps |
| CPU time | 28.92 seconds |
| Started | Oct 02 07:40:50 PM UTC 24 |
| Finished | Oct 02 07:41:20 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997210118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1997210118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/200.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/201.uart_fifo_reset.1977818643 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 14592151041 ps |
| CPU time | 39.72 seconds |
| Started | Oct 02 07:40:55 PM UTC 24 |
| Finished | Oct 02 07:41:36 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977818643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1977818643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/201.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/202.uart_fifo_reset.108807769 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 110663258909 ps |
| CPU time | 139.04 seconds |
| Started | Oct 02 07:40:55 PM UTC 24 |
| Finished | Oct 02 07:43:16 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108807769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.108807769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/202.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2953073779 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 198725016336 ps |
| CPU time | 58.6 seconds |
| Started | Oct 02 07:40:56 PM UTC 24 |
| Finished | Oct 02 07:41:56 PM UTC 24 |
| Peak memory | 209652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953073779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2953073779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/204.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/206.uart_fifo_reset.3157742329 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 41938010003 ps |
| CPU time | 46.53 seconds |
| Started | Oct 02 07:41:03 PM UTC 24 |
| Finished | Oct 02 07:41:51 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157742329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3157742329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/206.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2560654045 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 48345798445 ps |
| CPU time | 25.1 seconds |
| Started | Oct 02 07:41:05 PM UTC 24 |
| Finished | Oct 02 07:41:32 PM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560654045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2560654045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/208.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/209.uart_fifo_reset.11052747 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 17763910556 ps |
| CPU time | 7.94 seconds |
| Started | Oct 02 07:41:05 PM UTC 24 |
| Finished | Oct 02 07:41:14 PM UTC 24 |
| Peak memory | 208168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11052747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.11052747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/209.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_alert_test.361708935 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 25210221 ps |
| CPU time | 0.84 seconds |
| Started | Oct 02 07:14:52 PM UTC 24 |
| Finished | Oct 02 07:14:54 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361708935 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.361708935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_fifo_full.2456918730 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 55663440170 ps |
| CPU time | 37.6 seconds |
| Started | Oct 02 07:14:31 PM UTC 24 |
| Finished | Oct 02 07:15:10 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456918730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2456918730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_intr.3668205997 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 267285892338 ps |
| CPU time | 524.06 seconds |
| Started | Oct 02 07:14:34 PM UTC 24 |
| Finished | Oct 02 07:23:24 PM UTC 24 |
| Peak memory | 209132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668205997 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3668205997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.1955264946 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 128179451455 ps |
| CPU time | 622.19 seconds |
| Started | Oct 02 07:14:48 PM UTC 24 |
| Finished | Oct 02 07:25:18 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955264946 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1955264946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_loopback.2688482811 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 5727351853 ps |
| CPU time | 9.72 seconds |
| Started | Oct 02 07:14:44 PM UTC 24 |
| Finished | Oct 02 07:14:55 PM UTC 24 |
| Peak memory | 208876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688482811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2688482811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_noise_filter.2464274431 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 17122667337 ps |
| CPU time | 7.63 seconds |
| Started | Oct 02 07:14:34 PM UTC 24 |
| Finished | Oct 02 07:14:42 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464274431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2464274431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_perf.1616181018 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 10651211591 ps |
| CPU time | 205.52 seconds |
| Started | Oct 02 07:14:48 PM UTC 24 |
| Finished | Oct 02 07:18:17 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616181018 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1616181018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_rx_oversample.2601198649 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 6414464088 ps |
| CPU time | 13.12 seconds |
| Started | Oct 02 07:14:34 PM UTC 24 |
| Finished | Oct 02 07:14:48 PM UTC 24 |
| Peak memory | 203976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601198649 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2601198649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.3774764812 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 148521743064 ps |
| CPU time | 63.83 seconds |
| Started | Oct 02 07:14:43 PM UTC 24 |
| Finished | Oct 02 07:15:48 PM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774764812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3774764812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.2354796395 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 3042315007 ps |
| CPU time | 5.99 seconds |
| Started | Oct 02 07:14:35 PM UTC 24 |
| Finished | Oct 02 07:14:42 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354796395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2354796395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_smoke.3792261576 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 464439493 ps |
| CPU time | 2.79 seconds |
| Started | Oct 02 07:14:29 PM UTC 24 |
| Finished | Oct 02 07:14:33 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792261576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3792261576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_stress_all.2225748403 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 318969585712 ps |
| CPU time | 166.53 seconds |
| Started | Oct 02 07:14:49 PM UTC 24 |
| Finished | Oct 02 07:17:39 PM UTC 24 |
| Peak memory | 213340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225748403 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2225748403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.3024053945 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 3487634496 ps |
| CPU time | 51.96 seconds |
| Started | Oct 02 07:14:49 PM UTC 24 |
| Finished | Oct 02 07:15:43 PM UTC 24 |
| Peak memory | 222656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3024053945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all _with_rand_reset.3024053945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.334253442 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 978427040 ps |
| CPU time | 4.85 seconds |
| Started | Oct 02 07:14:43 PM UTC 24 |
| Finished | Oct 02 07:14:49 PM UTC 24 |
| Peak memory | 203804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334253442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.334253442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_tx_rx.9424433 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 279314662557 ps |
| CPU time | 47.45 seconds |
| Started | Oct 02 07:14:30 PM UTC 24 |
| Finished | Oct 02 07:15:19 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9424433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 21.uart_tx_rx.9424433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/21.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/210.uart_fifo_reset.3612018936 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 150274544606 ps |
| CPU time | 143.62 seconds |
| Started | Oct 02 07:41:11 PM UTC 24 |
| Finished | Oct 02 07:43:37 PM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612018936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3612018936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/210.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/211.uart_fifo_reset.1705131856 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 50269262859 ps |
| CPU time | 41.93 seconds |
| Started | Oct 02 07:41:11 PM UTC 24 |
| Finished | Oct 02 07:41:54 PM UTC 24 |
| Peak memory | 203860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705131856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1705131856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/211.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/212.uart_fifo_reset.898059475 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 22163081277 ps |
| CPU time | 33.78 seconds |
| Started | Oct 02 07:41:13 PM UTC 24 |
| Finished | Oct 02 07:41:48 PM UTC 24 |
| Peak memory | 203772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898059475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.898059475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/212.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/213.uart_fifo_reset.995117272 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 166096800722 ps |
| CPU time | 674.19 seconds |
| Started | Oct 02 07:41:15 PM UTC 24 |
| Finished | Oct 02 07:52:38 PM UTC 24 |
| Peak memory | 212664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995117272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.995117272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/213.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/214.uart_fifo_reset.4255906771 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 22334702564 ps |
| CPU time | 48.74 seconds |
| Started | Oct 02 07:41:15 PM UTC 24 |
| Finished | Oct 02 07:42:05 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255906771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4255906771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/214.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/215.uart_fifo_reset.3416319647 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 41876607201 ps |
| CPU time | 90.68 seconds |
| Started | Oct 02 07:41:19 PM UTC 24 |
| Finished | Oct 02 07:42:52 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416319647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3416319647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/215.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/216.uart_fifo_reset.1728075029 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 93110468041 ps |
| CPU time | 354.78 seconds |
| Started | Oct 02 07:41:20 PM UTC 24 |
| Finished | Oct 02 07:47:20 PM UTC 24 |
| Peak memory | 207248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728075029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1728075029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/216.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/217.uart_fifo_reset.4093303409 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 34937647036 ps |
| CPU time | 28.31 seconds |
| Started | Oct 02 07:41:21 PM UTC 24 |
| Finished | Oct 02 07:41:51 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093303409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.4093303409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/217.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/219.uart_fifo_reset.2893213374 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 139193654802 ps |
| CPU time | 294.18 seconds |
| Started | Oct 02 07:41:23 PM UTC 24 |
| Finished | Oct 02 07:46:22 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893213374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2893213374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/219.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_alert_test.19093309 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 12972149 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 07:15:18 PM UTC 24 |
| Finished | Oct 02 07:15:20 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19093309 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.19093309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_fifo_full.819351341 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 155054900874 ps |
| CPU time | 321.08 seconds |
| Started | Oct 02 07:14:55 PM UTC 24 |
| Finished | Oct 02 07:20:21 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819351341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.819351341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.2845007872 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 152732724552 ps |
| CPU time | 24.87 seconds |
| Started | Oct 02 07:14:56 PM UTC 24 |
| Finished | Oct 02 07:15:22 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845007872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2845007872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_intr.3904544735 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 266686887941 ps |
| CPU time | 380.33 seconds |
| Started | Oct 02 07:15:01 PM UTC 24 |
| Finished | Oct 02 07:21:26 PM UTC 24 |
| Peak memory | 207672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904544735 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3904544735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.1676630031 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 149416695221 ps |
| CPU time | 788.59 seconds |
| Started | Oct 02 07:15:11 PM UTC 24 |
| Finished | Oct 02 07:28:30 PM UTC 24 |
| Peak memory | 212660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676630031 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1676630031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_loopback.1443740565 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 3959256120 ps |
| CPU time | 14.26 seconds |
| Started | Oct 02 07:15:08 PM UTC 24 |
| Finished | Oct 02 07:15:24 PM UTC 24 |
| Peak memory | 205816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443740565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1443740565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_noise_filter.579017259 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 264321478502 ps |
| CPU time | 99.21 seconds |
| Started | Oct 02 07:15:04 PM UTC 24 |
| Finished | Oct 02 07:16:46 PM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579017259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.579017259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_perf.1610481387 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 11659916431 ps |
| CPU time | 152.32 seconds |
| Started | Oct 02 07:15:09 PM UTC 24 |
| Finished | Oct 02 07:17:45 PM UTC 24 |
| Peak memory | 203856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610481387 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1610481387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_rx_oversample.2357298519 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 6449720290 ps |
| CPU time | 73.27 seconds |
| Started | Oct 02 07:15:01 PM UTC 24 |
| Finished | Oct 02 07:16:16 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357298519 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2357298519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.834582043 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 38233036492 ps |
| CPU time | 16.77 seconds |
| Started | Oct 02 07:15:05 PM UTC 24 |
| Finished | Oct 02 07:15:23 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834582043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.834582043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.3597276995 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 4701860194 ps |
| CPU time | 1.3 seconds |
| Started | Oct 02 07:15:05 PM UTC 24 |
| Finished | Oct 02 07:15:07 PM UTC 24 |
| Peak memory | 203352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597276995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3597276995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_smoke.1413749669 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 709390884 ps |
| CPU time | 3.06 seconds |
| Started | Oct 02 07:14:52 PM UTC 24 |
| Finished | Oct 02 07:14:56 PM UTC 24 |
| Peak memory | 204040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413749669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1413749669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_stress_all.1459901914 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 313196818271 ps |
| CPU time | 745.54 seconds |
| Started | Oct 02 07:15:12 PM UTC 24 |
| Finished | Oct 02 07:27:46 PM UTC 24 |
| Peak memory | 219908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459901914 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1459901914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.1016032629 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1034001421 ps |
| CPU time | 2.17 seconds |
| Started | Oct 02 07:15:06 PM UTC 24 |
| Finished | Oct 02 07:15:09 PM UTC 24 |
| Peak memory | 203728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016032629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1016032629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_tx_rx.217549105 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 133961442722 ps |
| CPU time | 61.24 seconds |
| Started | Oct 02 07:14:54 PM UTC 24 |
| Finished | Oct 02 07:15:56 PM UTC 24 |
| Peak memory | 209464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217549105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.217549105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/22.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/220.uart_fifo_reset.3092835374 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 51617850513 ps |
| CPU time | 74.23 seconds |
| Started | Oct 02 07:41:23 PM UTC 24 |
| Finished | Oct 02 07:42:39 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092835374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3092835374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/220.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/221.uart_fifo_reset.927397029 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 38722162254 ps |
| CPU time | 72.44 seconds |
| Started | Oct 02 07:41:25 PM UTC 24 |
| Finished | Oct 02 07:42:39 PM UTC 24 |
| Peak memory | 209652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927397029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.927397029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/221.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/222.uart_fifo_reset.44130606 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 270084725547 ps |
| CPU time | 38.76 seconds |
| Started | Oct 02 07:41:25 PM UTC 24 |
| Finished | Oct 02 07:42:05 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44130606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.44130606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/222.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/223.uart_fifo_reset.624632625 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 29687215776 ps |
| CPU time | 25.45 seconds |
| Started | Oct 02 07:41:30 PM UTC 24 |
| Finished | Oct 02 07:41:56 PM UTC 24 |
| Peak memory | 207720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624632625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.624632625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/223.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/224.uart_fifo_reset.4092283682 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 96465946520 ps |
| CPU time | 63.03 seconds |
| Started | Oct 02 07:41:30 PM UTC 24 |
| Finished | Oct 02 07:42:34 PM UTC 24 |
| Peak memory | 209576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092283682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.4092283682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/224.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/225.uart_fifo_reset.3559739556 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 13450263257 ps |
| CPU time | 27.91 seconds |
| Started | Oct 02 07:41:30 PM UTC 24 |
| Finished | Oct 02 07:41:59 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559739556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3559739556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/225.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/226.uart_fifo_reset.2304908541 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 44933626836 ps |
| CPU time | 35.84 seconds |
| Started | Oct 02 07:41:31 PM UTC 24 |
| Finished | Oct 02 07:42:08 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304908541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2304908541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/226.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/227.uart_fifo_reset.3208683264 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 31730598516 ps |
| CPU time | 42.97 seconds |
| Started | Oct 02 07:41:31 PM UTC 24 |
| Finished | Oct 02 07:42:15 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208683264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3208683264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/227.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/228.uart_fifo_reset.1833361720 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 64441050389 ps |
| CPU time | 35.57 seconds |
| Started | Oct 02 07:41:32 PM UTC 24 |
| Finished | Oct 02 07:42:09 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833361720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1833361720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/228.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/229.uart_fifo_reset.3895370535 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 22820267973 ps |
| CPU time | 48.27 seconds |
| Started | Oct 02 07:41:33 PM UTC 24 |
| Finished | Oct 02 07:42:23 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895370535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3895370535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/229.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_alert_test.2580900865 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 87695922 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 07:15:57 PM UTC 24 |
| Finished | Oct 02 07:15:59 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580900865 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2580900865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.470068516 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 38335527156 ps |
| CPU time | 103.86 seconds |
| Started | Oct 02 07:15:23 PM UTC 24 |
| Finished | Oct 02 07:17:09 PM UTC 24 |
| Peak memory | 209168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470068516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.470068516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_fifo_reset.1671089245 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 109587585869 ps |
| CPU time | 255.36 seconds |
| Started | Oct 02 07:15:24 PM UTC 24 |
| Finished | Oct 02 07:19:44 PM UTC 24 |
| Peak memory | 208140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671089245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1671089245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_intr.3704275238 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 13908015078 ps |
| CPU time | 24.64 seconds |
| Started | Oct 02 07:15:24 PM UTC 24 |
| Finished | Oct 02 07:15:51 PM UTC 24 |
| Peak memory | 209320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704275238 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3704275238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.1931936287 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 42692069291 ps |
| CPU time | 411.4 seconds |
| Started | Oct 02 07:15:50 PM UTC 24 |
| Finished | Oct 02 07:22:47 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931936287 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1931936287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_loopback.158879920 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 3200873696 ps |
| CPU time | 7.94 seconds |
| Started | Oct 02 07:15:46 PM UTC 24 |
| Finished | Oct 02 07:15:55 PM UTC 24 |
| Peak memory | 207672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158879920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 23.uart_loopback.158879920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_noise_filter.1724719496 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 206208873062 ps |
| CPU time | 66.8 seconds |
| Started | Oct 02 07:15:28 PM UTC 24 |
| Finished | Oct 02 07:16:38 PM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724719496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1724719496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_perf.1994257954 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 31869614623 ps |
| CPU time | 1505.24 seconds |
| Started | Oct 02 07:15:49 PM UTC 24 |
| Finished | Oct 02 07:41:14 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994257954 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1994257954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_rx_oversample.2727546912 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 5061698694 ps |
| CPU time | 41.56 seconds |
| Started | Oct 02 07:15:24 PM UTC 24 |
| Finished | Oct 02 07:16:08 PM UTC 24 |
| Peak memory | 207944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727546912 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2727546912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.1288113982 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 182647892944 ps |
| CPU time | 31.95 seconds |
| Started | Oct 02 07:15:34 PM UTC 24 |
| Finished | Oct 02 07:16:07 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288113982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1288113982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.3441957850 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 6841433935 ps |
| CPU time | 29.95 seconds |
| Started | Oct 02 07:15:30 PM UTC 24 |
| Finished | Oct 02 07:16:02 PM UTC 24 |
| Peak memory | 203508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441957850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3441957850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_smoke.1778960968 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 6283395815 ps |
| CPU time | 23.8 seconds |
| Started | Oct 02 07:15:20 PM UTC 24 |
| Finished | Oct 02 07:15:45 PM UTC 24 |
| Peak memory | 204168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778960968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1778960968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_stress_all.439124162 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 135845387634 ps |
| CPU time | 319.12 seconds |
| Started | Oct 02 07:15:56 PM UTC 24 |
| Finished | Oct 02 07:21:20 PM UTC 24 |
| Peak memory | 203704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439124162 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.439124162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.317022576 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 6118078485 ps |
| CPU time | 32.47 seconds |
| Started | Oct 02 07:15:51 PM UTC 24 |
| Finished | Oct 02 07:16:25 PM UTC 24 |
| Peak memory | 220352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=317022576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all_ with_rand_reset.317022576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.2367701856 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 7016187699 ps |
| CPU time | 27.76 seconds |
| Started | Oct 02 07:15:44 PM UTC 24 |
| Finished | Oct 02 07:16:13 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367701856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2367701856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/23.uart_tx_rx.4275914184 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 117282476821 ps |
| CPU time | 66.94 seconds |
| Started | Oct 02 07:15:21 PM UTC 24 |
| Finished | Oct 02 07:16:30 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275914184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.4275914184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/23.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3307390627 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 51305158958 ps |
| CPU time | 83.42 seconds |
| Started | Oct 02 07:41:36 PM UTC 24 |
| Finished | Oct 02 07:43:02 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307390627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3307390627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/230.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/231.uart_fifo_reset.849666970 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 15713308285 ps |
| CPU time | 15.52 seconds |
| Started | Oct 02 07:41:36 PM UTC 24 |
| Finished | Oct 02 07:41:53 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849666970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.849666970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/231.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/232.uart_fifo_reset.1791856351 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 151588603666 ps |
| CPU time | 72 seconds |
| Started | Oct 02 07:41:36 PM UTC 24 |
| Finished | Oct 02 07:42:50 PM UTC 24 |
| Peak memory | 204088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791856351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1791856351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/232.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/233.uart_fifo_reset.969297601 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 30472292914 ps |
| CPU time | 66.24 seconds |
| Started | Oct 02 07:41:47 PM UTC 24 |
| Finished | Oct 02 07:42:54 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969297601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.969297601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/233.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/234.uart_fifo_reset.3928197739 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 86023243411 ps |
| CPU time | 220.57 seconds |
| Started | Oct 02 07:41:48 PM UTC 24 |
| Finished | Oct 02 07:45:32 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928197739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3928197739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/234.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/235.uart_fifo_reset.932872613 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 37435642696 ps |
| CPU time | 31.61 seconds |
| Started | Oct 02 07:41:49 PM UTC 24 |
| Finished | Oct 02 07:42:22 PM UTC 24 |
| Peak memory | 209184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932872613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.932872613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/235.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/236.uart_fifo_reset.2333207563 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 164958057417 ps |
| CPU time | 212.79 seconds |
| Started | Oct 02 07:41:52 PM UTC 24 |
| Finished | Oct 02 07:45:28 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333207563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2333207563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/236.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/237.uart_fifo_reset.3033169498 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 94482927949 ps |
| CPU time | 174.67 seconds |
| Started | Oct 02 07:41:52 PM UTC 24 |
| Finished | Oct 02 07:44:49 PM UTC 24 |
| Peak memory | 209392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033169498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3033169498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/237.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/238.uart_fifo_reset.29160528 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 16690720972 ps |
| CPU time | 28.06 seconds |
| Started | Oct 02 07:41:52 PM UTC 24 |
| Finished | Oct 02 07:42:22 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29160528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.29160528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/238.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/239.uart_fifo_reset.674932894 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 17002494185 ps |
| CPU time | 37.13 seconds |
| Started | Oct 02 07:41:52 PM UTC 24 |
| Finished | Oct 02 07:42:31 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674932894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.674932894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/239.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_alert_test.3565735852 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 37838939 ps |
| CPU time | 0.85 seconds |
| Started | Oct 02 07:16:32 PM UTC 24 |
| Finished | Oct 02 07:16:34 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565735852 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3565735852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_fifo_full.3849707661 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 57331921501 ps |
| CPU time | 112.39 seconds |
| Started | Oct 02 07:16:03 PM UTC 24 |
| Finished | Oct 02 07:17:57 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849707661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3849707661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.2669482541 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 123264633697 ps |
| CPU time | 32.31 seconds |
| Started | Oct 02 07:16:05 PM UTC 24 |
| Finished | Oct 02 07:16:38 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669482541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2669482541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_fifo_reset.2143626537 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 64169047982 ps |
| CPU time | 165.51 seconds |
| Started | Oct 02 07:16:08 PM UTC 24 |
| Finished | Oct 02 07:18:56 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143626537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2143626537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_intr.262594966 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 45650154383 ps |
| CPU time | 33.87 seconds |
| Started | Oct 02 07:16:09 PM UTC 24 |
| Finished | Oct 02 07:16:44 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262594966 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.262594966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.1386768558 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 151344390048 ps |
| CPU time | 1525.8 seconds |
| Started | Oct 02 07:16:24 PM UTC 24 |
| Finished | Oct 02 07:42:08 PM UTC 24 |
| Peak memory | 212984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386768558 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1386768558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_loopback.2669954939 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 4138485681 ps |
| CPU time | 9.21 seconds |
| Started | Oct 02 07:16:20 PM UTC 24 |
| Finished | Oct 02 07:16:31 PM UTC 24 |
| Peak memory | 204112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669954939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2669954939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_noise_filter.2151162927 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 152338120383 ps |
| CPU time | 274.17 seconds |
| Started | Oct 02 07:16:09 PM UTC 24 |
| Finished | Oct 02 07:20:47 PM UTC 24 |
| Peak memory | 209612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151162927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2151162927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_perf.4154763204 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 17950913645 ps |
| CPU time | 1100.21 seconds |
| Started | Oct 02 07:16:24 PM UTC 24 |
| Finished | Oct 02 07:34:57 PM UTC 24 |
| Peak memory | 207304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154763204 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.4154763204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_rx_oversample.1765364098 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1796726925 ps |
| CPU time | 9.97 seconds |
| Started | Oct 02 07:16:09 PM UTC 24 |
| Finished | Oct 02 07:16:20 PM UTC 24 |
| Peak memory | 208200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765364098 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1765364098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.3230798314 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 34786551493 ps |
| CPU time | 70.77 seconds |
| Started | Oct 02 07:16:16 PM UTC 24 |
| Finished | Oct 02 07:17:29 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230798314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3230798314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.3329699073 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 45048640351 ps |
| CPU time | 27.77 seconds |
| Started | Oct 02 07:16:14 PM UTC 24 |
| Finished | Oct 02 07:16:43 PM UTC 24 |
| Peak memory | 203504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329699073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3329699073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_smoke.1316671712 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 480406096 ps |
| CPU time | 1.99 seconds |
| Started | Oct 02 07:16:00 PM UTC 24 |
| Finished | Oct 02 07:16:03 PM UTC 24 |
| Peak memory | 203340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316671712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1316671712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_stress_all.3678686948 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 265190346898 ps |
| CPU time | 2187.76 seconds |
| Started | Oct 02 07:16:31 PM UTC 24 |
| Finished | Oct 02 07:53:24 PM UTC 24 |
| Peak memory | 207496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678686948 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3678686948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.1413597083 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 8419546772 ps |
| CPU time | 30.7 seconds |
| Started | Oct 02 07:16:26 PM UTC 24 |
| Finished | Oct 02 07:16:58 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1413597083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all _with_rand_reset.1413597083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.2918310735 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2146876741 ps |
| CPU time | 3.88 seconds |
| Started | Oct 02 07:16:17 PM UTC 24 |
| Finished | Oct 02 07:16:22 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918310735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2918310735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_tx_rx.1604339188 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 131625436145 ps |
| CPU time | 61.15 seconds |
| Started | Oct 02 07:16:02 PM UTC 24 |
| Finished | Oct 02 07:17:04 PM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604339188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1604339188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/24.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/240.uart_fifo_reset.2468306607 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 92703325535 ps |
| CPU time | 162.6 seconds |
| Started | Oct 02 07:41:54 PM UTC 24 |
| Finished | Oct 02 07:44:39 PM UTC 24 |
| Peak memory | 204036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468306607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2468306607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/240.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/241.uart_fifo_reset.1074832824 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 25178884566 ps |
| CPU time | 53.5 seconds |
| Started | Oct 02 07:41:54 PM UTC 24 |
| Finished | Oct 02 07:42:49 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074832824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1074832824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/241.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/242.uart_fifo_reset.4031138706 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 80726648972 ps |
| CPU time | 47.91 seconds |
| Started | Oct 02 07:41:54 PM UTC 24 |
| Finished | Oct 02 07:42:44 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031138706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.4031138706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/242.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/244.uart_fifo_reset.931858466 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 40360293953 ps |
| CPU time | 85.58 seconds |
| Started | Oct 02 07:41:57 PM UTC 24 |
| Finished | Oct 02 07:43:25 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931858466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.931858466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/244.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/245.uart_fifo_reset.238303428 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 370133147815 ps |
| CPU time | 471.81 seconds |
| Started | Oct 02 07:41:57 PM UTC 24 |
| Finished | Oct 02 07:49:56 PM UTC 24 |
| Peak memory | 207100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238303428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.238303428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/245.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/246.uart_fifo_reset.697309411 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 22538417105 ps |
| CPU time | 21.28 seconds |
| Started | Oct 02 07:42:00 PM UTC 24 |
| Finished | Oct 02 07:42:22 PM UTC 24 |
| Peak memory | 203712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697309411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.697309411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/246.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/247.uart_fifo_reset.2556612193 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 106942872339 ps |
| CPU time | 64.06 seconds |
| Started | Oct 02 07:42:00 PM UTC 24 |
| Finished | Oct 02 07:43:06 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556612193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2556612193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/247.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3502733745 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 14712816192 ps |
| CPU time | 16.69 seconds |
| Started | Oct 02 07:42:01 PM UTC 24 |
| Finished | Oct 02 07:42:19 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502733745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3502733745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/248.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/249.uart_fifo_reset.4274151520 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 44696394447 ps |
| CPU time | 72.43 seconds |
| Started | Oct 02 07:42:03 PM UTC 24 |
| Finished | Oct 02 07:43:17 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274151520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.4274151520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/249.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_alert_test.1203738905 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 13994574 ps |
| CPU time | 0.94 seconds |
| Started | Oct 02 07:17:17 PM UTC 24 |
| Finished | Oct 02 07:17:19 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203738905 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1203738905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_fifo_full.3430591560 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 71581898529 ps |
| CPU time | 114.2 seconds |
| Started | Oct 02 07:16:39 PM UTC 24 |
| Finished | Oct 02 07:18:35 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430591560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3430591560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.780873377 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 106383379890 ps |
| CPU time | 272.32 seconds |
| Started | Oct 02 07:16:39 PM UTC 24 |
| Finished | Oct 02 07:21:15 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780873377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.780873377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_fifo_reset.322103110 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 94061894281 ps |
| CPU time | 161.15 seconds |
| Started | Oct 02 07:16:44 PM UTC 24 |
| Finished | Oct 02 07:19:28 PM UTC 24 |
| Peak memory | 209468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322103110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.322103110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_intr.588110777 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 30704262784 ps |
| CPU time | 81.1 seconds |
| Started | Oct 02 07:16:47 PM UTC 24 |
| Finished | Oct 02 07:18:10 PM UTC 24 |
| Peak memory | 209060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588110777 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.588110777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.3844638524 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 54460478099 ps |
| CPU time | 588.49 seconds |
| Started | Oct 02 07:17:08 PM UTC 24 |
| Finished | Oct 02 07:27:05 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844638524 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3844638524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_loopback.2853222846 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 6326874867 ps |
| CPU time | 15.26 seconds |
| Started | Oct 02 07:17:05 PM UTC 24 |
| Finished | Oct 02 07:17:21 PM UTC 24 |
| Peak memory | 204176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853222846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2853222846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_noise_filter.1002617749 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 89386654368 ps |
| CPU time | 60.73 seconds |
| Started | Oct 02 07:16:51 PM UTC 24 |
| Finished | Oct 02 07:17:53 PM UTC 24 |
| Peak memory | 218772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002617749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1002617749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_perf.1799364883 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 21488087173 ps |
| CPU time | 260.13 seconds |
| Started | Oct 02 07:17:08 PM UTC 24 |
| Finished | Oct 02 07:21:33 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799364883 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1799364883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_rx_oversample.1351952992 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 4577016830 ps |
| CPU time | 15.11 seconds |
| Started | Oct 02 07:16:45 PM UTC 24 |
| Finished | Oct 02 07:17:02 PM UTC 24 |
| Peak memory | 208388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351952992 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1351952992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.2700390068 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 8260916685 ps |
| CPU time | 23.3 seconds |
| Started | Oct 02 07:17:00 PM UTC 24 |
| Finished | Oct 02 07:17:24 PM UTC 24 |
| Peak memory | 203912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700390068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2700390068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.2305305956 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 3275645448 ps |
| CPU time | 7.3 seconds |
| Started | Oct 02 07:16:59 PM UTC 24 |
| Finished | Oct 02 07:17:07 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305305956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2305305956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_smoke.1498032191 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 865841247 ps |
| CPU time | 2.64 seconds |
| Started | Oct 02 07:16:35 PM UTC 24 |
| Finished | Oct 02 07:16:39 PM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498032191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1498032191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_stress_all.1212003613 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 48974543694 ps |
| CPU time | 41.68 seconds |
| Started | Oct 02 07:17:14 PM UTC 24 |
| Finished | Oct 02 07:17:58 PM UTC 24 |
| Peak memory | 203708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212003613 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1212003613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.441259925 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 4449344518 ps |
| CPU time | 86.05 seconds |
| Started | Oct 02 07:17:10 PM UTC 24 |
| Finished | Oct 02 07:18:39 PM UTC 24 |
| Peak memory | 225832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=441259925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all_ with_rand_reset.441259925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.1657184470 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 4117113675 ps |
| CPU time | 3.41 seconds |
| Started | Oct 02 07:17:03 PM UTC 24 |
| Finished | Oct 02 07:17:07 PM UTC 24 |
| Peak memory | 207968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657184470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1657184470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_tx_rx.3076292563 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 114774823581 ps |
| CPU time | 65.47 seconds |
| Started | Oct 02 07:16:39 PM UTC 24 |
| Finished | Oct 02 07:17:46 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076292563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3076292563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/25.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/250.uart_fifo_reset.625671854 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 86127009845 ps |
| CPU time | 178.66 seconds |
| Started | Oct 02 07:42:04 PM UTC 24 |
| Finished | Oct 02 07:45:06 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625671854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.625671854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/250.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/252.uart_fifo_reset.3855462826 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 196893206819 ps |
| CPU time | 49.2 seconds |
| Started | Oct 02 07:42:06 PM UTC 24 |
| Finished | Oct 02 07:42:57 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855462826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3855462826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/252.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/253.uart_fifo_reset.490099724 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 218662669420 ps |
| CPU time | 31.82 seconds |
| Started | Oct 02 07:42:08 PM UTC 24 |
| Finished | Oct 02 07:42:42 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490099724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.490099724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/253.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/254.uart_fifo_reset.838981359 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 31278936217 ps |
| CPU time | 63.6 seconds |
| Started | Oct 02 07:42:08 PM UTC 24 |
| Finished | Oct 02 07:43:14 PM UTC 24 |
| Peak memory | 209412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838981359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.838981359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/254.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/256.uart_fifo_reset.1092839801 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 91388781810 ps |
| CPU time | 43.23 seconds |
| Started | Oct 02 07:42:09 PM UTC 24 |
| Finished | Oct 02 07:42:54 PM UTC 24 |
| Peak memory | 207600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092839801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1092839801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/256.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/257.uart_fifo_reset.204002033 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 34940550513 ps |
| CPU time | 93.42 seconds |
| Started | Oct 02 07:42:09 PM UTC 24 |
| Finished | Oct 02 07:43:45 PM UTC 24 |
| Peak memory | 209396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204002033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.204002033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/257.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/258.uart_fifo_reset.3947645155 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 137310002862 ps |
| CPU time | 101.58 seconds |
| Started | Oct 02 07:42:12 PM UTC 24 |
| Finished | Oct 02 07:43:55 PM UTC 24 |
| Peak memory | 209508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947645155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3947645155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/258.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/259.uart_fifo_reset.2000501575 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 53051212909 ps |
| CPU time | 51.41 seconds |
| Started | Oct 02 07:42:12 PM UTC 24 |
| Finished | Oct 02 07:43:05 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000501575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2000501575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/259.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_alert_test.205439000 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 11563765 ps |
| CPU time | 0.76 seconds |
| Started | Oct 02 07:18:08 PM UTC 24 |
| Finished | Oct 02 07:18:10 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205439000 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.205439000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_fifo_full.3202317613 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 54649684769 ps |
| CPU time | 83.5 seconds |
| Started | Oct 02 07:17:26 PM UTC 24 |
| Finished | Oct 02 07:18:51 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202317613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3202317613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.2563711210 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 69393969511 ps |
| CPU time | 46.62 seconds |
| Started | Oct 02 07:17:30 PM UTC 24 |
| Finished | Oct 02 07:18:18 PM UTC 24 |
| Peak memory | 203712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563711210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2563711210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_fifo_reset.670804889 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 122457288117 ps |
| CPU time | 35.17 seconds |
| Started | Oct 02 07:17:31 PM UTC 24 |
| Finished | Oct 02 07:18:07 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670804889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.670804889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_intr.1769295631 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 152460380659 ps |
| CPU time | 61.62 seconds |
| Started | Oct 02 07:17:45 PM UTC 24 |
| Finished | Oct 02 07:18:48 PM UTC 24 |
| Peak memory | 203968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769295631 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1769295631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.813412213 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 123960071481 ps |
| CPU time | 1251.78 seconds |
| Started | Oct 02 07:18:02 PM UTC 24 |
| Finished | Oct 02 07:39:09 PM UTC 24 |
| Peak memory | 212656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813412213 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.813412213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_loopback.792039466 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 5450280263 ps |
| CPU time | 10.49 seconds |
| Started | Oct 02 07:17:59 PM UTC 24 |
| Finished | Oct 02 07:18:10 PM UTC 24 |
| Peak memory | 203840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792039466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 26.uart_loopback.792039466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_noise_filter.2540295699 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 14726939385 ps |
| CPU time | 58.41 seconds |
| Started | Oct 02 07:17:47 PM UTC 24 |
| Finished | Oct 02 07:18:47 PM UTC 24 |
| Peak memory | 209404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540295699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2540295699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_perf.1533528692 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 19855773953 ps |
| CPU time | 960.8 seconds |
| Started | Oct 02 07:18:01 PM UTC 24 |
| Finished | Oct 02 07:34:14 PM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533528692 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1533528692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_rx_oversample.3814858703 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 7568663611 ps |
| CPU time | 19.66 seconds |
| Started | Oct 02 07:17:39 PM UTC 24 |
| Finished | Oct 02 07:18:00 PM UTC 24 |
| Peak memory | 208596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814858703 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3814858703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.1905550537 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 28133166359 ps |
| CPU time | 17.2 seconds |
| Started | Oct 02 07:17:54 PM UTC 24 |
| Finished | Oct 02 07:18:13 PM UTC 24 |
| Peak memory | 208284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905550537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1905550537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.15090208 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 32389781355 ps |
| CPU time | 60.51 seconds |
| Started | Oct 02 07:17:53 PM UTC 24 |
| Finished | Oct 02 07:18:55 PM UTC 24 |
| Peak memory | 203836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15090208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.15090208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_smoke.3796747127 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 5488442241 ps |
| CPU time | 30.98 seconds |
| Started | Oct 02 07:17:21 PM UTC 24 |
| Finished | Oct 02 07:17:53 PM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796747127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3796747127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_stress_all.2017279505 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 31312923857 ps |
| CPU time | 225.12 seconds |
| Started | Oct 02 07:18:07 PM UTC 24 |
| Finished | Oct 02 07:21:56 PM UTC 24 |
| Peak memory | 205816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017279505 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2017279505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.455250975 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 8054488546 ps |
| CPU time | 26.83 seconds |
| Started | Oct 02 07:18:06 PM UTC 24 |
| Finished | Oct 02 07:18:34 PM UTC 24 |
| Peak memory | 220236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=455250975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all_ with_rand_reset.455250975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.987271421 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 762654463 ps |
| CPU time | 5.43 seconds |
| Started | Oct 02 07:17:59 PM UTC 24 |
| Finished | Oct 02 07:18:05 PM UTC 24 |
| Peak memory | 203996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987271421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.987271421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/26.uart_tx_rx.3336416794 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 50612364663 ps |
| CPU time | 131.82 seconds |
| Started | Oct 02 07:17:23 PM UTC 24 |
| Finished | Oct 02 07:19:37 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336416794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3336416794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/26.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/260.uart_fifo_reset.2059858326 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 26452897379 ps |
| CPU time | 89.38 seconds |
| Started | Oct 02 07:42:14 PM UTC 24 |
| Finished | Oct 02 07:43:45 PM UTC 24 |
| Peak memory | 203832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059858326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2059858326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/260.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/261.uart_fifo_reset.1052529870 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 122537534568 ps |
| CPU time | 300.5 seconds |
| Started | Oct 02 07:42:16 PM UTC 24 |
| Finished | Oct 02 07:47:21 PM UTC 24 |
| Peak memory | 209212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052529870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1052529870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/261.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/262.uart_fifo_reset.2926568114 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 44107686862 ps |
| CPU time | 89.39 seconds |
| Started | Oct 02 07:42:20 PM UTC 24 |
| Finished | Oct 02 07:43:51 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926568114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2926568114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/262.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/263.uart_fifo_reset.2788366925 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 23121314950 ps |
| CPU time | 21.77 seconds |
| Started | Oct 02 07:42:22 PM UTC 24 |
| Finished | Oct 02 07:42:45 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788366925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2788366925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/263.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/264.uart_fifo_reset.3015809025 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 129425836847 ps |
| CPU time | 68.83 seconds |
| Started | Oct 02 07:42:22 PM UTC 24 |
| Finished | Oct 02 07:43:33 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015809025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3015809025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/264.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/265.uart_fifo_reset.3150980360 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 63942305847 ps |
| CPU time | 60.17 seconds |
| Started | Oct 02 07:42:23 PM UTC 24 |
| Finished | Oct 02 07:43:25 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150980360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3150980360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/265.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/266.uart_fifo_reset.3765847305 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 24755723976 ps |
| CPU time | 27.28 seconds |
| Started | Oct 02 07:42:23 PM UTC 24 |
| Finished | Oct 02 07:42:52 PM UTC 24 |
| Peak memory | 209512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765847305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3765847305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/266.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/267.uart_fifo_reset.1575371046 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 42958733554 ps |
| CPU time | 97.61 seconds |
| Started | Oct 02 07:42:24 PM UTC 24 |
| Finished | Oct 02 07:44:04 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575371046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1575371046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/267.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/269.uart_fifo_reset.2791003480 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 53316881783 ps |
| CPU time | 37.89 seconds |
| Started | Oct 02 07:42:28 PM UTC 24 |
| Finished | Oct 02 07:43:08 PM UTC 24 |
| Peak memory | 204040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791003480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2791003480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/269.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_alert_test.618781236 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 12362193 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 07:18:50 PM UTC 24 |
| Finished | Oct 02 07:18:51 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618781236 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.618781236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_fifo_full.3046468813 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 71136318924 ps |
| CPU time | 104.49 seconds |
| Started | Oct 02 07:18:11 PM UTC 24 |
| Finished | Oct 02 07:19:58 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046468813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3046468813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.3727357579 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 24528544824 ps |
| CPU time | 65.16 seconds |
| Started | Oct 02 07:18:11 PM UTC 24 |
| Finished | Oct 02 07:19:18 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727357579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3727357579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_fifo_reset.1892268389 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 53737143805 ps |
| CPU time | 98.84 seconds |
| Started | Oct 02 07:18:13 PM UTC 24 |
| Finished | Oct 02 07:19:54 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892268389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1892268389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_intr.249234378 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 17383339079 ps |
| CPU time | 50.85 seconds |
| Started | Oct 02 07:18:18 PM UTC 24 |
| Finished | Oct 02 07:19:10 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249234378 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.249234378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.2303514127 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 176083182367 ps |
| CPU time | 1415.34 seconds |
| Started | Oct 02 07:18:41 PM UTC 24 |
| Finished | Oct 02 07:42:33 PM UTC 24 |
| Peak memory | 212908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303514127 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2303514127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_loopback.1637971979 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 3979353486 ps |
| CPU time | 7.43 seconds |
| Started | Oct 02 07:18:39 PM UTC 24 |
| Finished | Oct 02 07:18:48 PM UTC 24 |
| Peak memory | 208152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637971979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1637971979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_noise_filter.849122531 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 75543007464 ps |
| CPU time | 76.28 seconds |
| Started | Oct 02 07:18:19 PM UTC 24 |
| Finished | Oct 02 07:19:37 PM UTC 24 |
| Peak memory | 209684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849122531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.849122531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_perf.1754262040 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 9452269285 ps |
| CPU time | 133.48 seconds |
| Started | Oct 02 07:18:39 PM UTC 24 |
| Finished | Oct 02 07:20:55 PM UTC 24 |
| Peak memory | 209456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754262040 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1754262040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_rx_oversample.2872031189 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 7347640199 ps |
| CPU time | 23.39 seconds |
| Started | Oct 02 07:18:14 PM UTC 24 |
| Finished | Oct 02 07:18:38 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872031189 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2872031189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.3576155189 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 24563013915 ps |
| CPU time | 14.54 seconds |
| Started | Oct 02 07:18:35 PM UTC 24 |
| Finished | Oct 02 07:18:51 PM UTC 24 |
| Peak memory | 209136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576155189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3576155189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.3172576228 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 76834611019 ps |
| CPU time | 145.91 seconds |
| Started | Oct 02 07:18:34 PM UTC 24 |
| Finished | Oct 02 07:21:03 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172576228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3172576228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_smoke.1766504760 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 135453840 ps |
| CPU time | 1.14 seconds |
| Started | Oct 02 07:18:10 PM UTC 24 |
| Finished | Oct 02 07:18:12 PM UTC 24 |
| Peak memory | 203340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766504760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1766504760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_stress_all.666477841 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 495323048301 ps |
| CPU time | 141.87 seconds |
| Started | Oct 02 07:18:48 PM UTC 24 |
| Finished | Oct 02 07:21:13 PM UTC 24 |
| Peak memory | 208192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666477841 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.666477841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.3497593401 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 5516607334 ps |
| CPU time | 44.01 seconds |
| Started | Oct 02 07:18:48 PM UTC 24 |
| Finished | Oct 02 07:19:34 PM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3497593401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all _with_rand_reset.3497593401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.3019394453 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 859642240 ps |
| CPU time | 3.35 seconds |
| Started | Oct 02 07:18:36 PM UTC 24 |
| Finished | Oct 02 07:18:41 PM UTC 24 |
| Peak memory | 204056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019394453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3019394453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_tx_rx.4032332987 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 40170804076 ps |
| CPU time | 43 seconds |
| Started | Oct 02 07:18:10 PM UTC 24 |
| Finished | Oct 02 07:18:55 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032332987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4032332987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/27.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/270.uart_fifo_reset.367595099 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 36932220117 ps |
| CPU time | 20.72 seconds |
| Started | Oct 02 07:42:32 PM UTC 24 |
| Finished | Oct 02 07:42:54 PM UTC 24 |
| Peak memory | 209320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367595099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.367595099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/270.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/271.uart_fifo_reset.584322554 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 120663711925 ps |
| CPU time | 45.08 seconds |
| Started | Oct 02 07:42:34 PM UTC 24 |
| Finished | Oct 02 07:43:20 PM UTC 24 |
| Peak memory | 209028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584322554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.584322554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/271.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/272.uart_fifo_reset.283917532 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 110198721472 ps |
| CPU time | 62.12 seconds |
| Started | Oct 02 07:42:35 PM UTC 24 |
| Finished | Oct 02 07:43:39 PM UTC 24 |
| Peak memory | 209224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283917532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.283917532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/272.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/273.uart_fifo_reset.1001146341 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 90876110466 ps |
| CPU time | 89.35 seconds |
| Started | Oct 02 07:42:35 PM UTC 24 |
| Finished | Oct 02 07:44:06 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001146341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1001146341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/273.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/274.uart_fifo_reset.3354245306 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 28740251423 ps |
| CPU time | 30.36 seconds |
| Started | Oct 02 07:42:40 PM UTC 24 |
| Finished | Oct 02 07:43:12 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354245306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3354245306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/274.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/275.uart_fifo_reset.3081227308 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 166777145960 ps |
| CPU time | 805.58 seconds |
| Started | Oct 02 07:42:40 PM UTC 24 |
| Finished | Oct 02 07:56:15 PM UTC 24 |
| Peak memory | 212852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081227308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3081227308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/275.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/276.uart_fifo_reset.4105968784 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 198562925683 ps |
| CPU time | 208.08 seconds |
| Started | Oct 02 07:42:42 PM UTC 24 |
| Finished | Oct 02 07:46:13 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105968784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.4105968784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/276.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/278.uart_fifo_reset.4118355441 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 41183578369 ps |
| CPU time | 21.89 seconds |
| Started | Oct 02 07:42:43 PM UTC 24 |
| Finished | Oct 02 07:43:07 PM UTC 24 |
| Peak memory | 209024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118355441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.4118355441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/278.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2390651020 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 25682299395 ps |
| CPU time | 66.67 seconds |
| Started | Oct 02 07:42:44 PM UTC 24 |
| Finished | Oct 02 07:43:53 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390651020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2390651020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/279.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_alert_test.1736574619 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 13431105 ps |
| CPU time | 0.87 seconds |
| Started | Oct 02 07:19:32 PM UTC 24 |
| Finished | Oct 02 07:19:34 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736574619 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1736574619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_fifo_full.620411026 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 113104029216 ps |
| CPU time | 103.5 seconds |
| Started | Oct 02 07:18:53 PM UTC 24 |
| Finished | Oct 02 07:20:38 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620411026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.620411026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.3565102297 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 36342825461 ps |
| CPU time | 115.12 seconds |
| Started | Oct 02 07:18:56 PM UTC 24 |
| Finished | Oct 02 07:20:53 PM UTC 24 |
| Peak memory | 203716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565102297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3565102297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_fifo_reset.2065567626 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 23559569318 ps |
| CPU time | 34.06 seconds |
| Started | Oct 02 07:18:56 PM UTC 24 |
| Finished | Oct 02 07:19:31 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065567626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2065567626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_intr.2673703303 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 29545380559 ps |
| CPU time | 45.31 seconds |
| Started | Oct 02 07:18:59 PM UTC 24 |
| Finished | Oct 02 07:19:46 PM UTC 24 |
| Peak memory | 207924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673703303 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2673703303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.351335540 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 164099304806 ps |
| CPU time | 1390.49 seconds |
| Started | Oct 02 07:19:15 PM UTC 24 |
| Finished | Oct 02 07:42:41 PM UTC 24 |
| Peak memory | 212640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351335540 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.351335540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_loopback.3609346251 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 6131651756 ps |
| CPU time | 22.93 seconds |
| Started | Oct 02 07:19:12 PM UTC 24 |
| Finished | Oct 02 07:19:36 PM UTC 24 |
| Peak memory | 207892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609346251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3609346251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_noise_filter.2957038300 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 117674085140 ps |
| CPU time | 103.05 seconds |
| Started | Oct 02 07:19:05 PM UTC 24 |
| Finished | Oct 02 07:20:50 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957038300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2957038300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_perf.2816373834 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 15434058087 ps |
| CPU time | 372.64 seconds |
| Started | Oct 02 07:19:14 PM UTC 24 |
| Finished | Oct 02 07:25:32 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816373834 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2816373834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_rx_oversample.2513775328 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 7571891121 ps |
| CPU time | 71.61 seconds |
| Started | Oct 02 07:18:57 PM UTC 24 |
| Finished | Oct 02 07:20:11 PM UTC 24 |
| Peak memory | 208336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513775328 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2513775328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.3969163368 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 32807018156 ps |
| CPU time | 29.04 seconds |
| Started | Oct 02 07:19:09 PM UTC 24 |
| Finished | Oct 02 07:19:40 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969163368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3969163368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.1726150515 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 6591974911 ps |
| CPU time | 5.07 seconds |
| Started | Oct 02 07:19:06 PM UTC 24 |
| Finished | Oct 02 07:19:12 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726150515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1726150515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_smoke.42729557 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 5356321105 ps |
| CPU time | 11.41 seconds |
| Started | Oct 02 07:18:52 PM UTC 24 |
| Finished | Oct 02 07:19:04 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42729557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 28.uart_smoke.42729557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_stress_all.1004522864 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 303241167183 ps |
| CPU time | 425.79 seconds |
| Started | Oct 02 07:19:29 PM UTC 24 |
| Finished | Oct 02 07:26:41 PM UTC 24 |
| Peak memory | 205824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004522864 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1004522864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.1506827304 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 6546892963 ps |
| CPU time | 53.63 seconds |
| Started | Oct 02 07:19:19 PM UTC 24 |
| Finished | Oct 02 07:20:14 PM UTC 24 |
| Peak memory | 222464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1506827304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all _with_rand_reset.1506827304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.4020744370 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1299640845 ps |
| CPU time | 2.84 seconds |
| Started | Oct 02 07:19:10 PM UTC 24 |
| Finished | Oct 02 07:19:14 PM UTC 24 |
| Peak memory | 203984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020744370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.4020744370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_tx_rx.269700237 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 40283196359 ps |
| CPU time | 64.23 seconds |
| Started | Oct 02 07:18:52 PM UTC 24 |
| Finished | Oct 02 07:19:58 PM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269700237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.269700237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/28.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/280.uart_fifo_reset.1259330247 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 43714265947 ps |
| CPU time | 39.76 seconds |
| Started | Oct 02 07:42:45 PM UTC 24 |
| Finished | Oct 02 07:43:27 PM UTC 24 |
| Peak memory | 203712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259330247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1259330247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/280.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/281.uart_fifo_reset.2085500717 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 91827909310 ps |
| CPU time | 140.73 seconds |
| Started | Oct 02 07:42:47 PM UTC 24 |
| Finished | Oct 02 07:45:09 PM UTC 24 |
| Peak memory | 209104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085500717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2085500717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/281.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/282.uart_fifo_reset.1039237240 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 49547143890 ps |
| CPU time | 24.44 seconds |
| Started | Oct 02 07:42:50 PM UTC 24 |
| Finished | Oct 02 07:43:15 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039237240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1039237240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/282.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/283.uart_fifo_reset.2071700441 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 30401382670 ps |
| CPU time | 32.28 seconds |
| Started | Oct 02 07:42:51 PM UTC 24 |
| Finished | Oct 02 07:43:24 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071700441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2071700441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/283.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/284.uart_fifo_reset.399646552 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 123374648981 ps |
| CPU time | 62.04 seconds |
| Started | Oct 02 07:42:53 PM UTC 24 |
| Finished | Oct 02 07:43:56 PM UTC 24 |
| Peak memory | 209396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399646552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.399646552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/284.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/285.uart_fifo_reset.1682425796 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 68930864776 ps |
| CPU time | 48.13 seconds |
| Started | Oct 02 07:42:53 PM UTC 24 |
| Finished | Oct 02 07:43:42 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682425796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1682425796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/285.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/286.uart_fifo_reset.2253301998 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 25678745700 ps |
| CPU time | 30.99 seconds |
| Started | Oct 02 07:42:55 PM UTC 24 |
| Finished | Oct 02 07:43:27 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253301998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2253301998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/286.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/287.uart_fifo_reset.3961842808 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 43876315551 ps |
| CPU time | 115.27 seconds |
| Started | Oct 02 07:42:55 PM UTC 24 |
| Finished | Oct 02 07:44:53 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961842808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3961842808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/287.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/288.uart_fifo_reset.1760264717 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 51305720967 ps |
| CPU time | 84.14 seconds |
| Started | Oct 02 07:42:55 PM UTC 24 |
| Finished | Oct 02 07:44:21 PM UTC 24 |
| Peak memory | 209032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760264717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1760264717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/288.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/289.uart_fifo_reset.603014691 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 65821070447 ps |
| CPU time | 38.45 seconds |
| Started | Oct 02 07:42:58 PM UTC 24 |
| Finished | Oct 02 07:43:38 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603014691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.603014691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/289.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_alert_test.1389113105 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 11933470 ps |
| CPU time | 0.8 seconds |
| Started | Oct 02 07:19:59 PM UTC 24 |
| Finished | Oct 02 07:20:01 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389113105 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1389113105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_fifo_full.2379990877 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 240655869774 ps |
| CPU time | 218.91 seconds |
| Started | Oct 02 07:19:36 PM UTC 24 |
| Finished | Oct 02 07:23:19 PM UTC 24 |
| Peak memory | 209284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379990877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2379990877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.2894771711 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 15620602184 ps |
| CPU time | 14.57 seconds |
| Started | Oct 02 07:19:37 PM UTC 24 |
| Finished | Oct 02 07:19:53 PM UTC 24 |
| Peak memory | 204168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894771711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2894771711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_fifo_reset.103710959 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 65909117810 ps |
| CPU time | 170.21 seconds |
| Started | Oct 02 07:19:37 PM UTC 24 |
| Finished | Oct 02 07:22:31 PM UTC 24 |
| Peak memory | 203760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103710959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.103710959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_intr.1108609094 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 41670446526 ps |
| CPU time | 61.05 seconds |
| Started | Oct 02 07:19:41 PM UTC 24 |
| Finished | Oct 02 07:20:43 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108609094 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1108609094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.347569169 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 77852047686 ps |
| CPU time | 601.44 seconds |
| Started | Oct 02 07:19:55 PM UTC 24 |
| Finished | Oct 02 07:30:04 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347569169 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.347569169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_loopback.2759155244 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 3563019990 ps |
| CPU time | 5.46 seconds |
| Started | Oct 02 07:19:54 PM UTC 24 |
| Finished | Oct 02 07:20:01 PM UTC 24 |
| Peak memory | 208192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759155244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2759155244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_noise_filter.2478616670 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 229093629981 ps |
| CPU time | 163.25 seconds |
| Started | Oct 02 07:19:45 PM UTC 24 |
| Finished | Oct 02 07:22:31 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478616670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2478616670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_perf.1774263381 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 14493349471 ps |
| CPU time | 526.95 seconds |
| Started | Oct 02 07:19:55 PM UTC 24 |
| Finished | Oct 02 07:28:49 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774263381 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1774263381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_rx_oversample.1448544817 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2005460773 ps |
| CPU time | 12.89 seconds |
| Started | Oct 02 07:19:39 PM UTC 24 |
| Finished | Oct 02 07:19:53 PM UTC 24 |
| Peak memory | 207880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448544817 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1448544817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.1056393461 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 117564783649 ps |
| CPU time | 57.6 seconds |
| Started | Oct 02 07:19:47 PM UTC 24 |
| Finished | Oct 02 07:20:46 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056393461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1056393461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.511857202 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 4124861492 ps |
| CPU time | 13.28 seconds |
| Started | Oct 02 07:19:46 PM UTC 24 |
| Finished | Oct 02 07:20:00 PM UTC 24 |
| Peak memory | 203584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511857202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.511857202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_smoke.4059280761 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 5376209780 ps |
| CPU time | 18.39 seconds |
| Started | Oct 02 07:19:35 PM UTC 24 |
| Finished | Oct 02 07:19:55 PM UTC 24 |
| Peak memory | 203816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059280761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.uart_smoke.4059280761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.3403262600 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 4167985411 ps |
| CPU time | 75.65 seconds |
| Started | Oct 02 07:19:58 PM UTC 24 |
| Finished | Oct 02 07:21:16 PM UTC 24 |
| Peak memory | 218644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3403262600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all _with_rand_reset.3403262600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.1175778712 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1993043011 ps |
| CPU time | 2.91 seconds |
| Started | Oct 02 07:19:53 PM UTC 24 |
| Finished | Oct 02 07:19:57 PM UTC 24 |
| Peak memory | 203712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175778712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1175778712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_tx_rx.1871147264 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 56719059473 ps |
| CPU time | 51.54 seconds |
| Started | Oct 02 07:19:35 PM UTC 24 |
| Finished | Oct 02 07:20:28 PM UTC 24 |
| Peak memory | 203528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871147264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1871147264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/29.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/290.uart_fifo_reset.925744953 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 149587708603 ps |
| CPU time | 173.91 seconds |
| Started | Oct 02 07:43:02 PM UTC 24 |
| Finished | Oct 02 07:45:59 PM UTC 24 |
| Peak memory | 209664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925744953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.925744953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/290.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/291.uart_fifo_reset.1725264364 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 10663743964 ps |
| CPU time | 30.81 seconds |
| Started | Oct 02 07:43:05 PM UTC 24 |
| Finished | Oct 02 07:43:37 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725264364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1725264364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/291.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/292.uart_fifo_reset.1867124176 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 107284883780 ps |
| CPU time | 19.17 seconds |
| Started | Oct 02 07:43:06 PM UTC 24 |
| Finished | Oct 02 07:43:27 PM UTC 24 |
| Peak memory | 204168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867124176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1867124176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/292.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/293.uart_fifo_reset.1464815732 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 57961868626 ps |
| CPU time | 133.65 seconds |
| Started | Oct 02 07:43:08 PM UTC 24 |
| Finished | Oct 02 07:45:24 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464815732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1464815732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/293.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/294.uart_fifo_reset.1566604900 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 22806251853 ps |
| CPU time | 16.6 seconds |
| Started | Oct 02 07:43:09 PM UTC 24 |
| Finished | Oct 02 07:43:26 PM UTC 24 |
| Peak memory | 204044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566604900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1566604900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/294.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/295.uart_fifo_reset.2882057126 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 32860970606 ps |
| CPU time | 27.99 seconds |
| Started | Oct 02 07:43:13 PM UTC 24 |
| Finished | Oct 02 07:43:42 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882057126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2882057126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/295.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/296.uart_fifo_reset.3221590045 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 98883347250 ps |
| CPU time | 44.78 seconds |
| Started | Oct 02 07:43:14 PM UTC 24 |
| Finished | Oct 02 07:44:00 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221590045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3221590045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/296.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/299.uart_fifo_reset.3485614404 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 78698937272 ps |
| CPU time | 71.91 seconds |
| Started | Oct 02 07:43:17 PM UTC 24 |
| Finished | Oct 02 07:44:31 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485614404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3485614404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/299.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_alert_test.371110030 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 12530863 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 07:07:17 PM UTC 24 |
| Finished | Oct 02 07:07:20 PM UTC 24 |
| Peak memory | 203192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371110030 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.371110030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_fifo_full.1864403273 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 69776438483 ps |
| CPU time | 145.97 seconds |
| Started | Oct 02 07:07:12 PM UTC 24 |
| Finished | Oct 02 07:09:42 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864403273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1864403273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_fifo_reset.4264502739 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 45516221215 ps |
| CPU time | 85.41 seconds |
| Started | Oct 02 07:07:12 PM UTC 24 |
| Finished | Oct 02 07:08:41 PM UTC 24 |
| Peak memory | 203908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264502739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.4264502739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_intr.170987136 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 52535509518 ps |
| CPU time | 143.35 seconds |
| Started | Oct 02 07:07:12 PM UTC 24 |
| Finished | Oct 02 07:09:39 PM UTC 24 |
| Peak memory | 209180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170987136 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.170987136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.3177739464 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 186562965390 ps |
| CPU time | 636.21 seconds |
| Started | Oct 02 07:07:16 PM UTC 24 |
| Finished | Oct 02 07:18:01 PM UTC 24 |
| Peak memory | 213056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177739464 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3177739464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_loopback.4281030349 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8230368684 ps |
| CPU time | 4.24 seconds |
| Started | Oct 02 07:07:14 PM UTC 24 |
| Finished | Oct 02 07:07:19 PM UTC 24 |
| Peak memory | 203840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281030349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 3.uart_loopback.4281030349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_perf.3042161654 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 19550539258 ps |
| CPU time | 172.26 seconds |
| Started | Oct 02 07:07:16 PM UTC 24 |
| Finished | Oct 02 07:10:11 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042161654 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3042161654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_rx_oversample.1107152019 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1487701109 ps |
| CPU time | 4.75 seconds |
| Started | Oct 02 07:07:12 PM UTC 24 |
| Finished | Oct 02 07:07:19 PM UTC 24 |
| Peak memory | 207808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107152019 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1107152019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.24402945 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 74020106846 ps |
| CPU time | 40.51 seconds |
| Started | Oct 02 07:07:12 PM UTC 24 |
| Finished | Oct 02 07:07:55 PM UTC 24 |
| Peak memory | 209460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24402945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.24402945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.4154658010 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 85296657231 ps |
| CPU time | 98.6 seconds |
| Started | Oct 02 07:07:12 PM UTC 24 |
| Finished | Oct 02 07:08:54 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154658010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.4154658010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_sec_cm.55142426 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 84247311 ps |
| CPU time | 1.54 seconds |
| Started | Oct 02 07:07:17 PM UTC 24 |
| Finished | Oct 02 07:07:21 PM UTC 24 |
| Peak memory | 237828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55142426 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.55142426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_smoke.549997570 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 315695847 ps |
| CPU time | 1.61 seconds |
| Started | Oct 02 07:07:11 PM UTC 24 |
| Finished | Oct 02 07:07:16 PM UTC 24 |
| Peak memory | 203392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549997570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 3.uart_smoke.549997570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_stress_all.3251156051 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 208841875753 ps |
| CPU time | 479.31 seconds |
| Started | Oct 02 07:07:17 PM UTC 24 |
| Finished | Oct 02 07:15:24 PM UTC 24 |
| Peak memory | 218440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251156051 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3251156051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.631375182 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2213583032 ps |
| CPU time | 37.27 seconds |
| Started | Oct 02 07:07:16 PM UTC 24 |
| Finished | Oct 02 07:07:54 PM UTC 24 |
| Peak memory | 218312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=631375182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_w ith_rand_reset.631375182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.2697019997 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 834662190 ps |
| CPU time | 6.05 seconds |
| Started | Oct 02 07:07:13 PM UTC 24 |
| Finished | Oct 02 07:07:21 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697019997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2697019997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/3.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_alert_test.4066106971 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 17643658 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 07:20:56 PM UTC 24 |
| Finished | Oct 02 07:20:58 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066106971 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.4066106971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_fifo_full.3501916946 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 158234978047 ps |
| CPU time | 276.39 seconds |
| Started | Oct 02 07:20:02 PM UTC 24 |
| Finished | Oct 02 07:24:42 PM UTC 24 |
| Peak memory | 205824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501916946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3501916946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.3165952768 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 203114717548 ps |
| CPU time | 635.62 seconds |
| Started | Oct 02 07:20:06 PM UTC 24 |
| Finished | Oct 02 07:30:50 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165952768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3165952768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_fifo_reset.878553935 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 39746175353 ps |
| CPU time | 157.37 seconds |
| Started | Oct 02 07:20:11 PM UTC 24 |
| Finished | Oct 02 07:22:51 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878553935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.878553935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_intr.3043434099 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 225018283592 ps |
| CPU time | 244.88 seconds |
| Started | Oct 02 07:20:21 PM UTC 24 |
| Finished | Oct 02 07:24:29 PM UTC 24 |
| Peak memory | 207924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043434099 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3043434099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.1905364421 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 161617508810 ps |
| CPU time | 524.86 seconds |
| Started | Oct 02 07:20:48 PM UTC 24 |
| Finished | Oct 02 07:29:39 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905364421 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1905364421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_loopback.1206665759 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 6369115160 ps |
| CPU time | 29.45 seconds |
| Started | Oct 02 07:20:47 PM UTC 24 |
| Finished | Oct 02 07:21:17 PM UTC 24 |
| Peak memory | 207952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206665759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1206665759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_noise_filter.1669363228 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 37091898385 ps |
| CPU time | 100.44 seconds |
| Started | Oct 02 07:20:29 PM UTC 24 |
| Finished | Oct 02 07:22:12 PM UTC 24 |
| Peak memory | 218452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669363228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1669363228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_perf.3315451592 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 15405982618 ps |
| CPU time | 927.76 seconds |
| Started | Oct 02 07:20:48 PM UTC 24 |
| Finished | Oct 02 07:36:27 PM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315451592 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3315451592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_rx_oversample.1054267408 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 6870605951 ps |
| CPU time | 84.48 seconds |
| Started | Oct 02 07:20:15 PM UTC 24 |
| Finished | Oct 02 07:21:42 PM UTC 24 |
| Peak memory | 204168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054267408 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1054267408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.607247660 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 94358840679 ps |
| CPU time | 258.13 seconds |
| Started | Oct 02 07:20:44 PM UTC 24 |
| Finished | Oct 02 07:25:06 PM UTC 24 |
| Peak memory | 209504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607247660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.607247660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.930951345 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 3890539331 ps |
| CPU time | 4.89 seconds |
| Started | Oct 02 07:20:39 PM UTC 24 |
| Finished | Oct 02 07:20:45 PM UTC 24 |
| Peak memory | 203584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930951345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.930951345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_smoke.3646272661 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 572358432 ps |
| CPU time | 2.63 seconds |
| Started | Oct 02 07:20:01 PM UTC 24 |
| Finished | Oct 02 07:20:05 PM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646272661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3646272661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_stress_all.910511181 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 322622319881 ps |
| CPU time | 354.46 seconds |
| Started | Oct 02 07:20:54 PM UTC 24 |
| Finished | Oct 02 07:26:53 PM UTC 24 |
| Peak memory | 205816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910511181 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.910511181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.146251210 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 5873203298 ps |
| CPU time | 44.94 seconds |
| Started | Oct 02 07:20:51 PM UTC 24 |
| Finished | Oct 02 07:21:37 PM UTC 24 |
| Peak memory | 220348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=146251210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all_ with_rand_reset.146251210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.3040153694 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 6737124554 ps |
| CPU time | 32 seconds |
| Started | Oct 02 07:20:47 PM UTC 24 |
| Finished | Oct 02 07:21:20 PM UTC 24 |
| Peak memory | 203916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040153694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3040153694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_tx_rx.2743105198 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 47237523026 ps |
| CPU time | 104.36 seconds |
| Started | Oct 02 07:20:02 PM UTC 24 |
| Finished | Oct 02 07:21:48 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743105198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2743105198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/30.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_alert_test.871811467 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 31310484 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 07:21:47 PM UTC 24 |
| Finished | Oct 02 07:21:49 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871811467 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.871811467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_fifo_full.1915362787 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 75796631187 ps |
| CPU time | 510.73 seconds |
| Started | Oct 02 07:21:07 PM UTC 24 |
| Finished | Oct 02 07:29:45 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915362787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1915362787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.2730597392 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 154252588645 ps |
| CPU time | 55.83 seconds |
| Started | Oct 02 07:21:14 PM UTC 24 |
| Finished | Oct 02 07:22:12 PM UTC 24 |
| Peak memory | 209176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730597392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2730597392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_fifo_reset.4112205201 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 102412084987 ps |
| CPU time | 94.33 seconds |
| Started | Oct 02 07:21:17 PM UTC 24 |
| Finished | Oct 02 07:22:53 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112205201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.4112205201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_intr.2297302273 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 20346625907 ps |
| CPU time | 30.11 seconds |
| Started | Oct 02 07:21:19 PM UTC 24 |
| Finished | Oct 02 07:21:50 PM UTC 24 |
| Peak memory | 209464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297302273 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2297302273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.752297425 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 89890996949 ps |
| CPU time | 910.96 seconds |
| Started | Oct 02 07:21:38 PM UTC 24 |
| Finished | Oct 02 07:37:01 PM UTC 24 |
| Peak memory | 212848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752297425 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.752297425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_loopback.3574969359 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 332267462 ps |
| CPU time | 1 seconds |
| Started | Oct 02 07:21:33 PM UTC 24 |
| Finished | Oct 02 07:21:35 PM UTC 24 |
| Peak memory | 205360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574969359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3574969359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_noise_filter.3935104486 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 25436315760 ps |
| CPU time | 70.9 seconds |
| Started | Oct 02 07:21:21 PM UTC 24 |
| Finished | Oct 02 07:22:33 PM UTC 24 |
| Peak memory | 209608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935104486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3935104486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_perf.2868777952 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 16228040334 ps |
| CPU time | 272.71 seconds |
| Started | Oct 02 07:21:36 PM UTC 24 |
| Finished | Oct 02 07:26:13 PM UTC 24 |
| Peak memory | 204024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868777952 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2868777952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_rx_oversample.3889197969 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 3890567613 ps |
| CPU time | 29.62 seconds |
| Started | Oct 02 07:21:17 PM UTC 24 |
| Finished | Oct 02 07:21:47 PM UTC 24 |
| Peak memory | 203976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889197969 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3889197969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.3227752898 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 203429504944 ps |
| CPU time | 167.4 seconds |
| Started | Oct 02 07:21:22 PM UTC 24 |
| Finished | Oct 02 07:24:12 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227752898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3227752898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.1628059645 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 49969719520 ps |
| CPU time | 32.19 seconds |
| Started | Oct 02 07:21:21 PM UTC 24 |
| Finished | Oct 02 07:21:54 PM UTC 24 |
| Peak memory | 203832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628059645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1628059645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_smoke.253207183 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 842879726 ps |
| CPU time | 6.32 seconds |
| Started | Oct 02 07:20:59 PM UTC 24 |
| Finished | Oct 02 07:21:06 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253207183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 31.uart_smoke.253207183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_stress_all.2044371012 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 76717422317 ps |
| CPU time | 96.22 seconds |
| Started | Oct 02 07:21:43 PM UTC 24 |
| Finished | Oct 02 07:23:22 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044371012 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2044371012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.1636065271 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 41749115745 ps |
| CPU time | 76.1 seconds |
| Started | Oct 02 07:21:42 PM UTC 24 |
| Finished | Oct 02 07:23:00 PM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1636065271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all _with_rand_reset.1636065271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.42616556 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 7992447799 ps |
| CPU time | 18.26 seconds |
| Started | Oct 02 07:21:26 PM UTC 24 |
| Finished | Oct 02 07:21:46 PM UTC 24 |
| Peak memory | 203868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42616556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.42616556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_tx_rx.4140196911 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 42862552851 ps |
| CPU time | 128.96 seconds |
| Started | Oct 02 07:21:03 PM UTC 24 |
| Finished | Oct 02 07:23:15 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140196911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.4140196911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/31.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_alert_test.914043714 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 22481518 ps |
| CPU time | 0.87 seconds |
| Started | Oct 02 07:22:38 PM UTC 24 |
| Finished | Oct 02 07:22:40 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914043714 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.914043714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_fifo_full.193481108 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 108365854648 ps |
| CPU time | 151.61 seconds |
| Started | Oct 02 07:21:50 PM UTC 24 |
| Finished | Oct 02 07:24:25 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193481108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.193481108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.2304748537 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 44575109654 ps |
| CPU time | 38.03 seconds |
| Started | Oct 02 07:21:51 PM UTC 24 |
| Finished | Oct 02 07:22:31 PM UTC 24 |
| Peak memory | 209416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304748537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2304748537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_fifo_reset.8247226 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 105530817604 ps |
| CPU time | 304.54 seconds |
| Started | Oct 02 07:21:55 PM UTC 24 |
| Finished | Oct 02 07:27:04 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8247226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.8247226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_intr.1595854998 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 38278342699 ps |
| CPU time | 62.89 seconds |
| Started | Oct 02 07:22:12 PM UTC 24 |
| Finished | Oct 02 07:23:17 PM UTC 24 |
| Peak memory | 204160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595854998 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1595854998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.3416933522 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 106713619781 ps |
| CPU time | 1034.57 seconds |
| Started | Oct 02 07:22:32 PM UTC 24 |
| Finished | Oct 02 07:39:59 PM UTC 24 |
| Peak memory | 209416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416933522 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3416933522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_loopback.462486233 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 10511712851 ps |
| CPU time | 21.03 seconds |
| Started | Oct 02 07:22:32 PM UTC 24 |
| Finished | Oct 02 07:22:54 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462486233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 32.uart_loopback.462486233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_noise_filter.3505386982 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 90595005056 ps |
| CPU time | 51.17 seconds |
| Started | Oct 02 07:22:13 PM UTC 24 |
| Finished | Oct 02 07:23:06 PM UTC 24 |
| Peak memory | 209608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505386982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3505386982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_perf.511196201 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 17913151934 ps |
| CPU time | 294.72 seconds |
| Started | Oct 02 07:22:32 PM UTC 24 |
| Finished | Oct 02 07:27:31 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511196201 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.511196201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_rx_oversample.305616060 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 4140425956 ps |
| CPU time | 39.48 seconds |
| Started | Oct 02 07:21:56 PM UTC 24 |
| Finished | Oct 02 07:22:37 PM UTC 24 |
| Peak memory | 208140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305616060 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.305616060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.3199413228 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 54813217443 ps |
| CPU time | 30.34 seconds |
| Started | Oct 02 07:22:21 PM UTC 24 |
| Finished | Oct 02 07:22:53 PM UTC 24 |
| Peak memory | 209404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199413228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3199413228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.2121099861 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 41288659249 ps |
| CPU time | 61.18 seconds |
| Started | Oct 02 07:22:18 PM UTC 24 |
| Finished | Oct 02 07:23:21 PM UTC 24 |
| Peak memory | 203768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121099861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2121099861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_smoke.2155013951 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 5874594818 ps |
| CPU time | 30.5 seconds |
| Started | Oct 02 07:21:49 PM UTC 24 |
| Finished | Oct 02 07:22:21 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155013951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2155013951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_stress_all.1273039635 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 222293365223 ps |
| CPU time | 899.05 seconds |
| Started | Oct 02 07:22:34 PM UTC 24 |
| Finished | Oct 02 07:37:44 PM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273039635 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1273039635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.192756323 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 18696051132 ps |
| CPU time | 54.99 seconds |
| Started | Oct 02 07:22:34 PM UTC 24 |
| Finished | Oct 02 07:23:31 PM UTC 24 |
| Peak memory | 225996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=192756323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all_ with_rand_reset.192756323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.3857853018 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1932552410 ps |
| CPU time | 2.33 seconds |
| Started | Oct 02 07:22:30 PM UTC 24 |
| Finished | Oct 02 07:22:33 PM UTC 24 |
| Peak memory | 208152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857853018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3857853018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_tx_rx.1356291002 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 106690071355 ps |
| CPU time | 217.2 seconds |
| Started | Oct 02 07:21:49 PM UTC 24 |
| Finished | Oct 02 07:25:30 PM UTC 24 |
| Peak memory | 204056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356291002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1356291002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/32.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_alert_test.1502344707 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 37521079 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 07:23:24 PM UTC 24 |
| Finished | Oct 02 07:23:25 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502344707 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1502344707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_fifo_full.1840342332 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 79315691971 ps |
| CPU time | 68.85 seconds |
| Started | Oct 02 07:22:52 PM UTC 24 |
| Finished | Oct 02 07:24:03 PM UTC 24 |
| Peak memory | 209608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840342332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1840342332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.2615538330 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 143972413160 ps |
| CPU time | 272.17 seconds |
| Started | Oct 02 07:22:53 PM UTC 24 |
| Finished | Oct 02 07:27:29 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615538330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2615538330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_fifo_reset.3591876922 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 17955841408 ps |
| CPU time | 66.23 seconds |
| Started | Oct 02 07:22:55 PM UTC 24 |
| Finished | Oct 02 07:24:03 PM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591876922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3591876922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_intr.2476177768 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 46103693289 ps |
| CPU time | 28.18 seconds |
| Started | Oct 02 07:23:01 PM UTC 24 |
| Finished | Oct 02 07:23:30 PM UTC 24 |
| Peak memory | 209412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476177768 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2476177768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.2370905268 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 139224668806 ps |
| CPU time | 299.89 seconds |
| Started | Oct 02 07:23:19 PM UTC 24 |
| Finished | Oct 02 07:28:24 PM UTC 24 |
| Peak memory | 209656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370905268 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2370905268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_loopback.3479550423 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 7655910186 ps |
| CPU time | 4.84 seconds |
| Started | Oct 02 07:23:17 PM UTC 24 |
| Finished | Oct 02 07:23:23 PM UTC 24 |
| Peak memory | 203832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479550423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3479550423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_noise_filter.1872815358 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 50093980874 ps |
| CPU time | 123.62 seconds |
| Started | Oct 02 07:23:06 PM UTC 24 |
| Finished | Oct 02 07:25:12 PM UTC 24 |
| Peak memory | 209684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872815358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1872815358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_perf.3406798231 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 32104010019 ps |
| CPU time | 647.97 seconds |
| Started | Oct 02 07:23:18 PM UTC 24 |
| Finished | Oct 02 07:34:15 PM UTC 24 |
| Peak memory | 204112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406798231 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3406798231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_rx_oversample.1596714140 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1801343179 ps |
| CPU time | 9.29 seconds |
| Started | Oct 02 07:22:55 PM UTC 24 |
| Finished | Oct 02 07:23:05 PM UTC 24 |
| Peak memory | 207880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596714140 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1596714140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.1463338204 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 57822620209 ps |
| CPU time | 91.35 seconds |
| Started | Oct 02 07:23:15 PM UTC 24 |
| Finished | Oct 02 07:24:49 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463338204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1463338204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.934650668 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2356561849 ps |
| CPU time | 9.27 seconds |
| Started | Oct 02 07:23:07 PM UTC 24 |
| Finished | Oct 02 07:23:17 PM UTC 24 |
| Peak memory | 203520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934650668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.934650668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_smoke.661107641 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 5767694521 ps |
| CPU time | 33 seconds |
| Started | Oct 02 07:22:41 PM UTC 24 |
| Finished | Oct 02 07:23:16 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661107641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 33.uart_smoke.661107641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_stress_all.1401718476 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 241547629005 ps |
| CPU time | 243.64 seconds |
| Started | Oct 02 07:23:24 PM UTC 24 |
| Finished | Oct 02 07:27:31 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401718476 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1401718476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.1668330937 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 7479208055 ps |
| CPU time | 35.12 seconds |
| Started | Oct 02 07:23:23 PM UTC 24 |
| Finished | Oct 02 07:23:59 PM UTC 24 |
| Peak memory | 218560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1668330937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all _with_rand_reset.1668330937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.2887760618 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 7920953815 ps |
| CPU time | 17.2 seconds |
| Started | Oct 02 07:23:16 PM UTC 24 |
| Finished | Oct 02 07:23:35 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887760618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2887760618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_tx_rx.4256151119 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 53414830180 ps |
| CPU time | 83.21 seconds |
| Started | Oct 02 07:22:48 PM UTC 24 |
| Finished | Oct 02 07:24:13 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256151119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.4256151119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/33.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_alert_test.965168512 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 22822563 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 07:24:04 PM UTC 24 |
| Finished | Oct 02 07:24:06 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965168512 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.965168512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_fifo_full.1178521377 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 102643389448 ps |
| CPU time | 32.26 seconds |
| Started | Oct 02 07:23:31 PM UTC 24 |
| Finished | Oct 02 07:24:05 PM UTC 24 |
| Peak memory | 206152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178521377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1178521377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.3447652010 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 44798347987 ps |
| CPU time | 54.08 seconds |
| Started | Oct 02 07:23:31 PM UTC 24 |
| Finished | Oct 02 07:24:27 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447652010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3447652010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_fifo_reset.2663401264 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 12193068545 ps |
| CPU time | 24.28 seconds |
| Started | Oct 02 07:23:33 PM UTC 24 |
| Finished | Oct 02 07:23:59 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663401264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2663401264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_intr.1101219605 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 21913986879 ps |
| CPU time | 26.58 seconds |
| Started | Oct 02 07:23:35 PM UTC 24 |
| Finished | Oct 02 07:24:04 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101219605 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1101219605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.37108028 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 73446199436 ps |
| CPU time | 300.83 seconds |
| Started | Oct 02 07:24:03 PM UTC 24 |
| Finished | Oct 02 07:29:08 PM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37108028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.37108028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_loopback.3300884437 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 1455031326 ps |
| CPU time | 6.81 seconds |
| Started | Oct 02 07:24:00 PM UTC 24 |
| Finished | Oct 02 07:24:08 PM UTC 24 |
| Peak memory | 203444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300884437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3300884437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_noise_filter.325933018 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 49423002469 ps |
| CPU time | 67.76 seconds |
| Started | Oct 02 07:23:38 PM UTC 24 |
| Finished | Oct 02 07:24:48 PM UTC 24 |
| Peak memory | 209680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325933018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.325933018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_perf.189389548 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 18952199896 ps |
| CPU time | 252.73 seconds |
| Started | Oct 02 07:24:02 PM UTC 24 |
| Finished | Oct 02 07:28:19 PM UTC 24 |
| Peak memory | 204172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189389548 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.189389548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_rx_oversample.1444177887 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 4226326946 ps |
| CPU time | 25.89 seconds |
| Started | Oct 02 07:23:34 PM UTC 24 |
| Finished | Oct 02 07:24:02 PM UTC 24 |
| Peak memory | 208136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444177887 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1444177887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.1433061807 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 38826078304 ps |
| CPU time | 45.04 seconds |
| Started | Oct 02 07:23:57 PM UTC 24 |
| Finished | Oct 02 07:24:43 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433061807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1433061807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.4276175541 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 4051890447 ps |
| CPU time | 18.3 seconds |
| Started | Oct 02 07:23:41 PM UTC 24 |
| Finished | Oct 02 07:24:01 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276175541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.4276175541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_smoke.3929860361 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 890420538 ps |
| CPU time | 7.55 seconds |
| Started | Oct 02 07:23:25 PM UTC 24 |
| Finished | Oct 02 07:23:33 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929860361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3929860361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_stress_all.4032485022 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 241537664803 ps |
| CPU time | 282.36 seconds |
| Started | Oct 02 07:24:04 PM UTC 24 |
| Finished | Oct 02 07:28:50 PM UTC 24 |
| Peak memory | 208204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032485022 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.4032485022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.2314888278 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 15993159966 ps |
| CPU time | 79.61 seconds |
| Started | Oct 02 07:24:04 PM UTC 24 |
| Finished | Oct 02 07:25:26 PM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2314888278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all _with_rand_reset.2314888278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.2819209414 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1432354179 ps |
| CPU time | 4.59 seconds |
| Started | Oct 02 07:24:00 PM UTC 24 |
| Finished | Oct 02 07:24:05 PM UTC 24 |
| Peak memory | 203984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819209414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2819209414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_tx_rx.1674086886 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 80646038767 ps |
| CPU time | 70.3 seconds |
| Started | Oct 02 07:23:26 PM UTC 24 |
| Finished | Oct 02 07:24:38 PM UTC 24 |
| Peak memory | 206088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674086886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1674086886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/34.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_alert_test.1193357013 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 14324146 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 07:24:39 PM UTC 24 |
| Finished | Oct 02 07:24:41 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193357013 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1193357013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_fifo_full.2428271141 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 68065301391 ps |
| CPU time | 148.25 seconds |
| Started | Oct 02 07:24:06 PM UTC 24 |
| Finished | Oct 02 07:26:37 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428271141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2428271141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.2050708516 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 15654975099 ps |
| CPU time | 16.56 seconds |
| Started | Oct 02 07:24:09 PM UTC 24 |
| Finished | Oct 02 07:24:26 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050708516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2050708516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_fifo_reset.429935892 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 57585207002 ps |
| CPU time | 112.68 seconds |
| Started | Oct 02 07:24:10 PM UTC 24 |
| Finished | Oct 02 07:26:04 PM UTC 24 |
| Peak memory | 209240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429935892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.429935892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_intr.2000700751 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 27555695964 ps |
| CPU time | 94.23 seconds |
| Started | Oct 02 07:24:13 PM UTC 24 |
| Finished | Oct 02 07:25:49 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000700751 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2000700751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.222495849 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 49522998805 ps |
| CPU time | 237.36 seconds |
| Started | Oct 02 07:24:31 PM UTC 24 |
| Finished | Oct 02 07:28:32 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222495849 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.222495849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_loopback.3807913936 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1487997424 ps |
| CPU time | 1.71 seconds |
| Started | Oct 02 07:24:27 PM UTC 24 |
| Finished | Oct 02 07:24:30 PM UTC 24 |
| Peak memory | 207344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807913936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3807913936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_noise_filter.366451545 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 81926361206 ps |
| CPU time | 77.84 seconds |
| Started | Oct 02 07:24:14 PM UTC 24 |
| Finished | Oct 02 07:25:34 PM UTC 24 |
| Peak memory | 209924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366451545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.366451545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_perf.3250311567 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 9146348992 ps |
| CPU time | 106.22 seconds |
| Started | Oct 02 07:24:27 PM UTC 24 |
| Finished | Oct 02 07:26:16 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250311567 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3250311567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_rx_oversample.342507731 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 2135198642 ps |
| CPU time | 3.61 seconds |
| Started | Oct 02 07:24:12 PM UTC 24 |
| Finished | Oct 02 07:24:17 PM UTC 24 |
| Peak memory | 207880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342507731 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.342507731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.1215828963 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 122234097588 ps |
| CPU time | 118.86 seconds |
| Started | Oct 02 07:24:17 PM UTC 24 |
| Finished | Oct 02 07:26:18 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215828963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1215828963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.1543868317 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 32088381715 ps |
| CPU time | 30.4 seconds |
| Started | Oct 02 07:24:16 PM UTC 24 |
| Finished | Oct 02 07:24:48 PM UTC 24 |
| Peak memory | 203832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543868317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1543868317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_smoke.2212852392 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 614521018 ps |
| CPU time | 2.5 seconds |
| Started | Oct 02 07:24:05 PM UTC 24 |
| Finished | Oct 02 07:24:09 PM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212852392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2212852392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_stress_all.1433382206 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 619393034688 ps |
| CPU time | 489.58 seconds |
| Started | Oct 02 07:24:39 PM UTC 24 |
| Finished | Oct 02 07:32:55 PM UTC 24 |
| Peak memory | 217300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433382206 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1433382206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.4288473751 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2079100029 ps |
| CPU time | 25.59 seconds |
| Started | Oct 02 07:24:31 PM UTC 24 |
| Finished | Oct 02 07:24:58 PM UTC 24 |
| Peak memory | 209464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4288473751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all _with_rand_reset.4288473751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.3547226414 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 7220066529 ps |
| CPU time | 11.51 seconds |
| Started | Oct 02 07:24:25 PM UTC 24 |
| Finished | Oct 02 07:24:38 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547226414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3547226414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_tx_rx.1061780246 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 21349504548 ps |
| CPU time | 34.43 seconds |
| Started | Oct 02 07:24:06 PM UTC 24 |
| Finished | Oct 02 07:24:42 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061780246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1061780246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/35.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_alert_test.2374049060 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 13972240 ps |
| CPU time | 0.83 seconds |
| Started | Oct 02 07:25:19 PM UTC 24 |
| Finished | Oct 02 07:25:21 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374049060 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2374049060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_fifo_full.1080462975 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 145328033689 ps |
| CPU time | 142.86 seconds |
| Started | Oct 02 07:24:43 PM UTC 24 |
| Finished | Oct 02 07:27:08 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080462975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1080462975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.4270761135 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 54415110932 ps |
| CPU time | 125.52 seconds |
| Started | Oct 02 07:24:44 PM UTC 24 |
| Finished | Oct 02 07:26:52 PM UTC 24 |
| Peak memory | 208996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270761135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.4270761135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_fifo_reset.373330745 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 24617433947 ps |
| CPU time | 40.84 seconds |
| Started | Oct 02 07:24:48 PM UTC 24 |
| Finished | Oct 02 07:25:30 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373330745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.373330745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_intr.3645085236 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 6839063035 ps |
| CPU time | 1.55 seconds |
| Started | Oct 02 07:24:49 PM UTC 24 |
| Finished | Oct 02 07:24:52 PM UTC 24 |
| Peak memory | 207404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645085236 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3645085236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.3504341398 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 132184565629 ps |
| CPU time | 1000.89 seconds |
| Started | Oct 02 07:25:07 PM UTC 24 |
| Finished | Oct 02 07:42:00 PM UTC 24 |
| Peak memory | 212856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504341398 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3504341398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_loopback.2626760039 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 5566784327 ps |
| CPU time | 10.76 seconds |
| Started | Oct 02 07:25:04 PM UTC 24 |
| Finished | Oct 02 07:25:16 PM UTC 24 |
| Peak memory | 209152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626760039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2626760039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_noise_filter.2105002058 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 61739323174 ps |
| CPU time | 73.59 seconds |
| Started | Oct 02 07:24:52 PM UTC 24 |
| Finished | Oct 02 07:26:08 PM UTC 24 |
| Peak memory | 209608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105002058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2105002058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_perf.211457849 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 13686049005 ps |
| CPU time | 202.46 seconds |
| Started | Oct 02 07:25:05 PM UTC 24 |
| Finished | Oct 02 07:28:30 PM UTC 24 |
| Peak memory | 203904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211457849 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.211457849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_rx_oversample.3794529285 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 7185812837 ps |
| CPU time | 27.96 seconds |
| Started | Oct 02 07:24:49 PM UTC 24 |
| Finished | Oct 02 07:25:19 PM UTC 24 |
| Peak memory | 208012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794529285 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3794529285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.179820722 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 223440415442 ps |
| CPU time | 185.95 seconds |
| Started | Oct 02 07:25:00 PM UTC 24 |
| Finished | Oct 02 07:28:08 PM UTC 24 |
| Peak memory | 209108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179820722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.179820722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.3999115629 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2304016951 ps |
| CPU time | 3.56 seconds |
| Started | Oct 02 07:24:59 PM UTC 24 |
| Finished | Oct 02 07:25:03 PM UTC 24 |
| Peak memory | 203508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999115629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3999115629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_smoke.1226315893 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 5678732743 ps |
| CPU time | 15.95 seconds |
| Started | Oct 02 07:24:42 PM UTC 24 |
| Finished | Oct 02 07:24:59 PM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226315893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1226315893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_stress_all.2906380980 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 82922024729 ps |
| CPU time | 202.45 seconds |
| Started | Oct 02 07:25:16 PM UTC 24 |
| Finished | Oct 02 07:28:42 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906380980 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2906380980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.1080346417 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2992811620 ps |
| CPU time | 12.13 seconds |
| Started | Oct 02 07:25:13 PM UTC 24 |
| Finished | Oct 02 07:25:26 PM UTC 24 |
| Peak memory | 218600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1080346417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all _with_rand_reset.1080346417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.2609985835 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1008609011 ps |
| CPU time | 2.4 seconds |
| Started | Oct 02 07:25:01 PM UTC 24 |
| Finished | Oct 02 07:25:04 PM UTC 24 |
| Peak memory | 203800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609985835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2609985835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_tx_rx.1144156368 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 38361570224 ps |
| CPU time | 67.11 seconds |
| Started | Oct 02 07:24:43 PM UTC 24 |
| Finished | Oct 02 07:25:52 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144156368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1144156368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/36.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_alert_test.2710856809 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 14659890 ps |
| CPU time | 0.84 seconds |
| Started | Oct 02 07:26:05 PM UTC 24 |
| Finished | Oct 02 07:26:07 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710856809 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2710856809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_fifo_full.2151028925 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 62745823621 ps |
| CPU time | 66.39 seconds |
| Started | Oct 02 07:25:27 PM UTC 24 |
| Finished | Oct 02 07:26:35 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151028925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2151028925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.2049757512 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 206274708504 ps |
| CPU time | 91.18 seconds |
| Started | Oct 02 07:25:27 PM UTC 24 |
| Finished | Oct 02 07:27:00 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049757512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2049757512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_fifo_reset.1892751298 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 21433138414 ps |
| CPU time | 38.63 seconds |
| Started | Oct 02 07:25:28 PM UTC 24 |
| Finished | Oct 02 07:26:08 PM UTC 24 |
| Peak memory | 204044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892751298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1892751298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_intr.659701716 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 28507950785 ps |
| CPU time | 69.06 seconds |
| Started | Oct 02 07:25:31 PM UTC 24 |
| Finished | Oct 02 07:26:42 PM UTC 24 |
| Peak memory | 203768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659701716 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.659701716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.1102511823 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 100015931672 ps |
| CPU time | 227 seconds |
| Started | Oct 02 07:25:50 PM UTC 24 |
| Finished | Oct 02 07:29:40 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102511823 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1102511823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_loopback.583950577 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 8140446016 ps |
| CPU time | 33.38 seconds |
| Started | Oct 02 07:25:46 PM UTC 24 |
| Finished | Oct 02 07:26:21 PM UTC 24 |
| Peak memory | 209620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583950577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 37.uart_loopback.583950577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_noise_filter.779776274 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 51687638184 ps |
| CPU time | 62.78 seconds |
| Started | Oct 02 07:25:32 PM UTC 24 |
| Finished | Oct 02 07:26:36 PM UTC 24 |
| Peak memory | 209680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779776274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.779776274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_perf.2615185909 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 7728771312 ps |
| CPU time | 488.9 seconds |
| Started | Oct 02 07:25:46 PM UTC 24 |
| Finished | Oct 02 07:34:02 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615185909 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2615185909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_rx_oversample.3499698724 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 3281901027 ps |
| CPU time | 8.61 seconds |
| Started | Oct 02 07:25:31 PM UTC 24 |
| Finished | Oct 02 07:25:40 PM UTC 24 |
| Peak memory | 207872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499698724 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3499698724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.2762772181 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 75474300369 ps |
| CPU time | 174.49 seconds |
| Started | Oct 02 07:25:39 PM UTC 24 |
| Finished | Oct 02 07:28:37 PM UTC 24 |
| Peak memory | 204024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762772181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2762772181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.885103287 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 4095592365 ps |
| CPU time | 2.85 seconds |
| Started | Oct 02 07:25:34 PM UTC 24 |
| Finished | Oct 02 07:25:38 PM UTC 24 |
| Peak memory | 203584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885103287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.885103287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_smoke.4202592405 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 737136322 ps |
| CPU time | 4.85 seconds |
| Started | Oct 02 07:25:19 PM UTC 24 |
| Finished | Oct 02 07:25:25 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202592405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.uart_smoke.4202592405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.1877869979 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 11847750125 ps |
| CPU time | 89.33 seconds |
| Started | Oct 02 07:25:51 PM UTC 24 |
| Finished | Oct 02 07:27:22 PM UTC 24 |
| Peak memory | 226432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1877869979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all _with_rand_reset.1877869979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.4243053666 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1011474546 ps |
| CPU time | 3.04 seconds |
| Started | Oct 02 07:25:41 PM UTC 24 |
| Finished | Oct 02 07:25:45 PM UTC 24 |
| Peak memory | 204056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243053666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.4243053666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_tx_rx.3937359151 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 22943791213 ps |
| CPU time | 24.48 seconds |
| Started | Oct 02 07:25:22 PM UTC 24 |
| Finished | Oct 02 07:25:48 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937359151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3937359151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/37.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_alert_test.3916700607 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 18565424 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 07:26:45 PM UTC 24 |
| Finished | Oct 02 07:26:47 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916700607 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3916700607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_fifo_full.2579309909 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 42137894376 ps |
| CPU time | 38.48 seconds |
| Started | Oct 02 07:26:09 PM UTC 24 |
| Finished | Oct 02 07:26:49 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579309909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2579309909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.3553184405 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 35773065437 ps |
| CPU time | 28.75 seconds |
| Started | Oct 02 07:26:13 PM UTC 24 |
| Finished | Oct 02 07:26:43 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553184405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3553184405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_intr.3004703523 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 69549962853 ps |
| CPU time | 130.47 seconds |
| Started | Oct 02 07:26:22 PM UTC 24 |
| Finished | Oct 02 07:28:35 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004703523 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3004703523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.2019790988 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 62171334492 ps |
| CPU time | 297 seconds |
| Started | Oct 02 07:26:41 PM UTC 24 |
| Finished | Oct 02 07:31:42 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019790988 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2019790988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_loopback.185598537 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 2860023371 ps |
| CPU time | 5.24 seconds |
| Started | Oct 02 07:26:38 PM UTC 24 |
| Finished | Oct 02 07:26:44 PM UTC 24 |
| Peak memory | 205560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185598537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 38.uart_loopback.185598537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_noise_filter.3927885270 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 241332317299 ps |
| CPU time | 62.84 seconds |
| Started | Oct 02 07:26:29 PM UTC 24 |
| Finished | Oct 02 07:27:33 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927885270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3927885270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_perf.268069683 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 24189854887 ps |
| CPU time | 276.42 seconds |
| Started | Oct 02 07:26:40 PM UTC 24 |
| Finished | Oct 02 07:31:21 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268069683 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.268069683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_rx_oversample.1220406392 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 2740326977 ps |
| CPU time | 15.74 seconds |
| Started | Oct 02 07:26:19 PM UTC 24 |
| Finished | Oct 02 07:26:36 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220406392 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1220406392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.2959609341 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 41431800463 ps |
| CPU time | 11.1 seconds |
| Started | Oct 02 07:26:37 PM UTC 24 |
| Finished | Oct 02 07:26:49 PM UTC 24 |
| Peak memory | 208048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959609341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2959609341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.2373374173 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 5793415617 ps |
| CPU time | 2.44 seconds |
| Started | Oct 02 07:26:36 PM UTC 24 |
| Finished | Oct 02 07:26:39 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373374173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2373374173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_smoke.2424296987 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 5958182669 ps |
| CPU time | 18.78 seconds |
| Started | Oct 02 07:26:08 PM UTC 24 |
| Finished | Oct 02 07:26:28 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424296987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2424296987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_stress_all.4160760019 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 34536460579 ps |
| CPU time | 88.24 seconds |
| Started | Oct 02 07:26:44 PM UTC 24 |
| Finished | Oct 02 07:28:14 PM UTC 24 |
| Peak memory | 203764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160760019 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.4160760019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.2519244190 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1373263239 ps |
| CPU time | 32.34 seconds |
| Started | Oct 02 07:26:42 PM UTC 24 |
| Finished | Oct 02 07:27:16 PM UTC 24 |
| Peak memory | 218828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2519244190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all _with_rand_reset.2519244190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.2403670451 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 7498460493 ps |
| CPU time | 11.91 seconds |
| Started | Oct 02 07:26:37 PM UTC 24 |
| Finished | Oct 02 07:26:50 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403670451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2403670451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_tx_rx.4226505782 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 106518135760 ps |
| CPU time | 58.87 seconds |
| Started | Oct 02 07:26:09 PM UTC 24 |
| Finished | Oct 02 07:27:10 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226505782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.4226505782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/38.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_alert_test.2436028377 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 35418263 ps |
| CPU time | 0.83 seconds |
| Started | Oct 02 07:27:19 PM UTC 24 |
| Finished | Oct 02 07:27:21 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436028377 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2436028377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_fifo_full.3754488545 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 88546510140 ps |
| CPU time | 116.01 seconds |
| Started | Oct 02 07:26:51 PM UTC 24 |
| Finished | Oct 02 07:28:49 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754488545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3754488545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.2752939145 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 8814492683 ps |
| CPU time | 33.09 seconds |
| Started | Oct 02 07:26:51 PM UTC 24 |
| Finished | Oct 02 07:27:25 PM UTC 24 |
| Peak memory | 208976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752939145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2752939145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_fifo_reset.2424581516 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 210050558351 ps |
| CPU time | 328.94 seconds |
| Started | Oct 02 07:26:53 PM UTC 24 |
| Finished | Oct 02 07:32:26 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424581516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2424581516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_intr.3802195647 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 86952883052 ps |
| CPU time | 237.94 seconds |
| Started | Oct 02 07:26:54 PM UTC 24 |
| Finished | Oct 02 07:30:56 PM UTC 24 |
| Peak memory | 204096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802195647 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3802195647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.1508596218 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 58152690746 ps |
| CPU time | 204.63 seconds |
| Started | Oct 02 07:27:16 PM UTC 24 |
| Finished | Oct 02 07:30:43 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508596218 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1508596218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_loopback.2292286019 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 2531400347 ps |
| CPU time | 3.53 seconds |
| Started | Oct 02 07:27:10 PM UTC 24 |
| Finished | Oct 02 07:27:15 PM UTC 24 |
| Peak memory | 204100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292286019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2292286019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_noise_filter.3689637019 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 34904989936 ps |
| CPU time | 61.91 seconds |
| Started | Oct 02 07:27:01 PM UTC 24 |
| Finished | Oct 02 07:28:05 PM UTC 24 |
| Peak memory | 209612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689637019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3689637019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_perf.3033338597 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 10895896592 ps |
| CPU time | 200.41 seconds |
| Started | Oct 02 07:27:15 PM UTC 24 |
| Finished | Oct 02 07:30:39 PM UTC 24 |
| Peak memory | 203840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033338597 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3033338597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_rx_oversample.845105961 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 7320773968 ps |
| CPU time | 95.46 seconds |
| Started | Oct 02 07:26:53 PM UTC 24 |
| Finished | Oct 02 07:28:30 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845105961 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.845105961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.4166029291 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 151021522983 ps |
| CPU time | 56.12 seconds |
| Started | Oct 02 07:27:05 PM UTC 24 |
| Finished | Oct 02 07:28:03 PM UTC 24 |
| Peak memory | 203356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166029291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.4166029291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.247173017 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 2955633095 ps |
| CPU time | 11.19 seconds |
| Started | Oct 02 07:27:05 PM UTC 24 |
| Finished | Oct 02 07:27:17 PM UTC 24 |
| Peak memory | 202952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247173017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.247173017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_smoke.2191801509 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 256251106 ps |
| CPU time | 2.02 seconds |
| Started | Oct 02 07:26:48 PM UTC 24 |
| Finished | Oct 02 07:26:51 PM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191801509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2191801509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_stress_all.275373671 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 178413982364 ps |
| CPU time | 337.38 seconds |
| Started | Oct 02 07:27:17 PM UTC 24 |
| Finished | Oct 02 07:32:59 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275373671 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.275373671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.1802771219 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4252148871 ps |
| CPU time | 67.8 seconds |
| Started | Oct 02 07:27:16 PM UTC 24 |
| Finished | Oct 02 07:28:25 PM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1802771219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all _with_rand_reset.1802771219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1266082933 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 770570102 ps |
| CPU time | 3.82 seconds |
| Started | Oct 02 07:27:09 PM UTC 24 |
| Finished | Oct 02 07:27:14 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266082933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1266082933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_tx_rx.2884491177 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 24663399766 ps |
| CPU time | 23.65 seconds |
| Started | Oct 02 07:26:50 PM UTC 24 |
| Finished | Oct 02 07:27:14 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884491177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2884491177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/39.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_alert_test.430291662 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12810866 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 07:07:33 PM UTC 24 |
| Finished | Oct 02 07:07:35 PM UTC 24 |
| Peak memory | 203192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430291662 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.430291662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_fifo_full.225882492 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 53566207517 ps |
| CPU time | 26.22 seconds |
| Started | Oct 02 07:07:19 PM UTC 24 |
| Finished | Oct 02 07:07:47 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225882492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.225882492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_fifo_reset.2017410741 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 98360156463 ps |
| CPU time | 185.43 seconds |
| Started | Oct 02 07:07:20 PM UTC 24 |
| Finished | Oct 02 07:10:28 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017410741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2017410741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_intr.3212320597 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 34610819783 ps |
| CPU time | 59.88 seconds |
| Started | Oct 02 07:07:21 PM UTC 24 |
| Finished | Oct 02 07:08:22 PM UTC 24 |
| Peak memory | 208580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212320597 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3212320597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.1133429161 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 35980982649 ps |
| CPU time | 198.19 seconds |
| Started | Oct 02 07:07:23 PM UTC 24 |
| Finished | Oct 02 07:10:44 PM UTC 24 |
| Peak memory | 204100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133429161 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1133429161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_loopback.2884019622 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2631127619 ps |
| CPU time | 10.36 seconds |
| Started | Oct 02 07:07:22 PM UTC 24 |
| Finished | Oct 02 07:07:34 PM UTC 24 |
| Peak memory | 207736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884019622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2884019622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_noise_filter.1825320350 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 122345378627 ps |
| CPU time | 68.9 seconds |
| Started | Oct 02 07:07:21 PM UTC 24 |
| Finished | Oct 02 07:08:32 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825320350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1825320350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_rx_oversample.2954696916 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5373584120 ps |
| CPU time | 15.92 seconds |
| Started | Oct 02 07:07:20 PM UTC 24 |
| Finished | Oct 02 07:07:37 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954696916 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2954696916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.2328701937 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 35808266987 ps |
| CPU time | 35.87 seconds |
| Started | Oct 02 07:07:22 PM UTC 24 |
| Finished | Oct 02 07:07:59 PM UTC 24 |
| Peak memory | 209180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328701937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2328701937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.378883924 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2873167213 ps |
| CPU time | 3.26 seconds |
| Started | Oct 02 07:07:21 PM UTC 24 |
| Finished | Oct 02 07:07:25 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378883924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.378883924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_sec_cm.2272909080 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 236234169 ps |
| CPU time | 1.42 seconds |
| Started | Oct 02 07:07:30 PM UTC 24 |
| Finished | Oct 02 07:07:33 PM UTC 24 |
| Peak memory | 237820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272909080 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2272909080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_smoke.647531512 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 5396806278 ps |
| CPU time | 27.28 seconds |
| Started | Oct 02 07:07:18 PM UTC 24 |
| Finished | Oct 02 07:07:47 PM UTC 24 |
| Peak memory | 204040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647531512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 4.uart_smoke.647531512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_stress_all.3371673534 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 90510410007 ps |
| CPU time | 144.17 seconds |
| Started | Oct 02 07:07:28 PM UTC 24 |
| Finished | Oct 02 07:09:55 PM UTC 24 |
| Peak memory | 220804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371673534 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3371673534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.2056253101 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2394878638 ps |
| CPU time | 4.24 seconds |
| Started | Oct 02 07:07:22 PM UTC 24 |
| Finished | Oct 02 07:07:27 PM UTC 24 |
| Peak memory | 203676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056253101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2056253101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/4.uart_tx_rx.1734289507 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 21522988168 ps |
| CPU time | 51.18 seconds |
| Started | Oct 02 07:07:18 PM UTC 24 |
| Finished | Oct 02 07:08:11 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734289507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1734289507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/4.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_alert_test.2985191782 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 19385184 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 07:28:01 PM UTC 24 |
| Finished | Oct 02 07:28:03 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985191782 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2985191782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_fifo_full.2525816493 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 92909734324 ps |
| CPU time | 174.83 seconds |
| Started | Oct 02 07:27:26 PM UTC 24 |
| Finished | Oct 02 07:30:24 PM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525816493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2525816493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.3345759689 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 52230757477 ps |
| CPU time | 31.77 seconds |
| Started | Oct 02 07:27:27 PM UTC 24 |
| Finished | Oct 02 07:28:00 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345759689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3345759689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_fifo_reset.1839887713 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 20984973660 ps |
| CPU time | 57.94 seconds |
| Started | Oct 02 07:27:30 PM UTC 24 |
| Finished | Oct 02 07:28:30 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839887713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1839887713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_intr.61382082 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 13357244628 ps |
| CPU time | 30.87 seconds |
| Started | Oct 02 07:27:31 PM UTC 24 |
| Finished | Oct 02 07:28:04 PM UTC 24 |
| Peak memory | 204116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61382082 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.61382082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.227390057 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 179332808832 ps |
| CPU time | 350.45 seconds |
| Started | Oct 02 07:27:51 PM UTC 24 |
| Finished | Oct 02 07:33:46 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227390057 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.227390057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_loopback.135258130 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 180753876 ps |
| CPU time | 1.96 seconds |
| Started | Oct 02 07:27:47 PM UTC 24 |
| Finished | Oct 02 07:27:50 PM UTC 24 |
| Peak memory | 207412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135258130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 40.uart_loopback.135258130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_noise_filter.3823453329 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 42742136813 ps |
| CPU time | 84.22 seconds |
| Started | Oct 02 07:27:31 PM UTC 24 |
| Finished | Oct 02 07:28:58 PM UTC 24 |
| Peak memory | 208408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823453329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3823453329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_perf.1059033868 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 11576304737 ps |
| CPU time | 774.65 seconds |
| Started | Oct 02 07:27:50 PM UTC 24 |
| Finished | Oct 02 07:40:55 PM UTC 24 |
| Peak memory | 207232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059033868 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1059033868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_rx_oversample.1641326711 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 2647552123 ps |
| CPU time | 7.73 seconds |
| Started | Oct 02 07:27:31 PM UTC 24 |
| Finished | Oct 02 07:27:40 PM UTC 24 |
| Peak memory | 203912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641326711 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1641326711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.3925293596 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 6992368982 ps |
| CPU time | 12.4 seconds |
| Started | Oct 02 07:27:41 PM UTC 24 |
| Finished | Oct 02 07:27:54 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925293596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3925293596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.3852454630 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 24777434262 ps |
| CPU time | 70.04 seconds |
| Started | Oct 02 07:27:34 PM UTC 24 |
| Finished | Oct 02 07:28:45 PM UTC 24 |
| Peak memory | 205624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852454630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3852454630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_smoke.2486929965 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 458332540 ps |
| CPU time | 3.38 seconds |
| Started | Oct 02 07:27:22 PM UTC 24 |
| Finished | Oct 02 07:27:26 PM UTC 24 |
| Peak memory | 203720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486929965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2486929965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_stress_all.2300776837 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 170624184833 ps |
| CPU time | 258.21 seconds |
| Started | Oct 02 07:27:55 PM UTC 24 |
| Finished | Oct 02 07:32:18 PM UTC 24 |
| Peak memory | 208256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300776837 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2300776837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.3732102331 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 4609094889 ps |
| CPU time | 64.1 seconds |
| Started | Oct 02 07:27:53 PM UTC 24 |
| Finished | Oct 02 07:28:59 PM UTC 24 |
| Peak memory | 220592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3732102331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all _with_rand_reset.3732102331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.4177864949 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 7252899605 ps |
| CPU time | 20.5 seconds |
| Started | Oct 02 07:27:44 PM UTC 24 |
| Finished | Oct 02 07:28:06 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177864949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.4177864949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_tx_rx.2137236541 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 10990288261 ps |
| CPU time | 18.33 seconds |
| Started | Oct 02 07:27:23 PM UTC 24 |
| Finished | Oct 02 07:27:43 PM UTC 24 |
| Peak memory | 209656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137236541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2137236541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/40.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_alert_test.1990118250 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 54917518 ps |
| CPU time | 0.7 seconds |
| Started | Oct 02 07:28:31 PM UTC 24 |
| Finished | Oct 02 07:28:32 PM UTC 24 |
| Peak memory | 202992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990118250 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1990118250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_fifo_full.3032844514 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 122367976153 ps |
| CPU time | 296.83 seconds |
| Started | Oct 02 07:28:05 PM UTC 24 |
| Finished | Oct 02 07:33:05 PM UTC 24 |
| Peak memory | 205836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032844514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3032844514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.4227800032 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 47580482348 ps |
| CPU time | 27.96 seconds |
| Started | Oct 02 07:28:06 PM UTC 24 |
| Finished | Oct 02 07:28:35 PM UTC 24 |
| Peak memory | 203860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227800032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.4227800032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_fifo_reset.3264019644 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 56319703431 ps |
| CPU time | 21.46 seconds |
| Started | Oct 02 07:28:07 PM UTC 24 |
| Finished | Oct 02 07:28:29 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264019644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3264019644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.1367552120 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 70445712570 ps |
| CPU time | 651.76 seconds |
| Started | Oct 02 07:28:26 PM UTC 24 |
| Finished | Oct 02 07:39:27 PM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367552120 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1367552120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_loopback.685529931 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 2631274732 ps |
| CPU time | 11.71 seconds |
| Started | Oct 02 07:28:25 PM UTC 24 |
| Finished | Oct 02 07:28:38 PM UTC 24 |
| Peak memory | 205624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685529931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 41.uart_loopback.685529931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_noise_filter.212366377 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 107226443778 ps |
| CPU time | 220.18 seconds |
| Started | Oct 02 07:28:19 PM UTC 24 |
| Finished | Oct 02 07:32:02 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212366377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.212366377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_perf.1857009081 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 21827149030 ps |
| CPU time | 295.2 seconds |
| Started | Oct 02 07:28:26 PM UTC 24 |
| Finished | Oct 02 07:33:26 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857009081 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1857009081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_rx_oversample.4100695099 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 2604961187 ps |
| CPU time | 9.66 seconds |
| Started | Oct 02 07:28:09 PM UTC 24 |
| Finished | Oct 02 07:28:20 PM UTC 24 |
| Peak memory | 207880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100695099 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.4100695099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.3318792848 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 184511962465 ps |
| CPU time | 702.66 seconds |
| Started | Oct 02 07:28:20 PM UTC 24 |
| Finished | Oct 02 07:40:11 PM UTC 24 |
| Peak memory | 207172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318792848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3318792848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.3227417540 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 2857830757 ps |
| CPU time | 3.43 seconds |
| Started | Oct 02 07:28:20 PM UTC 24 |
| Finished | Oct 02 07:28:25 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227417540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3227417540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_smoke.3690141772 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 6242976810 ps |
| CPU time | 28.59 seconds |
| Started | Oct 02 07:28:03 PM UTC 24 |
| Finished | Oct 02 07:28:33 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690141772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3690141772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_stress_all.2129212993 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 232223093124 ps |
| CPU time | 318.27 seconds |
| Started | Oct 02 07:28:31 PM UTC 24 |
| Finished | Oct 02 07:33:54 PM UTC 24 |
| Peak memory | 208084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129212993 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2129212993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.1612734308 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 3760934304 ps |
| CPU time | 8.5 seconds |
| Started | Oct 02 07:28:31 PM UTC 24 |
| Finished | Oct 02 07:28:40 PM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1612734308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all _with_rand_reset.1612734308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.265544765 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3462959711 ps |
| CPU time | 4.17 seconds |
| Started | Oct 02 07:28:24 PM UTC 24 |
| Finished | Oct 02 07:28:30 PM UTC 24 |
| Peak memory | 207964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265544765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.265544765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_tx_rx.2195634097 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 72242682376 ps |
| CPU time | 19.85 seconds |
| Started | Oct 02 07:28:05 PM UTC 24 |
| Finished | Oct 02 07:28:26 PM UTC 24 |
| Peak memory | 205832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195634097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2195634097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_alert_test.1969533912 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 13474698 ps |
| CPU time | 0.94 seconds |
| Started | Oct 02 07:28:49 PM UTC 24 |
| Finished | Oct 02 07:28:51 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969533912 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1969533912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_fifo_full.2808632827 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 142028867177 ps |
| CPU time | 111.2 seconds |
| Started | Oct 02 07:28:32 PM UTC 24 |
| Finished | Oct 02 07:30:25 PM UTC 24 |
| Peak memory | 206164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808632827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2808632827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.559862439 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 111966350856 ps |
| CPU time | 258.25 seconds |
| Started | Oct 02 07:28:33 PM UTC 24 |
| Finished | Oct 02 07:32:55 PM UTC 24 |
| Peak memory | 209224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559862439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.559862439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_fifo_reset.1396830556 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 31843714384 ps |
| CPU time | 57.91 seconds |
| Started | Oct 02 07:28:33 PM UTC 24 |
| Finished | Oct 02 07:29:33 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396830556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1396830556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_intr.1631511760 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 103421431540 ps |
| CPU time | 85.03 seconds |
| Started | Oct 02 07:28:34 PM UTC 24 |
| Finished | Oct 02 07:30:01 PM UTC 24 |
| Peak memory | 209204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631511760 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1631511760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.887039237 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 139151024493 ps |
| CPU time | 409.5 seconds |
| Started | Oct 02 07:28:44 PM UTC 24 |
| Finished | Oct 02 07:35:39 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887039237 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.887039237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_loopback.3931800251 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 1218205491 ps |
| CPU time | 5.62 seconds |
| Started | Oct 02 07:28:41 PM UTC 24 |
| Finished | Oct 02 07:28:47 PM UTC 24 |
| Peak memory | 203768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931800251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3931800251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_noise_filter.2296116151 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 29225279079 ps |
| CPU time | 64.43 seconds |
| Started | Oct 02 07:28:35 PM UTC 24 |
| Finished | Oct 02 07:29:41 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296116151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2296116151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_perf.1422193876 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 7561603685 ps |
| CPU time | 283.44 seconds |
| Started | Oct 02 07:28:43 PM UTC 24 |
| Finished | Oct 02 07:33:30 PM UTC 24 |
| Peak memory | 203768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422193876 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1422193876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_rx_oversample.549959240 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3504605721 ps |
| CPU time | 12.96 seconds |
| Started | Oct 02 07:28:34 PM UTC 24 |
| Finished | Oct 02 07:28:48 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549959240 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.549959240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.2791546530 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 47924501036 ps |
| CPU time | 29.23 seconds |
| Started | Oct 02 07:28:38 PM UTC 24 |
| Finished | Oct 02 07:29:08 PM UTC 24 |
| Peak memory | 209472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791546530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2791546530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.2993109710 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 6916590609 ps |
| CPU time | 17.12 seconds |
| Started | Oct 02 07:28:36 PM UTC 24 |
| Finished | Oct 02 07:28:55 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993109710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2993109710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_smoke.1175656861 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 545673471 ps |
| CPU time | 1.51 seconds |
| Started | Oct 02 07:28:31 PM UTC 24 |
| Finished | Oct 02 07:28:33 PM UTC 24 |
| Peak memory | 203380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175656861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1175656861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.2174432220 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 48934143597 ps |
| CPU time | 57.09 seconds |
| Started | Oct 02 07:28:46 PM UTC 24 |
| Finished | Oct 02 07:29:45 PM UTC 24 |
| Peak memory | 226172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2174432220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all _with_rand_reset.2174432220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.3658367589 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 500986376 ps |
| CPU time | 3.08 seconds |
| Started | Oct 02 07:28:39 PM UTC 24 |
| Finished | Oct 02 07:28:43 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658367589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3658367589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_tx_rx.4225321460 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 82305258494 ps |
| CPU time | 189.41 seconds |
| Started | Oct 02 07:28:32 PM UTC 24 |
| Finished | Oct 02 07:31:44 PM UTC 24 |
| Peak memory | 209664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225321460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4225321460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_alert_test.250355012 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 12911521 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 07:29:42 PM UTC 24 |
| Finished | Oct 02 07:29:44 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250355012 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.250355012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_fifo_full.1847257373 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 186610967409 ps |
| CPU time | 405.75 seconds |
| Started | Oct 02 07:28:51 PM UTC 24 |
| Finished | Oct 02 07:35:42 PM UTC 24 |
| Peak memory | 203716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847257373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1847257373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.1672525872 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 61500161519 ps |
| CPU time | 119.34 seconds |
| Started | Oct 02 07:28:53 PM UTC 24 |
| Finished | Oct 02 07:30:54 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672525872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1672525872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_fifo_reset.3165229931 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 74361083477 ps |
| CPU time | 50.83 seconds |
| Started | Oct 02 07:28:56 PM UTC 24 |
| Finished | Oct 02 07:29:48 PM UTC 24 |
| Peak memory | 209656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165229931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3165229931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_intr.2264555922 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 139565883403 ps |
| CPU time | 207.69 seconds |
| Started | Oct 02 07:29:00 PM UTC 24 |
| Finished | Oct 02 07:32:31 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264555922 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2264555922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.4154846421 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 37386895626 ps |
| CPU time | 199.3 seconds |
| Started | Oct 02 07:29:34 PM UTC 24 |
| Finished | Oct 02 07:32:56 PM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154846421 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.4154846421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_loopback.2153395424 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 514011104 ps |
| CPU time | 1.46 seconds |
| Started | Oct 02 07:29:14 PM UTC 24 |
| Finished | Oct 02 07:29:17 PM UTC 24 |
| Peak memory | 203376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153395424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2153395424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_noise_filter.2431728806 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 81836211991 ps |
| CPU time | 136.51 seconds |
| Started | Oct 02 07:29:04 PM UTC 24 |
| Finished | Oct 02 07:31:23 PM UTC 24 |
| Peak memory | 209612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431728806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2431728806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_perf.1310822087 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 20602133462 ps |
| CPU time | 948.84 seconds |
| Started | Oct 02 07:29:17 PM UTC 24 |
| Finished | Oct 02 07:45:18 PM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310822087 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1310822087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_rx_oversample.3683854164 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 2007601747 ps |
| CPU time | 9.35 seconds |
| Started | Oct 02 07:28:59 PM UTC 24 |
| Finished | Oct 02 07:29:09 PM UTC 24 |
| Peak memory | 208136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683854164 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3683854164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.3080340618 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 108745848839 ps |
| CPU time | 217.37 seconds |
| Started | Oct 02 07:29:09 PM UTC 24 |
| Finished | Oct 02 07:32:50 PM UTC 24 |
| Peak memory | 203844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080340618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3080340618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.3893977402 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 43264275183 ps |
| CPU time | 99.51 seconds |
| Started | Oct 02 07:29:09 PM UTC 24 |
| Finished | Oct 02 07:30:51 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893977402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3893977402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_smoke.593024494 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 5491704341 ps |
| CPU time | 11.56 seconds |
| Started | Oct 02 07:28:50 PM UTC 24 |
| Finished | Oct 02 07:29:03 PM UTC 24 |
| Peak memory | 203712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593024494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 43.uart_smoke.593024494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_stress_all.3775414282 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 324021800343 ps |
| CPU time | 470.88 seconds |
| Started | Oct 02 07:29:42 PM UTC 24 |
| Finished | Oct 02 07:37:39 PM UTC 24 |
| Peak memory | 209580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775414282 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3775414282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.515060094 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 1688497039 ps |
| CPU time | 38.99 seconds |
| Started | Oct 02 07:29:41 PM UTC 24 |
| Finished | Oct 02 07:30:21 PM UTC 24 |
| Peak memory | 220528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=515060094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all_ with_rand_reset.515060094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.1550682723 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1022904526 ps |
| CPU time | 2.48 seconds |
| Started | Oct 02 07:29:10 PM UTC 24 |
| Finished | Oct 02 07:29:14 PM UTC 24 |
| Peak memory | 208152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550682723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1550682723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_tx_rx.252424762 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 18278300400 ps |
| CPU time | 49.44 seconds |
| Started | Oct 02 07:28:50 PM UTC 24 |
| Finished | Oct 02 07:29:41 PM UTC 24 |
| Peak memory | 209356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252424762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.252424762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/43.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_alert_test.752680480 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 15871649 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 07:30:34 PM UTC 24 |
| Finished | Oct 02 07:30:37 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752680480 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.752680480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_fifo_full.1573628317 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 371778935326 ps |
| CPU time | 54.93 seconds |
| Started | Oct 02 07:29:46 PM UTC 24 |
| Finished | Oct 02 07:30:43 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573628317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1573628317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.3400186422 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 112057027609 ps |
| CPU time | 149.96 seconds |
| Started | Oct 02 07:29:46 PM UTC 24 |
| Finished | Oct 02 07:32:19 PM UTC 24 |
| Peak memory | 209184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400186422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3400186422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_fifo_reset.4269661301 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 368713356216 ps |
| CPU time | 44.96 seconds |
| Started | Oct 02 07:29:47 PM UTC 24 |
| Finished | Oct 02 07:30:34 PM UTC 24 |
| Peak memory | 209208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269661301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.4269661301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_intr.2720194108 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 28125384134 ps |
| CPU time | 6.78 seconds |
| Started | Oct 02 07:29:54 PM UTC 24 |
| Finished | Oct 02 07:30:02 PM UTC 24 |
| Peak memory | 209244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720194108 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2720194108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.2694016359 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 104028953040 ps |
| CPU time | 496.96 seconds |
| Started | Oct 02 07:30:22 PM UTC 24 |
| Finished | Oct 02 07:38:46 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694016359 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2694016359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_loopback.3435659215 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 3733075469 ps |
| CPU time | 2.71 seconds |
| Started | Oct 02 07:30:15 PM UTC 24 |
| Finished | Oct 02 07:30:19 PM UTC 24 |
| Peak memory | 208564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435659215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3435659215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_noise_filter.2719625925 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 39574609296 ps |
| CPU time | 98.81 seconds |
| Started | Oct 02 07:30:03 PM UTC 24 |
| Finished | Oct 02 07:31:44 PM UTC 24 |
| Peak memory | 208220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719625925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2719625925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_perf.1606140789 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 12717555238 ps |
| CPU time | 126.34 seconds |
| Started | Oct 02 07:30:20 PM UTC 24 |
| Finished | Oct 02 07:32:29 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606140789 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1606140789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_rx_oversample.1212722619 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 4416777292 ps |
| CPU time | 3.17 seconds |
| Started | Oct 02 07:29:49 PM UTC 24 |
| Finished | Oct 02 07:29:54 PM UTC 24 |
| Peak memory | 208588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212722619 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1212722619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.2201975852 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 9191470956 ps |
| CPU time | 8.2 seconds |
| Started | Oct 02 07:30:05 PM UTC 24 |
| Finished | Oct 02 07:30:14 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201975852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2201975852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.3161632466 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 4269036911 ps |
| CPU time | 3.81 seconds |
| Started | Oct 02 07:30:04 PM UTC 24 |
| Finished | Oct 02 07:30:09 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161632466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3161632466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_smoke.1010595369 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 592842850 ps |
| CPU time | 2.27 seconds |
| Started | Oct 02 07:29:43 PM UTC 24 |
| Finished | Oct 02 07:29:46 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010595369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1010595369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_stress_all.2174928427 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 203418967659 ps |
| CPU time | 159.16 seconds |
| Started | Oct 02 07:30:26 PM UTC 24 |
| Finished | Oct 02 07:33:08 PM UTC 24 |
| Peak memory | 207876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174928427 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2174928427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.944424050 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 11977028301 ps |
| CPU time | 53.97 seconds |
| Started | Oct 02 07:30:24 PM UTC 24 |
| Finished | Oct 02 07:31:20 PM UTC 24 |
| Peak memory | 224268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=944424050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all_ with_rand_reset.944424050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.949269931 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 6655271624 ps |
| CPU time | 25.42 seconds |
| Started | Oct 02 07:30:10 PM UTC 24 |
| Finished | Oct 02 07:30:37 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949269931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.949269931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_tx_rx.2469202769 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 93172756761 ps |
| CPU time | 169.98 seconds |
| Started | Oct 02 07:29:45 PM UTC 24 |
| Finished | Oct 02 07:32:38 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469202769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2469202769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/44.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_alert_test.446066456 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 85562282 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 07:31:24 PM UTC 24 |
| Finished | Oct 02 07:31:26 PM UTC 24 |
| Peak memory | 203252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446066456 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.446066456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_fifo_full.2058289201 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 31334653295 ps |
| CPU time | 56.02 seconds |
| Started | Oct 02 07:30:40 PM UTC 24 |
| Finished | Oct 02 07:31:37 PM UTC 24 |
| Peak memory | 204044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058289201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2058289201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.3797959251 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 27732186067 ps |
| CPU time | 50.27 seconds |
| Started | Oct 02 07:30:44 PM UTC 24 |
| Finished | Oct 02 07:31:36 PM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797959251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3797959251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_fifo_reset.1364886934 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 34821074523 ps |
| CPU time | 44.03 seconds |
| Started | Oct 02 07:30:44 PM UTC 24 |
| Finished | Oct 02 07:31:30 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364886934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1364886934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_intr.1905337110 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 65339366209 ps |
| CPU time | 207.03 seconds |
| Started | Oct 02 07:30:52 PM UTC 24 |
| Finished | Oct 02 07:34:23 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905337110 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1905337110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.64755920 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 128858269208 ps |
| CPU time | 308.78 seconds |
| Started | Oct 02 07:31:21 PM UTC 24 |
| Finished | Oct 02 07:36:34 PM UTC 24 |
| Peak memory | 204040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64755920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.64755920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_loopback.3084990545 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1168544955 ps |
| CPU time | 2.91 seconds |
| Started | Oct 02 07:31:07 PM UTC 24 |
| Finished | Oct 02 07:31:11 PM UTC 24 |
| Peak memory | 205752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084990545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3084990545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_noise_filter.3508601050 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 22489471507 ps |
| CPU time | 55.08 seconds |
| Started | Oct 02 07:30:55 PM UTC 24 |
| Finished | Oct 02 07:31:52 PM UTC 24 |
| Peak memory | 205896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508601050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3508601050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_perf.1670983892 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 17176333055 ps |
| CPU time | 527.52 seconds |
| Started | Oct 02 07:31:12 PM UTC 24 |
| Finished | Oct 02 07:40:06 PM UTC 24 |
| Peak memory | 203860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670983892 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1670983892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_rx_oversample.1585043550 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 3712064340 ps |
| CPU time | 10.69 seconds |
| Started | Oct 02 07:30:51 PM UTC 24 |
| Finished | Oct 02 07:31:03 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585043550 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1585043550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.3826569030 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 46356624228 ps |
| CPU time | 74.08 seconds |
| Started | Oct 02 07:31:00 PM UTC 24 |
| Finished | Oct 02 07:32:16 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826569030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3826569030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.2187865213 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 3224926078 ps |
| CPU time | 2.35 seconds |
| Started | Oct 02 07:30:56 PM UTC 24 |
| Finished | Oct 02 07:31:00 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187865213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2187865213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_smoke.804158605 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 5327267876 ps |
| CPU time | 26.41 seconds |
| Started | Oct 02 07:30:38 PM UTC 24 |
| Finished | Oct 02 07:31:05 PM UTC 24 |
| Peak memory | 203832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804158605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 45.uart_smoke.804158605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.2987710118 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 4577527228 ps |
| CPU time | 25.57 seconds |
| Started | Oct 02 07:31:22 PM UTC 24 |
| Finished | Oct 02 07:31:49 PM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2987710118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all _with_rand_reset.2987710118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.2943939702 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 6076076602 ps |
| CPU time | 29.47 seconds |
| Started | Oct 02 07:31:03 PM UTC 24 |
| Finished | Oct 02 07:31:34 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943939702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2943939702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_tx_rx.3354875582 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 59034804930 ps |
| CPU time | 110.22 seconds |
| Started | Oct 02 07:30:38 PM UTC 24 |
| Finished | Oct 02 07:32:30 PM UTC 24 |
| Peak memory | 203900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354875582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3354875582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/45.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_alert_test.2947967710 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 37083234 ps |
| CPU time | 0.9 seconds |
| Started | Oct 02 07:32:03 PM UTC 24 |
| Finished | Oct 02 07:32:05 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947967710 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2947967710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_fifo_full.2116220591 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 18250662885 ps |
| CPU time | 28.94 seconds |
| Started | Oct 02 07:31:30 PM UTC 24 |
| Finished | Oct 02 07:32:00 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116220591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2116220591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.2204966427 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 200905409306 ps |
| CPU time | 469.28 seconds |
| Started | Oct 02 07:31:35 PM UTC 24 |
| Finished | Oct 02 07:39:31 PM UTC 24 |
| Peak memory | 209204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204966427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2204966427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_fifo_reset.4125120466 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 85548025241 ps |
| CPU time | 256.19 seconds |
| Started | Oct 02 07:31:36 PM UTC 24 |
| Finished | Oct 02 07:35:57 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125120466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.4125120466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_intr.3967037768 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 50589301221 ps |
| CPU time | 92.38 seconds |
| Started | Oct 02 07:31:44 PM UTC 24 |
| Finished | Oct 02 07:33:19 PM UTC 24 |
| Peak memory | 204096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967037768 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3967037768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.3420333605 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 69895370989 ps |
| CPU time | 344.98 seconds |
| Started | Oct 02 07:31:56 PM UTC 24 |
| Finished | Oct 02 07:37:47 PM UTC 24 |
| Peak memory | 205896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420333605 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3420333605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_loopback.363004845 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 1037997223 ps |
| CPU time | 2.08 seconds |
| Started | Oct 02 07:31:53 PM UTC 24 |
| Finished | Oct 02 07:31:56 PM UTC 24 |
| Peak memory | 205560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363004845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 46.uart_loopback.363004845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_noise_filter.3755272229 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 105026561275 ps |
| CPU time | 171.75 seconds |
| Started | Oct 02 07:31:45 PM UTC 24 |
| Finished | Oct 02 07:34:40 PM UTC 24 |
| Peak memory | 218704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755272229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3755272229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_perf.3497726064 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 20534006277 ps |
| CPU time | 255.41 seconds |
| Started | Oct 02 07:31:54 PM UTC 24 |
| Finished | Oct 02 07:36:14 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497726064 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3497726064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_rx_oversample.3934583508 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 2832653253 ps |
| CPU time | 27.56 seconds |
| Started | Oct 02 07:31:39 PM UTC 24 |
| Finished | Oct 02 07:32:08 PM UTC 24 |
| Peak memory | 208496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934583508 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3934583508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.2285772600 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 16287510344 ps |
| CPU time | 53.98 seconds |
| Started | Oct 02 07:31:50 PM UTC 24 |
| Finished | Oct 02 07:32:46 PM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285772600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2285772600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.2328844266 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 3797408663 ps |
| CPU time | 3.6 seconds |
| Started | Oct 02 07:31:45 PM UTC 24 |
| Finished | Oct 02 07:31:50 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328844266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2328844266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_smoke.1365121637 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 110560186 ps |
| CPU time | 1.14 seconds |
| Started | Oct 02 07:31:27 PM UTC 24 |
| Finished | Oct 02 07:31:29 PM UTC 24 |
| Peak memory | 205364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365121637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1365121637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_stress_all.2330478337 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 136969501032 ps |
| CPU time | 334.38 seconds |
| Started | Oct 02 07:32:01 PM UTC 24 |
| Finished | Oct 02 07:37:41 PM UTC 24 |
| Peak memory | 206156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330478337 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2330478337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.3476229634 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 19251302907 ps |
| CPU time | 67.21 seconds |
| Started | Oct 02 07:31:57 PM UTC 24 |
| Finished | Oct 02 07:33:07 PM UTC 24 |
| Peak memory | 224460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3476229634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all _with_rand_reset.3476229634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.3736943972 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2106580825 ps |
| CPU time | 3.44 seconds |
| Started | Oct 02 07:31:51 PM UTC 24 |
| Finished | Oct 02 07:31:56 PM UTC 24 |
| Peak memory | 203868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736943972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3736943972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_tx_rx.1087705117 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 21262108450 ps |
| CPU time | 21.87 seconds |
| Started | Oct 02 07:31:30 PM UTC 24 |
| Finished | Oct 02 07:31:53 PM UTC 24 |
| Peak memory | 207676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087705117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1087705117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/46.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_alert_test.1547088852 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 13554285 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 07:32:39 PM UTC 24 |
| Finished | Oct 02 07:32:41 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547088852 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1547088852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_fifo_full.1019432252 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 160736718815 ps |
| CPU time | 184.42 seconds |
| Started | Oct 02 07:32:08 PM UTC 24 |
| Finished | Oct 02 07:35:15 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019432252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1019432252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.2388554042 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 103683912860 ps |
| CPU time | 24.65 seconds |
| Started | Oct 02 07:32:09 PM UTC 24 |
| Finished | Oct 02 07:32:35 PM UTC 24 |
| Peak memory | 209048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388554042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2388554042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_fifo_reset.3525095922 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 142880478052 ps |
| CPU time | 112.59 seconds |
| Started | Oct 02 07:32:17 PM UTC 24 |
| Finished | Oct 02 07:34:12 PM UTC 24 |
| Peak memory | 209028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525095922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3525095922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_intr.4267782012 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 130959795232 ps |
| CPU time | 348.3 seconds |
| Started | Oct 02 07:32:20 PM UTC 24 |
| Finished | Oct 02 07:38:14 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267782012 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.4267782012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.495333523 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 216254337214 ps |
| CPU time | 394.9 seconds |
| Started | Oct 02 07:32:36 PM UTC 24 |
| Finished | Oct 02 07:39:16 PM UTC 24 |
| Peak memory | 209404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495333523 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.495333523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_loopback.810842068 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 2246323958 ps |
| CPU time | 5.69 seconds |
| Started | Oct 02 07:32:35 PM UTC 24 |
| Finished | Oct 02 07:32:42 PM UTC 24 |
| Peak memory | 205624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810842068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 47.uart_loopback.810842068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_noise_filter.460933734 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 19590405732 ps |
| CPU time | 81.19 seconds |
| Started | Oct 02 07:32:26 PM UTC 24 |
| Finished | Oct 02 07:33:50 PM UTC 24 |
| Peak memory | 209668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460933734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.460933734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_perf.2426795593 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 21669560233 ps |
| CPU time | 555.08 seconds |
| Started | Oct 02 07:32:36 PM UTC 24 |
| Finished | Oct 02 07:41:59 PM UTC 24 |
| Peak memory | 205260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426795593 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2426795593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_rx_oversample.1812255893 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 1699673423 ps |
| CPU time | 14.92 seconds |
| Started | Oct 02 07:32:19 PM UTC 24 |
| Finished | Oct 02 07:32:35 PM UTC 24 |
| Peak memory | 203720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812255893 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1812255893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.4034908029 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 217572303396 ps |
| CPU time | 845.95 seconds |
| Started | Oct 02 07:32:31 PM UTC 24 |
| Finished | Oct 02 07:46:47 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034908029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.4034908029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.1089072161 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 3759448790 ps |
| CPU time | 5.44 seconds |
| Started | Oct 02 07:32:30 PM UTC 24 |
| Finished | Oct 02 07:32:36 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089072161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1089072161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_smoke.1381810918 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 901784128 ps |
| CPU time | 1.9 seconds |
| Started | Oct 02 07:32:04 PM UTC 24 |
| Finished | Oct 02 07:32:07 PM UTC 24 |
| Peak memory | 207480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381810918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1381810918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_stress_all.2623426262 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 443206400246 ps |
| CPU time | 1215.19 seconds |
| Started | Oct 02 07:32:37 PM UTC 24 |
| Finished | Oct 02 07:53:07 PM UTC 24 |
| Peak memory | 221824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623426262 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2623426262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.2248304442 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 5136303376 ps |
| CPU time | 30.4 seconds |
| Started | Oct 02 07:32:37 PM UTC 24 |
| Finished | Oct 02 07:33:09 PM UTC 24 |
| Peak memory | 209704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2248304442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all _with_rand_reset.2248304442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.2934632708 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 611908514 ps |
| CPU time | 3.52 seconds |
| Started | Oct 02 07:32:32 PM UTC 24 |
| Finished | Oct 02 07:32:36 PM UTC 24 |
| Peak memory | 204044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934632708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2934632708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_tx_rx.3699555543 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 50982889812 ps |
| CPU time | 27.01 seconds |
| Started | Oct 02 07:32:06 PM UTC 24 |
| Finished | Oct 02 07:32:34 PM UTC 24 |
| Peak memory | 209596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699555543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3699555543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/47.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_alert_test.1694469745 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 38248338 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 07:33:27 PM UTC 24 |
| Finished | Oct 02 07:33:29 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694469745 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1694469745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_fifo_full.3321903657 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 245790945105 ps |
| CPU time | 78.75 seconds |
| Started | Oct 02 07:32:45 PM UTC 24 |
| Finished | Oct 02 07:34:06 PM UTC 24 |
| Peak memory | 203712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321903657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3321903657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.2488986976 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 92704166749 ps |
| CPU time | 100.12 seconds |
| Started | Oct 02 07:32:47 PM UTC 24 |
| Finished | Oct 02 07:34:29 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488986976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2488986976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_fifo_reset.3272366589 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 17365132611 ps |
| CPU time | 71.85 seconds |
| Started | Oct 02 07:32:51 PM UTC 24 |
| Finished | Oct 02 07:34:04 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272366589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3272366589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_intr.1387182827 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 21824170301 ps |
| CPU time | 7.84 seconds |
| Started | Oct 02 07:32:56 PM UTC 24 |
| Finished | Oct 02 07:33:05 PM UTC 24 |
| Peak memory | 208964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387182827 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1387182827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.600287613 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 90117295674 ps |
| CPU time | 871.99 seconds |
| Started | Oct 02 07:33:09 PM UTC 24 |
| Finished | Oct 02 07:47:53 PM UTC 24 |
| Peak memory | 212656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600287613 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.600287613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_loopback.3294204239 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 12589575462 ps |
| CPU time | 47.12 seconds |
| Started | Oct 02 07:33:07 PM UTC 24 |
| Finished | Oct 02 07:33:56 PM UTC 24 |
| Peak memory | 203780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294204239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3294204239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_noise_filter.1812611657 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 91475685287 ps |
| CPU time | 307.34 seconds |
| Started | Oct 02 07:32:57 PM UTC 24 |
| Finished | Oct 02 07:38:09 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812611657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1812611657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_perf.2003093295 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 6286751697 ps |
| CPU time | 289.1 seconds |
| Started | Oct 02 07:33:08 PM UTC 24 |
| Finished | Oct 02 07:38:02 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003093295 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2003093295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_rx_oversample.623973710 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 6795100751 ps |
| CPU time | 56 seconds |
| Started | Oct 02 07:32:56 PM UTC 24 |
| Finished | Oct 02 07:33:53 PM UTC 24 |
| Peak memory | 207872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623973710 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.623973710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.2957598094 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 56041750731 ps |
| CPU time | 156.25 seconds |
| Started | Oct 02 07:33:05 PM UTC 24 |
| Finished | Oct 02 07:35:44 PM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957598094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2957598094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.2702705142 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 3699572847 ps |
| CPU time | 13.08 seconds |
| Started | Oct 02 07:33:00 PM UTC 24 |
| Finished | Oct 02 07:33:14 PM UTC 24 |
| Peak memory | 203504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702705142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2702705142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_smoke.3696547800 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 267431635 ps |
| CPU time | 1.52 seconds |
| Started | Oct 02 07:32:42 PM UTC 24 |
| Finished | Oct 02 07:32:45 PM UTC 24 |
| Peak memory | 203332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696547800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3696547800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_stress_all.4255759179 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 310671995385 ps |
| CPU time | 1016.21 seconds |
| Started | Oct 02 07:33:20 PM UTC 24 |
| Finished | Oct 02 07:50:28 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255759179 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.4255759179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.936091312 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 5356720740 ps |
| CPU time | 50.47 seconds |
| Started | Oct 02 07:33:16 PM UTC 24 |
| Finished | Oct 02 07:34:08 PM UTC 24 |
| Peak memory | 218304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=936091312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all_ with_rand_reset.936091312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.3339621383 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 6927794522 ps |
| CPU time | 45.63 seconds |
| Started | Oct 02 07:33:06 PM UTC 24 |
| Finished | Oct 02 07:33:53 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339621383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3339621383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_tx_rx.1886080402 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 70451194214 ps |
| CPU time | 186.79 seconds |
| Started | Oct 02 07:32:42 PM UTC 24 |
| Finished | Oct 02 07:35:52 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886080402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1886080402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/48.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_alert_test.79056108 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 25993999 ps |
| CPU time | 0.82 seconds |
| Started | Oct 02 07:34:13 PM UTC 24 |
| Finished | Oct 02 07:34:15 PM UTC 24 |
| Peak memory | 203184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79056108 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.79056108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_fifo_full.405088772 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 49790744428 ps |
| CPU time | 36.61 seconds |
| Started | Oct 02 07:33:47 PM UTC 24 |
| Finished | Oct 02 07:34:25 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405088772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.405088772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.3626517464 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 255623347260 ps |
| CPU time | 102.66 seconds |
| Started | Oct 02 07:33:50 PM UTC 24 |
| Finished | Oct 02 07:35:35 PM UTC 24 |
| Peak memory | 209520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626517464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3626517464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_fifo_reset.3129221435 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 22473496449 ps |
| CPU time | 46.34 seconds |
| Started | Oct 02 07:33:54 PM UTC 24 |
| Finished | Oct 02 07:34:42 PM UTC 24 |
| Peak memory | 209352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129221435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3129221435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_intr.1904076923 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 48866187431 ps |
| CPU time | 25.97 seconds |
| Started | Oct 02 07:33:54 PM UTC 24 |
| Finished | Oct 02 07:34:22 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904076923 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1904076923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.3834862243 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 73995045664 ps |
| CPU time | 429.26 seconds |
| Started | Oct 02 07:34:07 PM UTC 24 |
| Finished | Oct 02 07:41:22 PM UTC 24 |
| Peak memory | 209164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834862243 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3834862243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_loopback.3662161874 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 6080508587 ps |
| CPU time | 8.97 seconds |
| Started | Oct 02 07:34:05 PM UTC 24 |
| Finished | Oct 02 07:34:15 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662161874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3662161874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_noise_filter.1112198156 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 64163464488 ps |
| CPU time | 118.71 seconds |
| Started | Oct 02 07:33:57 PM UTC 24 |
| Finished | Oct 02 07:35:58 PM UTC 24 |
| Peak memory | 208996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112198156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1112198156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_perf.2785604619 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 12780943001 ps |
| CPU time | 245.41 seconds |
| Started | Oct 02 07:34:07 PM UTC 24 |
| Finished | Oct 02 07:38:16 PM UTC 24 |
| Peak memory | 203892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785604619 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2785604619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_rx_oversample.3349426827 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 1375224402 ps |
| CPU time | 6.19 seconds |
| Started | Oct 02 07:33:54 PM UTC 24 |
| Finished | Oct 02 07:34:02 PM UTC 24 |
| Peak memory | 208200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349426827 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3349426827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.2092195333 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 34312512772 ps |
| CPU time | 73.25 seconds |
| Started | Oct 02 07:34:03 PM UTC 24 |
| Finished | Oct 02 07:35:18 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092195333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2092195333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.466285519 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 38376957878 ps |
| CPU time | 14.03 seconds |
| Started | Oct 02 07:33:58 PM UTC 24 |
| Finished | Oct 02 07:34:13 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466285519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.466285519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_smoke.3594389645 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 5394204820 ps |
| CPU time | 25.61 seconds |
| Started | Oct 02 07:33:30 PM UTC 24 |
| Finished | Oct 02 07:33:57 PM UTC 24 |
| Peak memory | 204168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594389645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3594389645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_stress_all.14200646 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 182986740843 ps |
| CPU time | 260.87 seconds |
| Started | Oct 02 07:34:08 PM UTC 24 |
| Finished | Oct 02 07:38:33 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14200646 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.14200646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.3381799709 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 3249437972 ps |
| CPU time | 16.83 seconds |
| Started | Oct 02 07:34:08 PM UTC 24 |
| Finished | Oct 02 07:34:26 PM UTC 24 |
| Peak memory | 220344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3381799709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all _with_rand_reset.3381799709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.425293192 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 1482737713 ps |
| CPU time | 1.9 seconds |
| Started | Oct 02 07:34:03 PM UTC 24 |
| Finished | Oct 02 07:34:06 PM UTC 24 |
| Peak memory | 203332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425293192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.425293192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_tx_rx.2410206301 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 15292789980 ps |
| CPU time | 42.72 seconds |
| Started | Oct 02 07:33:31 PM UTC 24 |
| Finished | Oct 02 07:34:15 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410206301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2410206301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/49.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_alert_test.4228182824 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 43330765 ps |
| CPU time | 0.84 seconds |
| Started | Oct 02 07:07:46 PM UTC 24 |
| Finished | Oct 02 07:07:48 PM UTC 24 |
| Peak memory | 203256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228182824 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.4228182824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_fifo_full.844407706 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 100666551579 ps |
| CPU time | 42.01 seconds |
| Started | Oct 02 07:07:34 PM UTC 24 |
| Finished | Oct 02 07:08:17 PM UTC 24 |
| Peak memory | 209648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844407706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.844407706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.1972293968 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 46299959914 ps |
| CPU time | 20.77 seconds |
| Started | Oct 02 07:07:34 PM UTC 24 |
| Finished | Oct 02 07:07:56 PM UTC 24 |
| Peak memory | 204044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972293968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1972293968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_fifo_reset.1846366271 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 9363320137 ps |
| CPU time | 29.68 seconds |
| Started | Oct 02 07:07:35 PM UTC 24 |
| Finished | Oct 02 07:08:06 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846366271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1846366271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_intr.2080187674 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 286275410980 ps |
| CPU time | 271.82 seconds |
| Started | Oct 02 07:07:36 PM UTC 24 |
| Finished | Oct 02 07:12:12 PM UTC 24 |
| Peak memory | 203572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080187674 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2080187674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_loopback.3587716436 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 734093195 ps |
| CPU time | 3.91 seconds |
| Started | Oct 02 07:07:40 PM UTC 24 |
| Finished | Oct 02 07:07:45 PM UTC 24 |
| Peak memory | 205560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587716436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3587716436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_noise_filter.709537520 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 85703917409 ps |
| CPU time | 155.98 seconds |
| Started | Oct 02 07:07:37 PM UTC 24 |
| Finished | Oct 02 07:10:16 PM UTC 24 |
| Peak memory | 220808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709537520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.709537520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_perf.331358150 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 9473450857 ps |
| CPU time | 507.42 seconds |
| Started | Oct 02 07:07:41 PM UTC 24 |
| Finished | Oct 02 07:16:15 PM UTC 24 |
| Peak memory | 205168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331358150 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.331358150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_rx_oversample.2513944631 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2700830867 ps |
| CPU time | 31.85 seconds |
| Started | Oct 02 07:07:35 PM UTC 24 |
| Finished | Oct 02 07:08:08 PM UTC 24 |
| Peak memory | 208100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513944631 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2513944631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.2746593765 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 80885814985 ps |
| CPU time | 159.79 seconds |
| Started | Oct 02 07:07:37 PM UTC 24 |
| Finished | Oct 02 07:10:20 PM UTC 24 |
| Peak memory | 208588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746593765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2746593765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.1844618151 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3151759800 ps |
| CPU time | 12.5 seconds |
| Started | Oct 02 07:07:37 PM UTC 24 |
| Finished | Oct 02 07:07:51 PM UTC 24 |
| Peak memory | 203836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844618151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1844618151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_smoke.4179236315 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 127823200 ps |
| CPU time | 1.31 seconds |
| Started | Oct 02 07:07:34 PM UTC 24 |
| Finished | Oct 02 07:07:36 PM UTC 24 |
| Peak memory | 203268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179236315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.uart_smoke.4179236315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.88330207 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6042230265 ps |
| CPU time | 18.51 seconds |
| Started | Oct 02 07:07:45 PM UTC 24 |
| Finished | Oct 02 07:08:05 PM UTC 24 |
| Peak memory | 218556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=88330207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_wi th_rand_reset.88330207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.2915960850 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1089251263 ps |
| CPU time | 6.78 seconds |
| Started | Oct 02 07:07:39 PM UTC 24 |
| Finished | Oct 02 07:07:46 PM UTC 24 |
| Peak memory | 204040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915960850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2915960850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/5.uart_tx_rx.703197838 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 81739928296 ps |
| CPU time | 119.2 seconds |
| Started | Oct 02 07:07:34 PM UTC 24 |
| Finished | Oct 02 07:09:35 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703197838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.703197838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/5.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/50.uart_fifo_reset.689451929 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 126417723319 ps |
| CPU time | 46.58 seconds |
| Started | Oct 02 07:34:13 PM UTC 24 |
| Finished | Oct 02 07:35:01 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689451929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.689451929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/50.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.1550963986 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 10740518363 ps |
| CPU time | 53.57 seconds |
| Started | Oct 02 07:34:15 PM UTC 24 |
| Finished | Oct 02 07:35:10 PM UTC 24 |
| Peak memory | 222400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1550963986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all _with_rand_reset.1550963986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/51.uart_fifo_reset.664760812 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 31831865127 ps |
| CPU time | 20.65 seconds |
| Started | Oct 02 07:34:16 PM UTC 24 |
| Finished | Oct 02 07:34:38 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664760812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.664760812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/51.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.2734931479 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 2931231050 ps |
| CPU time | 58.88 seconds |
| Started | Oct 02 07:34:16 PM UTC 24 |
| Finished | Oct 02 07:35:16 PM UTC 24 |
| Peak memory | 220264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2734931479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all _with_rand_reset.2734931479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/52.uart_fifo_reset.1363652056 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 51007832802 ps |
| CPU time | 166.69 seconds |
| Started | Oct 02 07:34:16 PM UTC 24 |
| Finished | Oct 02 07:37:05 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363652056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1363652056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/52.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.1303185056 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 4039880291 ps |
| CPU time | 64.2 seconds |
| Started | Oct 02 07:34:17 PM UTC 24 |
| Finished | Oct 02 07:35:23 PM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1303185056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all _with_rand_reset.1303185056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/53.uart_fifo_reset.3317557689 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 122952228878 ps |
| CPU time | 162.31 seconds |
| Started | Oct 02 07:34:22 PM UTC 24 |
| Finished | Oct 02 07:37:07 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317557689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3317557689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/53.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.3086495777 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 3640534400 ps |
| CPU time | 130.63 seconds |
| Started | Oct 02 07:34:23 PM UTC 24 |
| Finished | Oct 02 07:36:37 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3086495777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all _with_rand_reset.3086495777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/54.uart_fifo_reset.2689990500 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 5028486703 ps |
| CPU time | 21.35 seconds |
| Started | Oct 02 07:34:26 PM UTC 24 |
| Finished | Oct 02 07:34:49 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689990500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2689990500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/54.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.3000971699 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 4274830600 ps |
| CPU time | 51.21 seconds |
| Started | Oct 02 07:34:27 PM UTC 24 |
| Finished | Oct 02 07:35:20 PM UTC 24 |
| Peak memory | 220616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3000971699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all _with_rand_reset.3000971699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/55.uart_fifo_reset.135354678 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 123804614407 ps |
| CPU time | 223.47 seconds |
| Started | Oct 02 07:34:29 PM UTC 24 |
| Finished | Oct 02 07:38:16 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135354678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.135354678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/55.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.1791359661 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 2997365772 ps |
| CPU time | 41.02 seconds |
| Started | Oct 02 07:34:39 PM UTC 24 |
| Finished | Oct 02 07:35:22 PM UTC 24 |
| Peak memory | 209460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1791359661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all _with_rand_reset.1791359661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/56.uart_fifo_reset.3881671919 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 90690294759 ps |
| CPU time | 27.15 seconds |
| Started | Oct 02 07:34:41 PM UTC 24 |
| Finished | Oct 02 07:35:09 PM UTC 24 |
| Peak memory | 209648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881671919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3881671919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/56.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.1553199 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 4328072607 ps |
| CPU time | 10.82 seconds |
| Started | Oct 02 07:34:43 PM UTC 24 |
| Finished | Oct 02 07:34:55 PM UTC 24 |
| Peak memory | 209452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1553199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all_wi th_rand_reset.1553199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/57.uart_fifo_reset.2201039071 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 78666934779 ps |
| CPU time | 181.49 seconds |
| Started | Oct 02 07:34:50 PM UTC 24 |
| Finished | Oct 02 07:37:54 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201039071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2201039071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/57.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.4037061528 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 10682754057 ps |
| CPU time | 30.61 seconds |
| Started | Oct 02 07:34:56 PM UTC 24 |
| Finished | Oct 02 07:35:28 PM UTC 24 |
| Peak memory | 220544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4037061528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all _with_rand_reset.4037061528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/58.uart_fifo_reset.2007629678 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 38405902284 ps |
| CPU time | 136.7 seconds |
| Started | Oct 02 07:34:58 PM UTC 24 |
| Finished | Oct 02 07:37:18 PM UTC 24 |
| Peak memory | 204152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007629678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2007629678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/58.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.2314704329 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 3937860647 ps |
| CPU time | 42.45 seconds |
| Started | Oct 02 07:35:02 PM UTC 24 |
| Finished | Oct 02 07:35:46 PM UTC 24 |
| Peak memory | 220668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2314704329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all _with_rand_reset.2314704329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/59.uart_fifo_reset.4094849466 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 78112401547 ps |
| CPU time | 118.06 seconds |
| Started | Oct 02 07:35:10 PM UTC 24 |
| Finished | Oct 02 07:37:10 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094849466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.4094849466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/59.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.3186405091 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 14436894559 ps |
| CPU time | 48.85 seconds |
| Started | Oct 02 07:35:10 PM UTC 24 |
| Finished | Oct 02 07:36:01 PM UTC 24 |
| Peak memory | 225748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3186405091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all _with_rand_reset.3186405091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_alert_test.4164946255 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 30841462 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 07:08:02 PM UTC 24 |
| Finished | Oct 02 07:08:04 PM UTC 24 |
| Peak memory | 203256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164946255 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.4164946255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_fifo_full.220099832 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 80491834591 ps |
| CPU time | 168.76 seconds |
| Started | Oct 02 07:07:49 PM UTC 24 |
| Finished | Oct 02 07:10:41 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220099832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.220099832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.516772517 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 17193944725 ps |
| CPU time | 41.36 seconds |
| Started | Oct 02 07:07:49 PM UTC 24 |
| Finished | Oct 02 07:08:32 PM UTC 24 |
| Peak memory | 204112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516772517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.516772517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_fifo_reset.3793722797 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6082081120 ps |
| CPU time | 13.53 seconds |
| Started | Oct 02 07:07:50 PM UTC 24 |
| Finished | Oct 02 07:08:05 PM UTC 24 |
| Peak memory | 209396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793722797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3793722797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.765119480 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 65032599983 ps |
| CPU time | 132.26 seconds |
| Started | Oct 02 07:08:01 PM UTC 24 |
| Finished | Oct 02 07:10:16 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765119480 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.765119480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_loopback.768338312 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 5409240480 ps |
| CPU time | 7.87 seconds |
| Started | Oct 02 07:07:56 PM UTC 24 |
| Finished | Oct 02 07:08:06 PM UTC 24 |
| Peak memory | 208004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768338312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 6.uart_loopback.768338312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_noise_filter.1892440270 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 56556215548 ps |
| CPU time | 36.02 seconds |
| Started | Oct 02 07:07:55 PM UTC 24 |
| Finished | Oct 02 07:08:33 PM UTC 24 |
| Peak memory | 209664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892440270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1892440270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_rx_oversample.1578179165 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 6837811397 ps |
| CPU time | 73.06 seconds |
| Started | Oct 02 07:07:52 PM UTC 24 |
| Finished | Oct 02 07:09:07 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578179165 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1578179165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.2135085644 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 104712122000 ps |
| CPU time | 138.45 seconds |
| Started | Oct 02 07:07:55 PM UTC 24 |
| Finished | Oct 02 07:10:16 PM UTC 24 |
| Peak memory | 208124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135085644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2135085644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.153355219 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3652996288 ps |
| CPU time | 4.87 seconds |
| Started | Oct 02 07:07:55 PM UTC 24 |
| Finished | Oct 02 07:08:01 PM UTC 24 |
| Peak memory | 203512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153355219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.153355219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_smoke.3837693309 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 626702781 ps |
| CPU time | 4.32 seconds |
| Started | Oct 02 07:07:47 PM UTC 24 |
| Finished | Oct 02 07:07:53 PM UTC 24 |
| Peak memory | 203728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837693309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3837693309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_stress_all.3720789584 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 105929817365 ps |
| CPU time | 56.07 seconds |
| Started | Oct 02 07:08:02 PM UTC 24 |
| Finished | Oct 02 07:09:00 PM UTC 24 |
| Peak memory | 205820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720789584 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3720789584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.2714375775 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8179786606 ps |
| CPU time | 60.24 seconds |
| Started | Oct 02 07:08:01 PM UTC 24 |
| Finished | Oct 02 07:09:03 PM UTC 24 |
| Peak memory | 225208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2714375775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_ with_rand_reset.2714375775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.1985177528 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 639521714 ps |
| CPU time | 2.21 seconds |
| Started | Oct 02 07:07:56 PM UTC 24 |
| Finished | Oct 02 07:08:00 PM UTC 24 |
| Peak memory | 203836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985177528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1985177528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/6.uart_tx_rx.96926690 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 115163143731 ps |
| CPU time | 35.13 seconds |
| Started | Oct 02 07:07:49 PM UTC 24 |
| Finished | Oct 02 07:08:25 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96926690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.96926690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/6.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/60.uart_fifo_reset.780532873 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 180416312290 ps |
| CPU time | 795.17 seconds |
| Started | Oct 02 07:35:16 PM UTC 24 |
| Finished | Oct 02 07:48:42 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780532873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.780532873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/60.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.3888381425 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 3509120668 ps |
| CPU time | 14.36 seconds |
| Started | Oct 02 07:35:18 PM UTC 24 |
| Finished | Oct 02 07:35:33 PM UTC 24 |
| Peak memory | 218304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3888381425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all _with_rand_reset.3888381425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/61.uart_fifo_reset.2861476795 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 7326758114 ps |
| CPU time | 11.14 seconds |
| Started | Oct 02 07:35:19 PM UTC 24 |
| Finished | Oct 02 07:35:31 PM UTC 24 |
| Peak memory | 208124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861476795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2861476795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/61.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.717061490 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 7237510914 ps |
| CPU time | 28.69 seconds |
| Started | Oct 02 07:35:21 PM UTC 24 |
| Finished | Oct 02 07:35:51 PM UTC 24 |
| Peak memory | 220328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=717061490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all_ with_rand_reset.717061490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/62.uart_fifo_reset.3999269713 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 121458037044 ps |
| CPU time | 41.51 seconds |
| Started | Oct 02 07:35:23 PM UTC 24 |
| Finished | Oct 02 07:36:06 PM UTC 24 |
| Peak memory | 209512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999269713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3999269713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/62.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.99332691 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 4258256380 ps |
| CPU time | 26.67 seconds |
| Started | Oct 02 07:35:24 PM UTC 24 |
| Finished | Oct 02 07:35:52 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=99332691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all_w ith_rand_reset.99332691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/63.uart_fifo_reset.1613184470 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 14937572792 ps |
| CPU time | 50.69 seconds |
| Started | Oct 02 07:35:29 PM UTC 24 |
| Finished | Oct 02 07:36:21 PM UTC 24 |
| Peak memory | 209464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613184470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1613184470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/63.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.708920852 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 9034960044 ps |
| CPU time | 43.39 seconds |
| Started | Oct 02 07:35:29 PM UTC 24 |
| Finished | Oct 02 07:36:14 PM UTC 24 |
| Peak memory | 220920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=708920852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all_ with_rand_reset.708920852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/64.uart_fifo_reset.3199687405 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 39329471089 ps |
| CPU time | 44.68 seconds |
| Started | Oct 02 07:35:32 PM UTC 24 |
| Finished | Oct 02 07:36:18 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199687405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3199687405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/64.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.455094354 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 1047726945 ps |
| CPU time | 17.36 seconds |
| Started | Oct 02 07:35:34 PM UTC 24 |
| Finished | Oct 02 07:35:53 PM UTC 24 |
| Peak memory | 224708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=455094354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all_ with_rand_reset.455094354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/65.uart_fifo_reset.863179736 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 166860824754 ps |
| CPU time | 201.98 seconds |
| Started | Oct 02 07:35:36 PM UTC 24 |
| Finished | Oct 02 07:39:02 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863179736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.863179736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/65.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.1358957412 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 3123942919 ps |
| CPU time | 60.87 seconds |
| Started | Oct 02 07:35:40 PM UTC 24 |
| Finished | Oct 02 07:36:43 PM UTC 24 |
| Peak memory | 218568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1358957412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all _with_rand_reset.1358957412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/66.uart_fifo_reset.2552153114 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 111004368232 ps |
| CPU time | 113.84 seconds |
| Started | Oct 02 07:35:44 PM UTC 24 |
| Finished | Oct 02 07:37:40 PM UTC 24 |
| Peak memory | 209608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552153114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2552153114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/66.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.425741744 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 3275658779 ps |
| CPU time | 51.7 seconds |
| Started | Oct 02 07:35:45 PM UTC 24 |
| Finished | Oct 02 07:36:38 PM UTC 24 |
| Peak memory | 220292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=425741744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all_ with_rand_reset.425741744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/67.uart_fifo_reset.1982110294 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 74222229863 ps |
| CPU time | 65.95 seconds |
| Started | Oct 02 07:35:47 PM UTC 24 |
| Finished | Oct 02 07:36:54 PM UTC 24 |
| Peak memory | 209184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982110294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1982110294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/67.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.1252437500 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 9368394470 ps |
| CPU time | 80.75 seconds |
| Started | Oct 02 07:35:52 PM UTC 24 |
| Finished | Oct 02 07:37:15 PM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1252437500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all _with_rand_reset.1252437500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/68.uart_fifo_reset.1623785197 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 67747485023 ps |
| CPU time | 148.81 seconds |
| Started | Oct 02 07:35:53 PM UTC 24 |
| Finished | Oct 02 07:38:24 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623785197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1623785197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/68.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.3343803784 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 22504927728 ps |
| CPU time | 132.26 seconds |
| Started | Oct 02 07:35:53 PM UTC 24 |
| Finished | Oct 02 07:38:08 PM UTC 24 |
| Peak memory | 222904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3343803784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all _with_rand_reset.3343803784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/69.uart_fifo_reset.3845941313 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 233849989877 ps |
| CPU time | 79.06 seconds |
| Started | Oct 02 07:35:54 PM UTC 24 |
| Finished | Oct 02 07:37:15 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845941313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3845941313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/69.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.83020375 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 1680463061 ps |
| CPU time | 32.6 seconds |
| Started | Oct 02 07:35:57 PM UTC 24 |
| Finished | Oct 02 07:36:31 PM UTC 24 |
| Peak memory | 209388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=83020375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all_w ith_rand_reset.83020375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_alert_test.185894995 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 12365038 ps |
| CPU time | 0.92 seconds |
| Started | Oct 02 07:08:26 PM UTC 24 |
| Finished | Oct 02 07:08:28 PM UTC 24 |
| Peak memory | 203192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185894995 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.185894995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_fifo_full.1056060223 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 112302251922 ps |
| CPU time | 92.74 seconds |
| Started | Oct 02 07:08:06 PM UTC 24 |
| Finished | Oct 02 07:09:41 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056060223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1056060223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.2831473011 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 78817759289 ps |
| CPU time | 164.13 seconds |
| Started | Oct 02 07:08:06 PM UTC 24 |
| Finished | Oct 02 07:10:53 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831473011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2831473011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2990719490 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 108415368863 ps |
| CPU time | 210.38 seconds |
| Started | Oct 02 07:08:07 PM UTC 24 |
| Finished | Oct 02 07:11:41 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990719490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2990719490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_intr.573831120 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 49836581392 ps |
| CPU time | 16.7 seconds |
| Started | Oct 02 07:08:10 PM UTC 24 |
| Finished | Oct 02 07:08:28 PM UTC 24 |
| Peak memory | 209324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573831120 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.573831120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.2639125186 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 138711869815 ps |
| CPU time | 1034.02 seconds |
| Started | Oct 02 07:08:19 PM UTC 24 |
| Finished | Oct 02 07:25:46 PM UTC 24 |
| Peak memory | 212992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639125186 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2639125186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_loopback.2477204974 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 3401445260 ps |
| CPU time | 5.29 seconds |
| Started | Oct 02 07:08:13 PM UTC 24 |
| Finished | Oct 02 07:08:19 PM UTC 24 |
| Peak memory | 208316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477204974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2477204974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_noise_filter.1537180912 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 36320237514 ps |
| CPU time | 58.03 seconds |
| Started | Oct 02 07:08:10 PM UTC 24 |
| Finished | Oct 02 07:09:10 PM UTC 24 |
| Peak memory | 208208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537180912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1537180912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_perf.1580705174 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 9185685032 ps |
| CPU time | 160.62 seconds |
| Started | Oct 02 07:08:18 PM UTC 24 |
| Finished | Oct 02 07:11:01 PM UTC 24 |
| Peak memory | 204112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580705174 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1580705174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_rx_oversample.591575005 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 5281439482 ps |
| CPU time | 48.9 seconds |
| Started | Oct 02 07:08:10 PM UTC 24 |
| Finished | Oct 02 07:09:00 PM UTC 24 |
| Peak memory | 208416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591575005 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.591575005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.103358808 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 77429620165 ps |
| CPU time | 38.21 seconds |
| Started | Oct 02 07:08:11 PM UTC 24 |
| Finished | Oct 02 07:08:51 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103358808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.103358808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.2482214892 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 32718808379 ps |
| CPU time | 43.3 seconds |
| Started | Oct 02 07:08:11 PM UTC 24 |
| Finished | Oct 02 07:08:56 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482214892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2482214892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_smoke.117447921 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 915145360 ps |
| CPU time | 4.24 seconds |
| Started | Oct 02 07:08:05 PM UTC 24 |
| Finished | Oct 02 07:08:10 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117447921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 7.uart_smoke.117447921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_stress_all.2419750592 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 66740038527 ps |
| CPU time | 93.12 seconds |
| Started | Oct 02 07:08:23 PM UTC 24 |
| Finished | Oct 02 07:09:58 PM UTC 24 |
| Peak memory | 206156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419750592 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2419750592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.2931061180 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1822114865 ps |
| CPU time | 26.57 seconds |
| Started | Oct 02 07:08:20 PM UTC 24 |
| Finished | Oct 02 07:08:48 PM UTC 24 |
| Peak memory | 218488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2931061180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_ with_rand_reset.2931061180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.3808680250 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1538704225 ps |
| CPU time | 3.45 seconds |
| Started | Oct 02 07:08:12 PM UTC 24 |
| Finished | Oct 02 07:08:17 PM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808680250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3808680250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_tx_rx.4030031236 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 47596210481 ps |
| CPU time | 101.52 seconds |
| Started | Oct 02 07:08:06 PM UTC 24 |
| Finished | Oct 02 07:09:50 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030031236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.4030031236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/7.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/70.uart_fifo_reset.1343624739 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 47233148689 ps |
| CPU time | 40.16 seconds |
| Started | Oct 02 07:35:58 PM UTC 24 |
| Finished | Oct 02 07:36:40 PM UTC 24 |
| Peak memory | 204120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343624739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1343624739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/70.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.3650316512 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 4132354698 ps |
| CPU time | 43.78 seconds |
| Started | Oct 02 07:36:01 PM UTC 24 |
| Finished | Oct 02 07:36:47 PM UTC 24 |
| Peak memory | 220612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3650316512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all _with_rand_reset.3650316512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/71.uart_fifo_reset.2018542295 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 24407927816 ps |
| CPU time | 43.08 seconds |
| Started | Oct 02 07:36:07 PM UTC 24 |
| Finished | Oct 02 07:36:51 PM UTC 24 |
| Peak memory | 209040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018542295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2018542295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/71.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.3751725560 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 12180828882 ps |
| CPU time | 98.28 seconds |
| Started | Oct 02 07:36:15 PM UTC 24 |
| Finished | Oct 02 07:37:55 PM UTC 24 |
| Peak memory | 220920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3751725560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all _with_rand_reset.3751725560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/72.uart_fifo_reset.1968985757 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 30078691674 ps |
| CPU time | 14.9 seconds |
| Started | Oct 02 07:36:15 PM UTC 24 |
| Finished | Oct 02 07:36:31 PM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968985757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1968985757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/72.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.3108148186 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 17720518783 ps |
| CPU time | 36.55 seconds |
| Started | Oct 02 07:36:19 PM UTC 24 |
| Finished | Oct 02 07:36:57 PM UTC 24 |
| Peak memory | 226140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3108148186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all _with_rand_reset.3108148186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/73.uart_fifo_reset.2575780244 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 124383774697 ps |
| CPU time | 210.93 seconds |
| Started | Oct 02 07:36:21 PM UTC 24 |
| Finished | Oct 02 07:39:55 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575780244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2575780244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/73.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.337279683 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 3834523763 ps |
| CPU time | 19.09 seconds |
| Started | Oct 02 07:36:22 PM UTC 24 |
| Finished | Oct 02 07:36:43 PM UTC 24 |
| Peak memory | 218508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=337279683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all_ with_rand_reset.337279683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/74.uart_fifo_reset.1324877380 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 59147626383 ps |
| CPU time | 76.63 seconds |
| Started | Oct 02 07:36:28 PM UTC 24 |
| Finished | Oct 02 07:37:47 PM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324877380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1324877380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/74.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.128203254 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 4323608935 ps |
| CPU time | 65.61 seconds |
| Started | Oct 02 07:36:29 PM UTC 24 |
| Finished | Oct 02 07:37:37 PM UTC 24 |
| Peak memory | 218364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=128203254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all_ with_rand_reset.128203254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/75.uart_fifo_reset.4020803974 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 62175334909 ps |
| CPU time | 133.92 seconds |
| Started | Oct 02 07:36:31 PM UTC 24 |
| Finished | Oct 02 07:38:48 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020803974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.4020803974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/75.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.1059247977 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 2664232264 ps |
| CPU time | 44.25 seconds |
| Started | Oct 02 07:36:32 PM UTC 24 |
| Finished | Oct 02 07:37:18 PM UTC 24 |
| Peak memory | 220288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1059247977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all _with_rand_reset.1059247977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.3594102303 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 1735531825 ps |
| CPU time | 54.45 seconds |
| Started | Oct 02 07:36:38 PM UTC 24 |
| Finished | Oct 02 07:37:34 PM UTC 24 |
| Peak memory | 209384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3594102303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all _with_rand_reset.3594102303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/77.uart_fifo_reset.2940661994 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 64449515412 ps |
| CPU time | 132.82 seconds |
| Started | Oct 02 07:36:39 PM UTC 24 |
| Finished | Oct 02 07:38:54 PM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940661994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2940661994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/77.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.3245118587 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 7991133865 ps |
| CPU time | 29.88 seconds |
| Started | Oct 02 07:36:41 PM UTC 24 |
| Finished | Oct 02 07:37:12 PM UTC 24 |
| Peak memory | 225948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3245118587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all _with_rand_reset.3245118587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/78.uart_fifo_reset.1474450919 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 32644201207 ps |
| CPU time | 33.99 seconds |
| Started | Oct 02 07:36:43 PM UTC 24 |
| Finished | Oct 02 07:37:18 PM UTC 24 |
| Peak memory | 204120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474450919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1474450919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/78.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.2001633524 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 2936889320 ps |
| CPU time | 42.15 seconds |
| Started | Oct 02 07:36:44 PM UTC 24 |
| Finished | Oct 02 07:37:28 PM UTC 24 |
| Peak memory | 218632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2001633524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all _with_rand_reset.2001633524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/79.uart_fifo_reset.908353367 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 141779430499 ps |
| CPU time | 283.77 seconds |
| Started | Oct 02 07:36:48 PM UTC 24 |
| Finished | Oct 02 07:41:36 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908353367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.908353367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/79.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.3778076537 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 2113757880 ps |
| CPU time | 45.65 seconds |
| Started | Oct 02 07:36:52 PM UTC 24 |
| Finished | Oct 02 07:37:40 PM UTC 24 |
| Peak memory | 218492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3778076537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all _with_rand_reset.3778076537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_alert_test.3100603359 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 32428282 ps |
| CPU time | 0.83 seconds |
| Started | Oct 02 07:08:59 PM UTC 24 |
| Finished | Oct 02 07:09:00 PM UTC 24 |
| Peak memory | 203256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100603359 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3100603359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_fifo_full.19869805 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 88354055981 ps |
| CPU time | 67.11 seconds |
| Started | Oct 02 07:08:31 PM UTC 24 |
| Finished | Oct 02 07:09:40 PM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19869805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.19869805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.1361571106 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 25732630940 ps |
| CPU time | 40.41 seconds |
| Started | Oct 02 07:08:32 PM UTC 24 |
| Finished | Oct 02 07:09:14 PM UTC 24 |
| Peak memory | 204116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361571106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1361571106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_fifo_reset.44330927 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 101080534680 ps |
| CPU time | 45.71 seconds |
| Started | Oct 02 07:08:33 PM UTC 24 |
| Finished | Oct 02 07:09:21 PM UTC 24 |
| Peak memory | 203776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44330927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.44330927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_intr.119731293 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 9202576534 ps |
| CPU time | 20.44 seconds |
| Started | Oct 02 07:08:37 PM UTC 24 |
| Finished | Oct 02 07:08:58 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119731293 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.119731293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.2878896951 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 65091118238 ps |
| CPU time | 186.95 seconds |
| Started | Oct 02 07:08:54 PM UTC 24 |
| Finished | Oct 02 07:12:05 PM UTC 24 |
| Peak memory | 203784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878896951 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2878896951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_loopback.1022340400 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 6974220085 ps |
| CPU time | 7.26 seconds |
| Started | Oct 02 07:08:52 PM UTC 24 |
| Finished | Oct 02 07:09:00 PM UTC 24 |
| Peak memory | 203972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022340400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1022340400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_perf.3172548209 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 15400172129 ps |
| CPU time | 354.65 seconds |
| Started | Oct 02 07:08:53 PM UTC 24 |
| Finished | Oct 02 07:14:53 PM UTC 24 |
| Peak memory | 203840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172548209 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3172548209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_rx_oversample.821180219 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 4395257665 ps |
| CPU time | 33.75 seconds |
| Started | Oct 02 07:08:33 PM UTC 24 |
| Finished | Oct 02 07:09:09 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821180219 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.821180219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.1770731219 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 70681614597 ps |
| CPU time | 46.85 seconds |
| Started | Oct 02 07:08:46 PM UTC 24 |
| Finished | Oct 02 07:09:34 PM UTC 24 |
| Peak memory | 209092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770731219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1770731219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.351538160 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 3380077655 ps |
| CPU time | 2.12 seconds |
| Started | Oct 02 07:08:42 PM UTC 24 |
| Finished | Oct 02 07:08:45 PM UTC 24 |
| Peak memory | 203832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351538160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.351538160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_smoke.2448556708 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 10584898137 ps |
| CPU time | 56.5 seconds |
| Started | Oct 02 07:08:29 PM UTC 24 |
| Finished | Oct 02 07:09:27 PM UTC 24 |
| Peak memory | 204104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448556708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2448556708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_stress_all.2740712234 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 265635025988 ps |
| CPU time | 873.91 seconds |
| Started | Oct 02 07:08:56 PM UTC 24 |
| Finished | Oct 02 07:23:41 PM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740712234 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2740712234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.1078195679 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13178518021 ps |
| CPU time | 94.43 seconds |
| Started | Oct 02 07:08:55 PM UTC 24 |
| Finished | Oct 02 07:10:32 PM UTC 24 |
| Peak memory | 220648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1078195679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_ with_rand_reset.1078195679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.3036452049 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 441033811 ps |
| CPU time | 2.53 seconds |
| Started | Oct 02 07:08:49 PM UTC 24 |
| Finished | Oct 02 07:08:53 PM UTC 24 |
| Peak memory | 203772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036452049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3036452049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_tx_rx.390439138 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 123298826017 ps |
| CPU time | 83.83 seconds |
| Started | Oct 02 07:08:29 PM UTC 24 |
| Finished | Oct 02 07:09:55 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390439138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.390439138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/8.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/80.uart_fifo_reset.3503988441 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 112042734952 ps |
| CPU time | 128.51 seconds |
| Started | Oct 02 07:36:55 PM UTC 24 |
| Finished | Oct 02 07:39:06 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503988441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3503988441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/80.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.2114626699 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 11427060227 ps |
| CPU time | 76.5 seconds |
| Started | Oct 02 07:36:58 PM UTC 24 |
| Finished | Oct 02 07:38:16 PM UTC 24 |
| Peak memory | 222344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2114626699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all _with_rand_reset.2114626699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/81.uart_fifo_reset.2506203259 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 112801738191 ps |
| CPU time | 71.66 seconds |
| Started | Oct 02 07:37:02 PM UTC 24 |
| Finished | Oct 02 07:38:15 PM UTC 24 |
| Peak memory | 209508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506203259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2506203259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/81.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.839512104 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 256447916 ps |
| CPU time | 3.91 seconds |
| Started | Oct 02 07:37:06 PM UTC 24 |
| Finished | Oct 02 07:37:11 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=839512104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all_ with_rand_reset.839512104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/82.uart_fifo_reset.1350800244 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 239287953066 ps |
| CPU time | 127.94 seconds |
| Started | Oct 02 07:37:08 PM UTC 24 |
| Finished | Oct 02 07:39:18 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350800244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1350800244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/82.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.2476217226 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 7357686510 ps |
| CPU time | 27.88 seconds |
| Started | Oct 02 07:37:11 PM UTC 24 |
| Finished | Oct 02 07:37:40 PM UTC 24 |
| Peak memory | 225024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2476217226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all _with_rand_reset.2476217226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/83.uart_fifo_reset.2438050338 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 95514532063 ps |
| CPU time | 33.87 seconds |
| Started | Oct 02 07:37:12 PM UTC 24 |
| Finished | Oct 02 07:37:47 PM UTC 24 |
| Peak memory | 208936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438050338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2438050338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/83.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.2752959548 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 11852666773 ps |
| CPU time | 76.29 seconds |
| Started | Oct 02 07:37:13 PM UTC 24 |
| Finished | Oct 02 07:38:31 PM UTC 24 |
| Peak memory | 221000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2752959548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all _with_rand_reset.2752959548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/84.uart_fifo_reset.2293773624 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 25259398204 ps |
| CPU time | 35.01 seconds |
| Started | Oct 02 07:37:15 PM UTC 24 |
| Finished | Oct 02 07:37:51 PM UTC 24 |
| Peak memory | 209464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293773624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2293773624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/84.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.1943715742 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 8488452382 ps |
| CPU time | 31.24 seconds |
| Started | Oct 02 07:37:16 PM UTC 24 |
| Finished | Oct 02 07:37:49 PM UTC 24 |
| Peak memory | 218300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1943715742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all _with_rand_reset.1943715742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/85.uart_fifo_reset.2550637880 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 160626259404 ps |
| CPU time | 195.88 seconds |
| Started | Oct 02 07:37:18 PM UTC 24 |
| Finished | Oct 02 07:40:38 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550637880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2550637880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/85.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/86.uart_fifo_reset.2502489190 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 17526008550 ps |
| CPU time | 52.05 seconds |
| Started | Oct 02 07:37:19 PM UTC 24 |
| Finished | Oct 02 07:38:13 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502489190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2502489190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/86.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.2653409287 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 2177650680 ps |
| CPU time | 41.9 seconds |
| Started | Oct 02 07:37:30 PM UTC 24 |
| Finished | Oct 02 07:38:13 PM UTC 24 |
| Peak memory | 209720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2653409287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all _with_rand_reset.2653409287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/87.uart_fifo_reset.945922211 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 80169034411 ps |
| CPU time | 154.95 seconds |
| Started | Oct 02 07:37:31 PM UTC 24 |
| Finished | Oct 02 07:40:08 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945922211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.945922211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/87.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.4167686995 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 24712711399 ps |
| CPU time | 107.78 seconds |
| Started | Oct 02 07:37:35 PM UTC 24 |
| Finished | Oct 02 07:39:25 PM UTC 24 |
| Peak memory | 224192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4167686995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all _with_rand_reset.4167686995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/88.uart_fifo_reset.3934207262 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 85663830363 ps |
| CPU time | 165.14 seconds |
| Started | Oct 02 07:37:38 PM UTC 24 |
| Finished | Oct 02 07:40:26 PM UTC 24 |
| Peak memory | 203912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934207262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3934207262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/88.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.3818857337 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 1956569465 ps |
| CPU time | 46.72 seconds |
| Started | Oct 02 07:37:40 PM UTC 24 |
| Finished | Oct 02 07:38:28 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3818857337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all _with_rand_reset.3818857337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/89.uart_fifo_reset.182601952 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 44716962442 ps |
| CPU time | 91.01 seconds |
| Started | Oct 02 07:37:40 PM UTC 24 |
| Finished | Oct 02 07:39:13 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182601952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.182601952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/89.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.2748639691 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 1321985360 ps |
| CPU time | 19.13 seconds |
| Started | Oct 02 07:37:41 PM UTC 24 |
| Finished | Oct 02 07:38:02 PM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2748639691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all _with_rand_reset.2748639691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_alert_test.839377094 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 141435933 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 07:09:28 PM UTC 24 |
| Finished | Oct 02 07:09:30 PM UTC 24 |
| Peak memory | 203192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839377094 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.839377094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_fifo_full.138938713 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 21682737502 ps |
| CPU time | 32.44 seconds |
| Started | Oct 02 07:09:02 PM UTC 24 |
| Finished | Oct 02 07:09:36 PM UTC 24 |
| Peak memory | 209204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138938713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.138938713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_fifo_reset.164639922 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 77533126557 ps |
| CPU time | 32.8 seconds |
| Started | Oct 02 07:09:04 PM UTC 24 |
| Finished | Oct 02 07:09:38 PM UTC 24 |
| Peak memory | 203708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164639922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.164639922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_intr.3056834803 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 175095485677 ps |
| CPU time | 224.33 seconds |
| Started | Oct 02 07:09:11 PM UTC 24 |
| Finished | Oct 02 07:12:58 PM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056834803 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3056834803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_loopback.4268913974 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2187850906 ps |
| CPU time | 4.16 seconds |
| Started | Oct 02 07:09:20 PM UTC 24 |
| Finished | Oct 02 07:09:26 PM UTC 24 |
| Peak memory | 207876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268913974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4268913974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_noise_filter.3403618217 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 59071645395 ps |
| CPU time | 108.02 seconds |
| Started | Oct 02 07:09:11 PM UTC 24 |
| Finished | Oct 02 07:11:01 PM UTC 24 |
| Peak memory | 209860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403618217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3403618217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_perf.2948655612 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 13908552404 ps |
| CPU time | 778.03 seconds |
| Started | Oct 02 07:09:20 PM UTC 24 |
| Finished | Oct 02 07:22:29 PM UTC 24 |
| Peak memory | 207176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948655612 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2948655612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_rx_oversample.3667802618 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 7570778985 ps |
| CPU time | 38.21 seconds |
| Started | Oct 02 07:09:08 PM UTC 24 |
| Finished | Oct 02 07:09:48 PM UTC 24 |
| Peak memory | 208348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667802618 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3667802618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.1111387175 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2795635259 ps |
| CPU time | 5.88 seconds |
| Started | Oct 02 07:09:12 PM UTC 24 |
| Finished | Oct 02 07:09:19 PM UTC 24 |
| Peak memory | 203508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111387175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1111387175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_smoke.3971996909 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 5362608490 ps |
| CPU time | 20.78 seconds |
| Started | Oct 02 07:09:01 PM UTC 24 |
| Finished | Oct 02 07:09:23 PM UTC 24 |
| Peak memory | 203788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971996909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3971996909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_stress_all.3049807989 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 408836941133 ps |
| CPU time | 2560.24 seconds |
| Started | Oct 02 07:09:26 PM UTC 24 |
| Finished | Oct 02 07:52:36 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049807989 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3049807989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.407026620 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7965195865 ps |
| CPU time | 29.61 seconds |
| Started | Oct 02 07:09:23 PM UTC 24 |
| Finished | Oct 02 07:09:54 PM UTC 24 |
| Peak memory | 218616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=407026620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_w ith_rand_reset.407026620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.1545702160 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 8599382600 ps |
| CPU time | 10.16 seconds |
| Started | Oct 02 07:09:16 PM UTC 24 |
| Finished | Oct 02 07:09:27 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545702160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1545702160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_tx_rx.3441502025 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 150236234332 ps |
| CPU time | 217.9 seconds |
| Started | Oct 02 07:09:02 PM UTC 24 |
| Finished | Oct 02 07:12:43 PM UTC 24 |
| Peak memory | 203848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441502025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3441502025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/9.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/90.uart_fifo_reset.1713178037 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 136206279638 ps |
| CPU time | 23.78 seconds |
| Started | Oct 02 07:37:41 PM UTC 24 |
| Finished | Oct 02 07:38:06 PM UTC 24 |
| Peak memory | 208380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713178037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1713178037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/90.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.2681018806 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 4634487525 ps |
| CPU time | 27.13 seconds |
| Started | Oct 02 07:37:42 PM UTC 24 |
| Finished | Oct 02 07:38:11 PM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2681018806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all _with_rand_reset.2681018806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/91.uart_fifo_reset.2701775819 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 116489033257 ps |
| CPU time | 103.52 seconds |
| Started | Oct 02 07:37:44 PM UTC 24 |
| Finished | Oct 02 07:39:30 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701775819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2701775819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/91.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.539181595 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 1775353627 ps |
| CPU time | 32.86 seconds |
| Started | Oct 02 07:37:47 PM UTC 24 |
| Finished | Oct 02 07:38:22 PM UTC 24 |
| Peak memory | 218836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=539181595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all_ with_rand_reset.539181595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/92.uart_fifo_reset.3747238006 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 170225087767 ps |
| CPU time | 394.84 seconds |
| Started | Oct 02 07:37:48 PM UTC 24 |
| Finished | Oct 02 07:44:28 PM UTC 24 |
| Peak memory | 203716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747238006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3747238006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/92.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.1698101721 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 7108396803 ps |
| CPU time | 33.21 seconds |
| Started | Oct 02 07:37:48 PM UTC 24 |
| Finished | Oct 02 07:38:22 PM UTC 24 |
| Peak memory | 220668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1698101721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all _with_rand_reset.1698101721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/93.uart_fifo_reset.1313874070 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 127448408612 ps |
| CPU time | 279.65 seconds |
| Started | Oct 02 07:37:50 PM UTC 24 |
| Finished | Oct 02 07:42:33 PM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313874070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1313874070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/93.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.3506619472 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 3618124219 ps |
| CPU time | 31.48 seconds |
| Started | Oct 02 07:37:52 PM UTC 24 |
| Finished | Oct 02 07:38:25 PM UTC 24 |
| Peak memory | 218772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3506619472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all _with_rand_reset.3506619472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/94.uart_fifo_reset.2401802794 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 37231978974 ps |
| CPU time | 49.8 seconds |
| Started | Oct 02 07:37:55 PM UTC 24 |
| Finished | Oct 02 07:38:46 PM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401802794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2401802794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/94.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.3795444436 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 1645707790 ps |
| CPU time | 23.11 seconds |
| Started | Oct 02 07:37:56 PM UTC 24 |
| Finished | Oct 02 07:38:20 PM UTC 24 |
| Peak memory | 209396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3795444436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all _with_rand_reset.3795444436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/95.uart_fifo_reset.2461952134 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 142744292404 ps |
| CPU time | 23.26 seconds |
| Started | Oct 02 07:38:00 PM UTC 24 |
| Finished | Oct 02 07:38:25 PM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461952134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2461952134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/95.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.555857583 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 16000122971 ps |
| CPU time | 41.8 seconds |
| Started | Oct 02 07:38:02 PM UTC 24 |
| Finished | Oct 02 07:38:45 PM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=555857583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all_ with_rand_reset.555857583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/96.uart_fifo_reset.2394828872 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 37751232890 ps |
| CPU time | 14.33 seconds |
| Started | Oct 02 07:38:03 PM UTC 24 |
| Finished | Oct 02 07:38:19 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394828872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2394828872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/96.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.3923776397 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 3370765163 ps |
| CPU time | 38.36 seconds |
| Started | Oct 02 07:38:07 PM UTC 24 |
| Finished | Oct 02 07:38:47 PM UTC 24 |
| Peak memory | 218548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3923776397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all _with_rand_reset.3923776397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.2569572670 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 6161548124 ps |
| CPU time | 75.94 seconds |
| Started | Oct 02 07:38:09 PM UTC 24 |
| Finished | Oct 02 07:39:27 PM UTC 24 |
| Peak memory | 222396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2569572670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all _with_rand_reset.2569572670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/98.uart_fifo_reset.1207568652 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 118507435502 ps |
| CPU time | 215.94 seconds |
| Started | Oct 02 07:38:12 PM UTC 24 |
| Finished | Oct 02 07:41:51 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207568652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1207568652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/98.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.3739646219 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 2874193378 ps |
| CPU time | 47.44 seconds |
| Started | Oct 02 07:38:14 PM UTC 24 |
| Finished | Oct 02 07:39:03 PM UTC 24 |
| Peak memory | 218444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3739646219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all _with_rand_reset.3739646219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/99.uart_fifo_reset.579987733 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 65892109272 ps |
| CPU time | 27.17 seconds |
| Started | Oct 02 07:38:15 PM UTC 24 |
| Finished | Oct 02 07:38:43 PM UTC 24 |
| Peak memory | 204116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579987733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.579987733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/99.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.1812564004 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 6421467146 ps |
| CPU time | 49.72 seconds |
| Started | Oct 02 07:38:15 PM UTC 24 |
| Finished | Oct 02 07:39:06 PM UTC 24 |
| Peak memory | 226088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1812564004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all _with_rand_reset.1812564004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest |
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