| T412 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_fifo_reset.878553935 |
|
|
Oct 02 07:20:11 PM UTC 24 |
Oct 02 07:22:51 PM UTC 24 |
39746175353 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_fifo_reset.4112205201 |
|
|
Oct 02 07:21:17 PM UTC 24 |
Oct 02 07:22:53 PM UTC 24 |
102412084987 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.3199413228 |
|
|
Oct 02 07:22:21 PM UTC 24 |
Oct 02 07:22:53 PM UTC 24 |
54813217443 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_loopback.462486233 |
|
|
Oct 02 07:22:32 PM UTC 24 |
Oct 02 07:22:54 PM UTC 24 |
10511712851 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.1636065271 |
|
|
Oct 02 07:21:42 PM UTC 24 |
Oct 02 07:23:00 PM UTC 24 |
41749115745 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_rx_oversample.1596714140 |
|
|
Oct 02 07:22:55 PM UTC 24 |
Oct 02 07:23:05 PM UTC 24 |
1801343179 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_noise_filter.3505386982 |
|
|
Oct 02 07:22:13 PM UTC 24 |
Oct 02 07:23:06 PM UTC 24 |
90595005056 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_tx_rx.4140196911 |
|
|
Oct 02 07:21:03 PM UTC 24 |
Oct 02 07:23:15 PM UTC 24 |
42862552851 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_smoke.661107641 |
|
|
Oct 02 07:22:41 PM UTC 24 |
Oct 02 07:23:16 PM UTC 24 |
5767694521 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_intr.1595854998 |
|
|
Oct 02 07:22:12 PM UTC 24 |
Oct 02 07:23:17 PM UTC 24 |
38278342699 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.934650668 |
|
|
Oct 02 07:23:07 PM UTC 24 |
Oct 02 07:23:17 PM UTC 24 |
2356561849 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_fifo_full.2379990877 |
|
|
Oct 02 07:19:36 PM UTC 24 |
Oct 02 07:23:19 PM UTC 24 |
240655869774 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.2121099861 |
|
|
Oct 02 07:22:18 PM UTC 24 |
Oct 02 07:23:21 PM UTC 24 |
41288659249 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_stress_all.2044371012 |
|
|
Oct 02 07:21:43 PM UTC 24 |
Oct 02 07:23:22 PM UTC 24 |
76717422317 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_loopback.3479550423 |
|
|
Oct 02 07:23:17 PM UTC 24 |
Oct 02 07:23:23 PM UTC 24 |
7655910186 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_intr.3668205997 |
|
|
Oct 02 07:14:34 PM UTC 24 |
Oct 02 07:23:24 PM UTC 24 |
267285892338 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_alert_test.1502344707 |
|
|
Oct 02 07:23:24 PM UTC 24 |
Oct 02 07:23:25 PM UTC 24 |
37521079 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_intr.2476177768 |
|
|
Oct 02 07:23:01 PM UTC 24 |
Oct 02 07:23:30 PM UTC 24 |
46103693289 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.192756323 |
|
|
Oct 02 07:22:34 PM UTC 24 |
Oct 02 07:23:31 PM UTC 24 |
18696051132 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.3810365716 |
|
|
Oct 02 07:12:54 PM UTC 24 |
Oct 02 07:23:33 PM UTC 24 |
96469820121 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_smoke.3929860361 |
|
|
Oct 02 07:23:25 PM UTC 24 |
Oct 02 07:23:33 PM UTC 24 |
890420538 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.2887760618 |
|
|
Oct 02 07:23:16 PM UTC 24 |
Oct 02 07:23:35 PM UTC 24 |
7920953815 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.4247176566 |
|
|
Oct 02 07:10:59 PM UTC 24 |
Oct 02 07:23:37 PM UTC 24 |
96048114570 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/8.uart_stress_all.2740712234 |
|
|
Oct 02 07:08:56 PM UTC 24 |
Oct 02 07:23:41 PM UTC 24 |
265635025988 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/16.uart_perf.3380604740 |
|
|
Oct 02 07:12:29 PM UTC 24 |
Oct 02 07:23:55 PM UTC 24 |
12662124448 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_fifo_reset.2663401264 |
|
|
Oct 02 07:23:33 PM UTC 24 |
Oct 02 07:23:59 PM UTC 24 |
12193068545 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.1668330937 |
|
|
Oct 02 07:23:23 PM UTC 24 |
Oct 02 07:23:59 PM UTC 24 |
7479208055 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.4276175541 |
|
|
Oct 02 07:23:41 PM UTC 24 |
Oct 02 07:24:01 PM UTC 24 |
4051890447 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_rx_oversample.1444177887 |
|
|
Oct 02 07:23:34 PM UTC 24 |
Oct 02 07:24:02 PM UTC 24 |
4226326946 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_fifo_reset.3591876922 |
|
|
Oct 02 07:22:55 PM UTC 24 |
Oct 02 07:24:03 PM UTC 24 |
17955841408 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_fifo_full.1840342332 |
|
|
Oct 02 07:22:52 PM UTC 24 |
Oct 02 07:24:03 PM UTC 24 |
79315691971 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_intr.1101219605 |
|
|
Oct 02 07:23:35 PM UTC 24 |
Oct 02 07:24:04 PM UTC 24 |
21913986879 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_fifo_full.1178521377 |
|
|
Oct 02 07:23:31 PM UTC 24 |
Oct 02 07:24:05 PM UTC 24 |
102643389448 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.2819209414 |
|
|
Oct 02 07:24:00 PM UTC 24 |
Oct 02 07:24:05 PM UTC 24 |
1432354179 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_alert_test.965168512 |
|
|
Oct 02 07:24:04 PM UTC 24 |
Oct 02 07:24:06 PM UTC 24 |
22822563 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_loopback.3300884437 |
|
|
Oct 02 07:24:00 PM UTC 24 |
Oct 02 07:24:08 PM UTC 24 |
1455031326 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_smoke.2212852392 |
|
|
Oct 02 07:24:05 PM UTC 24 |
Oct 02 07:24:09 PM UTC 24 |
614521018 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_stress_all.542056553 |
|
|
Oct 02 07:19:59 PM UTC 24 |
Oct 02 07:24:11 PM UTC 24 |
802337784633 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.3227752898 |
|
|
Oct 02 07:21:22 PM UTC 24 |
Oct 02 07:24:12 PM UTC 24 |
203429504944 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_tx_rx.4256151119 |
|
|
Oct 02 07:22:48 PM UTC 24 |
Oct 02 07:24:13 PM UTC 24 |
53414830180 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_rx_oversample.342507731 |
|
|
Oct 02 07:24:12 PM UTC 24 |
Oct 02 07:24:17 PM UTC 24 |
2135198642 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_fifo_full.193481108 |
|
|
Oct 02 07:21:50 PM UTC 24 |
Oct 02 07:24:25 PM UTC 24 |
108365854648 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.2050708516 |
|
|
Oct 02 07:24:09 PM UTC 24 |
Oct 02 07:24:26 PM UTC 24 |
15654975099 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.3447652010 |
|
|
Oct 02 07:23:31 PM UTC 24 |
Oct 02 07:24:27 PM UTC 24 |
44798347987 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_intr.3043434099 |
|
|
Oct 02 07:20:21 PM UTC 24 |
Oct 02 07:24:29 PM UTC 24 |
225018283592 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_loopback.3807913936 |
|
|
Oct 02 07:24:27 PM UTC 24 |
Oct 02 07:24:30 PM UTC 24 |
1487997424 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.3547226414 |
|
|
Oct 02 07:24:25 PM UTC 24 |
Oct 02 07:24:38 PM UTC 24 |
7220066529 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_tx_rx.1674086886 |
|
|
Oct 02 07:23:26 PM UTC 24 |
Oct 02 07:24:38 PM UTC 24 |
80646038767 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_alert_test.1193357013 |
|
|
Oct 02 07:24:39 PM UTC 24 |
Oct 02 07:24:41 PM UTC 24 |
14324146 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_tx_rx.1061780246 |
|
|
Oct 02 07:24:06 PM UTC 24 |
Oct 02 07:24:42 PM UTC 24 |
21349504548 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_fifo_full.3501916946 |
|
|
Oct 02 07:20:02 PM UTC 24 |
Oct 02 07:24:42 PM UTC 24 |
158234978047 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.1433061807 |
|
|
Oct 02 07:23:57 PM UTC 24 |
Oct 02 07:24:43 PM UTC 24 |
38826078304 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.1543868317 |
|
|
Oct 02 07:24:16 PM UTC 24 |
Oct 02 07:24:48 PM UTC 24 |
32088381715 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_noise_filter.325933018 |
|
|
Oct 02 07:23:38 PM UTC 24 |
Oct 02 07:24:48 PM UTC 24 |
49423002469 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.1463338204 |
|
|
Oct 02 07:23:15 PM UTC 24 |
Oct 02 07:24:49 PM UTC 24 |
57822620209 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_intr.3645085236 |
|
|
Oct 02 07:24:49 PM UTC 24 |
Oct 02 07:24:52 PM UTC 24 |
6839063035 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.4288473751 |
|
|
Oct 02 07:24:31 PM UTC 24 |
Oct 02 07:24:58 PM UTC 24 |
2079100029 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_smoke.1226315893 |
|
|
Oct 02 07:24:42 PM UTC 24 |
Oct 02 07:24:59 PM UTC 24 |
5678732743 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.1103140170 |
|
|
Oct 02 07:13:54 PM UTC 24 |
Oct 02 07:25:00 PM UTC 24 |
67178748765 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.3999115629 |
|
|
Oct 02 07:24:59 PM UTC 24 |
Oct 02 07:25:03 PM UTC 24 |
2304016951 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.2609985835 |
|
|
Oct 02 07:25:01 PM UTC 24 |
Oct 02 07:25:04 PM UTC 24 |
1008609011 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.607247660 |
|
|
Oct 02 07:20:44 PM UTC 24 |
Oct 02 07:25:06 PM UTC 24 |
94358840679 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_noise_filter.1872815358 |
|
|
Oct 02 07:23:06 PM UTC 24 |
Oct 02 07:25:12 PM UTC 24 |
50093980874 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_loopback.2626760039 |
|
|
Oct 02 07:25:04 PM UTC 24 |
Oct 02 07:25:16 PM UTC 24 |
5566784327 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.1955264946 |
|
|
Oct 02 07:14:48 PM UTC 24 |
Oct 02 07:25:18 PM UTC 24 |
128179451455 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_rx_oversample.3794529285 |
|
|
Oct 02 07:24:49 PM UTC 24 |
Oct 02 07:25:19 PM UTC 24 |
7185812837 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_alert_test.2374049060 |
|
|
Oct 02 07:25:19 PM UTC 24 |
Oct 02 07:25:21 PM UTC 24 |
13972240 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_smoke.4202592405 |
|
|
Oct 02 07:25:19 PM UTC 24 |
Oct 02 07:25:25 PM UTC 24 |
737136322 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.2314888278 |
|
|
Oct 02 07:24:04 PM UTC 24 |
Oct 02 07:25:26 PM UTC 24 |
15993159966 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.1080346417 |
|
|
Oct 02 07:25:13 PM UTC 24 |
Oct 02 07:25:26 PM UTC 24 |
2992811620 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_tx_rx.1356291002 |
|
|
Oct 02 07:21:49 PM UTC 24 |
Oct 02 07:25:30 PM UTC 24 |
106690071355 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_fifo_reset.373330745 |
|
|
Oct 02 07:24:48 PM UTC 24 |
Oct 02 07:25:30 PM UTC 24 |
24617433947 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_perf.2816373834 |
|
|
Oct 02 07:19:14 PM UTC 24 |
Oct 02 07:25:32 PM UTC 24 |
15434058087 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_noise_filter.366451545 |
|
|
Oct 02 07:24:14 PM UTC 24 |
Oct 02 07:25:34 PM UTC 24 |
81926361206 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.885103287 |
|
|
Oct 02 07:25:34 PM UTC 24 |
Oct 02 07:25:38 PM UTC 24 |
4095592365 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_rx_oversample.3499698724 |
|
|
Oct 02 07:25:31 PM UTC 24 |
Oct 02 07:25:40 PM UTC 24 |
3281901027 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.4243053666 |
|
|
Oct 02 07:25:41 PM UTC 24 |
Oct 02 07:25:45 PM UTC 24 |
1011474546 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.2639125186 |
|
|
Oct 02 07:08:19 PM UTC 24 |
Oct 02 07:25:46 PM UTC 24 |
138711869815 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_tx_rx.3937359151 |
|
|
Oct 02 07:25:22 PM UTC 24 |
Oct 02 07:25:48 PM UTC 24 |
22943791213 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_intr.2000700751 |
|
|
Oct 02 07:24:13 PM UTC 24 |
Oct 02 07:25:49 PM UTC 24 |
27555695964 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_tx_rx.1144156368 |
|
|
Oct 02 07:24:43 PM UTC 24 |
Oct 02 07:25:52 PM UTC 24 |
38361570224 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_fifo_reset.429935892 |
|
|
Oct 02 07:24:10 PM UTC 24 |
Oct 02 07:26:04 PM UTC 24 |
57585207002 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_alert_test.2710856809 |
|
|
Oct 02 07:26:05 PM UTC 24 |
Oct 02 07:26:07 PM UTC 24 |
14659890 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_noise_filter.2105002058 |
|
|
Oct 02 07:24:52 PM UTC 24 |
Oct 02 07:26:08 PM UTC 24 |
61739323174 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_fifo_reset.1892751298 |
|
|
Oct 02 07:25:28 PM UTC 24 |
Oct 02 07:26:08 PM UTC 24 |
21433138414 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_perf.2868777952 |
|
|
Oct 02 07:21:36 PM UTC 24 |
Oct 02 07:26:13 PM UTC 24 |
16228040334 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_perf.3250311567 |
|
|
Oct 02 07:24:27 PM UTC 24 |
Oct 02 07:26:16 PM UTC 24 |
9146348992 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.1215828963 |
|
|
Oct 02 07:24:17 PM UTC 24 |
Oct 02 07:26:18 PM UTC 24 |
122234097588 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_loopback.583950577 |
|
|
Oct 02 07:25:46 PM UTC 24 |
Oct 02 07:26:21 PM UTC 24 |
8140446016 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_smoke.2424296987 |
|
|
Oct 02 07:26:08 PM UTC 24 |
Oct 02 07:26:28 PM UTC 24 |
5958182669 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_fifo_full.2151028925 |
|
|
Oct 02 07:25:27 PM UTC 24 |
Oct 02 07:26:35 PM UTC 24 |
62745823621 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_rx_oversample.1220406392 |
|
|
Oct 02 07:26:19 PM UTC 24 |
Oct 02 07:26:36 PM UTC 24 |
2740326977 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_noise_filter.779776274 |
|
|
Oct 02 07:25:32 PM UTC 24 |
Oct 02 07:26:36 PM UTC 24 |
51687638184 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_fifo_full.2428271141 |
|
|
Oct 02 07:24:06 PM UTC 24 |
Oct 02 07:26:37 PM UTC 24 |
68065301391 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.2373374173 |
|
|
Oct 02 07:26:36 PM UTC 24 |
Oct 02 07:26:39 PM UTC 24 |
5793415617 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_stress_all.1004522864 |
|
|
Oct 02 07:19:29 PM UTC 24 |
Oct 02 07:26:41 PM UTC 24 |
303241167183 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_intr.659701716 |
|
|
Oct 02 07:25:31 PM UTC 24 |
Oct 02 07:26:42 PM UTC 24 |
28507950785 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.3553184405 |
|
|
Oct 02 07:26:13 PM UTC 24 |
Oct 02 07:26:43 PM UTC 24 |
35773065437 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_loopback.185598537 |
|
|
Oct 02 07:26:38 PM UTC 24 |
Oct 02 07:26:44 PM UTC 24 |
2860023371 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_alert_test.3916700607 |
|
|
Oct 02 07:26:45 PM UTC 24 |
Oct 02 07:26:47 PM UTC 24 |
18565424 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.2959609341 |
|
|
Oct 02 07:26:37 PM UTC 24 |
Oct 02 07:26:49 PM UTC 24 |
41431800463 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_fifo_full.2579309909 |
|
|
Oct 02 07:26:09 PM UTC 24 |
Oct 02 07:26:49 PM UTC 24 |
42137894376 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.2403670451 |
|
|
Oct 02 07:26:37 PM UTC 24 |
Oct 02 07:26:50 PM UTC 24 |
7498460493 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_smoke.2191801509 |
|
|
Oct 02 07:26:48 PM UTC 24 |
Oct 02 07:26:51 PM UTC 24 |
256251106 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.4270761135 |
|
|
Oct 02 07:24:44 PM UTC 24 |
Oct 02 07:26:52 PM UTC 24 |
54415110932 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_stress_all.910511181 |
|
|
Oct 02 07:20:54 PM UTC 24 |
Oct 02 07:26:53 PM UTC 24 |
322622319881 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.2049757512 |
|
|
Oct 02 07:25:27 PM UTC 24 |
Oct 02 07:27:00 PM UTC 24 |
206274708504 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_fifo_reset.8247226 |
|
|
Oct 02 07:21:55 PM UTC 24 |
Oct 02 07:27:04 PM UTC 24 |
105530817604 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.3844638524 |
|
|
Oct 02 07:17:08 PM UTC 24 |
Oct 02 07:27:05 PM UTC 24 |
54460478099 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_fifo_full.1080462975 |
|
|
Oct 02 07:24:43 PM UTC 24 |
Oct 02 07:27:08 PM UTC 24 |
145328033689 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_tx_rx.4226505782 |
|
|
Oct 02 07:26:09 PM UTC 24 |
Oct 02 07:27:10 PM UTC 24 |
106518135760 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1266082933 |
|
|
Oct 02 07:27:09 PM UTC 24 |
Oct 02 07:27:14 PM UTC 24 |
770570102 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_tx_rx.2884491177 |
|
|
Oct 02 07:26:50 PM UTC 24 |
Oct 02 07:27:14 PM UTC 24 |
24663399766 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_loopback.2292286019 |
|
|
Oct 02 07:27:10 PM UTC 24 |
Oct 02 07:27:15 PM UTC 24 |
2531400347 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.2519244190 |
|
|
Oct 02 07:26:42 PM UTC 24 |
Oct 02 07:27:16 PM UTC 24 |
1373263239 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.247173017 |
|
|
Oct 02 07:27:05 PM UTC 24 |
Oct 02 07:27:17 PM UTC 24 |
2955633095 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_alert_test.2436028377 |
|
|
Oct 02 07:27:19 PM UTC 24 |
Oct 02 07:27:21 PM UTC 24 |
35418263 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.1877869979 |
|
|
Oct 02 07:25:51 PM UTC 24 |
Oct 02 07:27:22 PM UTC 24 |
11847750125 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.2752939145 |
|
|
Oct 02 07:26:51 PM UTC 24 |
Oct 02 07:27:25 PM UTC 24 |
8814492683 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_smoke.2486929965 |
|
|
Oct 02 07:27:22 PM UTC 24 |
Oct 02 07:27:26 PM UTC 24 |
458332540 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.2615538330 |
|
|
Oct 02 07:22:53 PM UTC 24 |
Oct 02 07:27:29 PM UTC 24 |
143972413160 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.730821191 |
|
|
Oct 02 07:09:43 PM UTC 24 |
Oct 02 07:27:30 PM UTC 24 |
120055124159 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_stress_all.1401718476 |
|
|
Oct 02 07:23:24 PM UTC 24 |
Oct 02 07:27:31 PM UTC 24 |
241547629005 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/32.uart_perf.511196201 |
|
|
Oct 02 07:22:32 PM UTC 24 |
Oct 02 07:27:31 PM UTC 24 |
17913151934 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_noise_filter.3927885270 |
|
|
Oct 02 07:26:29 PM UTC 24 |
Oct 02 07:27:33 PM UTC 24 |
241332317299 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_rx_oversample.1641326711 |
|
|
Oct 02 07:27:31 PM UTC 24 |
Oct 02 07:27:40 PM UTC 24 |
2647552123 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_tx_rx.2137236541 |
|
|
Oct 02 07:27:23 PM UTC 24 |
Oct 02 07:27:43 PM UTC 24 |
10990288261 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_stress_all.1459901914 |
|
|
Oct 02 07:15:12 PM UTC 24 |
Oct 02 07:27:46 PM UTC 24 |
313196818271 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_fifo_reset.1035741244 |
|
|
Oct 02 07:26:16 PM UTC 24 |
Oct 02 07:27:49 PM UTC 24 |
64822875231 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_loopback.135258130 |
|
|
Oct 02 07:27:47 PM UTC 24 |
Oct 02 07:27:50 PM UTC 24 |
180753876 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/13.uart_perf.708295332 |
|
|
Oct 02 07:10:59 PM UTC 24 |
Oct 02 07:27:52 PM UTC 24 |
18359620083 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.3925293596 |
|
|
Oct 02 07:27:41 PM UTC 24 |
Oct 02 07:27:54 PM UTC 24 |
6992368982 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.3345759689 |
|
|
Oct 02 07:27:27 PM UTC 24 |
Oct 02 07:28:00 PM UTC 24 |
52230757477 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.4166029291 |
|
|
Oct 02 07:27:05 PM UTC 24 |
Oct 02 07:28:03 PM UTC 24 |
151021522983 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_alert_test.2985191782 |
|
|
Oct 02 07:28:01 PM UTC 24 |
Oct 02 07:28:03 PM UTC 24 |
19385184 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_intr.61382082 |
|
|
Oct 02 07:27:31 PM UTC 24 |
Oct 02 07:28:04 PM UTC 24 |
13357244628 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_noise_filter.3689637019 |
|
|
Oct 02 07:27:01 PM UTC 24 |
Oct 02 07:28:05 PM UTC 24 |
34904989936 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.4177864949 |
|
|
Oct 02 07:27:44 PM UTC 24 |
Oct 02 07:28:06 PM UTC 24 |
7252899605 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.179820722 |
|
|
Oct 02 07:25:00 PM UTC 24 |
Oct 02 07:28:08 PM UTC 24 |
223440415442 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_stress_all.4160760019 |
|
|
Oct 02 07:26:44 PM UTC 24 |
Oct 02 07:28:14 PM UTC 24 |
34536460579 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_perf.189389548 |
|
|
Oct 02 07:24:02 PM UTC 24 |
Oct 02 07:28:19 PM UTC 24 |
18952199896 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_intr.3802195647 |
|
|
Oct 02 07:26:54 PM UTC 24 |
Oct 02 07:30:56 PM UTC 24 |
86952883052 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_rx_oversample.4100695099 |
|
|
Oct 02 07:28:09 PM UTC 24 |
Oct 02 07:28:20 PM UTC 24 |
2604961187 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.2370905268 |
|
|
Oct 02 07:23:19 PM UTC 24 |
Oct 02 07:28:24 PM UTC 24 |
139224668806 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.3227417540 |
|
|
Oct 02 07:28:20 PM UTC 24 |
Oct 02 07:28:25 PM UTC 24 |
2857830757 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.1802771219 |
|
|
Oct 02 07:27:16 PM UTC 24 |
Oct 02 07:28:25 PM UTC 24 |
4252148871 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_tx_rx.2195634097 |
|
|
Oct 02 07:28:05 PM UTC 24 |
Oct 02 07:28:26 PM UTC 24 |
72242682376 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_fifo_reset.3264019644 |
|
|
Oct 02 07:28:07 PM UTC 24 |
Oct 02 07:28:29 PM UTC 24 |
56319703431 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.265544765 |
|
|
Oct 02 07:28:24 PM UTC 24 |
Oct 02 07:28:30 PM UTC 24 |
3462959711 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.1676630031 |
|
|
Oct 02 07:15:11 PM UTC 24 |
Oct 02 07:28:30 PM UTC 24 |
149416695221 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_fifo_reset.1839887713 |
|
|
Oct 02 07:27:30 PM UTC 24 |
Oct 02 07:28:30 PM UTC 24 |
20984973660 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_rx_oversample.845105961 |
|
|
Oct 02 07:26:53 PM UTC 24 |
Oct 02 07:28:30 PM UTC 24 |
7320773968 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_perf.211457849 |
|
|
Oct 02 07:25:05 PM UTC 24 |
Oct 02 07:28:30 PM UTC 24 |
13686049005 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.222495849 |
|
|
Oct 02 07:24:31 PM UTC 24 |
Oct 02 07:28:32 PM UTC 24 |
49522998805 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_alert_test.1990118250 |
|
|
Oct 02 07:28:31 PM UTC 24 |
Oct 02 07:28:32 PM UTC 24 |
54917518 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_smoke.1175656861 |
|
|
Oct 02 07:28:31 PM UTC 24 |
Oct 02 07:28:33 PM UTC 24 |
545673471 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_smoke.3690141772 |
|
|
Oct 02 07:28:03 PM UTC 24 |
Oct 02 07:28:33 PM UTC 24 |
6242976810 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.4227800032 |
|
|
Oct 02 07:28:06 PM UTC 24 |
Oct 02 07:28:35 PM UTC 24 |
47580482348 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_intr.3004703523 |
|
|
Oct 02 07:26:22 PM UTC 24 |
Oct 02 07:28:35 PM UTC 24 |
69549962853 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.2762772181 |
|
|
Oct 02 07:25:39 PM UTC 24 |
Oct 02 07:28:37 PM UTC 24 |
75474300369 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_loopback.685529931 |
|
|
Oct 02 07:28:25 PM UTC 24 |
Oct 02 07:28:38 PM UTC 24 |
2631274732 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.1612734308 |
|
|
Oct 02 07:28:31 PM UTC 24 |
Oct 02 07:28:40 PM UTC 24 |
3760934304 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_stress_all.2906380980 |
|
|
Oct 02 07:25:16 PM UTC 24 |
Oct 02 07:28:42 PM UTC 24 |
82922024729 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.3658367589 |
|
|
Oct 02 07:28:39 PM UTC 24 |
Oct 02 07:28:43 PM UTC 24 |
500986376 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.3852454630 |
|
|
Oct 02 07:27:34 PM UTC 24 |
Oct 02 07:28:45 PM UTC 24 |
24777434262 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_loopback.3931800251 |
|
|
Oct 02 07:28:41 PM UTC 24 |
Oct 02 07:28:47 PM UTC 24 |
1218205491 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_rx_oversample.549959240 |
|
|
Oct 02 07:28:34 PM UTC 24 |
Oct 02 07:28:48 PM UTC 24 |
3504605721 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_fifo_full.3754488545 |
|
|
Oct 02 07:26:51 PM UTC 24 |
Oct 02 07:28:49 PM UTC 24 |
88546510140 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_perf.1774263381 |
|
|
Oct 02 07:19:55 PM UTC 24 |
Oct 02 07:28:49 PM UTC 24 |
14493349471 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_stress_all.4032485022 |
|
|
Oct 02 07:24:04 PM UTC 24 |
Oct 02 07:28:50 PM UTC 24 |
241537664803 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_alert_test.1969533912 |
|
|
Oct 02 07:28:49 PM UTC 24 |
Oct 02 07:28:51 PM UTC 24 |
13474698 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.2993109710 |
|
|
Oct 02 07:28:36 PM UTC 24 |
Oct 02 07:28:55 PM UTC 24 |
6916590609 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_noise_filter.3823453329 |
|
|
Oct 02 07:27:31 PM UTC 24 |
Oct 02 07:28:58 PM UTC 24 |
42742136813 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.3732102331 |
|
|
Oct 02 07:27:53 PM UTC 24 |
Oct 02 07:28:59 PM UTC 24 |
4609094889 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_smoke.593024494 |
|
|
Oct 02 07:28:50 PM UTC 24 |
Oct 02 07:29:03 PM UTC 24 |
5491704341 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.2791546530 |
|
|
Oct 02 07:28:38 PM UTC 24 |
Oct 02 07:29:08 PM UTC 24 |
47924501036 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.37108028 |
|
|
Oct 02 07:24:03 PM UTC 24 |
Oct 02 07:29:08 PM UTC 24 |
73446199436 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_rx_oversample.3683854164 |
|
|
Oct 02 07:28:59 PM UTC 24 |
Oct 02 07:29:09 PM UTC 24 |
2007601747 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.1550682723 |
|
|
Oct 02 07:29:10 PM UTC 24 |
Oct 02 07:29:14 PM UTC 24 |
1022904526 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_loopback.2153395424 |
|
|
Oct 02 07:29:14 PM UTC 24 |
Oct 02 07:29:17 PM UTC 24 |
514011104 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_fifo_reset.1396830556 |
|
|
Oct 02 07:28:33 PM UTC 24 |
Oct 02 07:29:33 PM UTC 24 |
31843714384 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.1905364421 |
|
|
Oct 02 07:20:48 PM UTC 24 |
Oct 02 07:29:39 PM UTC 24 |
161617508810 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.1102511823 |
|
|
Oct 02 07:25:50 PM UTC 24 |
Oct 02 07:29:40 PM UTC 24 |
100015931672 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_tx_rx.252424762 |
|
|
Oct 02 07:28:50 PM UTC 24 |
Oct 02 07:29:41 PM UTC 24 |
18278300400 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_noise_filter.2296116151 |
|
|
Oct 02 07:28:35 PM UTC 24 |
Oct 02 07:29:41 PM UTC 24 |
29225279079 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_alert_test.250355012 |
|
|
Oct 02 07:29:42 PM UTC 24 |
Oct 02 07:29:44 PM UTC 24 |
12911521 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/31.uart_fifo_full.1915362787 |
|
|
Oct 02 07:21:07 PM UTC 24 |
Oct 02 07:29:45 PM UTC 24 |
75796631187 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.2174432220 |
|
|
Oct 02 07:28:46 PM UTC 24 |
Oct 02 07:29:45 PM UTC 24 |
48934143597 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_smoke.1010595369 |
|
|
Oct 02 07:29:43 PM UTC 24 |
Oct 02 07:29:46 PM UTC 24 |
592842850 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_fifo_reset.3165229931 |
|
|
Oct 02 07:28:56 PM UTC 24 |
Oct 02 07:29:48 PM UTC 24 |
74361083477 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_rx_oversample.1212722619 |
|
|
Oct 02 07:29:49 PM UTC 24 |
Oct 02 07:29:54 PM UTC 24 |
4416777292 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_intr.1631511760 |
|
|
Oct 02 07:28:34 PM UTC 24 |
Oct 02 07:30:01 PM UTC 24 |
103421431540 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_intr.2720194108 |
|
|
Oct 02 07:29:54 PM UTC 24 |
Oct 02 07:30:02 PM UTC 24 |
28125384134 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.347569169 |
|
|
Oct 02 07:19:55 PM UTC 24 |
Oct 02 07:30:04 PM UTC 24 |
77852047686 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.3161632466 |
|
|
Oct 02 07:30:04 PM UTC 24 |
Oct 02 07:30:09 PM UTC 24 |
4269036911 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.2201975852 |
|
|
Oct 02 07:30:05 PM UTC 24 |
Oct 02 07:30:14 PM UTC 24 |
9191470956 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_loopback.3435659215 |
|
|
Oct 02 07:30:15 PM UTC 24 |
Oct 02 07:30:19 PM UTC 24 |
3733075469 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.515060094 |
|
|
Oct 02 07:29:41 PM UTC 24 |
Oct 02 07:30:21 PM UTC 24 |
1688497039 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_fifo_full.2525816493 |
|
|
Oct 02 07:27:26 PM UTC 24 |
Oct 02 07:30:24 PM UTC 24 |
92909734324 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_fifo_full.2808632827 |
|
|
Oct 02 07:28:32 PM UTC 24 |
Oct 02 07:30:25 PM UTC 24 |
142028867177 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_fifo_reset.4269661301 |
|
|
Oct 02 07:29:47 PM UTC 24 |
Oct 02 07:30:34 PM UTC 24 |
368713356216 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_alert_test.752680480 |
|
|
Oct 02 07:30:34 PM UTC 24 |
Oct 02 07:30:37 PM UTC 24 |
15871649 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.949269931 |
|
|
Oct 02 07:30:10 PM UTC 24 |
Oct 02 07:30:37 PM UTC 24 |
6655271624 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_perf.3033338597 |
|
|
Oct 02 07:27:15 PM UTC 24 |
Oct 02 07:30:39 PM UTC 24 |
10895896592 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_fifo_full.1573628317 |
|
|
Oct 02 07:29:46 PM UTC 24 |
Oct 02 07:30:43 PM UTC 24 |
371778935326 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.1508596218 |
|
|
Oct 02 07:27:16 PM UTC 24 |
Oct 02 07:30:43 PM UTC 24 |
58152690746 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.3165952768 |
|
|
Oct 02 07:20:06 PM UTC 24 |
Oct 02 07:30:50 PM UTC 24 |
203114717548 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.3893977402 |
|
|
Oct 02 07:29:09 PM UTC 24 |
Oct 02 07:30:51 PM UTC 24 |
43264275183 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.1672525872 |
|
|
Oct 02 07:28:53 PM UTC 24 |
Oct 02 07:30:54 PM UTC 24 |
61500161519 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.2187865213 |
|
|
Oct 02 07:30:56 PM UTC 24 |
Oct 02 07:31:00 PM UTC 24 |
3224926078 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_rx_oversample.1585043550 |
|
|
Oct 02 07:30:51 PM UTC 24 |
Oct 02 07:31:03 PM UTC 24 |
3712064340 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_smoke.804158605 |
|
|
Oct 02 07:30:38 PM UTC 24 |
Oct 02 07:31:05 PM UTC 24 |
5327267876 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_loopback.3084990545 |
|
|
Oct 02 07:31:07 PM UTC 24 |
Oct 02 07:31:11 PM UTC 24 |
1168544955 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.944424050 |
|
|
Oct 02 07:30:24 PM UTC 24 |
Oct 02 07:31:20 PM UTC 24 |
11977028301 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_perf.268069683 |
|
|
Oct 02 07:26:40 PM UTC 24 |
Oct 02 07:31:21 PM UTC 24 |
24189854887 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/37.uart_stress_all.2523307790 |
|
|
Oct 02 07:25:53 PM UTC 24 |
Oct 02 07:31:22 PM UTC 24 |
376269755460 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_noise_filter.2431728806 |
|
|
Oct 02 07:29:04 PM UTC 24 |
Oct 02 07:31:23 PM UTC 24 |
81836211991 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_alert_test.446066456 |
|
|
Oct 02 07:31:24 PM UTC 24 |
Oct 02 07:31:26 PM UTC 24 |
85562282 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_smoke.1365121637 |
|
|
Oct 02 07:31:27 PM UTC 24 |
Oct 02 07:31:29 PM UTC 24 |
110560186 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_fifo_reset.1364886934 |
|
|
Oct 02 07:30:44 PM UTC 24 |
Oct 02 07:31:30 PM UTC 24 |
34821074523 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.2943939702 |
|
|
Oct 02 07:31:03 PM UTC 24 |
Oct 02 07:31:34 PM UTC 24 |
6076076602 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.3797959251 |
|
|
Oct 02 07:30:44 PM UTC 24 |
Oct 02 07:31:36 PM UTC 24 |
27732186067 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_fifo_full.2058289201 |
|
|
Oct 02 07:30:40 PM UTC 24 |
Oct 02 07:31:37 PM UTC 24 |
31334653295 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.2019790988 |
|
|
Oct 02 07:26:41 PM UTC 24 |
Oct 02 07:31:42 PM UTC 24 |
62171334492 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_noise_filter.2719625925 |
|
|
Oct 02 07:30:03 PM UTC 24 |
Oct 02 07:31:44 PM UTC 24 |
39574609296 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/42.uart_tx_rx.4225321460 |
|
|
Oct 02 07:28:32 PM UTC 24 |
Oct 02 07:31:44 PM UTC 24 |
82305258494 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.2987710118 |
|
|
Oct 02 07:31:22 PM UTC 24 |
Oct 02 07:31:49 PM UTC 24 |
4577527228 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.2328844266 |
|
|
Oct 02 07:31:45 PM UTC 24 |
Oct 02 07:31:50 PM UTC 24 |
3797408663 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_noise_filter.3508601050 |
|
|
Oct 02 07:30:55 PM UTC 24 |
Oct 02 07:31:52 PM UTC 24 |
22489471507 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_tx_rx.1087705117 |
|
|
Oct 02 07:31:30 PM UTC 24 |
Oct 02 07:31:53 PM UTC 24 |
21262108450 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.3736943972 |
|
|
Oct 02 07:31:51 PM UTC 24 |
Oct 02 07:31:56 PM UTC 24 |
2106580825 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_loopback.363004845 |
|
|
Oct 02 07:31:53 PM UTC 24 |
Oct 02 07:31:56 PM UTC 24 |
1037997223 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_fifo_full.2116220591 |
|
|
Oct 02 07:31:30 PM UTC 24 |
Oct 02 07:32:00 PM UTC 24 |
18250662885 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/20.uart_perf.2344314374 |
|
|
Oct 02 07:14:21 PM UTC 24 |
Oct 02 07:32:02 PM UTC 24 |
19721558737 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/41.uart_noise_filter.212366377 |
|
|
Oct 02 07:28:19 PM UTC 24 |
Oct 02 07:32:02 PM UTC 24 |
107226443778 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_alert_test.2947967710 |
|
|
Oct 02 07:32:03 PM UTC 24 |
Oct 02 07:32:05 PM UTC 24 |
37083234 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_smoke.1381810918 |
|
|
Oct 02 07:32:04 PM UTC 24 |
Oct 02 07:32:07 PM UTC 24 |
901784128 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/46.uart_rx_oversample.3934583508 |
|
|
Oct 02 07:31:39 PM UTC 24 |
Oct 02 07:32:08 PM UTC 24 |
2832653253 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.3826569030 |
|
|
Oct 02 07:31:00 PM UTC 24 |
Oct 02 07:32:16 PM UTC 24 |
46356624228 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/40.uart_stress_all.2300776837 |
|
|
Oct 02 07:27:55 PM UTC 24 |
Oct 02 07:32:18 PM UTC 24 |
170624184833 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.3400186422 |
|
|
Oct 02 07:29:46 PM UTC 24 |
Oct 02 07:32:19 PM UTC 24 |
112057027609 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/39.uart_fifo_reset.2424581516 |
|
|
Oct 02 07:26:53 PM UTC 24 |
Oct 02 07:32:26 PM UTC 24 |
210050558351 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/44.uart_perf.1606140789 |
|
|
Oct 02 07:30:20 PM UTC 24 |
Oct 02 07:32:29 PM UTC 24 |
12717555238 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/45.uart_tx_rx.3354875582 |
|
|
Oct 02 07:30:38 PM UTC 24 |
Oct 02 07:32:30 PM UTC 24 |
59034804930 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_intr.2264555922 |
|
|
Oct 02 07:29:00 PM UTC 24 |
Oct 02 07:32:31 PM UTC 24 |
139565883403 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_tx_rx.3699555543 |
|
|
Oct 02 07:32:06 PM UTC 24 |
Oct 02 07:32:34 PM UTC 24 |
50982889812 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.2388554042 |
|
|
Oct 02 07:32:09 PM UTC 24 |
Oct 02 07:32:35 PM UTC 24 |
103683912860 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_rx_oversample.1812255893 |
|
|
Oct 02 07:32:19 PM UTC 24 |
Oct 02 07:32:35 PM UTC 24 |
1699673423 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.1089072161 |
|
|
Oct 02 07:32:30 PM UTC 24 |
Oct 02 07:32:36 PM UTC 24 |
3759448790 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.2934632708 |
|
|
Oct 02 07:32:32 PM UTC 24 |
Oct 02 07:32:36 PM UTC 24 |
611908514 ps |