| T1056 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/200.uart_fifo_reset.1997210118 |
|
|
Oct 02 07:40:50 PM UTC 24 |
Oct 02 07:41:20 PM UTC 24 |
67775812125 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/140.uart_fifo_reset.3494648308 |
|
|
Oct 02 07:39:15 PM UTC 24 |
Oct 02 07:41:20 PM UTC 24 |
137309483123 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.3834862243 |
|
|
Oct 02 07:34:07 PM UTC 24 |
Oct 02 07:41:22 PM UTC 24 |
73995045664 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/193.uart_fifo_reset.1450051327 |
|
|
Oct 02 07:40:39 PM UTC 24 |
Oct 02 07:41:23 PM UTC 24 |
52748351283 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/183.uart_fifo_reset.1825804695 |
|
|
Oct 02 07:40:28 PM UTC 24 |
Oct 02 07:41:24 PM UTC 24 |
20789147753 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/207.uart_fifo_reset.3390816050 |
|
|
Oct 02 07:41:05 PM UTC 24 |
Oct 02 07:41:24 PM UTC 24 |
24730925153 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/186.uart_fifo_reset.2734044139 |
|
|
Oct 02 07:40:31 PM UTC 24 |
Oct 02 07:41:28 PM UTC 24 |
51453154069 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/176.uart_fifo_reset.1149278603 |
|
|
Oct 02 07:40:20 PM UTC 24 |
Oct 02 07:41:29 PM UTC 24 |
51536002573 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/190.uart_fifo_reset.3795188793 |
|
|
Oct 02 07:40:37 PM UTC 24 |
Oct 02 07:41:29 PM UTC 24 |
73573969252 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/148.uart_fifo_reset.3906898113 |
|
|
Oct 02 07:39:28 PM UTC 24 |
Oct 02 07:41:30 PM UTC 24 |
64669076400 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/180.uart_fifo_reset.1233701359 |
|
|
Oct 02 07:40:24 PM UTC 24 |
Oct 02 07:41:31 PM UTC 24 |
87065642021 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2560654045 |
|
|
Oct 02 07:41:05 PM UTC 24 |
Oct 02 07:41:32 PM UTC 24 |
48345798445 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/184.uart_fifo_reset.1915997919 |
|
|
Oct 02 07:40:30 PM UTC 24 |
Oct 02 07:41:32 PM UTC 24 |
35769955527 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/191.uart_fifo_reset.4235301549 |
|
|
Oct 02 07:40:37 PM UTC 24 |
Oct 02 07:41:35 PM UTC 24 |
25880883719 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/79.uart_fifo_reset.908353367 |
|
|
Oct 02 07:36:48 PM UTC 24 |
Oct 02 07:41:36 PM UTC 24 |
141779430499 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/201.uart_fifo_reset.1977818643 |
|
|
Oct 02 07:40:55 PM UTC 24 |
Oct 02 07:41:36 PM UTC 24 |
14592151041 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/141.uart_fifo_reset.4042413863 |
|
|
Oct 02 07:39:17 PM UTC 24 |
Oct 02 07:41:46 PM UTC 24 |
193431363235 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/164.uart_fifo_reset.1390106274 |
|
|
Oct 02 07:39:54 PM UTC 24 |
Oct 02 07:41:47 PM UTC 24 |
61566131312 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/212.uart_fifo_reset.898059475 |
|
|
Oct 02 07:41:13 PM UTC 24 |
Oct 02 07:41:48 PM UTC 24 |
22163081277 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/98.uart_fifo_reset.1207568652 |
|
|
Oct 02 07:38:12 PM UTC 24 |
Oct 02 07:41:51 PM UTC 24 |
118507435502 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/217.uart_fifo_reset.4093303409 |
|
|
Oct 02 07:41:21 PM UTC 24 |
Oct 02 07:41:51 PM UTC 24 |
34937647036 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/197.uart_fifo_reset.2198617285 |
|
|
Oct 02 07:40:44 PM UTC 24 |
Oct 02 07:41:51 PM UTC 24 |
73609992698 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/206.uart_fifo_reset.3157742329 |
|
|
Oct 02 07:41:03 PM UTC 24 |
Oct 02 07:41:51 PM UTC 24 |
41938010003 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/199.uart_fifo_reset.2704452513 |
|
|
Oct 02 07:40:50 PM UTC 24 |
Oct 02 07:41:53 PM UTC 24 |
60067121413 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/231.uart_fifo_reset.849666970 |
|
|
Oct 02 07:41:36 PM UTC 24 |
Oct 02 07:41:53 PM UTC 24 |
15713308285 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/198.uart_fifo_reset.455034521 |
|
|
Oct 02 07:40:46 PM UTC 24 |
Oct 02 07:41:53 PM UTC 24 |
70478091311 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/211.uart_fifo_reset.1705131856 |
|
|
Oct 02 07:41:11 PM UTC 24 |
Oct 02 07:41:54 PM UTC 24 |
50269262859 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2953073779 |
|
|
Oct 02 07:40:56 PM UTC 24 |
Oct 02 07:41:56 PM UTC 24 |
198725016336 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/223.uart_fifo_reset.624632625 |
|
|
Oct 02 07:41:30 PM UTC 24 |
Oct 02 07:41:56 PM UTC 24 |
29687215776 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_perf.2426795593 |
|
|
Oct 02 07:32:36 PM UTC 24 |
Oct 02 07:41:59 PM UTC 24 |
21669560233 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/225.uart_fifo_reset.3559739556 |
|
|
Oct 02 07:41:30 PM UTC 24 |
Oct 02 07:41:59 PM UTC 24 |
13450263257 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.3504341398 |
|
|
Oct 02 07:25:07 PM UTC 24 |
Oct 02 07:42:00 PM UTC 24 |
132184565629 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/218.uart_fifo_reset.3785139145 |
|
|
Oct 02 07:41:21 PM UTC 24 |
Oct 02 07:42:02 PM UTC 24 |
62088566025 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/134.uart_fifo_reset.841037326 |
|
|
Oct 02 07:39:08 PM UTC 24 |
Oct 02 07:42:03 PM UTC 24 |
83872409602 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/222.uart_fifo_reset.44130606 |
|
|
Oct 02 07:41:25 PM UTC 24 |
Oct 02 07:42:05 PM UTC 24 |
270084725547 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/214.uart_fifo_reset.4255906771 |
|
|
Oct 02 07:41:15 PM UTC 24 |
Oct 02 07:42:05 PM UTC 24 |
22334702564 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.1386768558 |
|
|
Oct 02 07:16:24 PM UTC 24 |
Oct 02 07:42:08 PM UTC 24 |
151344390048 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/196.uart_fifo_reset.2661560340 |
|
|
Oct 02 07:40:43 PM UTC 24 |
Oct 02 07:42:08 PM UTC 24 |
92584569345 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/237.uart_fifo_reset.3033169498 |
|
|
Oct 02 07:41:52 PM UTC 24 |
Oct 02 07:44:49 PM UTC 24 |
94482927949 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/195.uart_fifo_reset.1323613465 |
|
|
Oct 02 07:40:42 PM UTC 24 |
Oct 02 07:42:08 PM UTC 24 |
27214424983 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/226.uart_fifo_reset.2304908541 |
|
|
Oct 02 07:41:31 PM UTC 24 |
Oct 02 07:42:08 PM UTC 24 |
44933626836 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/228.uart_fifo_reset.1833361720 |
|
|
Oct 02 07:41:32 PM UTC 24 |
Oct 02 07:42:09 PM UTC 24 |
64441050389 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/192.uart_fifo_reset.768423795 |
|
|
Oct 02 07:40:39 PM UTC 24 |
Oct 02 07:42:10 PM UTC 24 |
109927948271 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/205.uart_fifo_reset.2808264805 |
|
|
Oct 02 07:40:58 PM UTC 24 |
Oct 02 07:42:11 PM UTC 24 |
96503943204 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/158.uart_fifo_reset.3456385421 |
|
|
Oct 02 07:39:45 PM UTC 24 |
Oct 02 07:42:13 PM UTC 24 |
67765451268 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/227.uart_fifo_reset.3208683264 |
|
|
Oct 02 07:41:31 PM UTC 24 |
Oct 02 07:42:15 PM UTC 24 |
31730598516 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3502733745 |
|
|
Oct 02 07:42:01 PM UTC 24 |
Oct 02 07:42:19 PM UTC 24 |
14712816192 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/131.uart_fifo_reset.860247698 |
|
|
Oct 02 07:39:04 PM UTC 24 |
Oct 02 07:42:21 PM UTC 24 |
116543951201 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/238.uart_fifo_reset.29160528 |
|
|
Oct 02 07:41:52 PM UTC 24 |
Oct 02 07:42:22 PM UTC 24 |
16690720972 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/235.uart_fifo_reset.932872613 |
|
|
Oct 02 07:41:49 PM UTC 24 |
Oct 02 07:42:22 PM UTC 24 |
37435642696 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/246.uart_fifo_reset.697309411 |
|
|
Oct 02 07:42:00 PM UTC 24 |
Oct 02 07:42:22 PM UTC 24 |
22538417105 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/229.uart_fifo_reset.3895370535 |
|
|
Oct 02 07:41:33 PM UTC 24 |
Oct 02 07:42:23 PM UTC 24 |
22820267973 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/160.uart_fifo_reset.3266279883 |
|
|
Oct 02 07:39:48 PM UTC 24 |
Oct 02 07:42:26 PM UTC 24 |
90766358986 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/157.uart_fifo_reset.2595311276 |
|
|
Oct 02 07:39:44 PM UTC 24 |
Oct 02 07:42:27 PM UTC 24 |
45956219859 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/239.uart_fifo_reset.674932894 |
|
|
Oct 02 07:41:52 PM UTC 24 |
Oct 02 07:42:31 PM UTC 24 |
17002494185 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.2303514127 |
|
|
Oct 02 07:18:41 PM UTC 24 |
Oct 02 07:42:33 PM UTC 24 |
176083182367 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/93.uart_fifo_reset.1313874070 |
|
|
Oct 02 07:37:50 PM UTC 24 |
Oct 02 07:42:33 PM UTC 24 |
127448408612 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/224.uart_fifo_reset.4092283682 |
|
|
Oct 02 07:41:30 PM UTC 24 |
Oct 02 07:42:34 PM UTC 24 |
96465946520 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/221.uart_fifo_reset.927397029 |
|
|
Oct 02 07:41:25 PM UTC 24 |
Oct 02 07:42:39 PM UTC 24 |
38722162254 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/220.uart_fifo_reset.3092835374 |
|
|
Oct 02 07:41:23 PM UTC 24 |
Oct 02 07:42:39 PM UTC 24 |
51617850513 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.351335540 |
|
|
Oct 02 07:19:15 PM UTC 24 |
Oct 02 07:42:41 PM UTC 24 |
164099304806 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/287.uart_fifo_reset.3961842808 |
|
|
Oct 02 07:42:55 PM UTC 24 |
Oct 02 07:44:53 PM UTC 24 |
43876315551 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/253.uart_fifo_reset.490099724 |
|
|
Oct 02 07:42:08 PM UTC 24 |
Oct 02 07:42:42 PM UTC 24 |
218662669420 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/150.uart_fifo_reset.3552810715 |
|
|
Oct 02 07:39:31 PM UTC 24 |
Oct 02 07:42:42 PM UTC 24 |
73141500485 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/242.uart_fifo_reset.4031138706 |
|
|
Oct 02 07:41:54 PM UTC 24 |
Oct 02 07:42:44 PM UTC 24 |
80726648972 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/263.uart_fifo_reset.2788366925 |
|
|
Oct 02 07:42:22 PM UTC 24 |
Oct 02 07:42:45 PM UTC 24 |
23121314950 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/153.uart_fifo_reset.3109800015 |
|
|
Oct 02 07:39:42 PM UTC 24 |
Oct 02 07:42:46 PM UTC 24 |
185327036150 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/241.uart_fifo_reset.1074832824 |
|
|
Oct 02 07:41:54 PM UTC 24 |
Oct 02 07:42:49 PM UTC 24 |
25178884566 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/232.uart_fifo_reset.1791856351 |
|
|
Oct 02 07:41:36 PM UTC 24 |
Oct 02 07:42:50 PM UTC 24 |
151588603666 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/215.uart_fifo_reset.3416319647 |
|
|
Oct 02 07:41:19 PM UTC 24 |
Oct 02 07:42:52 PM UTC 24 |
41876607201 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/266.uart_fifo_reset.3765847305 |
|
|
Oct 02 07:42:23 PM UTC 24 |
Oct 02 07:42:52 PM UTC 24 |
24755723976 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/270.uart_fifo_reset.367595099 |
|
|
Oct 02 07:42:32 PM UTC 24 |
Oct 02 07:42:54 PM UTC 24 |
36932220117 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/256.uart_fifo_reset.1092839801 |
|
|
Oct 02 07:42:09 PM UTC 24 |
Oct 02 07:42:54 PM UTC 24 |
91388781810 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/233.uart_fifo_reset.969297601 |
|
|
Oct 02 07:41:47 PM UTC 24 |
Oct 02 07:42:54 PM UTC 24 |
30472292914 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/252.uart_fifo_reset.3855462826 |
|
|
Oct 02 07:42:06 PM UTC 24 |
Oct 02 07:42:57 PM UTC 24 |
196893206819 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3307390627 |
|
|
Oct 02 07:41:36 PM UTC 24 |
Oct 02 07:43:02 PM UTC 24 |
51305158958 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/259.uart_fifo_reset.2000501575 |
|
|
Oct 02 07:42:12 PM UTC 24 |
Oct 02 07:43:05 PM UTC 24 |
53051212909 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/247.uart_fifo_reset.2556612193 |
|
|
Oct 02 07:42:00 PM UTC 24 |
Oct 02 07:43:06 PM UTC 24 |
106942872339 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/278.uart_fifo_reset.4118355441 |
|
|
Oct 02 07:42:43 PM UTC 24 |
Oct 02 07:43:07 PM UTC 24 |
41183578369 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/269.uart_fifo_reset.2791003480 |
|
|
Oct 02 07:42:28 PM UTC 24 |
Oct 02 07:43:08 PM UTC 24 |
53316881783 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/274.uart_fifo_reset.3354245306 |
|
|
Oct 02 07:42:40 PM UTC 24 |
Oct 02 07:43:12 PM UTC 24 |
28740251423 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/251.uart_fifo_reset.2475084973 |
|
|
Oct 02 07:42:05 PM UTC 24 |
Oct 02 07:43:13 PM UTC 24 |
134065470192 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/254.uart_fifo_reset.838981359 |
|
|
Oct 02 07:42:08 PM UTC 24 |
Oct 02 07:43:14 PM UTC 24 |
31278936217 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/282.uart_fifo_reset.1039237240 |
|
|
Oct 02 07:42:50 PM UTC 24 |
Oct 02 07:43:15 PM UTC 24 |
49547143890 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/202.uart_fifo_reset.108807769 |
|
|
Oct 02 07:40:55 PM UTC 24 |
Oct 02 07:43:16 PM UTC 24 |
110663258909 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/249.uart_fifo_reset.4274151520 |
|
|
Oct 02 07:42:03 PM UTC 24 |
Oct 02 07:43:17 PM UTC 24 |
44696394447 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/271.uart_fifo_reset.584322554 |
|
|
Oct 02 07:42:34 PM UTC 24 |
Oct 02 07:43:20 PM UTC 24 |
120663711925 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/283.uart_fifo_reset.2071700441 |
|
|
Oct 02 07:42:51 PM UTC 24 |
Oct 02 07:43:24 PM UTC 24 |
30401382670 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/244.uart_fifo_reset.931858466 |
|
|
Oct 02 07:41:57 PM UTC 24 |
Oct 02 07:43:25 PM UTC 24 |
40360293953 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/265.uart_fifo_reset.3150980360 |
|
|
Oct 02 07:42:23 PM UTC 24 |
Oct 02 07:43:25 PM UTC 24 |
63942305847 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/294.uart_fifo_reset.1566604900 |
|
|
Oct 02 07:43:09 PM UTC 24 |
Oct 02 07:43:26 PM UTC 24 |
22806251853 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/280.uart_fifo_reset.1259330247 |
|
|
Oct 02 07:42:45 PM UTC 24 |
Oct 02 07:43:27 PM UTC 24 |
43714265947 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/292.uart_fifo_reset.1867124176 |
|
|
Oct 02 07:43:06 PM UTC 24 |
Oct 02 07:43:27 PM UTC 24 |
107284883780 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/286.uart_fifo_reset.2253301998 |
|
|
Oct 02 07:42:55 PM UTC 24 |
Oct 02 07:43:27 PM UTC 24 |
25678745700 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/255.uart_fifo_reset.3072634782 |
|
|
Oct 02 07:42:09 PM UTC 24 |
Oct 02 07:43:32 PM UTC 24 |
61942664220 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/264.uart_fifo_reset.3015809025 |
|
|
Oct 02 07:42:22 PM UTC 24 |
Oct 02 07:43:33 PM UTC 24 |
129425836847 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/179.uart_fifo_reset.3506890215 |
|
|
Oct 02 07:40:23 PM UTC 24 |
Oct 02 07:43:33 PM UTC 24 |
147278675396 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/210.uart_fifo_reset.3612018936 |
|
|
Oct 02 07:41:11 PM UTC 24 |
Oct 02 07:43:37 PM UTC 24 |
150274544606 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/291.uart_fifo_reset.1725264364 |
|
|
Oct 02 07:43:05 PM UTC 24 |
Oct 02 07:43:37 PM UTC 24 |
10663743964 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/289.uart_fifo_reset.603014691 |
|
|
Oct 02 07:42:58 PM UTC 24 |
Oct 02 07:43:38 PM UTC 24 |
65821070447 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/272.uart_fifo_reset.283917532 |
|
|
Oct 02 07:42:35 PM UTC 24 |
Oct 02 07:43:39 PM UTC 24 |
110198721472 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/203.uart_fifo_reset.3925554206 |
|
|
Oct 02 07:40:56 PM UTC 24 |
Oct 02 07:43:40 PM UTC 24 |
51552766229 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/295.uart_fifo_reset.2882057126 |
|
|
Oct 02 07:43:13 PM UTC 24 |
Oct 02 07:43:42 PM UTC 24 |
32860970606 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/285.uart_fifo_reset.1682425796 |
|
|
Oct 02 07:42:53 PM UTC 24 |
Oct 02 07:43:42 PM UTC 24 |
68930864776 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/257.uart_fifo_reset.204002033 |
|
|
Oct 02 07:42:09 PM UTC 24 |
Oct 02 07:43:45 PM UTC 24 |
34940550513 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/260.uart_fifo_reset.2059858326 |
|
|
Oct 02 07:42:14 PM UTC 24 |
Oct 02 07:43:45 PM UTC 24 |
26452897379 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/262.uart_fifo_reset.2926568114 |
|
|
Oct 02 07:42:20 PM UTC 24 |
Oct 02 07:43:51 PM UTC 24 |
44107686862 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2390651020 |
|
|
Oct 02 07:42:44 PM UTC 24 |
Oct 02 07:43:53 PM UTC 24 |
25682299395 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/258.uart_fifo_reset.3947645155 |
|
|
Oct 02 07:42:12 PM UTC 24 |
Oct 02 07:43:55 PM UTC 24 |
137310002862 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/284.uart_fifo_reset.399646552 |
|
|
Oct 02 07:42:53 PM UTC 24 |
Oct 02 07:43:56 PM UTC 24 |
123374648981 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/296.uart_fifo_reset.3221590045 |
|
|
Oct 02 07:43:14 PM UTC 24 |
Oct 02 07:44:00 PM UTC 24 |
98883347250 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/298.uart_fifo_reset.1886520598 |
|
|
Oct 02 07:43:16 PM UTC 24 |
Oct 02 07:44:03 PM UTC 24 |
81562056799 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/155.uart_fifo_reset.4214281001 |
|
|
Oct 02 07:39:43 PM UTC 24 |
Oct 02 07:44:04 PM UTC 24 |
86774847337 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/267.uart_fifo_reset.1575371046 |
|
|
Oct 02 07:42:24 PM UTC 24 |
Oct 02 07:44:04 PM UTC 24 |
42958733554 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/273.uart_fifo_reset.1001146341 |
|
|
Oct 02 07:42:35 PM UTC 24 |
Oct 02 07:44:06 PM UTC 24 |
90876110466 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1427711873 |
|
|
Oct 02 07:41:55 PM UTC 24 |
Oct 02 07:44:09 PM UTC 24 |
63900911270 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/171.uart_fifo_reset.3882028273 |
|
|
Oct 02 07:40:02 PM UTC 24 |
Oct 02 07:44:19 PM UTC 24 |
237443964950 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/288.uart_fifo_reset.1760264717 |
|
|
Oct 02 07:42:55 PM UTC 24 |
Oct 02 07:44:21 PM UTC 24 |
51305720967 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/92.uart_fifo_reset.3747238006 |
|
|
Oct 02 07:37:48 PM UTC 24 |
Oct 02 07:44:28 PM UTC 24 |
170225087767 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/299.uart_fifo_reset.3485614404 |
|
|
Oct 02 07:43:17 PM UTC 24 |
Oct 02 07:44:31 PM UTC 24 |
78698937272 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/240.uart_fifo_reset.2468306607 |
|
|
Oct 02 07:41:54 PM UTC 24 |
Oct 02 07:44:39 PM UTC 24 |
92703325535 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/250.uart_fifo_reset.625671854 |
|
|
Oct 02 07:42:04 PM UTC 24 |
Oct 02 07:45:06 PM UTC 24 |
86127009845 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/281.uart_fifo_reset.2085500717 |
|
|
Oct 02 07:42:47 PM UTC 24 |
Oct 02 07:45:09 PM UTC 24 |
91827909310 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/297.uart_fifo_reset.2578903504 |
|
|
Oct 02 07:43:15 PM UTC 24 |
Oct 02 07:45:11 PM UTC 24 |
59581850963 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/43.uart_perf.1310822087 |
|
|
Oct 02 07:29:17 PM UTC 24 |
Oct 02 07:45:18 PM UTC 24 |
20602133462 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/277.uart_fifo_reset.277005012 |
|
|
Oct 02 07:42:42 PM UTC 24 |
Oct 02 07:45:22 PM UTC 24 |
82706976534 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/293.uart_fifo_reset.1464815732 |
|
|
Oct 02 07:43:08 PM UTC 24 |
Oct 02 07:45:24 PM UTC 24 |
57961868626 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/236.uart_fifo_reset.2333207563 |
|
|
Oct 02 07:41:52 PM UTC 24 |
Oct 02 07:45:28 PM UTC 24 |
164958057417 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/234.uart_fifo_reset.3928197739 |
|
|
Oct 02 07:41:48 PM UTC 24 |
Oct 02 07:45:32 PM UTC 24 |
86023243411 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/268.uart_fifo_reset.1414907490 |
|
|
Oct 02 07:42:26 PM UTC 24 |
Oct 02 07:45:58 PM UTC 24 |
97070044384 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/290.uart_fifo_reset.925744953 |
|
|
Oct 02 07:43:02 PM UTC 24 |
Oct 02 07:45:59 PM UTC 24 |
149587708603 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/276.uart_fifo_reset.4105968784 |
|
|
Oct 02 07:42:42 PM UTC 24 |
Oct 02 07:46:13 PM UTC 24 |
198562925683 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/219.uart_fifo_reset.2893213374 |
|
|
Oct 02 07:41:23 PM UTC 24 |
Oct 02 07:46:22 PM UTC 24 |
139193654802 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.4034908029 |
|
|
Oct 02 07:32:31 PM UTC 24 |
Oct 02 07:46:47 PM UTC 24 |
217572303396 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/216.uart_fifo_reset.1728075029 |
|
|
Oct 02 07:41:20 PM UTC 24 |
Oct 02 07:47:20 PM UTC 24 |
93110468041 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/261.uart_fifo_reset.1052529870 |
|
|
Oct 02 07:42:16 PM UTC 24 |
Oct 02 07:47:21 PM UTC 24 |
122537534568 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.600287613 |
|
|
Oct 02 07:33:09 PM UTC 24 |
Oct 02 07:47:53 PM UTC 24 |
90117295674 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/194.uart_fifo_reset.818188754 |
|
|
Oct 02 07:40:39 PM UTC 24 |
Oct 02 07:48:30 PM UTC 24 |
236105142954 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/60.uart_fifo_reset.780532873 |
|
|
Oct 02 07:35:16 PM UTC 24 |
Oct 02 07:48:42 PM UTC 24 |
180416312290 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/245.uart_fifo_reset.238303428 |
|
|
Oct 02 07:41:57 PM UTC 24 |
Oct 02 07:49:56 PM UTC 24 |
370133147815 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/48.uart_stress_all.4255759179 |
|
|
Oct 02 07:33:20 PM UTC 24 |
Oct 02 07:50:28 PM UTC 24 |
310671995385 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/9.uart_stress_all.3049807989 |
|
|
Oct 02 07:09:26 PM UTC 24 |
Oct 02 07:52:36 PM UTC 24 |
408836941133 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/213.uart_fifo_reset.995117272 |
|
|
Oct 02 07:41:15 PM UTC 24 |
Oct 02 07:52:38 PM UTC 24 |
166096800722 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/47.uart_stress_all.2623426262 |
|
|
Oct 02 07:32:37 PM UTC 24 |
Oct 02 07:53:07 PM UTC 24 |
443206400246 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/24.uart_stress_all.3678686948 |
|
|
Oct 02 07:16:31 PM UTC 24 |
Oct 02 07:53:24 PM UTC 24 |
265190346898 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/default/275.uart_fifo_reset.3081227308 |
|
|
Oct 02 07:42:40 PM UTC 24 |
Oct 02 07:56:15 PM UTC 24 |
166777145960 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2400589088 |
|
|
Oct 02 07:43:18 PM UTC 24 |
Oct 02 07:43:21 PM UTC 24 |
40607887 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.1579357533 |
|
|
Oct 02 07:43:21 PM UTC 24 |
Oct 02 07:43:23 PM UTC 24 |
48277382 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.4008487693 |
|
|
Oct 02 07:43:21 PM UTC 24 |
Oct 02 07:43:25 PM UTC 24 |
351127557 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.1479233825 |
|
|
Oct 02 07:43:24 PM UTC 24 |
Oct 02 07:43:26 PM UTC 24 |
17348638 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.631816948 |
|
|
Oct 02 07:43:26 PM UTC 24 |
Oct 02 07:43:28 PM UTC 24 |
15295122 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.484475078 |
|
|
Oct 02 07:43:26 PM UTC 24 |
Oct 02 07:43:28 PM UTC 24 |
47465706 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.2544853548 |
|
|
Oct 02 07:43:26 PM UTC 24 |
Oct 02 07:43:28 PM UTC 24 |
23666250 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.4152384623 |
|
|
Oct 02 07:43:27 PM UTC 24 |
Oct 02 07:43:29 PM UTC 24 |
23702074 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.602305350 |
|
|
Oct 02 07:43:26 PM UTC 24 |
Oct 02 07:43:29 PM UTC 24 |
132249496 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.3277513183 |
|
|
Oct 02 07:43:27 PM UTC 24 |
Oct 02 07:43:30 PM UTC 24 |
58499338 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.505249717 |
|
|
Oct 02 07:43:28 PM UTC 24 |
Oct 02 07:43:30 PM UTC 24 |
22249471 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.4254828196 |
|
|
Oct 02 07:43:28 PM UTC 24 |
Oct 02 07:43:30 PM UTC 24 |
16512448 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2399288062 |
|
|
Oct 02 07:43:28 PM UTC 24 |
Oct 02 07:43:31 PM UTC 24 |
370917775 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.2430322344 |
|
|
Oct 02 07:43:29 PM UTC 24 |
Oct 02 07:43:32 PM UTC 24 |
11751372 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.3592142404 |
|
|
Oct 02 07:43:29 PM UTC 24 |
Oct 02 07:43:32 PM UTC 24 |
17853417 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.3158373846 |
|
|
Oct 02 07:43:31 PM UTC 24 |
Oct 02 07:43:33 PM UTC 24 |
103633003 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.297623017 |
|
|
Oct 02 07:43:31 PM UTC 24 |
Oct 02 07:43:33 PM UTC 24 |
26181251 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3790720197 |
|
|
Oct 02 07:43:29 PM UTC 24 |
Oct 02 07:43:34 PM UTC 24 |
217739938 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.2007637220 |
|
|
Oct 02 07:43:45 PM UTC 24 |
Oct 02 07:43:47 PM UTC 24 |
199365247 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.297909912 |
|
|
Oct 02 07:43:31 PM UTC 24 |
Oct 02 07:43:34 PM UTC 24 |
351554861 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.3714080281 |
|
|
Oct 02 07:43:32 PM UTC 24 |
Oct 02 07:43:34 PM UTC 24 |
18606615 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.2523631889 |
|
|
Oct 02 07:43:31 PM UTC 24 |
Oct 02 07:43:34 PM UTC 24 |
131130217 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.1068492018 |
|
|
Oct 02 07:43:32 PM UTC 24 |
Oct 02 07:43:34 PM UTC 24 |
17456041 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3417856845 |
|
|
Oct 02 07:43:33 PM UTC 24 |
Oct 02 07:43:35 PM UTC 24 |
18927727 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3009091423 |
|
|
Oct 02 07:43:33 PM UTC 24 |
Oct 02 07:43:35 PM UTC 24 |
32759808 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.378703131 |
|
|
Oct 02 07:43:33 PM UTC 24 |
Oct 02 07:43:35 PM UTC 24 |
49425326 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.3887391354 |
|
|
Oct 02 07:43:33 PM UTC 24 |
Oct 02 07:43:36 PM UTC 24 |
116795853 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.638536883 |
|
|
Oct 02 07:43:44 PM UTC 24 |
Oct 02 07:43:48 PM UTC 24 |
475051956 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.645467053 |
|
|
Oct 02 07:43:35 PM UTC 24 |
Oct 02 07:43:37 PM UTC 24 |
23365625 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.3320283846 |
|
|
Oct 02 07:43:35 PM UTC 24 |
Oct 02 07:43:37 PM UTC 24 |
48488975 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2660085545 |
|
|
Oct 02 07:43:35 PM UTC 24 |
Oct 02 07:43:37 PM UTC 24 |
14733799 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.560113934 |
|
|
Oct 02 07:43:35 PM UTC 24 |
Oct 02 07:43:37 PM UTC 24 |
17813779 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.874129998 |
|
|
Oct 02 07:43:35 PM UTC 24 |
Oct 02 07:43:37 PM UTC 24 |
85405650 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.15112551 |
|
|
Oct 02 07:43:35 PM UTC 24 |
Oct 02 07:43:37 PM UTC 24 |
31062224 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2400439286 |
|
|
Oct 02 07:43:35 PM UTC 24 |
Oct 02 07:43:38 PM UTC 24 |
68189671 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.1482533811 |
|
|
Oct 02 07:43:35 PM UTC 24 |
Oct 02 07:43:38 PM UTC 24 |
85671438 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.268342260 |
|
|
Oct 02 07:43:36 PM UTC 24 |
Oct 02 07:43:38 PM UTC 24 |
288184399 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.235144026 |
|
|
Oct 02 07:43:36 PM UTC 24 |
Oct 02 07:43:39 PM UTC 24 |
20506093 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.2356431316 |
|
|
Oct 02 07:43:36 PM UTC 24 |
Oct 02 07:43:40 PM UTC 24 |
370211030 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.2998437329 |
|
|
Oct 02 07:43:38 PM UTC 24 |
Oct 02 07:43:40 PM UTC 24 |
25708809 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.1734450834 |
|
|
Oct 02 07:43:38 PM UTC 24 |
Oct 02 07:43:40 PM UTC 24 |
43634257 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.1557406425 |
|
|
Oct 02 07:43:38 PM UTC 24 |
Oct 02 07:43:40 PM UTC 24 |
28826360 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2635191623 |
|
|
Oct 02 07:43:38 PM UTC 24 |
Oct 02 07:43:40 PM UTC 24 |
37493170 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.4021990195 |
|
|
Oct 02 07:43:38 PM UTC 24 |
Oct 02 07:43:40 PM UTC 24 |
162538907 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.3102315915 |
|
|
Oct 02 07:43:38 PM UTC 24 |
Oct 02 07:43:40 PM UTC 24 |
53106846 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3828119570 |
|
|
Oct 02 07:43:38 PM UTC 24 |
Oct 02 07:43:40 PM UTC 24 |
26211106 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.1885285135 |
|
|
Oct 02 07:43:40 PM UTC 24 |
Oct 02 07:43:42 PM UTC 24 |
30743790 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.2722259958 |
|
|
Oct 02 07:43:40 PM UTC 24 |
Oct 02 07:43:42 PM UTC 24 |
122348024 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.4104040100 |
|
|
Oct 02 07:43:40 PM UTC 24 |
Oct 02 07:43:42 PM UTC 24 |
20134486 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1360847440 |
|
|
Oct 02 07:43:40 PM UTC 24 |
Oct 02 07:43:42 PM UTC 24 |
38540231 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.3102844293 |
|
|
Oct 02 07:43:40 PM UTC 24 |
Oct 02 07:43:42 PM UTC 24 |
36151606 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.4233259663 |
|
|
Oct 02 07:43:40 PM UTC 24 |
Oct 02 07:43:43 PM UTC 24 |
288052414 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.3674053266 |
|
|
Oct 02 07:43:38 PM UTC 24 |
Oct 02 07:43:43 PM UTC 24 |
1648065062 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.2733191600 |
|
|
Oct 02 07:43:40 PM UTC 24 |
Oct 02 07:43:43 PM UTC 24 |
54266420 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.579242566 |
|
|
Oct 02 07:43:42 PM UTC 24 |
Oct 02 07:43:44 PM UTC 24 |
17057151 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.2233617304 |
|
|
Oct 02 07:43:42 PM UTC 24 |
Oct 02 07:43:44 PM UTC 24 |
11005285 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1446905190 |
|
|
Oct 02 07:43:42 PM UTC 24 |
Oct 02 07:43:44 PM UTC 24 |
54976510 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.727410577 |
|
|
Oct 02 07:43:42 PM UTC 24 |
Oct 02 07:43:44 PM UTC 24 |
74350369 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.357534643 |
|
|
Oct 02 07:43:42 PM UTC 24 |
Oct 02 07:43:44 PM UTC 24 |
52052805 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.3295028942 |
|
|
Oct 02 07:43:42 PM UTC 24 |
Oct 02 07:43:44 PM UTC 24 |
24547315 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.1426290486 |
|
|
Oct 02 07:43:42 PM UTC 24 |
Oct 02 07:43:44 PM UTC 24 |
70202019 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.1628638957 |
|
|
Oct 02 07:43:42 PM UTC 24 |
Oct 02 07:43:44 PM UTC 24 |
39471763 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.3799349199 |
|
|
Oct 02 07:43:42 PM UTC 24 |
Oct 02 07:43:44 PM UTC 24 |
144022078 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.1578604761 |
|
|
Oct 02 07:43:44 PM UTC 24 |
Oct 02 07:43:46 PM UTC 24 |
22308081 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.475505802 |
|
|
Oct 02 07:43:44 PM UTC 24 |
Oct 02 07:43:46 PM UTC 24 |
45075884 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.2521714129 |
|
|
Oct 02 07:43:44 PM UTC 24 |
Oct 02 07:43:46 PM UTC 24 |
11507730 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2386896376 |
|
|
Oct 02 07:43:44 PM UTC 24 |
Oct 02 07:43:46 PM UTC 24 |
22488283 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1568474041 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
89603560 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.1347289273 |
|
|
Oct 02 07:43:45 PM UTC 24 |
Oct 02 07:43:46 PM UTC 24 |
19047292 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.4160032370 |
|
|
Oct 02 07:43:45 PM UTC 24 |
Oct 02 07:43:46 PM UTC 24 |
19218846 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.711294423 |
|
|
Oct 02 07:43:45 PM UTC 24 |
Oct 02 07:43:47 PM UTC 24 |
145327772 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3643756064 |
|
|
Oct 02 07:43:44 PM UTC 24 |
Oct 02 07:43:47 PM UTC 24 |
154178590 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1347748617 |
|
|
Oct 02 07:43:45 PM UTC 24 |
Oct 02 07:43:47 PM UTC 24 |
31326193 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.2984739372 |
|
|
Oct 02 07:43:45 PM UTC 24 |
Oct 02 07:43:48 PM UTC 24 |
106821930 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.2039080064 |
|
|
Oct 02 07:43:47 PM UTC 24 |
Oct 02 07:43:49 PM UTC 24 |
48141777 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.1566594184 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:49 PM UTC 24 |
16994348 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.133420467 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
75827888 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3645003228 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
71249226 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.880276856 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
14289642 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.2537705997 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
17674777 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.4206256903 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
47905453 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.474496335 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
39232514 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.1459461742 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
52401824 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.2980513850 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
17764940 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.1220135425 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
63013693 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2033524642 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:51 PM UTC 24 |
65420499 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3046505578 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
239687633 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.1100360416 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
160736080 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.3763791950 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
69367230 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1673512256 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:50 PM UTC 24 |
64892194 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.4011680408 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:51 PM UTC 24 |
725079783 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.3457693435 |
|
|
Oct 02 07:43:48 PM UTC 24 |
Oct 02 07:43:51 PM UTC 24 |
165666985 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.288802578 |
|
|
Oct 02 07:43:51 PM UTC 24 |
Oct 02 07:43:52 PM UTC 24 |
18442175 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.4063702450 |
|
|
Oct 02 07:43:51 PM UTC 24 |
Oct 02 07:43:53 PM UTC 24 |
13266875 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2093320271 |
|
|
Oct 02 07:43:51 PM UTC 24 |
Oct 02 07:43:53 PM UTC 24 |
103945911 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.547482261 |
|
|
Oct 02 07:43:51 PM UTC 24 |
Oct 02 07:43:53 PM UTC 24 |
46602770 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1005383489 |
|
|
Oct 02 07:43:51 PM UTC 24 |
Oct 02 07:43:53 PM UTC 24 |
24435053 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.3976618443 |
|
|
Oct 02 07:43:51 PM UTC 24 |
Oct 02 07:43:53 PM UTC 24 |
187653861 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.240514150 |
|
|
Oct 02 07:43:51 PM UTC 24 |
Oct 02 07:43:53 PM UTC 24 |
53338562 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2819706504 |
|
|
Oct 02 07:43:51 PM UTC 24 |
Oct 02 07:43:53 PM UTC 24 |
24042122 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.1648721462 |
|
|
Oct 02 07:43:51 PM UTC 24 |
Oct 02 07:43:53 PM UTC 24 |
55888516 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1607262479 |
|
|
Oct 02 07:43:51 PM UTC 24 |
Oct 02 07:43:53 PM UTC 24 |
27076797 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.3902036944 |
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Oct 02 07:43:51 PM UTC 24 |
Oct 02 07:43:54 PM UTC 24 |
94554124 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.3616897194 |
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Oct 02 07:43:51 PM UTC 24 |
Oct 02 07:43:54 PM UTC 24 |
91995613 ps |