| T639 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.558173580 |
|
|
Oct 12 01:45:49 PM UTC 24 |
Oct 12 01:46:06 PM UTC 24 |
53471294523 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_rx_oversample.898359533 |
|
|
Oct 12 01:45:57 PM UTC 24 |
Oct 12 01:46:14 PM UTC 24 |
3381810892 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_stress_all.4288218714 |
|
|
Oct 12 01:39:42 PM UTC 24 |
Oct 12 01:46:17 PM UTC 24 |
217086544049 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.2960839860 |
|
|
Oct 12 01:46:15 PM UTC 24 |
Oct 12 01:46:18 PM UTC 24 |
502488862 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.2188451559 |
|
|
Oct 12 01:43:14 PM UTC 24 |
Oct 12 01:46:21 PM UTC 24 |
36545163801 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_fifo_full.3861390074 |
|
|
Oct 12 01:44:45 PM UTC 24 |
Oct 12 01:46:24 PM UTC 24 |
91249144860 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_stress_all.1894589587 |
|
|
Oct 12 01:44:43 PM UTC 24 |
Oct 12 01:46:24 PM UTC 24 |
25726904901 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.1535560236 |
|
|
Oct 12 01:46:07 PM UTC 24 |
Oct 12 01:46:24 PM UTC 24 |
4925971673 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_tx_rx.4191130559 |
|
|
Oct 12 01:54:18 PM UTC 24 |
Oct 12 01:54:57 PM UTC 24 |
30706331428 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_loopback.1505882918 |
|
|
Oct 12 01:46:18 PM UTC 24 |
Oct 12 01:46:27 PM UTC 24 |
3613867808 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_alert_test.36525104 |
|
|
Oct 12 01:46:25 PM UTC 24 |
Oct 12 01:46:27 PM UTC 24 |
14903948 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_smoke.2543269508 |
|
|
Oct 12 01:46:27 PM UTC 24 |
Oct 12 01:46:30 PM UTC 24 |
319614720 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_noise_filter.4163797316 |
|
|
Oct 12 01:41:16 PM UTC 24 |
Oct 12 01:46:30 PM UTC 24 |
89211643225 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.2903764274 |
|
|
Oct 12 01:45:06 PM UTC 24 |
Oct 12 01:46:34 PM UTC 24 |
16844761750 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_fifo_reset.2473636754 |
|
|
Oct 12 01:44:48 PM UTC 24 |
Oct 12 01:46:38 PM UTC 24 |
242227061829 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_fifo_full.3000731327 |
|
|
Oct 12 01:45:23 PM UTC 24 |
Oct 12 01:46:44 PM UTC 24 |
45602086348 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.4242779126 |
|
|
Oct 12 01:46:31 PM UTC 24 |
Oct 12 01:46:48 PM UTC 24 |
19332816650 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_fifo_reset.1668323130 |
|
|
Oct 12 01:45:49 PM UTC 24 |
Oct 12 01:46:52 PM UTC 24 |
27814365776 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.4013901426 |
|
|
Oct 12 01:46:49 PM UTC 24 |
Oct 12 01:46:56 PM UTC 24 |
3022705375 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_rx_oversample.491255116 |
|
|
Oct 12 01:46:35 PM UTC 24 |
Oct 12 01:46:57 PM UTC 24 |
3585390545 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.2497132869 |
|
|
Oct 12 01:45:25 PM UTC 24 |
Oct 12 01:47:00 PM UTC 24 |
59435163594 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_fifo_full.1293365773 |
|
|
Oct 12 01:45:48 PM UTC 24 |
Oct 12 01:47:03 PM UTC 24 |
127988369573 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_loopback.251479515 |
|
|
Oct 12 01:46:57 PM UTC 24 |
Oct 12 01:47:12 PM UTC 24 |
6007066967 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_fifo_reset.3294096812 |
|
|
Oct 12 01:46:32 PM UTC 24 |
Oct 12 01:47:14 PM UTC 24 |
16411595336 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_fifo_full.2543609335 |
|
|
Oct 12 01:44:25 PM UTC 24 |
Oct 12 01:47:21 PM UTC 24 |
236976566178 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.2227649859 |
|
|
Oct 12 01:46:56 PM UTC 24 |
Oct 12 01:47:22 PM UTC 24 |
6873761082 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_alert_test.2760343765 |
|
|
Oct 12 01:47:22 PM UTC 24 |
Oct 12 01:47:24 PM UTC 24 |
11650599 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_intr.3750704765 |
|
|
Oct 12 01:45:58 PM UTC 24 |
Oct 12 01:47:24 PM UTC 24 |
48872384617 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_stress_all.2102770032 |
|
|
Oct 12 01:42:27 PM UTC 24 |
Oct 12 01:47:26 PM UTC 24 |
218223702261 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_smoke.1052367049 |
|
|
Oct 12 01:47:23 PM UTC 24 |
Oct 12 01:47:26 PM UTC 24 |
467298513 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_intr.3862395068 |
|
|
Oct 12 01:46:39 PM UTC 24 |
Oct 12 01:47:30 PM UTC 24 |
47160475366 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.2399866193 |
|
|
Oct 12 01:46:24 PM UTC 24 |
Oct 12 01:47:32 PM UTC 24 |
5245444926 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.2398334396 |
|
|
Oct 12 01:38:12 PM UTC 24 |
Oct 12 01:47:44 PM UTC 24 |
62213027008 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.2765861596 |
|
|
Oct 12 01:46:08 PM UTC 24 |
Oct 12 01:47:46 PM UTC 24 |
168391322231 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.1342582936 |
|
|
Oct 12 01:47:47 PM UTC 24 |
Oct 12 01:47:54 PM UTC 24 |
1725247079 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.2736794062 |
|
|
Oct 12 01:47:26 PM UTC 24 |
Oct 12 01:47:56 PM UTC 24 |
9385180287 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.2170321016 |
|
|
Oct 12 01:44:03 PM UTC 24 |
Oct 12 01:47:59 PM UTC 24 |
82508784717 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_noise_filter.3563673377 |
|
|
Oct 12 01:46:04 PM UTC 24 |
Oct 12 01:48:02 PM UTC 24 |
246126409962 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_tx_rx.3581534222 |
|
|
Oct 12 01:45:48 PM UTC 24 |
Oct 12 01:48:02 PM UTC 24 |
177541030525 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_fifo_reset.3053467380 |
|
|
Oct 12 01:47:27 PM UTC 24 |
Oct 12 01:48:03 PM UTC 24 |
16857963992 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_noise_filter.3703169205 |
|
|
Oct 12 01:45:33 PM UTC 24 |
Oct 12 01:48:10 PM UTC 24 |
170488331057 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_rx_oversample.2042574739 |
|
|
Oct 12 01:47:31 PM UTC 24 |
Oct 12 01:48:13 PM UTC 24 |
7279691479 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_loopback.1496668081 |
|
|
Oct 12 01:47:59 PM UTC 24 |
Oct 12 01:48:14 PM UTC 24 |
5455992153 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_alert_test.2454359656 |
|
|
Oct 12 01:48:14 PM UTC 24 |
Oct 12 01:48:15 PM UTC 24 |
23639264 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.2913139874 |
|
|
Oct 12 01:47:57 PM UTC 24 |
Oct 12 01:48:18 PM UTC 24 |
8629611219 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_tx_rx.3893770214 |
|
|
Oct 12 01:47:24 PM UTC 24 |
Oct 12 01:48:25 PM UTC 24 |
27842919729 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_smoke.1721469605 |
|
|
Oct 12 01:48:15 PM UTC 24 |
Oct 12 01:48:28 PM UTC 24 |
10612264571 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_perf.1538247257 |
|
|
Oct 12 01:32:39 PM UTC 24 |
Oct 12 01:48:31 PM UTC 24 |
26200140569 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.2841429767 |
|
|
Oct 12 01:40:56 PM UTC 24 |
Oct 12 01:48:34 PM UTC 24 |
197851642637 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_stress_all.3253259966 |
|
|
Oct 12 01:40:59 PM UTC 24 |
Oct 12 01:48:35 PM UTC 24 |
291376437341 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_fifo_full.1563196840 |
|
|
Oct 12 01:48:19 PM UTC 24 |
Oct 12 01:48:39 PM UTC 24 |
11159813621 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.460825994 |
|
|
Oct 12 01:47:13 PM UTC 24 |
Oct 12 01:48:39 PM UTC 24 |
16698636780 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_fifo_reset.4093684202 |
|
|
Oct 12 01:45:30 PM UTC 24 |
Oct 12 01:48:41 PM UTC 24 |
107029690630 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_noise_filter.2230702146 |
|
|
Oct 12 01:47:45 PM UTC 24 |
Oct 12 01:48:45 PM UTC 24 |
69796225130 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.1050387807 |
|
|
Oct 12 01:48:43 PM UTC 24 |
Oct 12 01:48:46 PM UTC 24 |
3860154125 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_loopback.1509460852 |
|
|
Oct 12 01:48:46 PM UTC 24 |
Oct 12 01:48:49 PM UTC 24 |
1482579809 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.2077280600 |
|
|
Oct 12 01:30:03 PM UTC 24 |
Oct 12 01:48:51 PM UTC 24 |
173581076776 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_fifo_reset.3454004287 |
|
|
Oct 12 01:48:29 PM UTC 24 |
Oct 12 01:48:56 PM UTC 24 |
29330684675 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.1913205227 |
|
|
Oct 12 01:46:53 PM UTC 24 |
Oct 12 01:48:57 PM UTC 24 |
49367661156 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_fifo_full.2237909801 |
|
|
Oct 12 01:47:25 PM UTC 24 |
Oct 12 01:48:57 PM UTC 24 |
44740492257 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_alert_test.2941963440 |
|
|
Oct 12 01:48:57 PM UTC 24 |
Oct 12 01:48:59 PM UTC 24 |
22443832 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_smoke.2497100250 |
|
|
Oct 12 01:48:58 PM UTC 24 |
Oct 12 01:49:02 PM UTC 24 |
292716810 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.2938801359 |
|
|
Oct 12 01:48:52 PM UTC 24 |
Oct 12 01:49:02 PM UTC 24 |
630020110 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_perf.3741948622 |
|
|
Oct 12 01:42:19 PM UTC 24 |
Oct 12 01:49:03 PM UTC 24 |
12647592038 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_intr.553024431 |
|
|
Oct 12 01:48:35 PM UTC 24 |
Oct 12 01:49:06 PM UTC 24 |
31603183523 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.1623762381 |
|
|
Oct 12 01:48:26 PM UTC 24 |
Oct 12 01:49:08 PM UTC 24 |
55426033529 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_rx_oversample.4160346825 |
|
|
Oct 12 01:49:07 PM UTC 24 |
Oct 12 01:49:12 PM UTC 24 |
1606576398 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_stress_all.2084981170 |
|
|
Oct 12 01:43:21 PM UTC 24 |
Oct 12 01:49:13 PM UTC 24 |
245946293532 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.3292655514 |
|
|
Oct 12 01:49:13 PM UTC 24 |
Oct 12 01:49:18 PM UTC 24 |
3904147925 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_stress_all.672845004 |
|
|
Oct 12 01:45:43 PM UTC 24 |
Oct 12 01:49:19 PM UTC 24 |
111556135384 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_noise_filter.3199480109 |
|
|
Oct 12 01:48:35 PM UTC 24 |
Oct 12 01:49:19 PM UTC 24 |
75667853006 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_tx_rx.3967522823 |
|
|
Oct 12 01:46:28 PM UTC 24 |
Oct 12 01:49:23 PM UTC 24 |
76058055413 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.2640981490 |
|
|
Oct 12 01:49:02 PM UTC 24 |
Oct 12 01:49:26 PM UTC 24 |
11475977273 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_tx_rx.2446355334 |
|
|
Oct 12 01:48:59 PM UTC 24 |
Oct 12 01:49:27 PM UTC 24 |
48240182173 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_loopback.1536032215 |
|
|
Oct 12 01:49:19 PM UTC 24 |
Oct 12 01:49:28 PM UTC 24 |
10753327411 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.1209106197 |
|
|
Oct 12 01:48:40 PM UTC 24 |
Oct 12 01:49:29 PM UTC 24 |
111511299688 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_rx_oversample.1063245650 |
|
|
Oct 12 01:48:32 PM UTC 24 |
Oct 12 01:49:30 PM UTC 24 |
5245844964 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_alert_test.3221362982 |
|
|
Oct 12 01:49:29 PM UTC 24 |
Oct 12 01:49:31 PM UTC 24 |
26221959 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_tx_rx.2356000832 |
|
|
Oct 12 01:48:16 PM UTC 24 |
Oct 12 01:49:31 PM UTC 24 |
45983155522 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_smoke.3472590303 |
|
|
Oct 12 01:49:30 PM UTC 24 |
Oct 12 01:49:33 PM UTC 24 |
501612682 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.3634103874 |
|
|
Oct 12 01:49:19 PM UTC 24 |
Oct 12 01:49:39 PM UTC 24 |
6093334736 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_fifo_full.2134690769 |
|
|
Oct 12 01:46:29 PM UTC 24 |
Oct 12 01:49:39 PM UTC 24 |
206721437035 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.4294788201 |
|
|
Oct 12 01:47:04 PM UTC 24 |
Oct 12 01:49:52 PM UTC 24 |
68529151200 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.2762696661 |
|
|
Oct 12 01:49:28 PM UTC 24 |
Oct 12 01:49:54 PM UTC 24 |
8182498059 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.2776265677 |
|
|
Oct 12 01:48:03 PM UTC 24 |
Oct 12 01:49:54 PM UTC 24 |
5605003596 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_fifo_full.1015007421 |
|
|
Oct 12 01:49:31 PM UTC 24 |
Oct 12 01:49:58 PM UTC 24 |
165176647204 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.1918761927 |
|
|
Oct 12 01:49:53 PM UTC 24 |
Oct 12 01:49:58 PM UTC 24 |
1709149449 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.3205080527 |
|
|
Oct 12 01:49:14 PM UTC 24 |
Oct 12 01:49:59 PM UTC 24 |
72902388214 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_fifo_reset.1530794679 |
|
|
Oct 12 01:49:04 PM UTC 24 |
Oct 12 01:50:01 PM UTC 24 |
93121513514 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_loopback.1585994697 |
|
|
Oct 12 01:49:58 PM UTC 24 |
Oct 12 01:50:01 PM UTC 24 |
293165394 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_stress_all.3717375275 |
|
|
Oct 12 01:37:04 PM UTC 24 |
Oct 12 01:50:01 PM UTC 24 |
137752655148 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.4209421472 |
|
|
Oct 12 01:49:55 PM UTC 24 |
Oct 12 01:50:01 PM UTC 24 |
1047046393 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_intr.1122070035 |
|
|
Oct 12 01:49:40 PM UTC 24 |
Oct 12 01:50:02 PM UTC 24 |
31280973418 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_alert_test.1118876303 |
|
|
Oct 12 01:50:03 PM UTC 24 |
Oct 12 01:50:05 PM UTC 24 |
15519053 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_stress_all.1783155904 |
|
|
Oct 12 01:46:25 PM UTC 24 |
Oct 12 01:50:10 PM UTC 24 |
226007518306 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_smoke.1726766339 |
|
|
Oct 12 01:50:03 PM UTC 24 |
Oct 12 01:50:21 PM UTC 24 |
5440473765 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.1445115015 |
|
|
Oct 12 01:49:55 PM UTC 24 |
Oct 12 01:50:25 PM UTC 24 |
74479836435 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.3057479475 |
|
|
Oct 12 01:48:03 PM UTC 24 |
Oct 12 01:50:26 PM UTC 24 |
217368636605 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_intr.1036289113 |
|
|
Oct 12 01:49:09 PM UTC 24 |
Oct 12 01:50:28 PM UTC 24 |
41929415979 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.2347433540 |
|
|
Oct 12 01:48:40 PM UTC 24 |
Oct 12 01:50:37 PM UTC 24 |
69801062564 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.1163663452 |
|
|
Oct 12 01:47:55 PM UTC 24 |
Oct 12 01:50:37 PM UTC 24 |
67722804379 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_rx_oversample.2987680779 |
|
|
Oct 12 01:50:26 PM UTC 24 |
Oct 12 01:50:38 PM UTC 24 |
3947795071 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_fifo_full.1869948583 |
|
|
Oct 12 01:50:06 PM UTC 24 |
Oct 12 01:50:39 PM UTC 24 |
169024638192 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_tx_rx.488179162 |
|
|
Oct 12 01:49:31 PM UTC 24 |
Oct 12 01:50:39 PM UTC 24 |
68644087133 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_fifo_reset.2813931809 |
|
|
Oct 12 01:49:33 PM UTC 24 |
Oct 12 01:50:39 PM UTC 24 |
17594648339 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_noise_filter.382439294 |
|
|
Oct 12 01:46:45 PM UTC 24 |
Oct 12 01:50:43 PM UTC 24 |
89137475700 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.2651357144 |
|
|
Oct 12 01:50:02 PM UTC 24 |
Oct 12 01:50:45 PM UTC 24 |
11176665495 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.1881572183 |
|
|
Oct 12 01:45:34 PM UTC 24 |
Oct 12 01:50:45 PM UTC 24 |
129468353876 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_rx_oversample.1590463534 |
|
|
Oct 12 01:49:35 PM UTC 24 |
Oct 12 01:50:45 PM UTC 24 |
6139860995 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.3712420616 |
|
|
Oct 12 01:50:37 PM UTC 24 |
Oct 12 01:50:46 PM UTC 24 |
1929829094 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_loopback.1295204710 |
|
|
Oct 12 01:50:40 PM UTC 24 |
Oct 12 01:50:47 PM UTC 24 |
5514398002 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_alert_test.1073618631 |
|
|
Oct 12 01:50:46 PM UTC 24 |
Oct 12 01:50:48 PM UTC 24 |
20369904 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.281948740 |
|
|
Oct 12 01:50:11 PM UTC 24 |
Oct 12 01:50:48 PM UTC 24 |
19828117486 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_smoke.140786673 |
|
|
Oct 12 01:50:46 PM UTC 24 |
Oct 12 01:50:49 PM UTC 24 |
334011299 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_intr.3756182355 |
|
|
Oct 12 01:50:27 PM UTC 24 |
Oct 12 01:50:49 PM UTC 24 |
19456786376 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.2501331902 |
|
|
Oct 12 01:50:40 PM UTC 24 |
Oct 12 01:51:00 PM UTC 24 |
7158402035 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_noise_filter.4078462364 |
|
|
Oct 12 01:50:29 PM UTC 24 |
Oct 12 01:51:04 PM UTC 24 |
43384394673 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_rx_oversample.172011432 |
|
|
Oct 12 01:50:50 PM UTC 24 |
Oct 12 01:51:07 PM UTC 24 |
5597773063 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.487717308 |
|
|
Oct 12 01:50:38 PM UTC 24 |
Oct 12 01:51:08 PM UTC 24 |
29118115528 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_noise_filter.3259241046 |
|
|
Oct 12 01:49:13 PM UTC 24 |
Oct 12 01:51:10 PM UTC 24 |
145731301508 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.2309479526 |
|
|
Oct 12 01:51:05 PM UTC 24 |
Oct 12 01:51:13 PM UTC 24 |
3326303934 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.660936609 |
|
|
Oct 12 01:50:48 PM UTC 24 |
Oct 12 01:51:14 PM UTC 24 |
14038541425 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1884700312 |
|
|
Oct 12 01:51:08 PM UTC 24 |
Oct 12 01:51:16 PM UTC 24 |
1177722983 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_tx_rx.313281886 |
|
|
Oct 12 01:50:47 PM UTC 24 |
Oct 12 01:51:18 PM UTC 24 |
12161572010 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.3097339416 |
|
|
Oct 12 01:45:05 PM UTC 24 |
Oct 12 01:51:21 PM UTC 24 |
47848901870 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_alert_test.1044659377 |
|
|
Oct 12 01:51:22 PM UTC 24 |
Oct 12 01:51:23 PM UTC 24 |
73021034 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_loopback.1509790132 |
|
|
Oct 12 01:51:10 PM UTC 24 |
Oct 12 01:51:26 PM UTC 24 |
4670635835 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_tx_rx.3832866709 |
|
|
Oct 12 01:50:04 PM UTC 24 |
Oct 12 01:51:27 PM UTC 24 |
55936124298 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.1988244413 |
|
|
Oct 12 01:35:49 PM UTC 24 |
Oct 12 01:51:29 PM UTC 24 |
141528449692 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.2669179528 |
|
|
Oct 12 01:51:08 PM UTC 24 |
Oct 12 01:51:31 PM UTC 24 |
30760695878 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_intr.4049416493 |
|
|
Oct 12 01:50:51 PM UTC 24 |
Oct 12 01:51:36 PM UTC 24 |
78869024421 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_stress_all.1797840866 |
|
|
Oct 12 01:50:45 PM UTC 24 |
Oct 12 01:51:38 PM UTC 24 |
126431545292 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.1824079509 |
|
|
Oct 12 01:51:17 PM UTC 24 |
Oct 12 01:51:48 PM UTC 24 |
3296096623 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_smoke.1929059815 |
|
|
Oct 12 01:51:25 PM UTC 24 |
Oct 12 01:51:49 PM UTC 24 |
5469843742 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_tx_rx.2857236738 |
|
|
Oct 12 01:51:27 PM UTC 24 |
Oct 12 01:51:50 PM UTC 24 |
10086955481 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.2289690808 |
|
|
Oct 12 01:51:50 PM UTC 24 |
Oct 12 01:51:54 PM UTC 24 |
4133964957 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.2755795259 |
|
|
Oct 12 01:51:55 PM UTC 24 |
Oct 12 01:51:58 PM UTC 24 |
1158418242 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_noise_filter.3586270847 |
|
|
Oct 12 01:51:01 PM UTC 24 |
Oct 12 01:52:02 PM UTC 24 |
34484564763 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_rx_oversample.3826805663 |
|
|
Oct 12 01:51:36 PM UTC 24 |
Oct 12 01:52:02 PM UTC 24 |
7272120441 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_fifo_reset.1716141207 |
|
|
Oct 12 01:51:32 PM UTC 24 |
Oct 12 01:52:09 PM UTC 24 |
24727032732 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_fifo_reset.76093660 |
|
|
Oct 12 01:50:21 PM UTC 24 |
Oct 12 01:52:13 PM UTC 24 |
41752576706 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.2567983783 |
|
|
Oct 12 01:51:51 PM UTC 24 |
Oct 12 01:52:25 PM UTC 24 |
19265546627 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.37605338 |
|
|
Oct 12 01:50:44 PM UTC 24 |
Oct 12 01:52:27 PM UTC 24 |
8258488852 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_alert_test.3157388135 |
|
|
Oct 12 01:52:25 PM UTC 24 |
Oct 12 01:52:27 PM UTC 24 |
85818247 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_loopback.1344133635 |
|
|
Oct 12 01:51:59 PM UTC 24 |
Oct 12 01:52:28 PM UTC 24 |
7727011354 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.3903407741 |
|
|
Oct 12 01:45:40 PM UTC 24 |
Oct 12 01:52:29 PM UTC 24 |
164254552253 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_smoke.4156365269 |
|
|
Oct 12 01:52:27 PM UTC 24 |
Oct 12 01:52:32 PM UTC 24 |
959640136 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_intr.994738528 |
|
|
Oct 12 01:51:39 PM UTC 24 |
Oct 12 01:52:32 PM UTC 24 |
45497670989 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_noise_filter.3148468742 |
|
|
Oct 12 01:51:48 PM UTC 24 |
Oct 12 01:52:37 PM UTC 24 |
63524690281 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_perf.1850983120 |
|
|
Oct 12 01:45:05 PM UTC 24 |
Oct 12 01:52:38 PM UTC 24 |
7393559672 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.1888979843 |
|
|
Oct 12 01:52:09 PM UTC 24 |
Oct 12 01:52:38 PM UTC 24 |
7641982473 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_noise_filter.290458698 |
|
|
Oct 12 01:49:40 PM UTC 24 |
Oct 12 01:52:41 PM UTC 24 |
182581248627 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_fifo_full.3408686391 |
|
|
Oct 12 01:51:28 PM UTC 24 |
Oct 12 01:52:42 PM UTC 24 |
87208120047 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_stress_all.2648615919 |
|
|
Oct 12 01:48:56 PM UTC 24 |
Oct 12 01:52:42 PM UTC 24 |
633208497086 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_rx_oversample.1877439568 |
|
|
Oct 12 01:52:33 PM UTC 24 |
Oct 12 01:52:42 PM UTC 24 |
6120808166 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.3061486956 |
|
|
Oct 12 01:52:42 PM UTC 24 |
Oct 12 01:52:47 PM UTC 24 |
868090786 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.3457634939 |
|
|
Oct 12 01:29:39 PM UTC 24 |
Oct 12 01:52:49 PM UTC 24 |
198364307310 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_loopback.3708830012 |
|
|
Oct 12 01:52:43 PM UTC 24 |
Oct 12 01:52:49 PM UTC 24 |
3831192089 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.3815850073 |
|
|
Oct 12 01:52:39 PM UTC 24 |
Oct 12 01:52:53 PM UTC 24 |
4507702757 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_perf.2139527184 |
|
|
Oct 12 01:43:13 PM UTC 24 |
Oct 12 01:52:54 PM UTC 24 |
10357727754 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_alert_test.998324777 |
|
|
Oct 12 01:52:54 PM UTC 24 |
Oct 12 01:52:55 PM UTC 24 |
15263020 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_fifo_full.4004172831 |
|
|
Oct 12 01:50:47 PM UTC 24 |
Oct 12 01:52:56 PM UTC 24 |
50162710654 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_tx_rx.3582743847 |
|
|
Oct 12 01:52:28 PM UTC 24 |
Oct 12 01:52:59 PM UTC 24 |
30773512450 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_smoke.3011745575 |
|
|
Oct 12 01:52:56 PM UTC 24 |
Oct 12 01:52:59 PM UTC 24 |
881161804 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.2245968774 |
|
|
Oct 12 01:51:29 PM UTC 24 |
Oct 12 01:53:00 PM UTC 24 |
175733616815 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.3051774838 |
|
|
Oct 12 01:52:50 PM UTC 24 |
Oct 12 01:53:01 PM UTC 24 |
526600341 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_perf.1683848398 |
|
|
Oct 12 01:35:45 PM UTC 24 |
Oct 12 01:53:03 PM UTC 24 |
19219590726 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_fifo_full.3646985930 |
|
|
Oct 12 01:49:02 PM UTC 24 |
Oct 12 01:53:11 PM UTC 24 |
113803427269 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_rx_oversample.2534011151 |
|
|
Oct 12 01:53:01 PM UTC 24 |
Oct 12 01:53:13 PM UTC 24 |
3292343023 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.3979305890 |
|
|
Oct 12 01:52:42 PM UTC 24 |
Oct 12 01:53:16 PM UTC 24 |
283222320553 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_fifo_reset.3740573508 |
|
|
Oct 12 01:52:33 PM UTC 24 |
Oct 12 01:53:19 PM UTC 24 |
79187252268 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.1002344710 |
|
|
Oct 12 01:53:17 PM UTC 24 |
Oct 12 01:53:21 PM UTC 24 |
538219847 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_noise_filter.1563389141 |
|
|
Oct 12 01:52:39 PM UTC 24 |
Oct 12 01:53:21 PM UTC 24 |
21762916793 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.1182583956 |
|
|
Oct 12 01:52:30 PM UTC 24 |
Oct 12 01:53:27 PM UTC 24 |
111094744718 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_tx_rx.46434374 |
|
|
Oct 12 01:52:56 PM UTC 24 |
Oct 12 01:53:30 PM UTC 24 |
50126226605 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.4097137087 |
|
|
Oct 12 01:53:12 PM UTC 24 |
Oct 12 01:53:30 PM UTC 24 |
4376399182 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_loopback.4028835890 |
|
|
Oct 12 01:53:20 PM UTC 24 |
Oct 12 01:53:31 PM UTC 24 |
10162290563 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_alert_test.3515174398 |
|
|
Oct 12 01:53:31 PM UTC 24 |
Oct 12 01:53:33 PM UTC 24 |
65843385 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_tx_rx.3846943634 |
|
|
Oct 12 01:53:34 PM UTC 24 |
Oct 12 01:53:49 PM UTC 24 |
13354164530 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_stress_all.720964752 |
|
|
Oct 12 01:39:02 PM UTC 24 |
Oct 12 01:53:51 PM UTC 24 |
200580161661 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_perf.2214079262 |
|
|
Oct 12 01:49:19 PM UTC 24 |
Oct 12 01:53:51 PM UTC 24 |
17039236674 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_intr.352008382 |
|
|
Oct 12 01:52:38 PM UTC 24 |
Oct 12 01:53:54 PM UTC 24 |
59028465969 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.2809989390 |
|
|
Oct 12 01:53:14 PM UTC 24 |
Oct 12 01:53:54 PM UTC 24 |
79374800391 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_smoke.1381612738 |
|
|
Oct 12 01:53:31 PM UTC 24 |
Oct 12 01:53:56 PM UTC 24 |
11053414317 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_fifo_full.40288151 |
|
|
Oct 12 01:52:29 PM UTC 24 |
Oct 12 01:54:02 PM UTC 24 |
46413126565 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_fifo_reset.2071029615 |
|
|
Oct 12 01:53:00 PM UTC 24 |
Oct 12 01:54:03 PM UTC 24 |
26462583922 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.505364135 |
|
|
Oct 12 01:38:58 PM UTC 24 |
Oct 12 01:54:05 PM UTC 24 |
145253585147 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_intr.2868976131 |
|
|
Oct 12 01:47:34 PM UTC 24 |
Oct 12 01:54:06 PM UTC 24 |
228556176402 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.2620403677 |
|
|
Oct 12 01:54:06 PM UTC 24 |
Oct 12 01:54:10 PM UTC 24 |
438751233 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_stress_all.985760660 |
|
|
Oct 12 01:41:34 PM UTC 24 |
Oct 12 01:54:12 PM UTC 24 |
301530482504 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_noise_filter.4035883781 |
|
|
Oct 12 01:53:04 PM UTC 24 |
Oct 12 01:54:12 PM UTC 24 |
250233910315 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_loopback.1120434589 |
|
|
Oct 12 01:54:07 PM UTC 24 |
Oct 12 01:54:13 PM UTC 24 |
4445175084 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_perf.198256826 |
|
|
Oct 12 01:47:01 PM UTC 24 |
Oct 12 01:54:13 PM UTC 24 |
12891707016 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_alert_test.1564778417 |
|
|
Oct 12 01:54:14 PM UTC 24 |
Oct 12 01:54:15 PM UTC 24 |
18302647 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_rx_oversample.3023713971 |
|
|
Oct 12 01:53:55 PM UTC 24 |
Oct 12 01:54:17 PM UTC 24 |
5183405569 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_perf.3259402130 |
|
|
Oct 12 01:48:48 PM UTC 24 |
Oct 12 01:54:20 PM UTC 24 |
6053183556 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.982256326 |
|
|
Oct 12 01:53:00 PM UTC 24 |
Oct 12 01:54:21 PM UTC 24 |
77829751163 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_perf.978200640 |
|
|
Oct 12 01:32:01 PM UTC 24 |
Oct 12 01:54:22 PM UTC 24 |
34909968522 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.2954900667 |
|
|
Oct 12 01:53:28 PM UTC 24 |
Oct 12 01:54:26 PM UTC 24 |
3029812445 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_perf.2998147602 |
|
|
Oct 12 01:38:06 PM UTC 24 |
Oct 12 01:54:28 PM UTC 24 |
17934031539 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.1415088899 |
|
|
Oct 12 01:53:52 PM UTC 24 |
Oct 12 01:54:29 PM UTC 24 |
17750405939 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_smoke.776671228 |
|
|
Oct 12 01:54:17 PM UTC 24 |
Oct 12 01:54:29 PM UTC 24 |
6292955108 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_intr.2267192161 |
|
|
Oct 12 01:53:01 PM UTC 24 |
Oct 12 01:54:29 PM UTC 24 |
27346297038 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_rx_oversample.2662922526 |
|
|
Oct 12 01:54:27 PM UTC 24 |
Oct 12 01:54:30 PM UTC 24 |
1777318140 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.61735673 |
|
|
Oct 12 01:54:12 PM UTC 24 |
Oct 12 01:54:46 PM UTC 24 |
10731887128 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.3390357999 |
|
|
Oct 12 01:54:32 PM UTC 24 |
Oct 12 01:54:47 PM UTC 24 |
10803897910 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_perf.1168163219 |
|
|
Oct 12 01:49:58 PM UTC 24 |
Oct 12 01:54:50 PM UTC 24 |
8676967588 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_fifo_full.3375724416 |
|
|
Oct 12 01:52:57 PM UTC 24 |
Oct 12 01:54:52 PM UTC 24 |
96482956449 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.3612026407 |
|
|
Oct 12 01:54:03 PM UTC 24 |
Oct 12 01:54:56 PM UTC 24 |
37251212045 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_alert_test.3600288826 |
|
|
Oct 12 01:54:58 PM UTC 24 |
Oct 12 01:55:00 PM UTC 24 |
10891413 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.352796106 |
|
|
Oct 12 01:54:04 PM UTC 24 |
Oct 12 01:55:01 PM UTC 24 |
31562258709 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_intr.816722685 |
|
|
Oct 12 01:54:29 PM UTC 24 |
Oct 12 01:55:02 PM UTC 24 |
19238653598 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_smoke.4157714244 |
|
|
Oct 12 01:55:01 PM UTC 24 |
Oct 12 01:55:05 PM UTC 24 |
428830017 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.1580156452 |
|
|
Oct 12 01:54:53 PM UTC 24 |
Oct 12 01:55:11 PM UTC 24 |
6363717783 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_loopback.2752531051 |
|
|
Oct 12 01:54:48 PM UTC 24 |
Oct 12 01:55:14 PM UTC 24 |
7615989599 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.2030761211 |
|
|
Oct 12 01:54:30 PM UTC 24 |
Oct 12 01:55:14 PM UTC 24 |
40920929371 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_fifo_full.1514041600 |
|
|
Oct 12 01:53:49 PM UTC 24 |
Oct 12 01:55:14 PM UTC 24 |
241320909133 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_intr.4121569502 |
|
|
Oct 12 01:53:55 PM UTC 24 |
Oct 12 01:55:18 PM UTC 24 |
40171217110 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.2981880443 |
|
|
Oct 12 01:55:19 PM UTC 24 |
Oct 12 01:55:24 PM UTC 24 |
4185596980 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_rx_oversample.2681515465 |
|
|
Oct 12 01:55:15 PM UTC 24 |
Oct 12 01:55:26 PM UTC 24 |
2543328493 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_tx_rx.3203598421 |
|
|
Oct 12 01:55:01 PM UTC 24 |
Oct 12 01:55:30 PM UTC 24 |
68001344988 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.753523290 |
|
|
Oct 12 01:55:26 PM UTC 24 |
Oct 12 01:55:31 PM UTC 24 |
1736947360 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_perf.1134195482 |
|
|
Oct 12 01:38:58 PM UTC 24 |
Oct 12 01:55:32 PM UTC 24 |
14530880990 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_tx_rx.413540263 |
|
|
Oct 12 01:58:20 PM UTC 24 |
Oct 12 01:58:58 PM UTC 24 |
62940322391 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.3459484692 |
|
|
Oct 12 01:52:03 PM UTC 24 |
Oct 12 01:55:32 PM UTC 24 |
189604310004 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_alert_test.2140216524 |
|
|
Oct 12 01:55:33 PM UTC 24 |
Oct 12 01:55:35 PM UTC 24 |
14413274 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_noise_filter.3664408337 |
|
|
Oct 12 01:53:57 PM UTC 24 |
Oct 12 01:55:36 PM UTC 24 |
119867262258 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.3937948533 |
|
|
Oct 12 01:49:24 PM UTC 24 |
Oct 12 01:55:39 PM UTC 24 |
77516031821 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_smoke.773343426 |
|
|
Oct 12 01:55:36 PM UTC 24 |
Oct 12 01:55:40 PM UTC 24 |
741530282 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.824703336 |
|
|
Oct 12 01:55:06 PM UTC 24 |
Oct 12 01:55:41 PM UTC 24 |
97985234866 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_noise_filter.399921459 |
|
|
Oct 12 01:55:16 PM UTC 24 |
Oct 12 01:55:44 PM UTC 24 |
147980773118 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_perf.3562812747 |
|
|
Oct 12 01:44:39 PM UTC 24 |
Oct 12 01:55:44 PM UTC 24 |
15741644545 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_stress_all.1189787119 |
|
|
Oct 12 01:30:41 PM UTC 24 |
Oct 12 01:55:56 PM UTC 24 |
46856287502 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.2993586363 |
|
|
Oct 12 01:55:24 PM UTC 24 |
Oct 12 01:55:56 PM UTC 24 |
29295402058 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_loopback.2767693263 |
|
|
Oct 12 01:55:28 PM UTC 24 |
Oct 12 01:56:07 PM UTC 24 |
11035825907 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.3004094951 |
|
|
Oct 12 01:48:50 PM UTC 24 |
Oct 12 01:56:08 PM UTC 24 |
109049209581 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.72107558 |
|
|
Oct 12 01:56:09 PM UTC 24 |
Oct 12 01:56:15 PM UTC 24 |
3191655775 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.3617725408 |
|
|
Oct 12 01:55:57 PM UTC 24 |
Oct 12 01:56:15 PM UTC 24 |
36975848235 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_loopback.34701236 |
|
|
Oct 12 01:56:16 PM UTC 24 |
Oct 12 01:56:19 PM UTC 24 |
583216166 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_perf.3767955077 |
|
|
Oct 12 01:50:40 PM UTC 24 |
Oct 12 01:56:21 PM UTC 24 |
10564150697 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.3383503145 |
|
|
Oct 12 01:55:33 PM UTC 24 |
Oct 12 01:56:22 PM UTC 24 |
3476542166 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.1139730372 |
|
|
Oct 12 01:49:32 PM UTC 24 |
Oct 12 01:56:24 PM UTC 24 |
159336088876 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_alert_test.4222702618 |
|
|
Oct 12 01:56:25 PM UTC 24 |
Oct 12 01:56:26 PM UTC 24 |
22670927 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_smoke.1308688804 |
|
|
Oct 12 01:56:28 PM UTC 24 |
Oct 12 01:56:32 PM UTC 24 |
910278761 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_rx_oversample.2823539331 |
|
|
Oct 12 01:55:45 PM UTC 24 |
Oct 12 01:56:38 PM UTC 24 |
5647592580 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_fifo_reset.2597776419 |
|
|
Oct 12 01:55:42 PM UTC 24 |
Oct 12 01:56:39 PM UTC 24 |
89623381567 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_fifo_reset.2133313205 |
|
|
Oct 12 01:55:12 PM UTC 24 |
Oct 12 01:56:52 PM UTC 24 |
53207330797 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.1180965616 |
|
|
Oct 12 01:56:08 PM UTC 24 |
Oct 12 01:56:54 PM UTC 24 |
20337766311 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_intr.293066133 |
|
|
Oct 12 01:55:45 PM UTC 24 |
Oct 12 01:56:58 PM UTC 24 |
39312473728 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.4260138917 |
|
|
Oct 12 01:54:31 PM UTC 24 |
Oct 12 01:56:58 PM UTC 24 |
60410761319 ps |