| T1059 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/153.uart_fifo_reset.2661226131 |
|
|
Oct 12 02:03:42 PM UTC 24 |
Oct 12 02:05:12 PM UTC 24 |
111070931030 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/196.uart_fifo_reset.361946955 |
|
|
Oct 12 02:04:48 PM UTC 24 |
Oct 12 02:05:13 PM UTC 24 |
23028221369 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/182.uart_fifo_reset.1443315073 |
|
|
Oct 12 02:04:25 PM UTC 24 |
Oct 12 02:05:15 PM UTC 24 |
17485548913 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/190.uart_fifo_reset.238811300 |
|
|
Oct 12 02:04:36 PM UTC 24 |
Oct 12 02:05:18 PM UTC 24 |
67671074619 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/186.uart_fifo_reset.838415692 |
|
|
Oct 12 02:04:34 PM UTC 24 |
Oct 12 02:05:20 PM UTC 24 |
138837751038 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/170.uart_fifo_reset.1475905347 |
|
|
Oct 12 02:04:12 PM UTC 24 |
Oct 12 02:05:22 PM UTC 24 |
28245554553 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/207.uart_fifo_reset.197960357 |
|
|
Oct 12 02:05:07 PM UTC 24 |
Oct 12 02:05:24 PM UTC 24 |
15588794733 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/187.uart_fifo_reset.1880145239 |
|
|
Oct 12 02:04:35 PM UTC 24 |
Oct 12 02:05:25 PM UTC 24 |
39203617282 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/201.uart_fifo_reset.125004182 |
|
|
Oct 12 02:04:59 PM UTC 24 |
Oct 12 02:05:28 PM UTC 24 |
40526466621 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_stress_all.1637953635 |
|
|
Oct 12 01:58:36 PM UTC 24 |
Oct 12 02:05:32 PM UTC 24 |
221289588592 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3466248188 |
|
|
Oct 12 02:05:00 PM UTC 24 |
Oct 12 02:05:34 PM UTC 24 |
80367445372 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/195.uart_fifo_reset.3484759799 |
|
|
Oct 12 02:04:46 PM UTC 24 |
Oct 12 02:05:38 PM UTC 24 |
101875044677 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/192.uart_fifo_reset.208647210 |
|
|
Oct 12 02:04:44 PM UTC 24 |
Oct 12 02:05:40 PM UTC 24 |
98590818771 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2219004021 |
|
|
Oct 12 02:05:01 PM UTC 24 |
Oct 12 02:05:41 PM UTC 24 |
98975215743 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2618179634 |
|
|
Oct 12 02:05:01 PM UTC 24 |
Oct 12 02:05:43 PM UTC 24 |
293089743133 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/216.uart_fifo_reset.2499998355 |
|
|
Oct 12 02:05:25 PM UTC 24 |
Oct 12 02:05:45 PM UTC 24 |
5822691249 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/174.uart_fifo_reset.332932310 |
|
|
Oct 12 02:04:14 PM UTC 24 |
Oct 12 02:05:46 PM UTC 24 |
301982453782 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/218.uart_fifo_reset.3040343590 |
|
|
Oct 12 02:05:29 PM UTC 24 |
Oct 12 02:05:47 PM UTC 24 |
28486628092 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/169.uart_fifo_reset.1098373638 |
|
|
Oct 12 02:04:11 PM UTC 24 |
Oct 12 02:05:47 PM UTC 24 |
84258809850 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/164.uart_fifo_reset.1932213912 |
|
|
Oct 12 02:04:03 PM UTC 24 |
Oct 12 02:05:47 PM UTC 24 |
190739803210 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/217.uart_fifo_reset.3191346821 |
|
|
Oct 12 02:05:26 PM UTC 24 |
Oct 12 02:05:49 PM UTC 24 |
7453246984 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/194.uart_fifo_reset.1965478984 |
|
|
Oct 12 02:04:45 PM UTC 24 |
Oct 12 02:05:49 PM UTC 24 |
44682302675 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_stress_all.625944748 |
|
|
Oct 12 01:40:23 PM UTC 24 |
Oct 12 02:05:51 PM UTC 24 |
176629622264 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/209.uart_fifo_reset.972595538 |
|
|
Oct 12 02:05:13 PM UTC 24 |
Oct 12 02:05:51 PM UTC 24 |
20277135632 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/211.uart_fifo_reset.3159561787 |
|
|
Oct 12 02:05:14 PM UTC 24 |
Oct 12 02:05:51 PM UTC 24 |
31601510279 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/199.uart_fifo_reset.3271477100 |
|
|
Oct 12 02:04:56 PM UTC 24 |
Oct 12 02:06:06 PM UTC 24 |
22339912840 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/75.uart_fifo_reset.1042268842 |
|
|
Oct 12 02:00:41 PM UTC 24 |
Oct 12 02:05:53 PM UTC 24 |
133316545796 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/167.uart_fifo_reset.683351831 |
|
|
Oct 12 02:04:07 PM UTC 24 |
Oct 12 02:05:53 PM UTC 24 |
49813727848 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/215.uart_fifo_reset.2077878459 |
|
|
Oct 12 02:05:24 PM UTC 24 |
Oct 12 02:05:56 PM UTC 24 |
22595221824 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/95.uart_fifo_reset.706250431 |
|
|
Oct 12 02:01:53 PM UTC 24 |
Oct 12 02:05:56 PM UTC 24 |
92905419883 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/137.uart_fifo_reset.3880584219 |
|
|
Oct 12 02:03:09 PM UTC 24 |
Oct 12 02:05:57 PM UTC 24 |
93787850953 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/210.uart_fifo_reset.394109349 |
|
|
Oct 12 02:05:13 PM UTC 24 |
Oct 12 02:05:57 PM UTC 24 |
18926713019 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/220.uart_fifo_reset.1521051842 |
|
|
Oct 12 02:05:35 PM UTC 24 |
Oct 12 02:05:59 PM UTC 24 |
11381920115 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/219.uart_fifo_reset.4166630349 |
|
|
Oct 12 02:05:33 PM UTC 24 |
Oct 12 02:06:00 PM UTC 24 |
13002045102 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/213.uart_fifo_reset.3327322569 |
|
|
Oct 12 02:05:20 PM UTC 24 |
Oct 12 02:06:02 PM UTC 24 |
82163790866 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/173.uart_fifo_reset.1237640054 |
|
|
Oct 12 02:04:14 PM UTC 24 |
Oct 12 02:06:03 PM UTC 24 |
46180618901 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/208.uart_fifo_reset.4024497137 |
|
|
Oct 12 02:05:13 PM UTC 24 |
Oct 12 02:06:07 PM UTC 24 |
61278044834 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/171.uart_fifo_reset.1878367236 |
|
|
Oct 12 02:04:12 PM UTC 24 |
Oct 12 02:06:05 PM UTC 24 |
35298344676 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/197.uart_fifo_reset.3089754414 |
|
|
Oct 12 02:04:50 PM UTC 24 |
Oct 12 02:06:09 PM UTC 24 |
32844607232 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/227.uart_fifo_reset.4157686024 |
|
|
Oct 12 02:05:48 PM UTC 24 |
Oct 12 02:06:12 PM UTC 24 |
137973688737 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/166.uart_fifo_reset.662992791 |
|
|
Oct 12 02:04:06 PM UTC 24 |
Oct 12 02:06:14 PM UTC 24 |
62971581189 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/111.uart_fifo_reset.537317469 |
|
|
Oct 12 02:02:23 PM UTC 24 |
Oct 12 02:06:16 PM UTC 24 |
98250262138 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/238.uart_fifo_reset.3236816990 |
|
|
Oct 12 02:05:57 PM UTC 24 |
Oct 12 02:06:16 PM UTC 24 |
6784809595 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_perf.2946587988 |
|
|
Oct 12 01:52:03 PM UTC 24 |
Oct 12 02:06:17 PM UTC 24 |
13866183109 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/244.uart_fifo_reset.1191392199 |
|
|
Oct 12 02:06:04 PM UTC 24 |
Oct 12 02:06:19 PM UTC 24 |
62611209873 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/229.uart_fifo_reset.2394972472 |
|
|
Oct 12 02:05:48 PM UTC 24 |
Oct 12 02:06:20 PM UTC 24 |
84958478650 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/224.uart_fifo_reset.2182219074 |
|
|
Oct 12 02:05:45 PM UTC 24 |
Oct 12 02:06:22 PM UTC 24 |
53745845933 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/228.uart_fifo_reset.2364231043 |
|
|
Oct 12 02:05:48 PM UTC 24 |
Oct 12 02:06:25 PM UTC 24 |
43380031942 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/152.uart_fifo_reset.1754400710 |
|
|
Oct 12 02:03:34 PM UTC 24 |
Oct 12 02:06:25 PM UTC 24 |
124392931183 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/235.uart_fifo_reset.6888098 |
|
|
Oct 12 02:05:53 PM UTC 24 |
Oct 12 02:06:26 PM UTC 24 |
47717722472 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/221.uart_fifo_reset.2916226798 |
|
|
Oct 12 02:05:39 PM UTC 24 |
Oct 12 02:06:37 PM UTC 24 |
211031666459 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/251.uart_fifo_reset.245340728 |
|
|
Oct 12 02:06:13 PM UTC 24 |
Oct 12 02:06:38 PM UTC 24 |
54072327573 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/250.uart_fifo_reset.3998610715 |
|
|
Oct 12 02:06:11 PM UTC 24 |
Oct 12 02:06:41 PM UTC 24 |
167658470424 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/258.uart_fifo_reset.456778250 |
|
|
Oct 12 02:06:23 PM UTC 24 |
Oct 12 02:06:42 PM UTC 24 |
39681805026 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/231.uart_fifo_reset.2310840486 |
|
|
Oct 12 02:05:50 PM UTC 24 |
Oct 12 02:06:43 PM UTC 24 |
150017978901 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3732862872 |
|
|
Oct 12 02:06:05 PM UTC 24 |
Oct 12 02:06:44 PM UTC 24 |
36375436645 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/226.uart_fifo_reset.4184716381 |
|
|
Oct 12 02:05:47 PM UTC 24 |
Oct 12 02:06:45 PM UTC 24 |
103018775233 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/236.uart_fifo_reset.2097331924 |
|
|
Oct 12 02:05:54 PM UTC 24 |
Oct 12 02:06:45 PM UTC 24 |
58717986033 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/253.uart_fifo_reset.916335232 |
|
|
Oct 12 02:06:17 PM UTC 24 |
Oct 12 02:06:46 PM UTC 24 |
15181148892 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/223.uart_fifo_reset.3819051254 |
|
|
Oct 12 02:05:42 PM UTC 24 |
Oct 12 02:06:46 PM UTC 24 |
136966596717 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/240.uart_fifo_reset.376310776 |
|
|
Oct 12 02:05:59 PM UTC 24 |
Oct 12 02:06:49 PM UTC 24 |
101485844208 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/205.uart_fifo_reset.606017795 |
|
|
Oct 12 02:05:02 PM UTC 24 |
Oct 12 02:06:49 PM UTC 24 |
106832609760 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/121.uart_fifo_reset.828982008 |
|
|
Oct 12 02:02:44 PM UTC 24 |
Oct 12 02:06:49 PM UTC 24 |
107390106240 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/222.uart_fifo_reset.2898100704 |
|
|
Oct 12 02:05:40 PM UTC 24 |
Oct 12 02:06:49 PM UTC 24 |
95011317664 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/237.uart_fifo_reset.2307069813 |
|
|
Oct 12 02:05:57 PM UTC 24 |
Oct 12 02:06:51 PM UTC 24 |
108531617506 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/142.uart_fifo_reset.2300663762 |
|
|
Oct 12 02:03:20 PM UTC 24 |
Oct 12 02:06:52 PM UTC 24 |
101059739743 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/252.uart_fifo_reset.2084521860 |
|
|
Oct 12 02:06:15 PM UTC 24 |
Oct 12 02:06:54 PM UTC 24 |
37509778113 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/260.uart_fifo_reset.3442848151 |
|
|
Oct 12 02:06:25 PM UTC 24 |
Oct 12 02:06:57 PM UTC 24 |
48757071870 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/249.uart_fifo_reset.2087895545 |
|
|
Oct 12 02:06:08 PM UTC 24 |
Oct 12 02:06:58 PM UTC 24 |
214249756542 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_perf.2220377493 |
|
|
Oct 12 01:52:43 PM UTC 24 |
Oct 12 02:06:59 PM UTC 24 |
13768078669 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/254.uart_fifo_reset.654375990 |
|
|
Oct 12 02:06:17 PM UTC 24 |
Oct 12 02:07:03 PM UTC 24 |
19872467604 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/259.uart_fifo_reset.598988601 |
|
|
Oct 12 02:06:25 PM UTC 24 |
Oct 12 02:07:10 PM UTC 24 |
31752687383 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1373795820 |
|
|
Oct 12 02:05:58 PM UTC 24 |
Oct 12 02:07:10 PM UTC 24 |
25943701830 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/273.uart_fifo_reset.1878105317 |
|
|
Oct 12 02:06:50 PM UTC 24 |
Oct 12 02:07:10 PM UTC 24 |
44638992864 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1425902875 |
|
|
Oct 12 02:06:03 PM UTC 24 |
Oct 12 02:07:11 PM UTC 24 |
85194626125 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/248.uart_fifo_reset.4081115734 |
|
|
Oct 12 02:06:07 PM UTC 24 |
Oct 12 02:07:11 PM UTC 24 |
24035359311 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/214.uart_fifo_reset.2556941523 |
|
|
Oct 12 02:05:22 PM UTC 24 |
Oct 12 02:07:11 PM UTC 24 |
247153904926 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/132.uart_fifo_reset.3300510001 |
|
|
Oct 12 02:03:03 PM UTC 24 |
Oct 12 02:07:11 PM UTC 24 |
112342804987 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_perf.4256308096 |
|
|
Oct 12 01:56:16 PM UTC 24 |
Oct 12 02:07:11 PM UTC 24 |
8653675917 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/247.uart_fifo_reset.3767275559 |
|
|
Oct 12 02:06:06 PM UTC 24 |
Oct 12 02:07:13 PM UTC 24 |
179637471140 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/178.uart_fifo_reset.723428795 |
|
|
Oct 12 02:04:21 PM UTC 24 |
Oct 12 02:07:18 PM UTC 24 |
107552039336 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/256.uart_fifo_reset.528474897 |
|
|
Oct 12 02:06:20 PM UTC 24 |
Oct 12 02:07:19 PM UTC 24 |
26564754718 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/275.uart_fifo_reset.3445699984 |
|
|
Oct 12 02:06:51 PM UTC 24 |
Oct 12 02:07:20 PM UTC 24 |
11295308835 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/157.uart_fifo_reset.239411562 |
|
|
Oct 12 02:03:53 PM UTC 24 |
Oct 12 02:07:20 PM UTC 24 |
260337443128 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/266.uart_fifo_reset.3197014113 |
|
|
Oct 12 02:06:44 PM UTC 24 |
Oct 12 02:07:24 PM UTC 24 |
30684214897 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/241.uart_fifo_reset.2028486389 |
|
|
Oct 12 02:06:00 PM UTC 24 |
Oct 12 02:07:25 PM UTC 24 |
156907196735 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/188.uart_fifo_reset.4126790829 |
|
|
Oct 12 02:04:35 PM UTC 24 |
Oct 12 02:07:27 PM UTC 24 |
121629018388 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/261.uart_fifo_reset.353943367 |
|
|
Oct 12 02:06:27 PM UTC 24 |
Oct 12 02:07:27 PM UTC 24 |
27487814632 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/262.uart_fifo_reset.2541751555 |
|
|
Oct 12 02:06:38 PM UTC 24 |
Oct 12 02:07:27 PM UTC 24 |
29035493667 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/288.uart_fifo_reset.2107542968 |
|
|
Oct 12 02:07:12 PM UTC 24 |
Oct 12 02:07:29 PM UTC 24 |
16987522798 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/277.uart_fifo_reset.1887956413 |
|
|
Oct 12 02:06:53 PM UTC 24 |
Oct 12 02:07:31 PM UTC 24 |
19785456921 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/285.uart_fifo_reset.3894594240 |
|
|
Oct 12 02:07:11 PM UTC 24 |
Oct 12 02:07:33 PM UTC 24 |
9592103217 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2938038284 |
|
|
Oct 12 02:07:04 PM UTC 24 |
Oct 12 02:07:33 PM UTC 24 |
26226621570 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/284.uart_fifo_reset.2967814566 |
|
|
Oct 12 02:07:11 PM UTC 24 |
Oct 12 02:07:34 PM UTC 24 |
8219365015 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/257.uart_fifo_reset.2923469165 |
|
|
Oct 12 02:06:21 PM UTC 24 |
Oct 12 02:07:36 PM UTC 24 |
138996802471 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/183.uart_fifo_reset.1629332121 |
|
|
Oct 12 02:04:29 PM UTC 24 |
Oct 12 02:07:36 PM UTC 24 |
153576083036 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/271.uart_fifo_reset.135256523 |
|
|
Oct 12 02:06:47 PM UTC 24 |
Oct 12 02:07:39 PM UTC 24 |
23062243990 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/279.uart_fifo_reset.1864004766 |
|
|
Oct 12 02:06:58 PM UTC 24 |
Oct 12 02:07:40 PM UTC 24 |
13946706116 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/225.uart_fifo_reset.1146866563 |
|
|
Oct 12 02:05:46 PM UTC 24 |
Oct 12 02:07:44 PM UTC 24 |
67003761186 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/270.uart_fifo_reset.3659404713 |
|
|
Oct 12 02:06:46 PM UTC 24 |
Oct 12 02:07:46 PM UTC 24 |
86893658067 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/289.uart_fifo_reset.369328741 |
|
|
Oct 12 02:07:12 PM UTC 24 |
Oct 12 02:07:47 PM UTC 24 |
154760680517 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/299.uart_fifo_reset.3371814427 |
|
|
Oct 12 02:07:29 PM UTC 24 |
Oct 12 02:07:49 PM UTC 24 |
43735614009 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/264.uart_fifo_reset.3771994726 |
|
|
Oct 12 02:06:42 PM UTC 24 |
Oct 12 02:07:49 PM UTC 24 |
180060352410 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/281.uart_fifo_reset.3514692006 |
|
|
Oct 12 02:07:00 PM UTC 24 |
Oct 12 02:07:50 PM UTC 24 |
140851125043 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/129.uart_fifo_reset.656261401 |
|
|
Oct 12 02:03:02 PM UTC 24 |
Oct 12 02:07:51 PM UTC 24 |
133523255282 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/276.uart_fifo_reset.4125939000 |
|
|
Oct 12 02:06:53 PM UTC 24 |
Oct 12 02:07:53 PM UTC 24 |
26637549500 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/272.uart_fifo_reset.3733213761 |
|
|
Oct 12 02:06:50 PM UTC 24 |
Oct 12 02:07:55 PM UTC 24 |
81294809530 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/185.uart_fifo_reset.590718433 |
|
|
Oct 12 02:04:33 PM UTC 24 |
Oct 12 02:07:57 PM UTC 24 |
77770734716 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/269.uart_fifo_reset.3671194185 |
|
|
Oct 12 02:06:46 PM UTC 24 |
Oct 12 02:07:59 PM UTC 24 |
126033555828 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/294.uart_fifo_reset.2131378109 |
|
|
Oct 12 02:07:20 PM UTC 24 |
Oct 12 02:08:00 PM UTC 24 |
17195126099 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/291.uart_fifo_reset.2913045287 |
|
|
Oct 12 02:07:14 PM UTC 24 |
Oct 12 02:08:07 PM UTC 24 |
203212033708 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/234.uart_fifo_reset.1766809447 |
|
|
Oct 12 02:05:51 PM UTC 24 |
Oct 12 02:08:08 PM UTC 24 |
104451323834 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/255.uart_fifo_reset.1539159501 |
|
|
Oct 12 02:06:18 PM UTC 24 |
Oct 12 02:08:08 PM UTC 24 |
117893553527 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/232.uart_fifo_reset.2480175427 |
|
|
Oct 12 02:05:51 PM UTC 24 |
Oct 12 02:08:08 PM UTC 24 |
47219704922 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/287.uart_fifo_reset.4239603151 |
|
|
Oct 12 02:07:12 PM UTC 24 |
Oct 12 02:08:09 PM UTC 24 |
118564914943 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2028651934 |
|
|
Oct 12 02:07:13 PM UTC 24 |
Oct 12 02:08:10 PM UTC 24 |
28218177776 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/283.uart_fifo_reset.2000337151 |
|
|
Oct 12 02:07:11 PM UTC 24 |
Oct 12 02:08:18 PM UTC 24 |
37668830134 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/200.uart_fifo_reset.271904161 |
|
|
Oct 12 02:04:57 PM UTC 24 |
Oct 12 02:08:19 PM UTC 24 |
107783977969 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/106.uart_fifo_reset.3117069710 |
|
|
Oct 12 02:02:17 PM UTC 24 |
Oct 12 02:08:23 PM UTC 24 |
127560254391 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/246.uart_fifo_reset.1232769385 |
|
|
Oct 12 02:06:06 PM UTC 24 |
Oct 12 02:08:35 PM UTC 24 |
91706252699 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/278.uart_fifo_reset.1418989060 |
|
|
Oct 12 02:06:55 PM UTC 24 |
Oct 12 02:08:37 PM UTC 24 |
111886618913 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/292.uart_fifo_reset.606732817 |
|
|
Oct 12 02:07:19 PM UTC 24 |
Oct 12 02:08:38 PM UTC 24 |
179415662485 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/298.uart_fifo_reset.3224367339 |
|
|
Oct 12 02:07:28 PM UTC 24 |
Oct 12 02:08:40 PM UTC 24 |
69964425431 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/280.uart_fifo_reset.3771917678 |
|
|
Oct 12 02:06:59 PM UTC 24 |
Oct 12 02:08:43 PM UTC 24 |
53093660713 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/180.uart_fifo_reset.2130339768 |
|
|
Oct 12 02:04:22 PM UTC 24 |
Oct 12 02:08:44 PM UTC 24 |
77967494759 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/181.uart_fifo_reset.1400378926 |
|
|
Oct 12 02:04:25 PM UTC 24 |
Oct 12 02:08:44 PM UTC 24 |
170128182304 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/297.uart_fifo_reset.4282855414 |
|
|
Oct 12 02:07:26 PM UTC 24 |
Oct 12 02:08:46 PM UTC 24 |
157034042889 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/191.uart_fifo_reset.435491274 |
|
|
Oct 12 02:04:38 PM UTC 24 |
Oct 12 02:08:46 PM UTC 24 |
119564751289 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/296.uart_fifo_reset.1517724451 |
|
|
Oct 12 02:07:24 PM UTC 24 |
Oct 12 02:08:55 PM UTC 24 |
87170467975 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/242.uart_fifo_reset.1506871131 |
|
|
Oct 12 02:06:01 PM UTC 24 |
Oct 12 02:09:01 PM UTC 24 |
115165792276 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/265.uart_fifo_reset.1219589845 |
|
|
Oct 12 02:06:43 PM UTC 24 |
Oct 12 02:09:04 PM UTC 24 |
72035777588 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_perf.2690608825 |
|
|
Oct 12 01:58:31 PM UTC 24 |
Oct 12 02:09:09 PM UTC 24 |
13926510717 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2774670438 |
|
|
Oct 12 02:05:04 PM UTC 24 |
Oct 12 02:09:25 PM UTC 24 |
85557554715 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/179.uart_fifo_reset.1850865505 |
|
|
Oct 12 02:04:22 PM UTC 24 |
Oct 12 02:09:26 PM UTC 24 |
177689403040 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/293.uart_fifo_reset.3430124495 |
|
|
Oct 12 02:07:20 PM UTC 24 |
Oct 12 02:09:29 PM UTC 24 |
236972349664 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/268.uart_fifo_reset.2468085529 |
|
|
Oct 12 02:06:46 PM UTC 24 |
Oct 12 02:09:33 PM UTC 24 |
83928816860 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/286.uart_fifo_reset.2233796703 |
|
|
Oct 12 02:07:12 PM UTC 24 |
Oct 12 02:09:33 PM UTC 24 |
88932757504 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/99.uart_fifo_reset.3466077941 |
|
|
Oct 12 02:02:04 PM UTC 24 |
Oct 12 02:09:34 PM UTC 24 |
240004944568 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/119.uart_fifo_reset.3526629597 |
|
|
Oct 12 02:02:44 PM UTC 24 |
Oct 12 02:09:36 PM UTC 24 |
216439782262 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3216028066 |
|
|
Oct 12 02:05:50 PM UTC 24 |
Oct 12 02:09:43 PM UTC 24 |
141885426642 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/295.uart_fifo_reset.3574506116 |
|
|
Oct 12 02:07:21 PM UTC 24 |
Oct 12 02:09:48 PM UTC 24 |
114384157171 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2365516569 |
|
|
Oct 12 02:05:51 PM UTC 24 |
Oct 12 02:10:06 PM UTC 24 |
157207887221 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.3901175076 |
|
|
Oct 12 01:58:34 PM UTC 24 |
Oct 12 02:10:48 PM UTC 24 |
121038230476 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/274.uart_fifo_reset.1716783625 |
|
|
Oct 12 02:06:50 PM UTC 24 |
Oct 12 02:11:21 PM UTC 24 |
126872333598 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/263.uart_fifo_reset.260030785 |
|
|
Oct 12 02:06:39 PM UTC 24 |
Oct 12 02:11:27 PM UTC 24 |
107549672398 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.2064243684 |
|
|
Oct 12 01:54:12 PM UTC 24 |
Oct 12 02:14:17 PM UTC 24 |
125586040759 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/267.uart_fifo_reset.1680123331 |
|
|
Oct 12 02:06:45 PM UTC 24 |
Oct 12 02:14:41 PM UTC 24 |
137370518134 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_perf.581035805 |
|
|
Oct 12 01:45:37 PM UTC 24 |
Oct 12 02:14:46 PM UTC 24 |
29582025487 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_stress_all.207669579 |
|
|
Oct 12 01:55:33 PM UTC 24 |
Oct 12 02:21:50 PM UTC 24 |
247410772763 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.3084840351 |
|
|
Oct 12 02:07:30 PM UTC 24 |
Oct 12 02:07:32 PM UTC 24 |
198444298 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.983829328 |
|
|
Oct 12 02:07:29 PM UTC 24 |
Oct 12 02:07:33 PM UTC 24 |
37357385 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.3044844188 |
|
|
Oct 12 02:07:32 PM UTC 24 |
Oct 12 02:07:34 PM UTC 24 |
77892184 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.2980273550 |
|
|
Oct 12 02:07:33 PM UTC 24 |
Oct 12 02:07:35 PM UTC 24 |
35480067 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.955120868 |
|
|
Oct 12 02:07:33 PM UTC 24 |
Oct 12 02:07:35 PM UTC 24 |
47219622 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.1928376366 |
|
|
Oct 12 02:07:33 PM UTC 24 |
Oct 12 02:07:36 PM UTC 24 |
35261563 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.2632253707 |
|
|
Oct 12 02:07:34 PM UTC 24 |
Oct 12 02:07:36 PM UTC 24 |
13472867 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.2165877866 |
|
|
Oct 12 02:07:34 PM UTC 24 |
Oct 12 02:07:36 PM UTC 24 |
16573648 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1889705283 |
|
|
Oct 12 02:07:35 PM UTC 24 |
Oct 12 02:07:37 PM UTC 24 |
57571409 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2840574655 |
|
|
Oct 12 02:07:36 PM UTC 24 |
Oct 12 02:07:38 PM UTC 24 |
44888799 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.3340505520 |
|
|
Oct 12 02:07:37 PM UTC 24 |
Oct 12 02:07:39 PM UTC 24 |
48466118 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3265081677 |
|
|
Oct 12 02:07:37 PM UTC 24 |
Oct 12 02:07:39 PM UTC 24 |
35972537 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1455409914 |
|
|
Oct 12 02:07:36 PM UTC 24 |
Oct 12 02:07:39 PM UTC 24 |
52428588 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.3611930461 |
|
|
Oct 12 02:07:37 PM UTC 24 |
Oct 12 02:07:39 PM UTC 24 |
15567772 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.2692253460 |
|
|
Oct 12 02:07:37 PM UTC 24 |
Oct 12 02:07:39 PM UTC 24 |
21346707 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3790604405 |
|
|
Oct 12 02:07:38 PM UTC 24 |
Oct 12 02:07:40 PM UTC 24 |
15128730 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.769599274 |
|
|
Oct 12 02:07:38 PM UTC 24 |
Oct 12 02:07:40 PM UTC 24 |
15923754 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3213020821 |
|
|
Oct 12 02:07:37 PM UTC 24 |
Oct 12 02:07:41 PM UTC 24 |
116260298 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.1719035597 |
|
|
Oct 12 02:07:40 PM UTC 24 |
Oct 12 02:07:41 PM UTC 24 |
18710172 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.630438898 |
|
|
Oct 12 02:07:40 PM UTC 24 |
Oct 12 02:07:41 PM UTC 24 |
31884291 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3134913079 |
|
|
Oct 12 02:07:40 PM UTC 24 |
Oct 12 02:07:42 PM UTC 24 |
15876852 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.3447143528 |
|
|
Oct 12 02:07:39 PM UTC 24 |
Oct 12 02:07:43 PM UTC 24 |
184799394 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.3559456919 |
|
|
Oct 12 02:07:41 PM UTC 24 |
Oct 12 02:07:43 PM UTC 24 |
41373185 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3175953822 |
|
|
Oct 12 02:07:41 PM UTC 24 |
Oct 12 02:07:43 PM UTC 24 |
48976068 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1892578584 |
|
|
Oct 12 02:07:41 PM UTC 24 |
Oct 12 02:07:43 PM UTC 24 |
58043636 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.560977436 |
|
|
Oct 12 02:07:39 PM UTC 24 |
Oct 12 02:07:43 PM UTC 24 |
113289042 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.806436234 |
|
|
Oct 12 02:07:42 PM UTC 24 |
Oct 12 02:07:44 PM UTC 24 |
40296818 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.3458009527 |
|
|
Oct 12 02:07:41 PM UTC 24 |
Oct 12 02:07:44 PM UTC 24 |
535432407 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.1938496104 |
|
|
Oct 12 02:07:42 PM UTC 24 |
Oct 12 02:07:44 PM UTC 24 |
14708454 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.358301678 |
|
|
Oct 12 02:07:42 PM UTC 24 |
Oct 12 02:07:45 PM UTC 24 |
91372827 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.3339624471 |
|
|
Oct 12 02:07:54 PM UTC 24 |
Oct 12 02:07:56 PM UTC 24 |
35488827 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.125077685 |
|
|
Oct 12 02:07:44 PM UTC 24 |
Oct 12 02:07:45 PM UTC 24 |
30529745 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.3279484759 |
|
|
Oct 12 02:07:42 PM UTC 24 |
Oct 12 02:07:46 PM UTC 24 |
74209736 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.1362033776 |
|
|
Oct 12 02:07:44 PM UTC 24 |
Oct 12 02:07:46 PM UTC 24 |
18174193 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.568300069 |
|
|
Oct 12 02:07:44 PM UTC 24 |
Oct 12 02:07:46 PM UTC 24 |
116231569 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.4061088170 |
|
|
Oct 12 02:07:45 PM UTC 24 |
Oct 12 02:07:47 PM UTC 24 |
14001772 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.255854582 |
|
|
Oct 12 02:07:45 PM UTC 24 |
Oct 12 02:07:47 PM UTC 24 |
45839544 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3971492129 |
|
|
Oct 12 02:07:45 PM UTC 24 |
Oct 12 02:07:47 PM UTC 24 |
109301244 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.545352369 |
|
|
Oct 12 02:07:44 PM UTC 24 |
Oct 12 02:07:48 PM UTC 24 |
230437185 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.1442295392 |
|
|
Oct 12 02:07:45 PM UTC 24 |
Oct 12 02:07:48 PM UTC 24 |
79822349 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.3740218098 |
|
|
Oct 12 02:07:45 PM UTC 24 |
Oct 12 02:07:49 PM UTC 24 |
428516699 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.2393858980 |
|
|
Oct 12 02:07:47 PM UTC 24 |
Oct 12 02:07:49 PM UTC 24 |
50177949 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.2492566652 |
|
|
Oct 12 02:07:47 PM UTC 24 |
Oct 12 02:07:49 PM UTC 24 |
14448740 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.1604424081 |
|
|
Oct 12 02:07:47 PM UTC 24 |
Oct 12 02:07:49 PM UTC 24 |
68755232 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1204061556 |
|
|
Oct 12 02:07:47 PM UTC 24 |
Oct 12 02:07:49 PM UTC 24 |
41445621 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3447056505 |
|
|
Oct 12 02:07:53 PM UTC 24 |
Oct 12 02:07:56 PM UTC 24 |
74665576 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.1543072978 |
|
|
Oct 12 02:07:49 PM UTC 24 |
Oct 12 02:07:50 PM UTC 24 |
12555913 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.3302234372 |
|
|
Oct 12 02:07:49 PM UTC 24 |
Oct 12 02:07:50 PM UTC 24 |
48865376 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1433258363 |
|
|
Oct 12 02:07:49 PM UTC 24 |
Oct 12 02:07:51 PM UTC 24 |
19431539 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.3750737589 |
|
|
Oct 12 02:07:47 PM UTC 24 |
Oct 12 02:07:51 PM UTC 24 |
190217405 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.1580064015 |
|
|
Oct 12 02:07:49 PM UTC 24 |
Oct 12 02:07:51 PM UTC 24 |
102471647 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.2684708774 |
|
|
Oct 12 02:07:48 PM UTC 24 |
Oct 12 02:07:51 PM UTC 24 |
542005510 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.3627116307 |
|
|
Oct 12 02:07:48 PM UTC 24 |
Oct 12 02:07:52 PM UTC 24 |
79602676 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.3258781349 |
|
|
Oct 12 02:07:51 PM UTC 24 |
Oct 12 02:07:52 PM UTC 24 |
19522570 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.867114483 |
|
|
Oct 12 02:07:51 PM UTC 24 |
Oct 12 02:07:52 PM UTC 24 |
52013086 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.3452124526 |
|
|
Oct 12 02:07:51 PM UTC 24 |
Oct 12 02:07:53 PM UTC 24 |
46899569 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3010261333 |
|
|
Oct 12 02:07:51 PM UTC 24 |
Oct 12 02:07:53 PM UTC 24 |
31684446 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.3993309103 |
|
|
Oct 12 02:07:50 PM UTC 24 |
Oct 12 02:07:53 PM UTC 24 |
126383769 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.221281681 |
|
|
Oct 12 02:07:51 PM UTC 24 |
Oct 12 02:07:53 PM UTC 24 |
223505192 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3907462173 |
|
|
Oct 12 02:07:50 PM UTC 24 |
Oct 12 02:07:53 PM UTC 24 |
56827571 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.4193757747 |
|
|
Oct 12 02:07:51 PM UTC 24 |
Oct 12 02:07:54 PM UTC 24 |
188526725 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.2563269336 |
|
|
Oct 12 02:07:53 PM UTC 24 |
Oct 12 02:07:55 PM UTC 24 |
45954074 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.1556516905 |
|
|
Oct 12 02:07:53 PM UTC 24 |
Oct 12 02:07:55 PM UTC 24 |
12741186 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.1832615202 |
|
|
Oct 12 02:07:56 PM UTC 24 |
Oct 12 02:07:58 PM UTC 24 |
27400619 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.1628317649 |
|
|
Oct 12 02:07:53 PM UTC 24 |
Oct 12 02:07:55 PM UTC 24 |
39773572 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.4149522763 |
|
|
Oct 12 02:07:53 PM UTC 24 |
Oct 12 02:07:55 PM UTC 24 |
49472684 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.2720405724 |
|
|
Oct 12 02:07:53 PM UTC 24 |
Oct 12 02:07:55 PM UTC 24 |
101346702 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.272003191 |
|
|
Oct 12 02:07:53 PM UTC 24 |
Oct 12 02:07:55 PM UTC 24 |
67330599 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2962722683 |
|
|
Oct 12 02:07:53 PM UTC 24 |
Oct 12 02:07:55 PM UTC 24 |
80075087 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.2854380023 |
|
|
Oct 12 02:07:53 PM UTC 24 |
Oct 12 02:07:56 PM UTC 24 |
26058010 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.432564294 |
|
|
Oct 12 02:07:53 PM UTC 24 |
Oct 12 02:07:56 PM UTC 24 |
266101855 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.3852014217 |
|
|
Oct 12 02:07:54 PM UTC 24 |
Oct 12 02:07:56 PM UTC 24 |
287624104 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.2961546859 |
|
|
Oct 12 02:07:56 PM UTC 24 |
Oct 12 02:07:58 PM UTC 24 |
18150668 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.708418240 |
|
|
Oct 12 02:07:56 PM UTC 24 |
Oct 12 02:07:58 PM UTC 24 |
21891500 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.144845319 |
|
|
Oct 12 02:07:56 PM UTC 24 |
Oct 12 02:07:58 PM UTC 24 |
14410430 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.1482244979 |
|
|
Oct 12 02:07:56 PM UTC 24 |
Oct 12 02:07:58 PM UTC 24 |
20119436 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.3043855303 |
|
|
Oct 12 02:07:57 PM UTC 24 |
Oct 12 02:07:58 PM UTC 24 |
65837758 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.1605271345 |
|
|
Oct 12 02:07:56 PM UTC 24 |
Oct 12 02:07:58 PM UTC 24 |
56640039 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.536100927 |
|
|
Oct 12 02:07:57 PM UTC 24 |
Oct 12 02:07:59 PM UTC 24 |
69580118 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.1102165087 |
|
|
Oct 12 02:07:56 PM UTC 24 |
Oct 12 02:07:59 PM UTC 24 |
120742952 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.899906559 |
|
|
Oct 12 02:07:57 PM UTC 24 |
Oct 12 02:07:59 PM UTC 24 |
24798788 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1367956408 |
|
|
Oct 12 02:07:56 PM UTC 24 |
Oct 12 02:07:59 PM UTC 24 |
94267646 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1713699915 |
|
|
Oct 12 02:07:56 PM UTC 24 |
Oct 12 02:07:59 PM UTC 24 |
258893141 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2835081882 |
|
|
Oct 12 02:07:57 PM UTC 24 |
Oct 12 02:07:59 PM UTC 24 |
383028112 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.2503933268 |
|
|
Oct 12 02:07:59 PM UTC 24 |
Oct 12 02:08:01 PM UTC 24 |
37765962 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1287062189 |
|
|
Oct 12 02:07:59 PM UTC 24 |
Oct 12 02:08:01 PM UTC 24 |
256114196 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.3264247910 |
|
|
Oct 12 02:07:59 PM UTC 24 |
Oct 12 02:08:01 PM UTC 24 |
24644705 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1733439680 |
|
|
Oct 12 02:07:59 PM UTC 24 |
Oct 12 02:08:01 PM UTC 24 |
84555924 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.3322500191 |
|
|
Oct 12 02:07:59 PM UTC 24 |
Oct 12 02:08:01 PM UTC 24 |
14748997 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.2660462562 |
|
|
Oct 12 02:07:59 PM UTC 24 |
Oct 12 02:08:01 PM UTC 24 |
22522439 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.2986874603 |
|
|
Oct 12 02:07:59 PM UTC 24 |
Oct 12 02:08:01 PM UTC 24 |
16966557 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2860650733 |
|
|
Oct 12 02:08:00 PM UTC 24 |
Oct 12 02:08:01 PM UTC 24 |
18651969 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2719062045 |
|
|
Oct 12 02:07:59 PM UTC 24 |
Oct 12 02:08:01 PM UTC 24 |
68999126 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.1422877903 |
|
|
Oct 12 02:08:00 PM UTC 24 |
Oct 12 02:08:01 PM UTC 24 |
36456894 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.2369508390 |
|
|
Oct 12 02:07:59 PM UTC 24 |
Oct 12 02:08:01 PM UTC 24 |
48656887 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.3466290452 |
|
|
Oct 12 02:07:59 PM UTC 24 |
Oct 12 02:08:02 PM UTC 24 |
412648995 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1135552149 |
|
|
Oct 12 02:07:59 PM UTC 24 |
Oct 12 02:08:02 PM UTC 24 |
33170384 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.351281829 |
|
|
Oct 12 02:07:59 PM UTC 24 |
Oct 12 02:08:03 PM UTC 24 |
98096721 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.2288747743 |
|
|
Oct 12 02:08:03 PM UTC 24 |
Oct 12 02:08:04 PM UTC 24 |
16718662 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1909957392 |
|
|
Oct 12 02:08:03 PM UTC 24 |
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