| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.12 | 99.08 | 97.65 | 100.00 | 98.35 | 100.00 | 99.62 |
| T65 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.1210251200 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:05 PM UTC 24 | 22639183 ps | ||
| T1255 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.302521535 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:05 PM UTC 24 | 25464303 ps | ||
| T1256 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2039182067 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:05 PM UTC 24 | 44240879 ps | ||
| T1257 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.3067586021 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:05 PM UTC 24 | 108734954 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.650027420 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:05 PM UTC 24 | 35238793 ps | ||
| T1258 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.563430794 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:05 PM UTC 24 | 55270690 ps | ||
| T1259 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.3359177756 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:05 PM UTC 24 | 24650308 ps | ||
| T1260 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3616665106 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:05 PM UTC 24 | 55481385 ps | ||
| T1261 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3072621589 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:05 PM UTC 24 | 315437026 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.3051005735 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:05 PM UTC 24 | 75387038 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.460864832 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:05 PM UTC 24 | 505662480 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1946511865 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:05 PM UTC 24 | 41249176 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3164805583 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:06 PM UTC 24 | 233619656 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.274645192 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:06 PM UTC 24 | 63207108 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.941780210 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:06 PM UTC 24 | 348419981 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.2073989537 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:06 PM UTC 24 | 182316284 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.3296615705 | Oct 12 02:08:03 PM UTC 24 | Oct 12 02:08:06 PM UTC 24 | 54376017 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.3416573891 | Oct 12 02:08:06 PM UTC 24 | Oct 12 02:08:08 PM UTC 24 | 31688305 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2691274961 | Oct 12 02:08:06 PM UTC 24 | Oct 12 02:08:08 PM UTC 24 | 15199958 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.3091968705 | Oct 12 02:08:06 PM UTC 24 | Oct 12 02:08:08 PM UTC 24 | 152264790 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4264868096 | Oct 12 02:08:06 PM UTC 24 | Oct 12 02:08:08 PM UTC 24 | 199467469 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.718344352 | Oct 12 02:08:06 PM UTC 24 | Oct 12 02:08:08 PM UTC 24 | 32476279 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.3165424848 | Oct 12 02:08:06 PM UTC 24 | Oct 12 02:08:08 PM UTC 24 | 43779335 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.1224083708 | Oct 12 02:08:07 PM UTC 24 | Oct 12 02:08:08 PM UTC 24 | 43748771 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2304677942 | Oct 12 02:08:07 PM UTC 24 | Oct 12 02:08:08 PM UTC 24 | 71478496 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.1363476358 | Oct 12 02:08:06 PM UTC 24 | Oct 12 02:08:08 PM UTC 24 | 74232445 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3397094399 | Oct 12 02:08:06 PM UTC 24 | Oct 12 02:08:09 PM UTC 24 | 288338919 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.2948271494 | Oct 12 02:08:07 PM UTC 24 | Oct 12 02:08:09 PM UTC 24 | 53213501 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.85944000 | Oct 12 02:08:06 PM UTC 24 | Oct 12 02:08:09 PM UTC 24 | 133416563 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.3893640458 | Oct 12 02:08:07 PM UTC 24 | Oct 12 02:08:09 PM UTC 24 | 145945550 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.1365898085 | Oct 12 02:08:07 PM UTC 24 | Oct 12 02:08:10 PM UTC 24 | 172304217 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2623722874 | Oct 12 02:08:11 PM UTC 24 | Oct 12 02:08:13 PM UTC 24 | 14717958 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.982987409 | Oct 12 02:08:11 PM UTC 24 | Oct 12 02:08:13 PM UTC 24 | 13008742 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.475701270 | Oct 12 02:08:11 PM UTC 24 | Oct 12 02:08:13 PM UTC 24 | 32082125 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.866629871 | Oct 12 02:08:11 PM UTC 24 | Oct 12 02:08:13 PM UTC 24 | 18491821 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.2167606655 | Oct 12 02:08:11 PM UTC 24 | Oct 12 02:08:13 PM UTC 24 | 15022346 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.192362029 | Oct 12 02:08:11 PM UTC 24 | Oct 12 02:08:13 PM UTC 24 | 211798277 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2117431134 | Oct 12 02:08:11 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 116105710 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3233102416 | Oct 12 02:08:11 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 23655757 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.3259958006 | Oct 12 02:08:11 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 44613525 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.965465337 | Oct 12 02:08:11 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 35895859 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.1036349266 | Oct 12 02:08:11 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 55121438 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2351038997 | Oct 12 02:08:11 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 28235012 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.3993387357 | Oct 12 02:08:11 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 26265602 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.2807994452 | Oct 12 02:08:12 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 65222987 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.3030968462 | Oct 12 02:08:12 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 40671952 ps | ||
| T1297 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1097449041 | Oct 12 02:08:12 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 32889511 ps | ||
| T1298 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2260005801 | Oct 12 02:08:12 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 78386713 ps | ||
| T1299 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.4050267931 | Oct 12 02:08:12 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 22178662 ps | ||
| T1300 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3265733552 | Oct 12 02:08:12 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 155555096 ps | ||
| T1301 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.2777274914 | Oct 12 02:08:12 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 41795530 ps | ||
| T1302 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.2165962056 | Oct 12 02:08:12 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 37069183 ps | ||
| T1303 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.1451160197 | Oct 12 02:08:12 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 46699883 ps | ||
| T1304 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.91589531 | Oct 12 02:08:12 PM UTC 24 | Oct 12 02:08:14 PM UTC 24 | 12536031 ps | ||
| T1305 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1332529586 | Oct 12 02:08:14 PM UTC 24 | Oct 12 02:08:16 PM UTC 24 | 16705246 ps | ||
| T1306 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.3792637927 | Oct 12 02:08:14 PM UTC 24 | Oct 12 02:08:16 PM UTC 24 | 33745438 ps | ||
| T1307 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.2408518042 | Oct 12 02:08:14 PM UTC 24 | Oct 12 02:08:16 PM UTC 24 | 14598024 ps | ||
| T1308 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.2718720078 | Oct 12 02:08:14 PM UTC 24 | Oct 12 02:08:16 PM UTC 24 | 106468386 ps | ||
| T1309 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.823704779 | Oct 12 02:08:14 PM UTC 24 | Oct 12 02:08:16 PM UTC 24 | 47450833 ps | ||
| T1310 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.1437350631 | Oct 12 02:08:20 PM UTC 24 | Oct 12 02:08:22 PM UTC 24 | 14746470 ps | ||
| T1311 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.3205712704 | Oct 12 02:08:20 PM UTC 24 | Oct 12 02:08:22 PM UTC 24 | 29579905 ps | ||
| T1312 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.2447166200 | Oct 12 02:08:20 PM UTC 24 | Oct 12 02:08:22 PM UTC 24 | 25825994 ps | ||
| T1313 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2090322514 | Oct 12 02:08:20 PM UTC 24 | Oct 12 02:08:22 PM UTC 24 | 104183984 ps | ||
| T1314 | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.2057829514 | Oct 12 02:08:21 PM UTC 24 | Oct 12 02:08:22 PM UTC 24 | 39593093 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.1226577108 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11510114092 ps |
| CPU time | 5.89 seconds |
| Started | Oct 12 01:29:01 PM UTC 24 |
| Finished | Oct 12 01:29:08 PM UTC 24 |
| Peak memory | 208404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226577108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1226577108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_fifo_reset.2934967020 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 85033052485 ps |
| CPU time | 16.48 seconds |
| Started | Oct 12 01:29:13 PM UTC 24 |
| Finished | Oct 12 01:29:31 PM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934967020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2934967020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.2529714818 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1597002862 ps |
| CPU time | 48.7 seconds |
| Started | Oct 12 01:29:39 PM UTC 24 |
| Finished | Oct 12 01:30:29 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2529714818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_ with_rand_reset.2529714818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_stress_all.3145900777 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 424423546752 ps |
| CPU time | 287.03 seconds |
| Started | Oct 12 01:30:24 PM UTC 24 |
| Finished | Oct 12 01:35:16 PM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145900777 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3145900777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.1272072341 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 68215738619 ps |
| CPU time | 209.99 seconds |
| Started | Oct 12 01:29:04 PM UTC 24 |
| Finished | Oct 12 01:32:38 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272072341 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1272072341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_stress_all.763871102 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 85234364679 ps |
| CPU time | 248.25 seconds |
| Started | Oct 12 01:29:05 PM UTC 24 |
| Finished | Oct 12 01:33:17 PM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763871102 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.763871102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_stress_all.1947339213 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 152279086931 ps |
| CPU time | 331.23 seconds |
| Started | Oct 12 01:29:40 PM UTC 24 |
| Finished | Oct 12 01:35:15 PM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947339213 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1947339213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.864596570 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 57478057124 ps |
| CPU time | 117.86 seconds |
| Started | Oct 12 01:29:36 PM UTC 24 |
| Finished | Oct 12 01:31:36 PM UTC 24 |
| Peak memory | 208476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864596570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.864596570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.2378229274 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 219274259533 ps |
| CPU time | 273.53 seconds |
| Started | Oct 12 01:30:41 PM UTC 24 |
| Finished | Oct 12 01:35:18 PM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378229274 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2378229274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_intr.3946557102 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 27391495711 ps |
| CPU time | 78.73 seconds |
| Started | Oct 12 01:30:56 PM UTC 24 |
| Finished | Oct 12 01:32:17 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946557102 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3946557102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_sec_cm.3118056519 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 62708233 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 01:29:11 PM UTC 24 |
| Finished | Oct 12 01:29:13 PM UTC 24 |
| Peak memory | 237600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118056519 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3118056519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.8463463 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 356902107754 ps |
| CPU time | 186.44 seconds |
| Started | Oct 12 01:29:33 PM UTC 24 |
| Finished | Oct 12 01:32:42 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8463463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.8463463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.1266786636 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2437891791 ps |
| CPU time | 54.49 seconds |
| Started | Oct 12 01:29:17 PM UTC 24 |
| Finished | Oct 12 01:30:13 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1266786636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_ with_rand_reset.1266786636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_noise_filter.2332035439 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 139316115358 ps |
| CPU time | 58.37 seconds |
| Started | Oct 12 01:29:02 PM UTC 24 |
| Finished | Oct 12 01:30:02 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332035439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2332035439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_rx_oversample.3923539439 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3472977047 ps |
| CPU time | 7.66 seconds |
| Started | Oct 12 01:29:09 PM UTC 24 |
| Finished | Oct 12 01:29:18 PM UTC 24 |
| Peak memory | 207416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923539439 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3923539439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_fifo_reset.1859885179 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 211354422300 ps |
| CPU time | 26.5 seconds |
| Started | Oct 12 01:29:47 PM UTC 24 |
| Finished | Oct 12 01:30:16 PM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859885179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1859885179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_stress_all.22474645 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 686642028855 ps |
| CPU time | 609.84 seconds |
| Started | Oct 12 01:30:06 PM UTC 24 |
| Finished | Oct 12 01:40:24 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22474645 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.22474645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.3322500191 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 14748997 ps |
| CPU time | 0.93 seconds |
| Started | Oct 12 02:07:59 PM UTC 24 |
| Finished | Oct 12 02:08:01 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322500191 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3322500191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.75436432 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 215045268340 ps |
| CPU time | 150.46 seconds |
| Started | Oct 12 01:31:14 PM UTC 24 |
| Finished | Oct 12 01:33:47 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75436432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.75436432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.3875802764 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 126825279801 ps |
| CPU time | 287.34 seconds |
| Started | Oct 12 01:29:17 PM UTC 24 |
| Finished | Oct 12 01:34:08 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875802764 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3875802764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.2299177663 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 4825927454 ps |
| CPU time | 123.24 seconds |
| Started | Oct 12 01:37:35 PM UTC 24 |
| Finished | Oct 12 01:39:41 PM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2299177663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all _with_rand_reset.2299177663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_fifo_reset.793868352 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 34979786547 ps |
| CPU time | 64.95 seconds |
| Started | Oct 12 01:30:29 PM UTC 24 |
| Finished | Oct 12 01:31:35 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793868352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.793868352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_stress_all.1656149931 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 313510861614 ps |
| CPU time | 196.1 seconds |
| Started | Oct 12 01:33:16 PM UTC 24 |
| Finished | Oct 12 01:36:35 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656149931 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1656149931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.81435788 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 163335906658 ps |
| CPU time | 199.52 seconds |
| Started | Oct 12 01:33:06 PM UTC 24 |
| Finished | Oct 12 01:36:28 PM UTC 24 |
| Peak memory | 208808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81435788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.81435788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.1805795786 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 64967577307 ps |
| CPU time | 50.06 seconds |
| Started | Oct 12 01:30:51 PM UTC 24 |
| Finished | Oct 12 01:31:43 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805795786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1805795786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.3852014217 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 287624104 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:07:54 PM UTC 24 |
| Finished | Oct 12 02:07:56 PM UTC 24 |
| Peak memory | 208160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852014217 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3852014217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.2501796 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 99887691326 ps |
| CPU time | 250.43 seconds |
| Started | Oct 12 01:37:00 PM UTC 24 |
| Finished | Oct 12 01:41:14 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM _TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2501796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_stress_all.224091557 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 184747591143 ps |
| CPU time | 162.59 seconds |
| Started | Oct 12 01:32:43 PM UTC 24 |
| Finished | Oct 12 01:35:28 PM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224091557 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.224091557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_alert_test.1762089786 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13221386 ps |
| CPU time | 0.82 seconds |
| Started | Oct 12 01:29:11 PM UTC 24 |
| Finished | Oct 12 01:29:13 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762089786 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1762089786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.90797749 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 160128398593 ps |
| CPU time | 86.95 seconds |
| Started | Oct 12 01:35:34 PM UTC 24 |
| Finished | Oct 12 01:37:03 PM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90797749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.90797749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_fifo_reset.2406898493 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 85124556446 ps |
| CPU time | 71.93 seconds |
| Started | Oct 12 01:34:00 PM UTC 24 |
| Finished | Oct 12 01:35:14 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406898493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2406898493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_fifo_reset.1715576110 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 156697588541 ps |
| CPU time | 279.75 seconds |
| Started | Oct 12 01:29:09 PM UTC 24 |
| Finished | Oct 12 01:33:53 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715576110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1715576110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_fifo_reset.2038608598 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 28189160420 ps |
| CPU time | 49.91 seconds |
| Started | Oct 12 01:31:40 PM UTC 24 |
| Finished | Oct 12 01:32:32 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038608598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2038608598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.3499950221 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 297068840913 ps |
| CPU time | 90.5 seconds |
| Started | Oct 12 01:29:46 PM UTC 24 |
| Finished | Oct 12 01:31:19 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499950221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3499950221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.2980273550 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 35480067 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 02:07:33 PM UTC 24 |
| Finished | Oct 12 02:07:35 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980273550 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2980273550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.4119877594 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1668748417 ps |
| CPU time | 21.93 seconds |
| Started | Oct 12 01:35:49 PM UTC 24 |
| Finished | Oct 12 01:36:12 PM UTC 24 |
| Peak memory | 225340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4119877594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all _with_rand_reset.4119877594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_fifo_full.3775452206 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 227056565380 ps |
| CPU time | 161.67 seconds |
| Started | Oct 12 01:32:48 PM UTC 24 |
| Finished | Oct 12 01:35:32 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775452206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3775452206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_fifo_reset.1982443931 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 31602113014 ps |
| CPU time | 18.28 seconds |
| Started | Oct 12 01:32:54 PM UTC 24 |
| Finished | Oct 12 01:33:14 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982443931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1982443931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_fifo_full.2472184206 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 57334379637 ps |
| CPU time | 50.98 seconds |
| Started | Oct 12 01:29:18 PM UTC 24 |
| Finished | Oct 12 01:30:11 PM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472184206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2472184206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_stress_all.2695254900 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 325053105060 ps |
| CPU time | 327.83 seconds |
| Started | Oct 12 01:36:30 PM UTC 24 |
| Finished | Oct 12 01:42:03 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695254900 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2695254900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_fifo_reset.577809901 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 100642437526 ps |
| CPU time | 76.46 seconds |
| Started | Oct 12 01:39:20 PM UTC 24 |
| Finished | Oct 12 01:40:38 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577809901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.577809901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/151.uart_fifo_reset.3320027035 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 17441688641 ps |
| CPU time | 17.24 seconds |
| Started | Oct 12 02:03:30 PM UTC 24 |
| Finished | Oct 12 02:03:49 PM UTC 24 |
| Peak memory | 208480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320027035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3320027035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/151.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/166.uart_fifo_reset.662992791 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 62971581189 ps |
| CPU time | 125.87 seconds |
| Started | Oct 12 02:04:06 PM UTC 24 |
| Finished | Oct 12 02:06:14 PM UTC 24 |
| Peak memory | 208596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662992791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.662992791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/166.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_intr.3862395068 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 47160475366 ps |
| CPU time | 49.18 seconds |
| Started | Oct 12 01:46:39 PM UTC 24 |
| Finished | Oct 12 01:47:30 PM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862395068 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3862395068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_fifo_reset.3035426992 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 9652172490 ps |
| CPU time | 36.64 seconds |
| Started | Oct 12 01:29:34 PM UTC 24 |
| Finished | Oct 12 01:30:12 PM UTC 24 |
| Peak memory | 208660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035426992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3035426992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.3084840351 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 198444298 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 02:07:30 PM UTC 24 |
| Finished | Oct 12 02:07:32 PM UTC 24 |
| Peak memory | 208452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084840351 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3084840351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_tx_rx.4237774286 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 47500109386 ps |
| CPU time | 22.69 seconds |
| Started | Oct 12 01:29:12 PM UTC 24 |
| Finished | Oct 12 01:29:36 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237774286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.4237774286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.3968557020 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 91657864511 ps |
| CPU time | 131.47 seconds |
| Started | Oct 12 01:37:39 PM UTC 24 |
| Finished | Oct 12 01:39:52 PM UTC 24 |
| Peak memory | 208568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968557020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3968557020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_smoke.3691639655 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6075327901 ps |
| CPU time | 8.82 seconds |
| Started | Oct 12 01:29:07 PM UTC 24 |
| Finished | Oct 12 01:29:17 PM UTC 24 |
| Peak memory | 208352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691639655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3691639655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/150.uart_fifo_reset.3795831174 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 56708070323 ps |
| CPU time | 27.41 seconds |
| Started | Oct 12 02:03:26 PM UTC 24 |
| Finished | Oct 12 02:03:55 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795831174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3795831174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/150.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/197.uart_fifo_reset.3089754414 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 32844607232 ps |
| CPU time | 77.18 seconds |
| Started | Oct 12 02:04:50 PM UTC 24 |
| Finished | Oct 12 02:06:09 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089754414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3089754414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/197.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_fifo_reset.4086480336 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 35039884704 ps |
| CPU time | 41.25 seconds |
| Started | Oct 12 01:29:19 PM UTC 24 |
| Finished | Oct 12 01:30:02 PM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086480336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.4086480336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_tx_rx.2741203470 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 65959687047 ps |
| CPU time | 147.2 seconds |
| Started | Oct 12 01:32:48 PM UTC 24 |
| Finished | Oct 12 01:35:18 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741203470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2741203470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_stress_all.2268594931 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 701559029019 ps |
| CPU time | 230.41 seconds |
| Started | Oct 12 01:34:24 PM UTC 24 |
| Finished | Oct 12 01:38:18 PM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268594931 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2268594931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/161.uart_fifo_reset.637565490 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 86745143387 ps |
| CPU time | 32.94 seconds |
| Started | Oct 12 02:04:00 PM UTC 24 |
| Finished | Oct 12 02:04:34 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637565490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.637565490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/161.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/190.uart_fifo_reset.238811300 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 67671074619 ps |
| CPU time | 41.36 seconds |
| Started | Oct 12 02:04:36 PM UTC 24 |
| Finished | Oct 12 02:05:18 PM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238811300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.238811300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/190.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_fifo_reset.2473636754 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 242227061829 ps |
| CPU time | 108.15 seconds |
| Started | Oct 12 01:44:48 PM UTC 24 |
| Finished | Oct 12 01:46:38 PM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473636754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2473636754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.219826975 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 7758526550 ps |
| CPU time | 43.85 seconds |
| Started | Oct 12 01:32:43 PM UTC 24 |
| Finished | Oct 12 01:33:28 PM UTC 24 |
| Peak memory | 225464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=219826975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all_ with_rand_reset.219826975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_noise_filter.1207156983 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 74827435881 ps |
| CPU time | 66.26 seconds |
| Started | Oct 12 01:34:05 PM UTC 24 |
| Finished | Oct 12 01:35:14 PM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207156983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1207156983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/149.uart_fifo_reset.1808988946 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 82677997639 ps |
| CPU time | 61.9 seconds |
| Started | Oct 12 02:03:25 PM UTC 24 |
| Finished | Oct 12 02:04:29 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808988946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1808988946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/149.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/156.uart_fifo_reset.3616832606 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 29563191562 ps |
| CPU time | 65.42 seconds |
| Started | Oct 12 02:03:51 PM UTC 24 |
| Finished | Oct 12 02:04:58 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616832606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3616832606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/156.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/176.uart_fifo_reset.3697608998 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 41676388751 ps |
| CPU time | 18.28 seconds |
| Started | Oct 12 02:04:15 PM UTC 24 |
| Finished | Oct 12 02:04:35 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697608998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3697608998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/176.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_perf.2910779063 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 10257817685 ps |
| CPU time | 598.83 seconds |
| Started | Oct 12 01:29:27 PM UTC 24 |
| Finished | Oct 12 01:39:33 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910779063 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2910779063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.2590658400 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 168632035127 ps |
| CPU time | 148.48 seconds |
| Started | Oct 12 01:29:09 PM UTC 24 |
| Finished | Oct 12 01:31:40 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590658400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2590658400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_stress_all.4193248395 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 4259344779 ps |
| CPU time | 7 seconds |
| Started | Oct 12 01:33:52 PM UTC 24 |
| Finished | Oct 12 01:34:00 PM UTC 24 |
| Peak memory | 205312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193248395 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.4193248395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.3203800595 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1946701121 ps |
| CPU time | 42.81 seconds |
| Started | Oct 12 01:34:19 PM UTC 24 |
| Finished | Oct 12 01:35:04 PM UTC 24 |
| Peak memory | 219740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3203800595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all _with_rand_reset.3203800595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/138.uart_fifo_reset.3666568311 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 91043873770 ps |
| CPU time | 80.72 seconds |
| Started | Oct 12 02:03:09 PM UTC 24 |
| Finished | Oct 12 02:04:32 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666568311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3666568311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/138.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/163.uart_fifo_reset.2600530751 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 35312215363 ps |
| CPU time | 68.35 seconds |
| Started | Oct 12 02:04:02 PM UTC 24 |
| Finished | Oct 12 02:05:12 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600530751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2600530751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/163.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/221.uart_fifo_reset.2916226798 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 211031666459 ps |
| CPU time | 55.86 seconds |
| Started | Oct 12 02:05:39 PM UTC 24 |
| Finished | Oct 12 02:06:37 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916226798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2916226798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/221.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/227.uart_fifo_reset.4157686024 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 137973688737 ps |
| CPU time | 22.55 seconds |
| Started | Oct 12 02:05:48 PM UTC 24 |
| Finished | Oct 12 02:06:12 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157686024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.4157686024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/227.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/251.uart_fifo_reset.245340728 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 54072327573 ps |
| CPU time | 24.05 seconds |
| Started | Oct 12 02:06:13 PM UTC 24 |
| Finished | Oct 12 02:06:38 PM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245340728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.245340728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/251.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_stress_all.2084981170 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 245946293532 ps |
| CPU time | 347.48 seconds |
| Started | Oct 12 01:43:21 PM UTC 24 |
| Finished | Oct 12 01:49:13 PM UTC 24 |
| Peak memory | 219904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084981170 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2084981170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/70.uart_fifo_reset.110603514 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 98676412105 ps |
| CPU time | 234.8 seconds |
| Started | Oct 12 02:00:23 PM UTC 24 |
| Finished | Oct 12 02:04:21 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110603514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.110603514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/70.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/99.uart_fifo_reset.3466077941 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 240004944568 ps |
| CPU time | 444.61 seconds |
| Started | Oct 12 02:02:04 PM UTC 24 |
| Finished | Oct 12 02:09:34 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466077941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3466077941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/99.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2840574655 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 44888799 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:07:36 PM UTC 24 |
| Finished | Oct 12 02:07:38 PM UTC 24 |
| Peak memory | 207604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840574655 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2840574655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_noise_filter.368286402 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7026184346 ps |
| CPU time | 7.41 seconds |
| Started | Oct 12 01:29:09 PM UTC 24 |
| Finished | Oct 12 01:29:18 PM UTC 24 |
| Peak memory | 205316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368286402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.368286402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/101.uart_fifo_reset.2526168516 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 30074148532 ps |
| CPU time | 70.75 seconds |
| Started | Oct 12 02:02:10 PM UTC 24 |
| Finished | Oct 12 02:03:22 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526168516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2526168516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/101.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/103.uart_fifo_reset.855450167 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 175113667855 ps |
| CPU time | 107.6 seconds |
| Started | Oct 12 02:02:12 PM UTC 24 |
| Finished | Oct 12 02:04:02 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855450167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.855450167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/103.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/105.uart_fifo_reset.1913790607 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 87200986843 ps |
| CPU time | 65.31 seconds |
| Started | Oct 12 02:02:15 PM UTC 24 |
| Finished | Oct 12 02:03:22 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913790607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1913790607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/105.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/124.uart_fifo_reset.1297060715 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 87236503416 ps |
| CPU time | 77.48 seconds |
| Started | Oct 12 02:02:55 PM UTC 24 |
| Finished | Oct 12 02:04:14 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297060715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1297060715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/124.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/126.uart_fifo_reset.1403972485 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 94468290132 ps |
| CPU time | 23.1 seconds |
| Started | Oct 12 02:02:57 PM UTC 24 |
| Finished | Oct 12 02:03:21 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403972485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1403972485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/126.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/160.uart_fifo_reset.149357554 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 49228169420 ps |
| CPU time | 35.42 seconds |
| Started | Oct 12 02:04:00 PM UTC 24 |
| Finished | Oct 12 02:04:37 PM UTC 24 |
| Peak memory | 208740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149357554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.149357554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/160.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/165.uart_fifo_reset.3226457278 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 151527604953 ps |
| CPU time | 37.52 seconds |
| Started | Oct 12 02:04:05 PM UTC 24 |
| Finished | Oct 12 02:04:43 PM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226457278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3226457278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/165.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/172.uart_fifo_reset.2913794692 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 34708286801 ps |
| CPU time | 16.86 seconds |
| Started | Oct 12 02:04:14 PM UTC 24 |
| Finished | Oct 12 02:04:32 PM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913794692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2913794692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/172.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/195.uart_fifo_reset.3484759799 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 101875044677 ps |
| CPU time | 50.52 seconds |
| Started | Oct 12 02:04:46 PM UTC 24 |
| Finished | Oct 12 02:05:38 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484759799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3484759799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/195.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_stress_all.2687480261 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 244768536214 ps |
| CPU time | 201.95 seconds |
| Started | Oct 12 01:29:17 PM UTC 24 |
| Finished | Oct 12 01:32:42 PM UTC 24 |
| Peak memory | 217848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687480261 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2687480261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/213.uart_fifo_reset.3327322569 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 82163790866 ps |
| CPU time | 40.92 seconds |
| Started | Oct 12 02:05:20 PM UTC 24 |
| Finished | Oct 12 02:06:02 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327322569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3327322569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/213.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/215.uart_fifo_reset.2077878459 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 22595221824 ps |
| CPU time | 30.92 seconds |
| Started | Oct 12 02:05:24 PM UTC 24 |
| Finished | Oct 12 02:05:56 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077878459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2077878459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/215.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/240.uart_fifo_reset.376310776 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 101485844208 ps |
| CPU time | 48.29 seconds |
| Started | Oct 12 02:05:59 PM UTC 24 |
| Finished | Oct 12 02:06:49 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376310776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.376310776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/240.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/276.uart_fifo_reset.4125939000 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 26637549500 ps |
| CPU time | 57.93 seconds |
| Started | Oct 12 02:06:53 PM UTC 24 |
| Finished | Oct 12 02:07:53 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125939000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.4125939000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/276.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/53.uart_fifo_reset.457165970 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 66770635733 ps |
| CPU time | 187.62 seconds |
| Started | Oct 12 01:58:59 PM UTC 24 |
| Finished | Oct 12 02:02:09 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457165970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.457165970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/53.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.2632253707 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 13472867 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 02:07:34 PM UTC 24 |
| Finished | Oct 12 02:07:36 PM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632253707 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2632253707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.1928376366 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 35261563 ps |
| CPU time | 2.05 seconds |
| Started | Oct 12 02:07:33 PM UTC 24 |
| Finished | Oct 12 02:07:36 PM UTC 24 |
| Peak memory | 207544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928376366 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1928376366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.955120868 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 47219622 ps |
| CPU time | 0.88 seconds |
| Started | Oct 12 02:07:33 PM UTC 24 |
| Finished | Oct 12 02:07:35 PM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955120868 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.955120868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1889705283 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 57571409 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:07:35 PM UTC 24 |
| Finished | Oct 12 02:07:37 PM UTC 24 |
| Peak memory | 206432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1889705283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_r eset.1889705283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.3044844188 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 77892184 ps |
| CPU time | 0.87 seconds |
| Started | Oct 12 02:07:32 PM UTC 24 |
| Finished | Oct 12 02:07:34 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044844188 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3044844188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.2165877866 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 16573648 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:07:34 PM UTC 24 |
| Finished | Oct 12 02:07:36 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165877866 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.2165877866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.983829328 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 37357385 ps |
| CPU time | 2.75 seconds |
| Started | Oct 12 02:07:29 PM UTC 24 |
| Finished | Oct 12 02:07:33 PM UTC 24 |
| Peak memory | 208940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983829328 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.983829328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.2692253460 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 21346707 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 02:07:37 PM UTC 24 |
| Finished | Oct 12 02:07:39 PM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692253460 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2692253460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3213020821 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 116260298 ps |
| CPU time | 3.17 seconds |
| Started | Oct 12 02:07:37 PM UTC 24 |
| Finished | Oct 12 02:07:41 PM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213020821 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3213020821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3265081677 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 35972537 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 02:07:37 PM UTC 24 |
| Finished | Oct 12 02:07:39 PM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265081677 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3265081677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3790604405 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 15128730 ps |
| CPU time | 0.94 seconds |
| Started | Oct 12 02:07:38 PM UTC 24 |
| Finished | Oct 12 02:07:40 PM UTC 24 |
| Peak memory | 206432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3790604405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_r eset.3790604405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.3611930461 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 15567772 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:07:37 PM UTC 24 |
| Finished | Oct 12 02:07:39 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611930461 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3611930461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.3340505520 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 48466118 ps |
| CPU time | 0.83 seconds |
| Started | Oct 12 02:07:37 PM UTC 24 |
| Finished | Oct 12 02:07:39 PM UTC 24 |
| Peak memory | 204388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340505520 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3340505520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.769599274 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 15923754 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:07:38 PM UTC 24 |
| Finished | Oct 12 02:07:40 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769599274 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.769599274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1455409914 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 52428588 ps |
| CPU time | 2.08 seconds |
| Started | Oct 12 02:07:36 PM UTC 24 |
| Finished | Oct 12 02:07:39 PM UTC 24 |
| Peak memory | 209020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455409914 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1455409914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.899906559 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 24798788 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:07:57 PM UTC 24 |
| Finished | Oct 12 02:07:59 PM UTC 24 |
| Peak memory | 206312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=899906559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_r eset.899906559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.144845319 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 14410430 ps |
| CPU time | 0.7 seconds |
| Started | Oct 12 02:07:56 PM UTC 24 |
| Finished | Oct 12 02:07:58 PM UTC 24 |
| Peak memory | 206308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144845319 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.144845319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.1482244979 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 20119436 ps |
| CPU time | 0.68 seconds |
| Started | Oct 12 02:07:56 PM UTC 24 |
| Finished | Oct 12 02:07:58 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482244979 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1482244979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.1605271345 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 56640039 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 02:07:56 PM UTC 24 |
| Finished | Oct 12 02:07:58 PM UTC 24 |
| Peak memory | 206372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605271345 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.1605271345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1713699915 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 258893141 ps |
| CPU time | 1.84 seconds |
| Started | Oct 12 02:07:56 PM UTC 24 |
| Finished | Oct 12 02:07:59 PM UTC 24 |
| Peak memory | 209124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713699915 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1713699915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.1102165087 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 120742952 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:07:56 PM UTC 24 |
| Finished | Oct 12 02:07:59 PM UTC 24 |
| Peak memory | 207596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102165087 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1102165087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1733439680 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 84555924 ps |
| CPU time | 0.72 seconds |
| Started | Oct 12 02:07:59 PM UTC 24 |
| Finished | Oct 12 02:08:01 PM UTC 24 |
| Peak memory | 206372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1733439680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_ reset.1733439680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.3264247910 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 24644705 ps |
| CPU time | 0.76 seconds |
| Started | Oct 12 02:07:59 PM UTC 24 |
| Finished | Oct 12 02:08:01 PM UTC 24 |
| Peak memory | 206304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264247910 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3264247910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.3043855303 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 65837758 ps |
| CPU time | 0.69 seconds |
| Started | Oct 12 02:07:57 PM UTC 24 |
| Finished | Oct 12 02:07:58 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043855303 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3043855303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1287062189 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 256114196 ps |
| CPU time | 0.79 seconds |
| Started | Oct 12 02:07:59 PM UTC 24 |
| Finished | Oct 12 02:08:01 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287062189 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.1287062189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2835081882 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 383028112 ps |
| CPU time | 1.88 seconds |
| Started | Oct 12 02:07:57 PM UTC 24 |
| Finished | Oct 12 02:07:59 PM UTC 24 |
| Peak memory | 209132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835081882 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2835081882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.536100927 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 69580118 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:07:57 PM UTC 24 |
| Finished | Oct 12 02:07:59 PM UTC 24 |
| Peak memory | 207068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536100927 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.536100927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2719062045 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 68999126 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 02:07:59 PM UTC 24 |
| Finished | Oct 12 02:08:01 PM UTC 24 |
| Peak memory | 207748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2719062045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_ reset.2719062045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.2503933268 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 37765962 ps |
| CPU time | 0.72 seconds |
| Started | Oct 12 02:07:59 PM UTC 24 |
| Finished | Oct 12 02:08:01 PM UTC 24 |
| Peak memory | 204320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503933268 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2503933268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.2986874603 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 16966557 ps |
| CPU time | 0.9 seconds |
| Started | Oct 12 02:07:59 PM UTC 24 |
| Finished | Oct 12 02:08:01 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986874603 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.2986874603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.351281829 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 98096721 ps |
| CPU time | 2.51 seconds |
| Started | Oct 12 02:07:59 PM UTC 24 |
| Finished | Oct 12 02:08:03 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351281829 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.351281829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.3466290452 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 412648995 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:07:59 PM UTC 24 |
| Finished | Oct 12 02:08:02 PM UTC 24 |
| Peak memory | 207572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466290452 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3466290452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.302521535 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 25464303 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 207136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=302521535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_r eset.302521535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.1422877903 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 36456894 ps |
| CPU time | 0.74 seconds |
| Started | Oct 12 02:08:00 PM UTC 24 |
| Finished | Oct 12 02:08:01 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422877903 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1422877903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.2660462562 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 22522439 ps |
| CPU time | 0.66 seconds |
| Started | Oct 12 02:07:59 PM UTC 24 |
| Finished | Oct 12 02:08:01 PM UTC 24 |
| Peak memory | 204444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660462562 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2660462562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2860650733 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 18651969 ps |
| CPU time | 0.68 seconds |
| Started | Oct 12 02:08:00 PM UTC 24 |
| Finished | Oct 12 02:08:01 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860650733 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.2860650733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1135552149 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 33170384 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 02:07:59 PM UTC 24 |
| Finished | Oct 12 02:08:02 PM UTC 24 |
| Peak memory | 209076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135552149 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1135552149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.2369508390 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 48656887 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 02:07:59 PM UTC 24 |
| Finished | Oct 12 02:08:01 PM UTC 24 |
| Peak memory | 207824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369508390 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2369508390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4281150888 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 18345986 ps |
| CPU time | 0.65 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 206372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4281150888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_ reset.4281150888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.1210251200 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 22639183 ps |
| CPU time | 0.68 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210251200 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1210251200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.2288747743 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 16718662 ps |
| CPU time | 0.67 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:04 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288747743 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2288747743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1909957392 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 32128222 ps |
| CPU time | 0.77 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909957392 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.1909957392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.460864832 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 505662480 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 209016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460864832 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.460864832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3072621589 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 315437026 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 207924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072621589 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3072621589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3616665106 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 55481385 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 206352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3616665106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_ reset.3616665106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.650027420 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 35238793 ps |
| CPU time | 0.82 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650027420 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.650027420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.3067586021 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 108734954 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067586021 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3067586021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2039182067 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 44240879 ps |
| CPU time | 0.71 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039182067 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.2039182067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.2073989537 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 182316284 ps |
| CPU time | 1.94 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:06 PM UTC 24 |
| Peak memory | 209136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073989537 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2073989537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.3051005735 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 75387038 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 207860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051005735 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3051005735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3164805583 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 233619656 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:06 PM UTC 24 |
| Peak memory | 207484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3164805583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_ reset.3164805583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.3359177756 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 24650308 ps |
| CPU time | 0.67 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 204256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359177756 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3359177756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.563430794 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 55270690 ps |
| CPU time | 0.66 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563430794 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.563430794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1946511865 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 41249176 ps |
| CPU time | 0.98 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:05 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946511865 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.1946511865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.274645192 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 63207108 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:06 PM UTC 24 |
| Peak memory | 209076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274645192 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.274645192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.941780210 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 348419981 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:06 PM UTC 24 |
| Peak memory | 207616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941780210 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.941780210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4264868096 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 199467469 ps |
| CPU time | 0.78 seconds |
| Started | Oct 12 02:08:06 PM UTC 24 |
| Finished | Oct 12 02:08:08 PM UTC 24 |
| Peak memory | 206692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4264868096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_ reset.4264868096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2691274961 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 15199958 ps |
| CPU time | 0.72 seconds |
| Started | Oct 12 02:08:06 PM UTC 24 |
| Finished | Oct 12 02:08:08 PM UTC 24 |
| Peak memory | 203984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691274961 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2691274961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.3416573891 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 31688305 ps |
| CPU time | 0.62 seconds |
| Started | Oct 12 02:08:06 PM UTC 24 |
| Finished | Oct 12 02:08:08 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416573891 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3416573891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.3091968705 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 152264790 ps |
| CPU time | 0.76 seconds |
| Started | Oct 12 02:08:06 PM UTC 24 |
| Finished | Oct 12 02:08:08 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091968705 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.3091968705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.3296615705 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 54376017 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:08:03 PM UTC 24 |
| Finished | Oct 12 02:08:06 PM UTC 24 |
| Peak memory | 209180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296615705 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3296615705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3397094399 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 288338919 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:08:06 PM UTC 24 |
| Finished | Oct 12 02:08:09 PM UTC 24 |
| Peak memory | 207260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397094399 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3397094399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2304677942 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 71478496 ps |
| CPU time | 0.74 seconds |
| Started | Oct 12 02:08:07 PM UTC 24 |
| Finished | Oct 12 02:08:08 PM UTC 24 |
| Peak memory | 206372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2304677942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_ reset.2304677942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.718344352 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 32476279 ps |
| CPU time | 0.68 seconds |
| Started | Oct 12 02:08:06 PM UTC 24 |
| Finished | Oct 12 02:08:08 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718344352 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.718344352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.3165424848 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 43779335 ps |
| CPU time | 0.77 seconds |
| Started | Oct 12 02:08:06 PM UTC 24 |
| Finished | Oct 12 02:08:08 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165424848 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3165424848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.1224083708 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 43748771 ps |
| CPU time | 0.77 seconds |
| Started | Oct 12 02:08:07 PM UTC 24 |
| Finished | Oct 12 02:08:08 PM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224083708 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.1224083708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.1363476358 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 74232445 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 02:08:06 PM UTC 24 |
| Finished | Oct 12 02:08:08 PM UTC 24 |
| Peak memory | 207748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363476358 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1363476358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.85944000 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 133416563 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:08:06 PM UTC 24 |
| Finished | Oct 12 02:08:09 PM UTC 24 |
| Peak memory | 208104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85944000 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.85944000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.192362029 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 211798277 ps |
| CPU time | 0.68 seconds |
| Started | Oct 12 02:08:11 PM UTC 24 |
| Finished | Oct 12 02:08:13 PM UTC 24 |
| Peak memory | 205508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=192362029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_r eset.192362029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.982987409 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 13008742 ps |
| CPU time | 0.62 seconds |
| Started | Oct 12 02:08:11 PM UTC 24 |
| Finished | Oct 12 02:08:13 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982987409 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.982987409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.2948271494 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 53213501 ps |
| CPU time | 0.58 seconds |
| Started | Oct 12 02:08:07 PM UTC 24 |
| Finished | Oct 12 02:08:09 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948271494 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2948271494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2117431134 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 116105710 ps |
| CPU time | 0.82 seconds |
| Started | Oct 12 02:08:11 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117431134 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.2117431134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.1365898085 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 172304217 ps |
| CPU time | 1.81 seconds |
| Started | Oct 12 02:08:07 PM UTC 24 |
| Finished | Oct 12 02:08:10 PM UTC 24 |
| Peak memory | 209132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365898085 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1365898085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.3893640458 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 145945550 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:08:07 PM UTC 24 |
| Finished | Oct 12 02:08:09 PM UTC 24 |
| Peak memory | 207860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893640458 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3893640458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3175953822 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 48976068 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:07:41 PM UTC 24 |
| Finished | Oct 12 02:07:43 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175953822 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3175953822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.3458009527 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 535432407 ps |
| CPU time | 2.39 seconds |
| Started | Oct 12 02:07:41 PM UTC 24 |
| Finished | Oct 12 02:07:44 PM UTC 24 |
| Peak memory | 207556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458009527 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3458009527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.630438898 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 31884291 ps |
| CPU time | 0.88 seconds |
| Started | Oct 12 02:07:40 PM UTC 24 |
| Finished | Oct 12 02:07:41 PM UTC 24 |
| Peak memory | 204240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630438898 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.630438898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1892578584 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 58043636 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:07:41 PM UTC 24 |
| Finished | Oct 12 02:07:43 PM UTC 24 |
| Peak memory | 207752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1892578584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_r eset.1892578584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3134913079 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 15876852 ps |
| CPU time | 0.93 seconds |
| Started | Oct 12 02:07:40 PM UTC 24 |
| Finished | Oct 12 02:07:42 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134913079 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3134913079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.1719035597 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 18710172 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 02:07:40 PM UTC 24 |
| Finished | Oct 12 02:07:41 PM UTC 24 |
| Peak memory | 204388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719035597 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1719035597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.3559456919 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 41373185 ps |
| CPU time | 0.9 seconds |
| Started | Oct 12 02:07:41 PM UTC 24 |
| Finished | Oct 12 02:07:43 PM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559456919 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.3559456919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.560977436 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 113289042 ps |
| CPU time | 3.09 seconds |
| Started | Oct 12 02:07:39 PM UTC 24 |
| Finished | Oct 12 02:07:43 PM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560977436 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.560977436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.3447143528 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 184799394 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 02:07:39 PM UTC 24 |
| Finished | Oct 12 02:07:43 PM UTC 24 |
| Peak memory | 208352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447143528 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3447143528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2623722874 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 14717958 ps |
| CPU time | 0.65 seconds |
| Started | Oct 12 02:08:11 PM UTC 24 |
| Finished | Oct 12 02:08:13 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623722874 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2623722874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.475701270 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 32082125 ps |
| CPU time | 0.58 seconds |
| Started | Oct 12 02:08:11 PM UTC 24 |
| Finished | Oct 12 02:08:13 PM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475701270 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.475701270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.866629871 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 18491821 ps |
| CPU time | 0.59 seconds |
| Started | Oct 12 02:08:11 PM UTC 24 |
| Finished | Oct 12 02:08:13 PM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866629871 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.866629871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.2167606655 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 15022346 ps |
| CPU time | 0.63 seconds |
| Started | Oct 12 02:08:11 PM UTC 24 |
| Finished | Oct 12 02:08:13 PM UTC 24 |
| Peak memory | 203496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167606655 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2167606655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3233102416 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 23655757 ps |
| CPU time | 0.54 seconds |
| Started | Oct 12 02:08:11 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233102416 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3233102416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.965465337 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 35895859 ps |
| CPU time | 0.58 seconds |
| Started | Oct 12 02:08:11 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965465337 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.965465337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.1036349266 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 55121438 ps |
| CPU time | 0.62 seconds |
| Started | Oct 12 02:08:11 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036349266 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1036349266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.3259958006 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 44613525 ps |
| CPU time | 0.57 seconds |
| Started | Oct 12 02:08:11 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259958006 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3259958006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.3993387357 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 26265602 ps |
| CPU time | 0.54 seconds |
| Started | Oct 12 02:08:11 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993387357 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3993387357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2351038997 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 28235012 ps |
| CPU time | 0.59 seconds |
| Started | Oct 12 02:08:11 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351038997 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2351038997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.568300069 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 116231569 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:07:44 PM UTC 24 |
| Finished | Oct 12 02:07:46 PM UTC 24 |
| Peak memory | 206312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568300069 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.568300069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.545352369 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 230437185 ps |
| CPU time | 3.11 seconds |
| Started | Oct 12 02:07:44 PM UTC 24 |
| Finished | Oct 12 02:07:48 PM UTC 24 |
| Peak memory | 207492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545352369 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.545352369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.806436234 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 40296818 ps |
| CPU time | 0.7 seconds |
| Started | Oct 12 02:07:42 PM UTC 24 |
| Finished | Oct 12 02:07:44 PM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806436234 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.806436234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3971492129 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 109301244 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:07:45 PM UTC 24 |
| Finished | Oct 12 02:07:47 PM UTC 24 |
| Peak memory | 207752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3971492129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_r eset.3971492129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.125077685 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 30529745 ps |
| CPU time | 0.78 seconds |
| Started | Oct 12 02:07:44 PM UTC 24 |
| Finished | Oct 12 02:07:45 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125077685 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.125077685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.1938496104 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 14708454 ps |
| CPU time | 0.9 seconds |
| Started | Oct 12 02:07:42 PM UTC 24 |
| Finished | Oct 12 02:07:44 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938496104 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1938496104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.1362033776 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 18174193 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:07:44 PM UTC 24 |
| Finished | Oct 12 02:07:46 PM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362033776 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.1362033776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.3279484759 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 74209736 ps |
| CPU time | 2.44 seconds |
| Started | Oct 12 02:07:42 PM UTC 24 |
| Finished | Oct 12 02:07:46 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279484759 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3279484759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.358301678 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 91372827 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 02:07:42 PM UTC 24 |
| Finished | Oct 12 02:07:45 PM UTC 24 |
| Peak memory | 207524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358301678 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.358301678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1097449041 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 32889511 ps |
| CPU time | 0.61 seconds |
| Started | Oct 12 02:08:12 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097449041 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1097449041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.2807994452 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 65222987 ps |
| CPU time | 0.58 seconds |
| Started | Oct 12 02:08:12 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807994452 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2807994452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.2165962056 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 37069183 ps |
| CPU time | 0.69 seconds |
| Started | Oct 12 02:08:12 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165962056 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2165962056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.3030968462 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 40671952 ps |
| CPU time | 0.61 seconds |
| Started | Oct 12 02:08:12 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030968462 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3030968462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.4050267931 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 22178662 ps |
| CPU time | 0.66 seconds |
| Started | Oct 12 02:08:12 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050267931 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.4050267931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.1451160197 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 46699883 ps |
| CPU time | 0.61 seconds |
| Started | Oct 12 02:08:12 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451160197 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1451160197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.91589531 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 12536031 ps |
| CPU time | 0.58 seconds |
| Started | Oct 12 02:08:12 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91589531 -assert nopostproc +UVM_TESTNAME=uart_base_te st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.91589531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2260005801 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 78386713 ps |
| CPU time | 0.55 seconds |
| Started | Oct 12 02:08:12 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260005801 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2260005801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3265733552 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 155555096 ps |
| CPU time | 0.61 seconds |
| Started | Oct 12 02:08:12 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265733552 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3265733552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.2777274914 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 41795530 ps |
| CPU time | 0.58 seconds |
| Started | Oct 12 02:08:12 PM UTC 24 |
| Finished | Oct 12 02:08:14 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777274914 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2777274914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.2492566652 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 14448740 ps |
| CPU time | 0.92 seconds |
| Started | Oct 12 02:07:47 PM UTC 24 |
| Finished | Oct 12 02:07:49 PM UTC 24 |
| Peak memory | 204388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492566652 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2492566652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.3750737589 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 190217405 ps |
| CPU time | 2.83 seconds |
| Started | Oct 12 02:07:47 PM UTC 24 |
| Finished | Oct 12 02:07:51 PM UTC 24 |
| Peak memory | 207428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750737589 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3750737589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.255854582 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 45839544 ps |
| CPU time | 0.87 seconds |
| Started | Oct 12 02:07:45 PM UTC 24 |
| Finished | Oct 12 02:07:47 PM UTC 24 |
| Peak memory | 204268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255854582 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.255854582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1204061556 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 41445621 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 02:07:47 PM UTC 24 |
| Finished | Oct 12 02:07:49 PM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1204061556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_r eset.1204061556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.2393858980 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 50177949 ps |
| CPU time | 0.92 seconds |
| Started | Oct 12 02:07:47 PM UTC 24 |
| Finished | Oct 12 02:07:49 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393858980 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2393858980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.4061088170 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 14001772 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 02:07:45 PM UTC 24 |
| Finished | Oct 12 02:07:47 PM UTC 24 |
| Peak memory | 204448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061088170 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4061088170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.1604424081 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 68755232 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:07:47 PM UTC 24 |
| Finished | Oct 12 02:07:49 PM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604424081 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.1604424081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.3740218098 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 428516699 ps |
| CPU time | 2.44 seconds |
| Started | Oct 12 02:07:45 PM UTC 24 |
| Finished | Oct 12 02:07:49 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740218098 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3740218098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.1442295392 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 79822349 ps |
| CPU time | 1.95 seconds |
| Started | Oct 12 02:07:45 PM UTC 24 |
| Finished | Oct 12 02:07:48 PM UTC 24 |
| Peak memory | 209076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442295392 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1442295392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1332529586 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 16705246 ps |
| CPU time | 0.6 seconds |
| Started | Oct 12 02:08:14 PM UTC 24 |
| Finished | Oct 12 02:08:16 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332529586 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1332529586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.2718720078 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 106468386 ps |
| CPU time | 0.58 seconds |
| Started | Oct 12 02:08:14 PM UTC 24 |
| Finished | Oct 12 02:08:16 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718720078 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2718720078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.3792637927 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 33745438 ps |
| CPU time | 0.64 seconds |
| Started | Oct 12 02:08:14 PM UTC 24 |
| Finished | Oct 12 02:08:16 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792637927 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3792637927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.2408518042 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 14598024 ps |
| CPU time | 0.63 seconds |
| Started | Oct 12 02:08:14 PM UTC 24 |
| Finished | Oct 12 02:08:16 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408518042 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2408518042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.823704779 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 47450833 ps |
| CPU time | 0.7 seconds |
| Started | Oct 12 02:08:14 PM UTC 24 |
| Finished | Oct 12 02:08:16 PM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823704779 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.823704779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.3205712704 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 29579905 ps |
| CPU time | 0.63 seconds |
| Started | Oct 12 02:08:20 PM UTC 24 |
| Finished | Oct 12 02:08:22 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205712704 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3205712704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.1437350631 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 14746470 ps |
| CPU time | 0.63 seconds |
| Started | Oct 12 02:08:20 PM UTC 24 |
| Finished | Oct 12 02:08:22 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437350631 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1437350631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.2447166200 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 25825994 ps |
| CPU time | 0.55 seconds |
| Started | Oct 12 02:08:20 PM UTC 24 |
| Finished | Oct 12 02:08:22 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447166200 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2447166200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2090322514 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 104183984 ps |
| CPU time | 0.59 seconds |
| Started | Oct 12 02:08:20 PM UTC 24 |
| Finished | Oct 12 02:08:22 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090322514 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2090322514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.2057829514 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 39593093 ps |
| CPU time | 0.64 seconds |
| Started | Oct 12 02:08:21 PM UTC 24 |
| Finished | Oct 12 02:08:22 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057829514 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2057829514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1433258363 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 19431539 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 02:07:49 PM UTC 24 |
| Finished | Oct 12 02:07:51 PM UTC 24 |
| Peak memory | 206432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1433258363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_r eset.1433258363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.3302234372 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 48865376 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 02:07:49 PM UTC 24 |
| Finished | Oct 12 02:07:50 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302234372 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3302234372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.1543072978 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 12555913 ps |
| CPU time | 0.78 seconds |
| Started | Oct 12 02:07:49 PM UTC 24 |
| Finished | Oct 12 02:07:50 PM UTC 24 |
| Peak memory | 204448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543072978 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1543072978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.1580064015 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 102471647 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:07:49 PM UTC 24 |
| Finished | Oct 12 02:07:51 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580064015 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.1580064015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.3627116307 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 79602676 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 02:07:48 PM UTC 24 |
| Finished | Oct 12 02:07:52 PM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627116307 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3627116307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.2684708774 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 542005510 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 02:07:48 PM UTC 24 |
| Finished | Oct 12 02:07:51 PM UTC 24 |
| Peak memory | 207616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684708774 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2684708774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3010261333 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 31684446 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:07:51 PM UTC 24 |
| Finished | Oct 12 02:07:53 PM UTC 24 |
| Peak memory | 207924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3010261333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_r eset.3010261333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.867114483 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 52013086 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 02:07:51 PM UTC 24 |
| Finished | Oct 12 02:07:52 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867114483 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.867114483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.3258781349 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 19522570 ps |
| CPU time | 0.81 seconds |
| Started | Oct 12 02:07:51 PM UTC 24 |
| Finished | Oct 12 02:07:52 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258781349 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3258781349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.3452124526 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 46899569 ps |
| CPU time | 0.93 seconds |
| Started | Oct 12 02:07:51 PM UTC 24 |
| Finished | Oct 12 02:07:53 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452124526 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.3452124526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3907462173 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 56827571 ps |
| CPU time | 1.94 seconds |
| Started | Oct 12 02:07:50 PM UTC 24 |
| Finished | Oct 12 02:07:53 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907462173 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3907462173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.3993309103 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 126383769 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:07:50 PM UTC 24 |
| Finished | Oct 12 02:07:53 PM UTC 24 |
| Peak memory | 206972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993309103 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3993309103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.272003191 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 67330599 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:07:53 PM UTC 24 |
| Finished | Oct 12 02:07:55 PM UTC 24 |
| Peak memory | 207924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=272003191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_re set.272003191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.1556516905 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 12741186 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 02:07:53 PM UTC 24 |
| Finished | Oct 12 02:07:55 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556516905 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1556516905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.2563269336 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 45954074 ps |
| CPU time | 0.68 seconds |
| Started | Oct 12 02:07:53 PM UTC 24 |
| Finished | Oct 12 02:07:55 PM UTC 24 |
| Peak memory | 204388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563269336 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2563269336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.4149522763 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 49472684 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 02:07:53 PM UTC 24 |
| Finished | Oct 12 02:07:55 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149522763 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.4149522763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.221281681 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 223505192 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:07:51 PM UTC 24 |
| Finished | Oct 12 02:07:53 PM UTC 24 |
| Peak memory | 207748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221281681 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.221281681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.4193757747 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 188526725 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 02:07:51 PM UTC 24 |
| Finished | Oct 12 02:07:54 PM UTC 24 |
| Peak memory | 206864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193757747 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.4193757747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2962722683 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 80075087 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 02:07:53 PM UTC 24 |
| Finished | Oct 12 02:07:55 PM UTC 24 |
| Peak memory | 207216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2962722683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_r eset.2962722683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.2720405724 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 101346702 ps |
| CPU time | 0.79 seconds |
| Started | Oct 12 02:07:53 PM UTC 24 |
| Finished | Oct 12 02:07:55 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720405724 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2720405724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.1628317649 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 39773572 ps |
| CPU time | 0.8 seconds |
| Started | Oct 12 02:07:53 PM UTC 24 |
| Finished | Oct 12 02:07:55 PM UTC 24 |
| Peak memory | 204448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628317649 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1628317649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.2854380023 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 26058010 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:07:53 PM UTC 24 |
| Finished | Oct 12 02:07:56 PM UTC 24 |
| Peak memory | 202140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854380023 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.2854380023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.432564294 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 266101855 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:07:53 PM UTC 24 |
| Finished | Oct 12 02:07:56 PM UTC 24 |
| Peak memory | 209180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432564294 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.432564294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3447056505 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 74665576 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:07:53 PM UTC 24 |
| Finished | Oct 12 02:07:56 PM UTC 24 |
| Peak memory | 207956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447056505 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3447056505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1367956408 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 94267646 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:07:56 PM UTC 24 |
| Finished | Oct 12 02:07:59 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1367956408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_r eset.1367956408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.2961546859 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 18150668 ps |
| CPU time | 0.73 seconds |
| Started | Oct 12 02:07:56 PM UTC 24 |
| Finished | Oct 12 02:07:58 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961546859 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2961546859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.1832615202 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 27400619 ps |
| CPU time | 0.73 seconds |
| Started | Oct 12 02:07:56 PM UTC 24 |
| Finished | Oct 12 02:07:58 PM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832615202 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1832615202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.708418240 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 21891500 ps |
| CPU time | 0.83 seconds |
| Started | Oct 12 02:07:56 PM UTC 24 |
| Finished | Oct 12 02:07:58 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708418240 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.708418240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.3339624471 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 35488827 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:07:54 PM UTC 24 |
| Finished | Oct 12 02:07:56 PM UTC 24 |
| Peak memory | 208376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339624471 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3339624471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_alert_test.2111401700 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 31466542 ps |
| CPU time | 0.64 seconds |
| Started | Oct 12 01:29:07 PM UTC 24 |
| Finished | Oct 12 01:29:08 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111401700 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2111401700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_fifo_full.423623438 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 74743028674 ps |
| CPU time | 262.67 seconds |
| Started | Oct 12 01:29:01 PM UTC 24 |
| Finished | Oct 12 01:33:27 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423623438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.423623438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2000730686 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 18250731784 ps |
| CPU time | 14.11 seconds |
| Started | Oct 12 01:29:01 PM UTC 24 |
| Finished | Oct 12 01:29:16 PM UTC 24 |
| Peak memory | 208628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000730686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2000730686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_intr.1665387511 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13195122461 ps |
| CPU time | 13.66 seconds |
| Started | Oct 12 01:29:02 PM UTC 24 |
| Finished | Oct 12 01:29:17 PM UTC 24 |
| Peak memory | 207228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665387511 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1665387511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_loopback.2282149727 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 9911277821 ps |
| CPU time | 10.88 seconds |
| Started | Oct 12 01:29:04 PM UTC 24 |
| Finished | Oct 12 01:29:16 PM UTC 24 |
| Peak memory | 208284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282149727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2282149727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_perf.446903854 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 11045738168 ps |
| CPU time | 165.46 seconds |
| Started | Oct 12 01:29:04 PM UTC 24 |
| Finished | Oct 12 01:31:52 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446903854 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.446903854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_rx_oversample.2491185498 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3251539486 ps |
| CPU time | 2.83 seconds |
| Started | Oct 12 01:29:02 PM UTC 24 |
| Finished | Oct 12 01:29:06 PM UTC 24 |
| Peak memory | 207492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491185498 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2491185498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.452125614 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 204819684111 ps |
| CPU time | 93.46 seconds |
| Started | Oct 12 01:29:04 PM UTC 24 |
| Finished | Oct 12 01:30:40 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452125614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.452125614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.2283069988 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 43042496825 ps |
| CPU time | 34.32 seconds |
| Started | Oct 12 01:29:03 PM UTC 24 |
| Finished | Oct 12 01:29:39 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283069988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2283069988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_sec_cm.420097880 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 153452273 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 01:29:07 PM UTC 24 |
| Finished | Oct 12 01:29:08 PM UTC 24 |
| Peak memory | 239376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420097880 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.420097880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_smoke.1555349923 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11056038158 ps |
| CPU time | 15.52 seconds |
| Started | Oct 12 01:29:01 PM UTC 24 |
| Finished | Oct 12 01:29:17 PM UTC 24 |
| Peak memory | 208500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555349923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1555349923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.1329028583 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1383945866 ps |
| CPU time | 37.36 seconds |
| Started | Oct 12 01:29:04 PM UTC 24 |
| Finished | Oct 12 01:29:43 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1329028583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_ with_rand_reset.1329028583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.2993165467 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 879738061 ps |
| CPU time | 2.79 seconds |
| Started | Oct 12 01:29:04 PM UTC 24 |
| Finished | Oct 12 01:29:08 PM UTC 24 |
| Peak memory | 207852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993165467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2993165467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_tx_rx.1393250158 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 56146255144 ps |
| CPU time | 43.46 seconds |
| Started | Oct 12 01:29:01 PM UTC 24 |
| Finished | Oct 12 01:29:46 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393250158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1393250158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/0.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_fifo_full.1396988775 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 97402155784 ps |
| CPU time | 74.99 seconds |
| Started | Oct 12 01:29:09 PM UTC 24 |
| Finished | Oct 12 01:30:26 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396988775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1396988775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.2479321724 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 52447220287 ps |
| CPU time | 41.35 seconds |
| Started | Oct 12 01:29:09 PM UTC 24 |
| Finished | Oct 12 01:29:52 PM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479321724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2479321724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_intr.2256358058 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 26640065747 ps |
| CPU time | 58.1 seconds |
| Started | Oct 12 01:29:09 PM UTC 24 |
| Finished | Oct 12 01:30:09 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256358058 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2256358058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.4252430169 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 231589229863 ps |
| CPU time | 167.74 seconds |
| Started | Oct 12 01:29:10 PM UTC 24 |
| Finished | Oct 12 01:32:00 PM UTC 24 |
| Peak memory | 208596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252430169 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.4252430169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_loopback.1333358568 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 200022579 ps |
| CPU time | 0.98 seconds |
| Started | Oct 12 01:29:09 PM UTC 24 |
| Finished | Oct 12 01:29:11 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333358568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1333358568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_perf.498893301 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 8431796975 ps |
| CPU time | 432.12 seconds |
| Started | Oct 12 01:29:09 PM UTC 24 |
| Finished | Oct 12 01:36:27 PM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498893301 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.498893301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.1129291082 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5432848153 ps |
| CPU time | 8.65 seconds |
| Started | Oct 12 01:29:09 PM UTC 24 |
| Finished | Oct 12 01:29:19 PM UTC 24 |
| Peak memory | 207352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129291082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1129291082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.1049956664 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2132307767 ps |
| CPU time | 24.48 seconds |
| Started | Oct 12 01:29:10 PM UTC 24 |
| Finished | Oct 12 01:29:35 PM UTC 24 |
| Peak memory | 224012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1049956664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_ with_rand_reset.1049956664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.3051167058 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 469414899 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 01:29:09 PM UTC 24 |
| Finished | Oct 12 01:29:12 PM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051167058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3051167058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_tx_rx.3504956203 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 63172779981 ps |
| CPU time | 101.97 seconds |
| Started | Oct 12 01:29:08 PM UTC 24 |
| Finished | Oct 12 01:30:52 PM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504956203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3504956203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_alert_test.3963534709 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 31482006 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 01:32:46 PM UTC 24 |
| Finished | Oct 12 01:32:48 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963534709 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3963534709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_fifo_full.3919924051 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 38311182756 ps |
| CPU time | 38.53 seconds |
| Started | Oct 12 01:32:14 PM UTC 24 |
| Finished | Oct 12 01:32:54 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919924051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3919924051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.348269767 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 60570155136 ps |
| CPU time | 153.3 seconds |
| Started | Oct 12 01:32:18 PM UTC 24 |
| Finished | Oct 12 01:34:54 PM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348269767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.348269767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_fifo_reset.3798393167 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 18414289513 ps |
| CPU time | 33.75 seconds |
| Started | Oct 12 01:32:19 PM UTC 24 |
| Finished | Oct 12 01:32:54 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798393167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3798393167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_intr.1074580806 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 213164188529 ps |
| CPU time | 150.6 seconds |
| Started | Oct 12 01:32:30 PM UTC 24 |
| Finished | Oct 12 01:35:03 PM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074580806 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1074580806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.382774602 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 78311869944 ps |
| CPU time | 234.65 seconds |
| Started | Oct 12 01:32:43 PM UTC 24 |
| Finished | Oct 12 01:36:41 PM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382774602 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.382774602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_loopback.976949341 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 7196888295 ps |
| CPU time | 27.92 seconds |
| Started | Oct 12 01:32:39 PM UTC 24 |
| Finished | Oct 12 01:33:08 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976949341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 10.uart_loopback.976949341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_noise_filter.1120092215 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 63460642859 ps |
| CPU time | 56.43 seconds |
| Started | Oct 12 01:32:31 PM UTC 24 |
| Finished | Oct 12 01:33:29 PM UTC 24 |
| Peak memory | 208196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120092215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1120092215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_perf.1538247257 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 26200140569 ps |
| CPU time | 941.31 seconds |
| Started | Oct 12 01:32:39 PM UTC 24 |
| Finished | Oct 12 01:48:31 PM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538247257 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1538247257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_rx_oversample.3916581232 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 3480330105 ps |
| CPU time | 14.69 seconds |
| Started | Oct 12 01:32:26 PM UTC 24 |
| Finished | Oct 12 01:32:42 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916581232 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3916581232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.3369834547 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 164535528482 ps |
| CPU time | 181.26 seconds |
| Started | Oct 12 01:32:32 PM UTC 24 |
| Finished | Oct 12 01:35:36 PM UTC 24 |
| Peak memory | 208516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369834547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3369834547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.4283717686 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4156481027 ps |
| CPU time | 12.64 seconds |
| Started | Oct 12 01:32:32 PM UTC 24 |
| Finished | Oct 12 01:32:46 PM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283717686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.4283717686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_smoke.3854462212 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 6095379014 ps |
| CPU time | 15.54 seconds |
| Started | Oct 12 01:32:09 PM UTC 24 |
| Finished | Oct 12 01:32:25 PM UTC 24 |
| Peak memory | 208476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854462212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3854462212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.1418934054 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 11660567067 ps |
| CPU time | 29.76 seconds |
| Started | Oct 12 01:32:33 PM UTC 24 |
| Finished | Oct 12 01:33:04 PM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418934054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1418934054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_tx_rx.3605257524 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 132945959014 ps |
| CPU time | 86.64 seconds |
| Started | Oct 12 01:32:12 PM UTC 24 |
| Finished | Oct 12 01:33:40 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605257524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3605257524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/10.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/100.uart_fifo_reset.2202933849 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 46499285829 ps |
| CPU time | 44.03 seconds |
| Started | Oct 12 02:02:09 PM UTC 24 |
| Finished | Oct 12 02:02:54 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202933849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2202933849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/100.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/102.uart_fifo_reset.237044169 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 16040845427 ps |
| CPU time | 18.66 seconds |
| Started | Oct 12 02:02:11 PM UTC 24 |
| Finished | Oct 12 02:02:31 PM UTC 24 |
| Peak memory | 208384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237044169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.237044169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/102.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/104.uart_fifo_reset.2328082699 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 51743002123 ps |
| CPU time | 111.37 seconds |
| Started | Oct 12 02:02:14 PM UTC 24 |
| Finished | Oct 12 02:04:07 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328082699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2328082699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/104.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/106.uart_fifo_reset.3117069710 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 127560254391 ps |
| CPU time | 360.9 seconds |
| Started | Oct 12 02:02:17 PM UTC 24 |
| Finished | Oct 12 02:08:23 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117069710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3117069710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/106.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/107.uart_fifo_reset.1690352724 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 117186286722 ps |
| CPU time | 171.4 seconds |
| Started | Oct 12 02:02:18 PM UTC 24 |
| Finished | Oct 12 02:05:12 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690352724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1690352724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/107.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/108.uart_fifo_reset.1714703196 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 45369575385 ps |
| CPU time | 24.45 seconds |
| Started | Oct 12 02:02:18 PM UTC 24 |
| Finished | Oct 12 02:02:44 PM UTC 24 |
| Peak memory | 208504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714703196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1714703196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/108.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/109.uart_fifo_reset.4203928573 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 54970765217 ps |
| CPU time | 46.94 seconds |
| Started | Oct 12 02:02:19 PM UTC 24 |
| Finished | Oct 12 02:03:08 PM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203928573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.4203928573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/109.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_alert_test.3355802709 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 97807849 ps |
| CPU time | 0.75 seconds |
| Started | Oct 12 01:33:18 PM UTC 24 |
| Finished | Oct 12 01:33:20 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355802709 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3355802709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.70918239 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 288937647413 ps |
| CPU time | 140.76 seconds |
| Started | Oct 12 01:32:52 PM UTC 24 |
| Finished | Oct 12 01:35:15 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70918239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.70918239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_intr.3845543158 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 378919715449 ps |
| CPU time | 237.58 seconds |
| Started | Oct 12 01:32:55 PM UTC 24 |
| Finished | Oct 12 01:36:56 PM UTC 24 |
| Peak memory | 208492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845543158 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3845543158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.711254610 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 202908529331 ps |
| CPU time | 680.08 seconds |
| Started | Oct 12 01:33:10 PM UTC 24 |
| Finished | Oct 12 01:44:38 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711254610 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.711254610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_loopback.2842111681 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 10457661580 ps |
| CPU time | 40.47 seconds |
| Started | Oct 12 01:33:09 PM UTC 24 |
| Finished | Oct 12 01:33:51 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842111681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2842111681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_noise_filter.4170587173 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 71964172830 ps |
| CPU time | 57.91 seconds |
| Started | Oct 12 01:32:59 PM UTC 24 |
| Finished | Oct 12 01:33:59 PM UTC 24 |
| Peak memory | 207636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170587173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.4170587173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_perf.595010335 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 13351657574 ps |
| CPU time | 680.49 seconds |
| Started | Oct 12 01:33:09 PM UTC 24 |
| Finished | Oct 12 01:44:38 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595010335 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.595010335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_rx_oversample.3565546273 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 7260869043 ps |
| CPU time | 3.35 seconds |
| Started | Oct 12 01:32:54 PM UTC 24 |
| Finished | Oct 12 01:32:59 PM UTC 24 |
| Peak memory | 207476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565546273 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3565546273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.304303227 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 4116479876 ps |
| CPU time | 2.85 seconds |
| Started | Oct 12 01:33:05 PM UTC 24 |
| Finished | Oct 12 01:33:09 PM UTC 24 |
| Peak memory | 207296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304303227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.304303227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_smoke.962220918 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 694197980 ps |
| CPU time | 5.2 seconds |
| Started | Oct 12 01:32:47 PM UTC 24 |
| Finished | Oct 12 01:32:53 PM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962220918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 11.uart_smoke.962220918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.1096466100 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2226174963 ps |
| CPU time | 21.12 seconds |
| Started | Oct 12 01:33:14 PM UTC 24 |
| Finished | Oct 12 01:33:36 PM UTC 24 |
| Peak memory | 208880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1096466100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all _with_rand_reset.1096466100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.3707550354 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1435842593 ps |
| CPU time | 6.91 seconds |
| Started | Oct 12 01:33:08 PM UTC 24 |
| Finished | Oct 12 01:33:16 PM UTC 24 |
| Peak memory | 208140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707550354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3707550354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/11.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/110.uart_fifo_reset.4074613111 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 212521752136 ps |
| CPU time | 45.61 seconds |
| Started | Oct 12 02:02:21 PM UTC 24 |
| Finished | Oct 12 02:03:09 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074613111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.4074613111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/110.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/111.uart_fifo_reset.537317469 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 98250262138 ps |
| CPU time | 230.12 seconds |
| Started | Oct 12 02:02:23 PM UTC 24 |
| Finished | Oct 12 02:06:16 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537317469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.537317469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/111.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/112.uart_fifo_reset.1110887734 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 20907615745 ps |
| CPU time | 31.88 seconds |
| Started | Oct 12 02:02:29 PM UTC 24 |
| Finished | Oct 12 02:03:02 PM UTC 24 |
| Peak memory | 208572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110887734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1110887734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/112.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/113.uart_fifo_reset.321109152 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 57195912577 ps |
| CPU time | 32.84 seconds |
| Started | Oct 12 02:02:29 PM UTC 24 |
| Finished | Oct 12 02:03:03 PM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321109152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.321109152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/113.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/114.uart_fifo_reset.1419670086 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 36307853418 ps |
| CPU time | 46.46 seconds |
| Started | Oct 12 02:02:31 PM UTC 24 |
| Finished | Oct 12 02:03:19 PM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419670086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1419670086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/114.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/115.uart_fifo_reset.76674216 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 49988934625 ps |
| CPU time | 100.07 seconds |
| Started | Oct 12 02:02:31 PM UTC 24 |
| Finished | Oct 12 02:04:13 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76674216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.76674216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/115.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/116.uart_fifo_reset.2529633817 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 106451234469 ps |
| CPU time | 44.81 seconds |
| Started | Oct 12 02:02:32 PM UTC 24 |
| Finished | Oct 12 02:03:18 PM UTC 24 |
| Peak memory | 208732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529633817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2529633817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/116.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/117.uart_fifo_reset.4154361529 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 101001180547 ps |
| CPU time | 104.43 seconds |
| Started | Oct 12 02:02:33 PM UTC 24 |
| Finished | Oct 12 02:04:20 PM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154361529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.4154361529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/117.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/118.uart_fifo_reset.3726676366 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 41168396624 ps |
| CPU time | 28.41 seconds |
| Started | Oct 12 02:02:34 PM UTC 24 |
| Finished | Oct 12 02:03:04 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726676366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3726676366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/118.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/119.uart_fifo_reset.3526629597 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 216439782262 ps |
| CPU time | 407.3 seconds |
| Started | Oct 12 02:02:44 PM UTC 24 |
| Finished | Oct 12 02:09:36 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526629597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3526629597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/119.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_alert_test.967466544 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 49951217 ps |
| CPU time | 0.88 seconds |
| Started | Oct 12 01:33:54 PM UTC 24 |
| Finished | Oct 12 01:33:56 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967466544 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.967466544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_fifo_full.329818488 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 73445746574 ps |
| CPU time | 35.31 seconds |
| Started | Oct 12 01:33:22 PM UTC 24 |
| Finished | Oct 12 01:34:00 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329818488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.329818488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.2708255844 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 87461209294 ps |
| CPU time | 105.07 seconds |
| Started | Oct 12 01:33:29 PM UTC 24 |
| Finished | Oct 12 01:35:16 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708255844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2708255844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_fifo_reset.1230253998 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 50509532816 ps |
| CPU time | 176.24 seconds |
| Started | Oct 12 01:33:29 PM UTC 24 |
| Finished | Oct 12 01:36:28 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230253998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1230253998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_intr.2816882612 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 7623541091 ps |
| CPU time | 27.35 seconds |
| Started | Oct 12 01:33:36 PM UTC 24 |
| Finished | Oct 12 01:34:05 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816882612 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2816882612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.2791965970 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 125432502982 ps |
| CPU time | 220.51 seconds |
| Started | Oct 12 01:33:49 PM UTC 24 |
| Finished | Oct 12 01:37:33 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791965970 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2791965970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_loopback.2713284366 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 9207132095 ps |
| CPU time | 22.2 seconds |
| Started | Oct 12 01:33:46 PM UTC 24 |
| Finished | Oct 12 01:34:10 PM UTC 24 |
| Peak memory | 207984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713284366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2713284366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_noise_filter.2139344855 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 12929146266 ps |
| CPU time | 39.52 seconds |
| Started | Oct 12 01:33:37 PM UTC 24 |
| Finished | Oct 12 01:34:18 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139344855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2139344855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_perf.2985356147 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 10502041205 ps |
| CPU time | 307.52 seconds |
| Started | Oct 12 01:33:47 PM UTC 24 |
| Finished | Oct 12 01:38:59 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985356147 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2985356147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_rx_oversample.3185990348 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 3135747905 ps |
| CPU time | 5.28 seconds |
| Started | Oct 12 01:33:30 PM UTC 24 |
| Finished | Oct 12 01:33:36 PM UTC 24 |
| Peak memory | 207624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185990348 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3185990348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.3123908205 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 37245624709 ps |
| CPU time | 30.9 seconds |
| Started | Oct 12 01:33:40 PM UTC 24 |
| Finished | Oct 12 01:34:13 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123908205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3123908205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.726181477 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 3057713378 ps |
| CPU time | 10.66 seconds |
| Started | Oct 12 01:33:37 PM UTC 24 |
| Finished | Oct 12 01:33:49 PM UTC 24 |
| Peak memory | 205184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726181477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.726181477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_smoke.2838247255 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 6168645198 ps |
| CPU time | 13.64 seconds |
| Started | Oct 12 01:33:20 PM UTC 24 |
| Finished | Oct 12 01:33:35 PM UTC 24 |
| Peak memory | 208224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838247255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2838247255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.1037176408 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 5957860823 ps |
| CPU time | 34.89 seconds |
| Started | Oct 12 01:33:51 PM UTC 24 |
| Finished | Oct 12 01:34:27 PM UTC 24 |
| Peak memory | 219876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1037176408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all _with_rand_reset.1037176408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.3903527724 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 8616510008 ps |
| CPU time | 15.83 seconds |
| Started | Oct 12 01:33:41 PM UTC 24 |
| Finished | Oct 12 01:33:58 PM UTC 24 |
| Peak memory | 208540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903527724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3903527724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_tx_rx.346404411 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 35317842160 ps |
| CPU time | 33.19 seconds |
| Started | Oct 12 01:33:21 PM UTC 24 |
| Finished | Oct 12 01:33:56 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346404411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.346404411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/12.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/120.uart_fifo_reset.165924794 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 23790288519 ps |
| CPU time | 15.62 seconds |
| Started | Oct 12 02:02:44 PM UTC 24 |
| Finished | Oct 12 02:03:01 PM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165924794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.165924794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/120.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/121.uart_fifo_reset.828982008 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 107390106240 ps |
| CPU time | 241.15 seconds |
| Started | Oct 12 02:02:44 PM UTC 24 |
| Finished | Oct 12 02:06:49 PM UTC 24 |
| Peak memory | 208884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828982008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.828982008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/121.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/122.uart_fifo_reset.2920204078 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 140669278524 ps |
| CPU time | 121.44 seconds |
| Started | Oct 12 02:02:45 PM UTC 24 |
| Finished | Oct 12 02:04:49 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920204078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2920204078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/122.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/123.uart_fifo_reset.3135838615 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 64624843088 ps |
| CPU time | 36.04 seconds |
| Started | Oct 12 02:02:47 PM UTC 24 |
| Finished | Oct 12 02:03:24 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135838615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3135838615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/123.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/125.uart_fifo_reset.2647643165 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 31454215809 ps |
| CPU time | 43.99 seconds |
| Started | Oct 12 02:02:56 PM UTC 24 |
| Finished | Oct 12 02:03:41 PM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647643165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2647643165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/125.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/127.uart_fifo_reset.849732112 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 34759512985 ps |
| CPU time | 15.8 seconds |
| Started | Oct 12 02:02:57 PM UTC 24 |
| Finished | Oct 12 02:03:14 PM UTC 24 |
| Peak memory | 208416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849732112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.849732112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/127.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/128.uart_fifo_reset.890471212 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 10501520027 ps |
| CPU time | 19.64 seconds |
| Started | Oct 12 02:02:58 PM UTC 24 |
| Finished | Oct 12 02:03:19 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890471212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.890471212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/128.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/129.uart_fifo_reset.656261401 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 133523255282 ps |
| CPU time | 285.25 seconds |
| Started | Oct 12 02:03:02 PM UTC 24 |
| Finished | Oct 12 02:07:51 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656261401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.656261401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/129.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_alert_test.3210782153 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 37214488 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 01:34:29 PM UTC 24 |
| Finished | Oct 12 01:34:31 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210782153 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3210782153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_fifo_full.1536649458 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 143236624440 ps |
| CPU time | 283.55 seconds |
| Started | Oct 12 01:33:59 PM UTC 24 |
| Finished | Oct 12 01:38:46 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536649458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1536649458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.4200885088 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 151548479702 ps |
| CPU time | 71.36 seconds |
| Started | Oct 12 01:34:00 PM UTC 24 |
| Finished | Oct 12 01:35:13 PM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200885088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.4200885088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_intr.3238864230 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 22994528713 ps |
| CPU time | 77.72 seconds |
| Started | Oct 12 01:34:01 PM UTC 24 |
| Finished | Oct 12 01:35:21 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238864230 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3238864230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.2638608103 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 238494415396 ps |
| CPU time | 258.81 seconds |
| Started | Oct 12 01:34:19 PM UTC 24 |
| Finished | Oct 12 01:38:42 PM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638608103 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2638608103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_loopback.3124971017 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 152663435 ps |
| CPU time | 1 seconds |
| Started | Oct 12 01:34:14 PM UTC 24 |
| Finished | Oct 12 01:34:16 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124971017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3124971017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_perf.1542400979 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 5334172285 ps |
| CPU time | 73.8 seconds |
| Started | Oct 12 01:34:17 PM UTC 24 |
| Finished | Oct 12 01:35:32 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542400979 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1542400979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_rx_oversample.4160417464 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1483446893 ps |
| CPU time | 5.62 seconds |
| Started | Oct 12 01:34:00 PM UTC 24 |
| Finished | Oct 12 01:34:07 PM UTC 24 |
| Peak memory | 207296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160417464 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.4160417464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.4095246627 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 58709805587 ps |
| CPU time | 48 seconds |
| Started | Oct 12 01:34:09 PM UTC 24 |
| Finished | Oct 12 01:34:58 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095246627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.4095246627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.2543034214 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 5551160480 ps |
| CPU time | 9.95 seconds |
| Started | Oct 12 01:34:08 PM UTC 24 |
| Finished | Oct 12 01:34:19 PM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543034214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2543034214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_smoke.2227834259 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 580413084 ps |
| CPU time | 2.16 seconds |
| Started | Oct 12 01:33:57 PM UTC 24 |
| Finished | Oct 12 01:34:00 PM UTC 24 |
| Peak memory | 207464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227834259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2227834259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.3186613977 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 6862136154 ps |
| CPU time | 11.62 seconds |
| Started | Oct 12 01:34:11 PM UTC 24 |
| Finished | Oct 12 01:34:24 PM UTC 24 |
| Peak memory | 208408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186613977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3186613977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_tx_rx.2480325128 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 226871845666 ps |
| CPU time | 47.61 seconds |
| Started | Oct 12 01:33:57 PM UTC 24 |
| Finished | Oct 12 01:34:46 PM UTC 24 |
| Peak memory | 208884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480325128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2480325128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/13.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/130.uart_fifo_reset.3569019085 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 24034968780 ps |
| CPU time | 80.1 seconds |
| Started | Oct 12 02:03:02 PM UTC 24 |
| Finished | Oct 12 02:04:24 PM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569019085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3569019085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/130.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/131.uart_fifo_reset.2758854011 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 5978379608 ps |
| CPU time | 17.74 seconds |
| Started | Oct 12 02:03:02 PM UTC 24 |
| Finished | Oct 12 02:03:21 PM UTC 24 |
| Peak memory | 208544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758854011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2758854011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/131.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/132.uart_fifo_reset.3300510001 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 112342804987 ps |
| CPU time | 245.14 seconds |
| Started | Oct 12 02:03:03 PM UTC 24 |
| Finished | Oct 12 02:07:11 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300510001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3300510001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/132.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/133.uart_fifo_reset.3614954371 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 28101166061 ps |
| CPU time | 54.53 seconds |
| Started | Oct 12 02:03:03 PM UTC 24 |
| Finished | Oct 12 02:03:59 PM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614954371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3614954371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/133.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/134.uart_fifo_reset.2683329411 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 11476569244 ps |
| CPU time | 20.37 seconds |
| Started | Oct 12 02:03:04 PM UTC 24 |
| Finished | Oct 12 02:03:25 PM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683329411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2683329411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/134.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/135.uart_fifo_reset.1297554523 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 29579033077 ps |
| CPU time | 27.15 seconds |
| Started | Oct 12 02:03:05 PM UTC 24 |
| Finished | Oct 12 02:03:33 PM UTC 24 |
| Peak memory | 208216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297554523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1297554523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/135.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/136.uart_fifo_reset.352938523 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 91836651247 ps |
| CPU time | 104.89 seconds |
| Started | Oct 12 02:03:09 PM UTC 24 |
| Finished | Oct 12 02:04:56 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352938523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.352938523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/136.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/137.uart_fifo_reset.3880584219 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 93787850953 ps |
| CPU time | 164.81 seconds |
| Started | Oct 12 02:03:09 PM UTC 24 |
| Finished | Oct 12 02:05:57 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880584219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3880584219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/137.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/139.uart_fifo_reset.732238473 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 36653255398 ps |
| CPU time | 44.08 seconds |
| Started | Oct 12 02:03:12 PM UTC 24 |
| Finished | Oct 12 02:03:58 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732238473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.732238473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/139.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_alert_test.2682570365 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 45123449 ps |
| CPU time | 0.81 seconds |
| Started | Oct 12 01:35:14 PM UTC 24 |
| Finished | Oct 12 01:35:16 PM UTC 24 |
| Peak memory | 204100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682570365 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2682570365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_fifo_full.2990672372 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 80126992041 ps |
| CPU time | 41.98 seconds |
| Started | Oct 12 01:34:38 PM UTC 24 |
| Finished | Oct 12 01:35:21 PM UTC 24 |
| Peak memory | 208800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990672372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2990672372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.3807058331 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 38850522909 ps |
| CPU time | 119.8 seconds |
| Started | Oct 12 01:34:40 PM UTC 24 |
| Finished | Oct 12 01:36:42 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807058331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3807058331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_fifo_reset.3109779618 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 234699904156 ps |
| CPU time | 169.82 seconds |
| Started | Oct 12 01:34:42 PM UTC 24 |
| Finished | Oct 12 01:37:34 PM UTC 24 |
| Peak memory | 208664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109779618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3109779618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_intr.3173461082 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 18955706046 ps |
| CPU time | 74.03 seconds |
| Started | Oct 12 01:34:48 PM UTC 24 |
| Finished | Oct 12 01:36:04 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173461082 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3173461082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.1613037585 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 71970542802 ps |
| CPU time | 257.9 seconds |
| Started | Oct 12 01:35:09 PM UTC 24 |
| Finished | Oct 12 01:39:31 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613037585 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1613037585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_loopback.2615581505 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 3186792877 ps |
| CPU time | 3.19 seconds |
| Started | Oct 12 01:35:05 PM UTC 24 |
| Finished | Oct 12 01:35:09 PM UTC 24 |
| Peak memory | 207348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615581505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2615581505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_noise_filter.1842965682 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 45008529570 ps |
| CPU time | 35.55 seconds |
| Started | Oct 12 01:34:54 PM UTC 24 |
| Finished | Oct 12 01:35:31 PM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842965682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1842965682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_perf.2311910394 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 16412121785 ps |
| CPU time | 216.36 seconds |
| Started | Oct 12 01:35:05 PM UTC 24 |
| Finished | Oct 12 01:38:45 PM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311910394 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2311910394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_rx_oversample.2622092992 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 7910227693 ps |
| CPU time | 16.14 seconds |
| Started | Oct 12 01:34:42 PM UTC 24 |
| Finished | Oct 12 01:34:59 PM UTC 24 |
| Peak memory | 207108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622092992 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2622092992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.630462273 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 111023737232 ps |
| CPU time | 222.52 seconds |
| Started | Oct 12 01:35:00 PM UTC 24 |
| Finished | Oct 12 01:38:46 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630462273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.630462273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.1974839346 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 31926598786 ps |
| CPU time | 13.56 seconds |
| Started | Oct 12 01:35:00 PM UTC 24 |
| Finished | Oct 12 01:35:15 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974839346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1974839346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_smoke.2362427169 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 886295692 ps |
| CPU time | 5.07 seconds |
| Started | Oct 12 01:34:32 PM UTC 24 |
| Finished | Oct 12 01:34:38 PM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362427169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2362427169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_stress_all.2165400035 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 253809299411 ps |
| CPU time | 102 seconds |
| Started | Oct 12 01:35:10 PM UTC 24 |
| Finished | Oct 12 01:36:54 PM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165400035 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2165400035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.2145300805 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 9067490173 ps |
| CPU time | 55.94 seconds |
| Started | Oct 12 01:35:10 PM UTC 24 |
| Finished | Oct 12 01:36:08 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2145300805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all _with_rand_reset.2145300805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.2569047138 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1464639877 ps |
| CPU time | 5.64 seconds |
| Started | Oct 12 01:35:00 PM UTC 24 |
| Finished | Oct 12 01:35:07 PM UTC 24 |
| Peak memory | 207332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569047138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2569047138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_tx_rx.2438020977 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 77341180698 ps |
| CPU time | 158.09 seconds |
| Started | Oct 12 01:34:38 PM UTC 24 |
| Finished | Oct 12 01:37:19 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438020977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2438020977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/14.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/140.uart_fifo_reset.1475297810 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 172609335598 ps |
| CPU time | 110.13 seconds |
| Started | Oct 12 02:03:14 PM UTC 24 |
| Finished | Oct 12 02:05:07 PM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475297810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1475297810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/140.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/141.uart_fifo_reset.263837998 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 18981440128 ps |
| CPU time | 46.73 seconds |
| Started | Oct 12 02:03:16 PM UTC 24 |
| Finished | Oct 12 02:04:05 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263837998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.263837998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/141.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/142.uart_fifo_reset.2300663762 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 101059739743 ps |
| CPU time | 209.02 seconds |
| Started | Oct 12 02:03:20 PM UTC 24 |
| Finished | Oct 12 02:06:52 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300663762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2300663762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/142.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/143.uart_fifo_reset.3033082997 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 27884361386 ps |
| CPU time | 52.59 seconds |
| Started | Oct 12 02:03:20 PM UTC 24 |
| Finished | Oct 12 02:04:14 PM UTC 24 |
| Peak memory | 208404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033082997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3033082997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/143.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/144.uart_fifo_reset.330844479 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 13842480297 ps |
| CPU time | 41.59 seconds |
| Started | Oct 12 02:03:20 PM UTC 24 |
| Finished | Oct 12 02:04:03 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330844479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.330844479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/144.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/145.uart_fifo_reset.3097727717 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 98814678034 ps |
| CPU time | 97.13 seconds |
| Started | Oct 12 02:03:22 PM UTC 24 |
| Finished | Oct 12 02:05:01 PM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097727717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3097727717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/145.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/146.uart_fifo_reset.3590612172 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 145346993782 ps |
| CPU time | 50.82 seconds |
| Started | Oct 12 02:03:22 PM UTC 24 |
| Finished | Oct 12 02:04:14 PM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590612172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3590612172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/146.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/147.uart_fifo_reset.3109932725 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 94458893203 ps |
| CPU time | 80.62 seconds |
| Started | Oct 12 02:03:23 PM UTC 24 |
| Finished | Oct 12 02:04:45 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109932725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3109932725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/147.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/148.uart_fifo_reset.4213832012 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 15979000733 ps |
| CPU time | 27.67 seconds |
| Started | Oct 12 02:03:23 PM UTC 24 |
| Finished | Oct 12 02:03:52 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213832012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.4213832012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/148.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_alert_test.396663488 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 13986395 ps |
| CPU time | 0.88 seconds |
| Started | Oct 12 01:35:29 PM UTC 24 |
| Finished | Oct 12 01:35:31 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396663488 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.396663488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_fifo_full.2938438088 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 259401312200 ps |
| CPU time | 534.21 seconds |
| Started | Oct 12 01:35:16 PM UTC 24 |
| Finished | Oct 12 01:44:17 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938438088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2938438088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.3119033959 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 94792513925 ps |
| CPU time | 58.59 seconds |
| Started | Oct 12 01:35:16 PM UTC 24 |
| Finished | Oct 12 01:36:17 PM UTC 24 |
| Peak memory | 208812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119033959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3119033959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_fifo_reset.3742636726 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 172017476209 ps |
| CPU time | 19.74 seconds |
| Started | Oct 12 01:35:16 PM UTC 24 |
| Finished | Oct 12 01:35:38 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742636726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3742636726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_intr.2795502667 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 15959326758 ps |
| CPU time | 4.36 seconds |
| Started | Oct 12 01:35:17 PM UTC 24 |
| Finished | Oct 12 01:35:22 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795502667 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2795502667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.2905059616 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 46612558061 ps |
| CPU time | 269.63 seconds |
| Started | Oct 12 01:35:23 PM UTC 24 |
| Finished | Oct 12 01:39:57 PM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905059616 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2905059616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_loopback.4114401502 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 13945174038 ps |
| CPU time | 16.61 seconds |
| Started | Oct 12 01:35:19 PM UTC 24 |
| Finished | Oct 12 01:35:37 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114401502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 15.uart_loopback.4114401502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_noise_filter.3285263985 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 27515042662 ps |
| CPU time | 12.25 seconds |
| Started | Oct 12 01:35:17 PM UTC 24 |
| Finished | Oct 12 01:35:30 PM UTC 24 |
| Peak memory | 205324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285263985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3285263985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_perf.491125648 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 16951508360 ps |
| CPU time | 196.14 seconds |
| Started | Oct 12 01:35:23 PM UTC 24 |
| Finished | Oct 12 01:38:43 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491125648 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.491125648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_rx_oversample.764431778 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 7279873683 ps |
| CPU time | 45.32 seconds |
| Started | Oct 12 01:35:17 PM UTC 24 |
| Finished | Oct 12 01:36:04 PM UTC 24 |
| Peak memory | 207656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764431778 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.764431778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.2012927368 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 14399537254 ps |
| CPU time | 17.82 seconds |
| Started | Oct 12 01:35:19 PM UTC 24 |
| Finished | Oct 12 01:35:38 PM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012927368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2012927368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.2782618308 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 3392855174 ps |
| CPU time | 15.65 seconds |
| Started | Oct 12 01:35:19 PM UTC 24 |
| Finished | Oct 12 01:35:36 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782618308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2782618308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_smoke.1695338671 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 761343385 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 01:35:14 PM UTC 24 |
| Finished | Oct 12 01:35:17 PM UTC 24 |
| Peak memory | 207664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695338671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1695338671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_stress_all.2588665558 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 74534184552 ps |
| CPU time | 495.55 seconds |
| Started | Oct 12 01:35:27 PM UTC 24 |
| Finished | Oct 12 01:43:49 PM UTC 24 |
| Peak memory | 217776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588665558 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2588665558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.1839853265 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1510312593 ps |
| CPU time | 73.26 seconds |
| Started | Oct 12 01:35:23 PM UTC 24 |
| Finished | Oct 12 01:36:38 PM UTC 24 |
| Peak memory | 208960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1839853265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all _with_rand_reset.1839853265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.1792603411 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 779882087 ps |
| CPU time | 4.83 seconds |
| Started | Oct 12 01:35:19 PM UTC 24 |
| Finished | Oct 12 01:35:25 PM UTC 24 |
| Peak memory | 207984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792603411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1792603411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_tx_rx.3266395744 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 251220424984 ps |
| CPU time | 110.06 seconds |
| Started | Oct 12 01:35:16 PM UTC 24 |
| Finished | Oct 12 01:37:09 PM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266395744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3266395744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/15.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/152.uart_fifo_reset.1754400710 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 124392931183 ps |
| CPU time | 167.47 seconds |
| Started | Oct 12 02:03:34 PM UTC 24 |
| Finished | Oct 12 02:06:25 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754400710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1754400710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/152.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/153.uart_fifo_reset.2661226131 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 111070931030 ps |
| CPU time | 88.23 seconds |
| Started | Oct 12 02:03:42 PM UTC 24 |
| Finished | Oct 12 02:05:12 PM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661226131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2661226131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/153.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/154.uart_fifo_reset.2996794279 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 24071945457 ps |
| CPU time | 46.53 seconds |
| Started | Oct 12 02:03:47 PM UTC 24 |
| Finished | Oct 12 02:04:35 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996794279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2996794279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/154.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/155.uart_fifo_reset.3409505003 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 20475481485 ps |
| CPU time | 67.96 seconds |
| Started | Oct 12 02:03:50 PM UTC 24 |
| Finished | Oct 12 02:04:59 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409505003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3409505003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/155.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/157.uart_fifo_reset.239411562 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 260337443128 ps |
| CPU time | 204.21 seconds |
| Started | Oct 12 02:03:53 PM UTC 24 |
| Finished | Oct 12 02:07:20 PM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239411562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.239411562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/157.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/158.uart_fifo_reset.1877582205 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 25641556679 ps |
| CPU time | 14.5 seconds |
| Started | Oct 12 02:03:56 PM UTC 24 |
| Finished | Oct 12 02:04:12 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877582205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1877582205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/158.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/159.uart_fifo_reset.988814211 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 88676228088 ps |
| CPU time | 34.45 seconds |
| Started | Oct 12 02:03:59 PM UTC 24 |
| Finished | Oct 12 02:04:35 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988814211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.988814211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/159.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_alert_test.2391085916 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 22469487 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 01:36:02 PM UTC 24 |
| Finished | Oct 12 01:36:04 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391085916 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2391085916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_fifo_full.2649154381 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 15705432208 ps |
| CPU time | 11.58 seconds |
| Started | Oct 12 01:35:34 PM UTC 24 |
| Finished | Oct 12 01:35:47 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649154381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2649154381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_fifo_reset.4041003601 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 8552149996 ps |
| CPU time | 15.39 seconds |
| Started | Oct 12 01:35:34 PM UTC 24 |
| Finished | Oct 12 01:35:50 PM UTC 24 |
| Peak memory | 208316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041003601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.4041003601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_intr.4289511859 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 331096283935 ps |
| CPU time | 102.31 seconds |
| Started | Oct 12 01:35:38 PM UTC 24 |
| Finished | Oct 12 01:37:22 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289511859 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.4289511859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.1988244413 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 141528449692 ps |
| CPU time | 928.96 seconds |
| Started | Oct 12 01:35:49 PM UTC 24 |
| Finished | Oct 12 01:51:29 PM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988244413 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1988244413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_loopback.2027043629 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 9559538241 ps |
| CPU time | 27.67 seconds |
| Started | Oct 12 01:35:42 PM UTC 24 |
| Finished | Oct 12 01:36:11 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027043629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2027043629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_noise_filter.2930245729 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 21560225062 ps |
| CPU time | 42.66 seconds |
| Started | Oct 12 01:35:38 PM UTC 24 |
| Finished | Oct 12 01:36:22 PM UTC 24 |
| Peak memory | 208052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930245729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2930245729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_perf.1683848398 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 19219590726 ps |
| CPU time | 1026.66 seconds |
| Started | Oct 12 01:35:45 PM UTC 24 |
| Finished | Oct 12 01:53:03 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683848398 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1683848398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_rx_oversample.1983560837 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2667488913 ps |
| CPU time | 7.31 seconds |
| Started | Oct 12 01:35:38 PM UTC 24 |
| Finished | Oct 12 01:35:46 PM UTC 24 |
| Peak memory | 207432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983560837 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1983560837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.1858858584 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 146218990016 ps |
| CPU time | 103.23 seconds |
| Started | Oct 12 01:35:38 PM UTC 24 |
| Finished | Oct 12 01:37:24 PM UTC 24 |
| Peak memory | 208344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858858584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1858858584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.3827111402 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 918054517 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 01:35:38 PM UTC 24 |
| Finished | Oct 12 01:35:41 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827111402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3827111402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_smoke.1349216960 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 555718034 ps |
| CPU time | 4.47 seconds |
| Started | Oct 12 01:35:32 PM UTC 24 |
| Finished | Oct 12 01:35:37 PM UTC 24 |
| Peak memory | 207468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349216960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1349216960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_stress_all.4042594513 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 29120925662 ps |
| CPU time | 203.27 seconds |
| Started | Oct 12 01:35:51 PM UTC 24 |
| Finished | Oct 12 01:39:17 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042594513 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.4042594513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.1049266118 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 7458388746 ps |
| CPU time | 2.79 seconds |
| Started | Oct 12 01:35:40 PM UTC 24 |
| Finished | Oct 12 01:35:44 PM UTC 24 |
| Peak memory | 207580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049266118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1049266118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_tx_rx.2909077230 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 22220889242 ps |
| CPU time | 37.16 seconds |
| Started | Oct 12 01:35:32 PM UTC 24 |
| Finished | Oct 12 01:36:10 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909077230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2909077230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/16.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/162.uart_fifo_reset.284412752 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 153335110348 ps |
| CPU time | 45.39 seconds |
| Started | Oct 12 02:04:00 PM UTC 24 |
| Finished | Oct 12 02:04:47 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284412752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.284412752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/162.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/164.uart_fifo_reset.1932213912 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 190739803210 ps |
| CPU time | 101.49 seconds |
| Started | Oct 12 02:04:03 PM UTC 24 |
| Finished | Oct 12 02:05:47 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932213912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1932213912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/164.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/167.uart_fifo_reset.683351831 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 49813727848 ps |
| CPU time | 104.79 seconds |
| Started | Oct 12 02:04:07 PM UTC 24 |
| Finished | Oct 12 02:05:53 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683351831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.683351831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/167.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/168.uart_fifo_reset.2483384112 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 26972913288 ps |
| CPU time | 12.16 seconds |
| Started | Oct 12 02:04:08 PM UTC 24 |
| Finished | Oct 12 02:04:21 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483384112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2483384112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/168.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/169.uart_fifo_reset.1098373638 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 84258809850 ps |
| CPU time | 93.97 seconds |
| Started | Oct 12 02:04:11 PM UTC 24 |
| Finished | Oct 12 02:05:47 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098373638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1098373638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/169.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_alert_test.3820828279 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 11008061 ps |
| CPU time | 0.75 seconds |
| Started | Oct 12 01:36:30 PM UTC 24 |
| Finished | Oct 12 01:36:32 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820828279 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3820828279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_fifo_full.1187678760 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 21565410260 ps |
| CPU time | 18.14 seconds |
| Started | Oct 12 01:36:05 PM UTC 24 |
| Finished | Oct 12 01:36:25 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187678760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1187678760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.1003453611 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 34228752221 ps |
| CPU time | 96.39 seconds |
| Started | Oct 12 01:36:08 PM UTC 24 |
| Finished | Oct 12 01:37:47 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003453611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1003453611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_fifo_reset.843602200 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 22451265048 ps |
| CPU time | 36.25 seconds |
| Started | Oct 12 01:36:09 PM UTC 24 |
| Finished | Oct 12 01:36:47 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843602200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.843602200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_intr.3426253329 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 58926231290 ps |
| CPU time | 91.74 seconds |
| Started | Oct 12 01:36:13 PM UTC 24 |
| Finished | Oct 12 01:37:46 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426253329 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3426253329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.1341245185 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 63637784221 ps |
| CPU time | 421.98 seconds |
| Started | Oct 12 01:36:29 PM UTC 24 |
| Finished | Oct 12 01:43:37 PM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341245185 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1341245185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_loopback.2394847584 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 6002458182 ps |
| CPU time | 3.84 seconds |
| Started | Oct 12 01:36:26 PM UTC 24 |
| Finished | Oct 12 01:36:31 PM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394847584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2394847584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_noise_filter.1344435398 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 59494857707 ps |
| CPU time | 81.56 seconds |
| Started | Oct 12 01:36:13 PM UTC 24 |
| Finished | Oct 12 01:37:36 PM UTC 24 |
| Peak memory | 208856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344435398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1344435398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_perf.258471496 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 14103015165 ps |
| CPU time | 61.77 seconds |
| Started | Oct 12 01:36:28 PM UTC 24 |
| Finished | Oct 12 01:37:32 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258471496 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.258471496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_rx_oversample.3536638746 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 6198279721 ps |
| CPU time | 79.9 seconds |
| Started | Oct 12 01:36:10 PM UTC 24 |
| Finished | Oct 12 01:37:32 PM UTC 24 |
| Peak memory | 207308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536638746 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3536638746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.970180899 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 14018875581 ps |
| CPU time | 28.08 seconds |
| Started | Oct 12 01:36:23 PM UTC 24 |
| Finished | Oct 12 01:36:52 PM UTC 24 |
| Peak memory | 208280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970180899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.970180899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.577445292 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3524018239 ps |
| CPU time | 6.79 seconds |
| Started | Oct 12 01:36:18 PM UTC 24 |
| Finished | Oct 12 01:36:26 PM UTC 24 |
| Peak memory | 205248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577445292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.577445292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_smoke.423087753 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 539829988 ps |
| CPU time | 2.92 seconds |
| Started | Oct 12 01:36:04 PM UTC 24 |
| Finished | Oct 12 01:36:08 PM UTC 24 |
| Peak memory | 207468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423087753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 17.uart_smoke.423087753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.513005664 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1249063349 ps |
| CPU time | 28.37 seconds |
| Started | Oct 12 01:36:29 PM UTC 24 |
| Finished | Oct 12 01:36:59 PM UTC 24 |
| Peak memory | 219816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=513005664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all_ with_rand_reset.513005664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.290562692 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1471985564 ps |
| CPU time | 3.53 seconds |
| Started | Oct 12 01:36:25 PM UTC 24 |
| Finished | Oct 12 01:36:30 PM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290562692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.290562692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_tx_rx.191591984 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 87434287467 ps |
| CPU time | 40.65 seconds |
| Started | Oct 12 01:36:05 PM UTC 24 |
| Finished | Oct 12 01:36:47 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191591984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.191591984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/17.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/170.uart_fifo_reset.1475905347 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 28245554553 ps |
| CPU time | 68.73 seconds |
| Started | Oct 12 02:04:12 PM UTC 24 |
| Finished | Oct 12 02:05:22 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475905347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1475905347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/170.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/171.uart_fifo_reset.1878367236 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 35298344676 ps |
| CPU time | 110.55 seconds |
| Started | Oct 12 02:04:12 PM UTC 24 |
| Finished | Oct 12 02:06:05 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878367236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1878367236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/171.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/173.uart_fifo_reset.1237640054 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 46180618901 ps |
| CPU time | 106.64 seconds |
| Started | Oct 12 02:04:14 PM UTC 24 |
| Finished | Oct 12 02:06:03 PM UTC 24 |
| Peak memory | 208960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237640054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1237640054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/173.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/174.uart_fifo_reset.332932310 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 301982453782 ps |
| CPU time | 89.52 seconds |
| Started | Oct 12 02:04:14 PM UTC 24 |
| Finished | Oct 12 02:05:46 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332932310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.332932310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/174.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/175.uart_fifo_reset.3743427989 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 65460851034 ps |
| CPU time | 43.4 seconds |
| Started | Oct 12 02:04:15 PM UTC 24 |
| Finished | Oct 12 02:05:00 PM UTC 24 |
| Peak memory | 208364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743427989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3743427989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/175.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/177.uart_fifo_reset.407977575 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 115031553114 ps |
| CPU time | 31.86 seconds |
| Started | Oct 12 02:04:21 PM UTC 24 |
| Finished | Oct 12 02:04:54 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407977575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.407977575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/177.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/178.uart_fifo_reset.723428795 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 107552039336 ps |
| CPU time | 174.72 seconds |
| Started | Oct 12 02:04:21 PM UTC 24 |
| Finished | Oct 12 02:07:18 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723428795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.723428795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/178.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/179.uart_fifo_reset.1850865505 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 177689403040 ps |
| CPU time | 300.02 seconds |
| Started | Oct 12 02:04:22 PM UTC 24 |
| Finished | Oct 12 02:09:26 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850865505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1850865505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/179.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_alert_test.3636891145 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 13522551 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 01:37:09 PM UTC 24 |
| Finished | Oct 12 01:37:11 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636891145 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3636891145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_fifo_full.982815778 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 101449333893 ps |
| CPU time | 77.87 seconds |
| Started | Oct 12 01:36:36 PM UTC 24 |
| Finished | Oct 12 01:37:56 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982815778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.982815778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.669305781 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 22222184265 ps |
| CPU time | 32.08 seconds |
| Started | Oct 12 01:36:39 PM UTC 24 |
| Finished | Oct 12 01:37:12 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669305781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.669305781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_fifo_reset.3395319775 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 56901855230 ps |
| CPU time | 53.34 seconds |
| Started | Oct 12 01:36:42 PM UTC 24 |
| Finished | Oct 12 01:37:37 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395319775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3395319775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_intr.4201946680 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 14139487825 ps |
| CPU time | 5.5 seconds |
| Started | Oct 12 01:36:47 PM UTC 24 |
| Finished | Oct 12 01:36:54 PM UTC 24 |
| Peak memory | 207228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201946680 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.4201946680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_loopback.2695036362 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 6640626208 ps |
| CPU time | 21.79 seconds |
| Started | Oct 12 01:36:55 PM UTC 24 |
| Finished | Oct 12 01:37:18 PM UTC 24 |
| Peak memory | 207884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695036362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2695036362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_noise_filter.3769454589 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 56121639551 ps |
| CPU time | 206.94 seconds |
| Started | Oct 12 01:36:48 PM UTC 24 |
| Finished | Oct 12 01:40:19 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769454589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3769454589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_perf.3293861800 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 6345579686 ps |
| CPU time | 413.44 seconds |
| Started | Oct 12 01:36:57 PM UTC 24 |
| Finished | Oct 12 01:43:55 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293861800 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3293861800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_rx_oversample.3468990111 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1172650139 ps |
| CPU time | 2.39 seconds |
| Started | Oct 12 01:36:43 PM UTC 24 |
| Finished | Oct 12 01:36:46 PM UTC 24 |
| Peak memory | 205048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468990111 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3468990111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.1889664355 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 112343250836 ps |
| CPU time | 53.43 seconds |
| Started | Oct 12 01:36:53 PM UTC 24 |
| Finished | Oct 12 01:37:48 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889664355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1889664355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.4203966050 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 41120289025 ps |
| CPU time | 31.28 seconds |
| Started | Oct 12 01:36:48 PM UTC 24 |
| Finished | Oct 12 01:37:21 PM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203966050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.4203966050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_smoke.2393952229 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 6300384694 ps |
| CPU time | 34.63 seconds |
| Started | Oct 12 01:36:32 PM UTC 24 |
| Finished | Oct 12 01:37:08 PM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393952229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2393952229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_stress_all.3717375275 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 137752655148 ps |
| CPU time | 769.38 seconds |
| Started | Oct 12 01:37:04 PM UTC 24 |
| Finished | Oct 12 01:50:01 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717375275 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3717375275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.2186519294 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 7073452679 ps |
| CPU time | 31.52 seconds |
| Started | Oct 12 01:37:00 PM UTC 24 |
| Finished | Oct 12 01:37:33 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2186519294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all _with_rand_reset.2186519294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.1850479193 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 750552336 ps |
| CPU time | 2.94 seconds |
| Started | Oct 12 01:36:54 PM UTC 24 |
| Finished | Oct 12 01:36:58 PM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850479193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1850479193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_tx_rx.2416974641 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 53176496509 ps |
| CPU time | 88.05 seconds |
| Started | Oct 12 01:36:34 PM UTC 24 |
| Finished | Oct 12 01:38:04 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416974641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2416974641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/18.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/180.uart_fifo_reset.2130339768 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 77967494759 ps |
| CPU time | 258.08 seconds |
| Started | Oct 12 02:04:22 PM UTC 24 |
| Finished | Oct 12 02:08:44 PM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130339768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2130339768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/180.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/181.uart_fifo_reset.1400378926 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 170128182304 ps |
| CPU time | 256.05 seconds |
| Started | Oct 12 02:04:25 PM UTC 24 |
| Finished | Oct 12 02:08:44 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400378926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1400378926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/181.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/182.uart_fifo_reset.1443315073 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 17485548913 ps |
| CPU time | 48.45 seconds |
| Started | Oct 12 02:04:25 PM UTC 24 |
| Finished | Oct 12 02:05:15 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443315073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1443315073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/182.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/183.uart_fifo_reset.1629332121 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 153576083036 ps |
| CPU time | 184.07 seconds |
| Started | Oct 12 02:04:29 PM UTC 24 |
| Finished | Oct 12 02:07:36 PM UTC 24 |
| Peak memory | 208676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629332121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1629332121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/183.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/184.uart_fifo_reset.4195786701 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 7733868950 ps |
| CPU time | 11.15 seconds |
| Started | Oct 12 02:04:32 PM UTC 24 |
| Finished | Oct 12 02:04:44 PM UTC 24 |
| Peak memory | 207356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195786701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.4195786701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/184.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/185.uart_fifo_reset.590718433 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 77770734716 ps |
| CPU time | 200.32 seconds |
| Started | Oct 12 02:04:33 PM UTC 24 |
| Finished | Oct 12 02:07:57 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590718433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.590718433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/185.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/186.uart_fifo_reset.838415692 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 138837751038 ps |
| CPU time | 44.7 seconds |
| Started | Oct 12 02:04:34 PM UTC 24 |
| Finished | Oct 12 02:05:20 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838415692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.838415692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/186.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/187.uart_fifo_reset.1880145239 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 39203617282 ps |
| CPU time | 48.6 seconds |
| Started | Oct 12 02:04:35 PM UTC 24 |
| Finished | Oct 12 02:05:25 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880145239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1880145239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/187.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/188.uart_fifo_reset.4126790829 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 121629018388 ps |
| CPU time | 169.35 seconds |
| Started | Oct 12 02:04:35 PM UTC 24 |
| Finished | Oct 12 02:07:27 PM UTC 24 |
| Peak memory | 208876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126790829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.4126790829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/188.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/189.uart_fifo_reset.2471866791 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 5567742034 ps |
| CPU time | 6.53 seconds |
| Started | Oct 12 02:04:36 PM UTC 24 |
| Finished | Oct 12 02:04:43 PM UTC 24 |
| Peak memory | 207228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471866791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2471866791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/189.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_alert_test.125453423 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 11545795 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 01:37:36 PM UTC 24 |
| Finished | Oct 12 01:37:38 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125453423 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.125453423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_fifo_full.1756416058 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 34960095175 ps |
| CPU time | 97.25 seconds |
| Started | Oct 12 01:37:13 PM UTC 24 |
| Finished | Oct 12 01:38:53 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756416058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1756416058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.2318697745 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 305843744815 ps |
| CPU time | 164.99 seconds |
| Started | Oct 12 01:37:13 PM UTC 24 |
| Finished | Oct 12 01:40:01 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318697745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2318697745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_fifo_reset.3630996687 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 25127880860 ps |
| CPU time | 24.7 seconds |
| Started | Oct 12 01:37:18 PM UTC 24 |
| Finished | Oct 12 01:37:45 PM UTC 24 |
| Peak memory | 208388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630996687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3630996687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_intr.1243715959 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 14514917460 ps |
| CPU time | 14.62 seconds |
| Started | Oct 12 01:37:22 PM UTC 24 |
| Finished | Oct 12 01:37:37 PM UTC 24 |
| Peak memory | 207352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243715959 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1243715959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.3464782025 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 165687051105 ps |
| CPU time | 324.45 seconds |
| Started | Oct 12 01:37:34 PM UTC 24 |
| Finished | Oct 12 01:43:03 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464782025 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3464782025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_loopback.3926274829 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 6182228676 ps |
| CPU time | 23.89 seconds |
| Started | Oct 12 01:37:33 PM UTC 24 |
| Finished | Oct 12 01:37:58 PM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926274829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3926274829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_noise_filter.1583395348 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 56535523378 ps |
| CPU time | 79.28 seconds |
| Started | Oct 12 01:37:23 PM UTC 24 |
| Finished | Oct 12 01:38:44 PM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583395348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1583395348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_perf.900432775 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 4404935214 ps |
| CPU time | 82.85 seconds |
| Started | Oct 12 01:37:33 PM UTC 24 |
| Finished | Oct 12 01:38:58 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900432775 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.900432775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_rx_oversample.3455008892 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 3081678378 ps |
| CPU time | 17.33 seconds |
| Started | Oct 12 01:37:20 PM UTC 24 |
| Finished | Oct 12 01:37:38 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455008892 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3455008892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.3351234418 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 113639945679 ps |
| CPU time | 156.9 seconds |
| Started | Oct 12 01:37:31 PM UTC 24 |
| Finished | Oct 12 01:40:10 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351234418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3351234418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.877891525 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 4055730381 ps |
| CPU time | 4.52 seconds |
| Started | Oct 12 01:37:25 PM UTC 24 |
| Finished | Oct 12 01:37:30 PM UTC 24 |
| Peak memory | 205248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877891525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.877891525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_smoke.376426995 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 750015547 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 01:37:10 PM UTC 24 |
| Finished | Oct 12 01:37:13 PM UTC 24 |
| Peak memory | 206260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376426995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 19.uart_smoke.376426995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_stress_all.281404594 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 215967301399 ps |
| CPU time | 327.25 seconds |
| Started | Oct 12 01:37:36 PM UTC 24 |
| Finished | Oct 12 01:43:08 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281404594 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.281404594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.2145851474 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1210666807 ps |
| CPU time | 2.56 seconds |
| Started | Oct 12 01:37:32 PM UTC 24 |
| Finished | Oct 12 01:37:36 PM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145851474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2145851474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_tx_rx.1760349604 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 68228203341 ps |
| CPU time | 147.68 seconds |
| Started | Oct 12 01:37:12 PM UTC 24 |
| Finished | Oct 12 01:39:42 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760349604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1760349604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/19.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/191.uart_fifo_reset.435491274 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 119564751289 ps |
| CPU time | 244.97 seconds |
| Started | Oct 12 02:04:38 PM UTC 24 |
| Finished | Oct 12 02:08:46 PM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435491274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.435491274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/191.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/192.uart_fifo_reset.208647210 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 98590818771 ps |
| CPU time | 54.72 seconds |
| Started | Oct 12 02:04:44 PM UTC 24 |
| Finished | Oct 12 02:05:40 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208647210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.208647210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/192.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3417795891 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 17956362101 ps |
| CPU time | 18.24 seconds |
| Started | Oct 12 02:04:44 PM UTC 24 |
| Finished | Oct 12 02:05:03 PM UTC 24 |
| Peak memory | 208812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417795891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3417795891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/193.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/194.uart_fifo_reset.1965478984 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 44682302675 ps |
| CPU time | 62.89 seconds |
| Started | Oct 12 02:04:45 PM UTC 24 |
| Finished | Oct 12 02:05:49 PM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965478984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1965478984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/194.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/196.uart_fifo_reset.361946955 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 23028221369 ps |
| CPU time | 23.78 seconds |
| Started | Oct 12 02:04:48 PM UTC 24 |
| Finished | Oct 12 02:05:13 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361946955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.361946955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/196.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/198.uart_fifo_reset.224756143 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 26858180042 ps |
| CPU time | 70.33 seconds |
| Started | Oct 12 02:04:54 PM UTC 24 |
| Finished | Oct 12 02:06:06 PM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224756143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.224756143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/198.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/199.uart_fifo_reset.3271477100 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 22339912840 ps |
| CPU time | 67.47 seconds |
| Started | Oct 12 02:04:56 PM UTC 24 |
| Finished | Oct 12 02:06:06 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271477100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3271477100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/199.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_alert_test.2346126769 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 34505269 ps |
| CPU time | 0.72 seconds |
| Started | Oct 12 01:29:18 PM UTC 24 |
| Finished | Oct 12 01:29:20 PM UTC 24 |
| Peak memory | 201980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346126769 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2346126769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_fifo_full.1859271144 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 28274279064 ps |
| CPU time | 14.79 seconds |
| Started | Oct 12 01:29:13 PM UTC 24 |
| Finished | Oct 12 01:29:29 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859271144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1859271144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.3211408769 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 80765132434 ps |
| CPU time | 51.25 seconds |
| Started | Oct 12 01:29:13 PM UTC 24 |
| Finished | Oct 12 01:30:06 PM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211408769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3211408769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_intr.1831168029 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 18947646257 ps |
| CPU time | 19.59 seconds |
| Started | Oct 12 01:29:13 PM UTC 24 |
| Finished | Oct 12 01:29:34 PM UTC 24 |
| Peak memory | 207164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831168029 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1831168029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_loopback.1553832376 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3489682169 ps |
| CPU time | 11.21 seconds |
| Started | Oct 12 01:29:15 PM UTC 24 |
| Finished | Oct 12 01:29:27 PM UTC 24 |
| Peak memory | 205240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553832376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1553832376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_noise_filter.496011640 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 239781314219 ps |
| CPU time | 121.73 seconds |
| Started | Oct 12 01:29:13 PM UTC 24 |
| Finished | Oct 12 01:31:17 PM UTC 24 |
| Peak memory | 217576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496011640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.496011640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_perf.132770871 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 13196825999 ps |
| CPU time | 846.84 seconds |
| Started | Oct 12 01:29:17 PM UTC 24 |
| Finished | Oct 12 01:43:34 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132770871 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.132770871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_rx_oversample.2708019929 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2344899710 ps |
| CPU time | 2.54 seconds |
| Started | Oct 12 01:29:13 PM UTC 24 |
| Finished | Oct 12 01:29:17 PM UTC 24 |
| Peak memory | 207492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708019929 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2708019929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.3009204485 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 166291862721 ps |
| CPU time | 318.19 seconds |
| Started | Oct 12 01:29:14 PM UTC 24 |
| Finished | Oct 12 01:34:36 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009204485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3009204485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.525959140 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 38874323860 ps |
| CPU time | 50.78 seconds |
| Started | Oct 12 01:29:13 PM UTC 24 |
| Finished | Oct 12 01:30:06 PM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525959140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.525959140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_sec_cm.1545291424 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 57239984 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 01:29:18 PM UTC 24 |
| Finished | Oct 12 01:29:20 PM UTC 24 |
| Peak memory | 240112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545291424 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1545291424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_smoke.2027405055 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 525871257 ps |
| CPU time | 3.86 seconds |
| Started | Oct 12 01:29:11 PM UTC 24 |
| Finished | Oct 12 01:29:16 PM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027405055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2027405055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.3021113921 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2043562579 ps |
| CPU time | 3.82 seconds |
| Started | Oct 12 01:29:15 PM UTC 24 |
| Finished | Oct 12 01:29:19 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021113921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3021113921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/2.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_alert_test.783680285 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 62142969 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 01:38:32 PM UTC 24 |
| Finished | Oct 12 01:38:34 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783680285 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.783680285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_fifo_full.3865754162 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 220340335071 ps |
| CPU time | 192.85 seconds |
| Started | Oct 12 01:37:39 PM UTC 24 |
| Finished | Oct 12 01:40:55 PM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865754162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3865754162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_fifo_reset.425325901 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 53058456760 ps |
| CPU time | 46.6 seconds |
| Started | Oct 12 01:37:43 PM UTC 24 |
| Finished | Oct 12 01:38:31 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425325901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.425325901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_intr.3952492751 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 40616872746 ps |
| CPU time | 113.95 seconds |
| Started | Oct 12 01:37:47 PM UTC 24 |
| Finished | Oct 12 01:39:43 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952492751 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3952492751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.2398334396 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 62213027008 ps |
| CPU time | 565.02 seconds |
| Started | Oct 12 01:38:12 PM UTC 24 |
| Finished | Oct 12 01:47:44 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398334396 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2398334396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_loopback.730681206 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 3915409935 ps |
| CPU time | 4.88 seconds |
| Started | Oct 12 01:38:05 PM UTC 24 |
| Finished | Oct 12 01:38:11 PM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730681206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 20.uart_loopback.730681206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_noise_filter.2011793843 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 272934865312 ps |
| CPU time | 209.94 seconds |
| Started | Oct 12 01:37:48 PM UTC 24 |
| Finished | Oct 12 01:41:21 PM UTC 24 |
| Peak memory | 207500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011793843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2011793843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_perf.2998147602 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 17934031539 ps |
| CPU time | 971.2 seconds |
| Started | Oct 12 01:38:06 PM UTC 24 |
| Finished | Oct 12 01:54:28 PM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998147602 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2998147602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_rx_oversample.2359810179 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 4016374902 ps |
| CPU time | 26.24 seconds |
| Started | Oct 12 01:37:45 PM UTC 24 |
| Finished | Oct 12 01:38:13 PM UTC 24 |
| Peak memory | 207412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359810179 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2359810179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.467348843 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 50896040820 ps |
| CPU time | 137.53 seconds |
| Started | Oct 12 01:37:56 PM UTC 24 |
| Finished | Oct 12 01:40:16 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467348843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.467348843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.2047452407 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 41506791849 ps |
| CPU time | 73.66 seconds |
| Started | Oct 12 01:37:49 PM UTC 24 |
| Finished | Oct 12 01:39:05 PM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047452407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2047452407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_smoke.1342854146 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 903544355 ps |
| CPU time | 3.3 seconds |
| Started | Oct 12 01:37:38 PM UTC 24 |
| Finished | Oct 12 01:37:42 PM UTC 24 |
| Peak memory | 207300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342854146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1342854146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_stress_all.1912293005 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 65762916249 ps |
| CPU time | 44.29 seconds |
| Started | Oct 12 01:38:19 PM UTC 24 |
| Finished | Oct 12 01:39:05 PM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912293005 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1912293005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.3686222109 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 17832696119 ps |
| CPU time | 37.21 seconds |
| Started | Oct 12 01:38:13 PM UTC 24 |
| Finished | Oct 12 01:38:52 PM UTC 24 |
| Peak memory | 217784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3686222109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all _with_rand_reset.3686222109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.1159243761 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 535386888 ps |
| CPU time | 3.81 seconds |
| Started | Oct 12 01:37:59 PM UTC 24 |
| Finished | Oct 12 01:38:04 PM UTC 24 |
| Peak memory | 207560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159243761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1159243761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_tx_rx.2515699322 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 32361650185 ps |
| CPU time | 61.62 seconds |
| Started | Oct 12 01:37:39 PM UTC 24 |
| Finished | Oct 12 01:38:42 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515699322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2515699322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/20.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/200.uart_fifo_reset.271904161 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 107783977969 ps |
| CPU time | 198.24 seconds |
| Started | Oct 12 02:04:57 PM UTC 24 |
| Finished | Oct 12 02:08:19 PM UTC 24 |
| Peak memory | 208532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271904161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.271904161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/200.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/201.uart_fifo_reset.125004182 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 40526466621 ps |
| CPU time | 28.54 seconds |
| Started | Oct 12 02:04:59 PM UTC 24 |
| Finished | Oct 12 02:05:28 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125004182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.125004182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/201.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3466248188 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 80367445372 ps |
| CPU time | 32.89 seconds |
| Started | Oct 12 02:05:00 PM UTC 24 |
| Finished | Oct 12 02:05:34 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466248188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3466248188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/202.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2618179634 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 293089743133 ps |
| CPU time | 41.22 seconds |
| Started | Oct 12 02:05:01 PM UTC 24 |
| Finished | Oct 12 02:05:43 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618179634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2618179634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/203.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2219004021 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 98975215743 ps |
| CPU time | 39.06 seconds |
| Started | Oct 12 02:05:01 PM UTC 24 |
| Finished | Oct 12 02:05:41 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219004021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2219004021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/204.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/205.uart_fifo_reset.606017795 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 106832609760 ps |
| CPU time | 105.06 seconds |
| Started | Oct 12 02:05:02 PM UTC 24 |
| Finished | Oct 12 02:06:49 PM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606017795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.606017795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/205.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2774670438 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 85557554715 ps |
| CPU time | 257.4 seconds |
| Started | Oct 12 02:05:04 PM UTC 24 |
| Finished | Oct 12 02:09:25 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774670438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2774670438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/206.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/207.uart_fifo_reset.197960357 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 15588794733 ps |
| CPU time | 15.87 seconds |
| Started | Oct 12 02:05:07 PM UTC 24 |
| Finished | Oct 12 02:05:24 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197960357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.197960357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/207.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/208.uart_fifo_reset.4024497137 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 61278044834 ps |
| CPU time | 51.97 seconds |
| Started | Oct 12 02:05:13 PM UTC 24 |
| Finished | Oct 12 02:06:07 PM UTC 24 |
| Peak memory | 208532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024497137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.4024497137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/208.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/209.uart_fifo_reset.972595538 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 20277135632 ps |
| CPU time | 35.88 seconds |
| Started | Oct 12 02:05:13 PM UTC 24 |
| Finished | Oct 12 02:05:51 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972595538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.972595538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/209.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_alert_test.2386767882 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 28808748 ps |
| CPU time | 0.83 seconds |
| Started | Oct 12 01:39:06 PM UTC 24 |
| Finished | Oct 12 01:39:07 PM UTC 24 |
| Peak memory | 202340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386767882 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2386767882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_fifo_full.621753207 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 114201404857 ps |
| CPU time | 112.18 seconds |
| Started | Oct 12 01:38:42 PM UTC 24 |
| Finished | Oct 12 01:40:36 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621753207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.621753207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.3840292106 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 24160509665 ps |
| CPU time | 40.03 seconds |
| Started | Oct 12 01:38:43 PM UTC 24 |
| Finished | Oct 12 01:39:25 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840292106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3840292106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_fifo_reset.3627836139 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 184223998540 ps |
| CPU time | 107.44 seconds |
| Started | Oct 12 01:38:44 PM UTC 24 |
| Finished | Oct 12 01:40:34 PM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627836139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3627836139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_intr.2808550730 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 193215283576 ps |
| CPU time | 28.69 seconds |
| Started | Oct 12 01:38:47 PM UTC 24 |
| Finished | Oct 12 01:39:17 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808550730 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2808550730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.505364135 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 145253585147 ps |
| CPU time | 896.25 seconds |
| Started | Oct 12 01:38:58 PM UTC 24 |
| Finished | Oct 12 01:54:05 PM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505364135 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.505364135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_loopback.723448397 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 7621800613 ps |
| CPU time | 29.27 seconds |
| Started | Oct 12 01:38:58 PM UTC 24 |
| Finished | Oct 12 01:39:29 PM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723448397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 21.uart_loopback.723448397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_noise_filter.1371139728 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 336549605984 ps |
| CPU time | 239.08 seconds |
| Started | Oct 12 01:38:47 PM UTC 24 |
| Finished | Oct 12 01:42:49 PM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371139728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1371139728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_perf.1134195482 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 14530880990 ps |
| CPU time | 982.7 seconds |
| Started | Oct 12 01:38:58 PM UTC 24 |
| Finished | Oct 12 01:55:32 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134195482 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1134195482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_rx_oversample.2870324336 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 5643501373 ps |
| CPU time | 14.82 seconds |
| Started | Oct 12 01:38:46 PM UTC 24 |
| Finished | Oct 12 01:39:02 PM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870324336 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2870324336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.2797599932 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 52698719056 ps |
| CPU time | 31.47 seconds |
| Started | Oct 12 01:38:53 PM UTC 24 |
| Finished | Oct 12 01:39:26 PM UTC 24 |
| Peak memory | 208684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797599932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2797599932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.1900987317 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 3883384447 ps |
| CPU time | 7.31 seconds |
| Started | Oct 12 01:38:49 PM UTC 24 |
| Finished | Oct 12 01:38:57 PM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900987317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1900987317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_smoke.3019273955 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 5901933552 ps |
| CPU time | 11.37 seconds |
| Started | Oct 12 01:38:35 PM UTC 24 |
| Finished | Oct 12 01:38:48 PM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019273955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3019273955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_stress_all.720964752 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 200580161661 ps |
| CPU time | 876.83 seconds |
| Started | Oct 12 01:39:02 PM UTC 24 |
| Finished | Oct 12 01:53:51 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720964752 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.720964752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.2478196306 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 4271234290 ps |
| CPU time | 80.06 seconds |
| Started | Oct 12 01:39:00 PM UTC 24 |
| Finished | Oct 12 01:40:22 PM UTC 24 |
| Peak memory | 219900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2478196306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all _with_rand_reset.2478196306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.922817393 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 957510405 ps |
| CPU time | 2.54 seconds |
| Started | Oct 12 01:38:54 PM UTC 24 |
| Finished | Oct 12 01:38:58 PM UTC 24 |
| Peak memory | 207304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922817393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.922817393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/21.uart_tx_rx.1633355301 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 330678873469 ps |
| CPU time | 48.54 seconds |
| Started | Oct 12 01:38:42 PM UTC 24 |
| Finished | Oct 12 01:39:32 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633355301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1633355301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/21.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/210.uart_fifo_reset.394109349 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 18926713019 ps |
| CPU time | 42.57 seconds |
| Started | Oct 12 02:05:13 PM UTC 24 |
| Finished | Oct 12 02:05:57 PM UTC 24 |
| Peak memory | 208656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394109349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.394109349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/210.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/211.uart_fifo_reset.3159561787 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 31601510279 ps |
| CPU time | 35.04 seconds |
| Started | Oct 12 02:05:14 PM UTC 24 |
| Finished | Oct 12 02:05:51 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159561787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3159561787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/211.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/212.uart_fifo_reset.3761121324 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 64298014737 ps |
| CPU time | 47.77 seconds |
| Started | Oct 12 02:05:16 PM UTC 24 |
| Finished | Oct 12 02:06:06 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761121324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3761121324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/212.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/214.uart_fifo_reset.2556941523 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 247153904926 ps |
| CPU time | 107.55 seconds |
| Started | Oct 12 02:05:22 PM UTC 24 |
| Finished | Oct 12 02:07:11 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556941523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2556941523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/214.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/216.uart_fifo_reset.2499998355 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 5822691249 ps |
| CPU time | 19.33 seconds |
| Started | Oct 12 02:05:25 PM UTC 24 |
| Finished | Oct 12 02:05:45 PM UTC 24 |
| Peak memory | 207800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499998355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2499998355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/216.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/217.uart_fifo_reset.3191346821 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 7453246984 ps |
| CPU time | 22.05 seconds |
| Started | Oct 12 02:05:26 PM UTC 24 |
| Finished | Oct 12 02:05:49 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191346821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3191346821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/217.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/218.uart_fifo_reset.3040343590 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 28486628092 ps |
| CPU time | 16.51 seconds |
| Started | Oct 12 02:05:29 PM UTC 24 |
| Finished | Oct 12 02:05:47 PM UTC 24 |
| Peak memory | 208560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040343590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3040343590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/218.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/219.uart_fifo_reset.4166630349 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 13002045102 ps |
| CPU time | 26.01 seconds |
| Started | Oct 12 02:05:33 PM UTC 24 |
| Finished | Oct 12 02:06:00 PM UTC 24 |
| Peak memory | 208920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166630349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.4166630349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/219.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_alert_test.1890010615 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 16987082 ps |
| CPU time | 0.87 seconds |
| Started | Oct 12 01:39:43 PM UTC 24 |
| Finished | Oct 12 01:39:45 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890010615 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1890010615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_fifo_full.1132038103 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 52458457507 ps |
| CPU time | 172.04 seconds |
| Started | Oct 12 01:39:18 PM UTC 24 |
| Finished | Oct 12 01:42:13 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132038103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1132038103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.4256236930 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 93855531703 ps |
| CPU time | 79.69 seconds |
| Started | Oct 12 01:39:18 PM UTC 24 |
| Finished | Oct 12 01:40:39 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256236930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.4256236930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_intr.4260363554 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 4226402528 ps |
| CPU time | 3.24 seconds |
| Started | Oct 12 01:39:26 PM UTC 24 |
| Finished | Oct 12 01:39:30 PM UTC 24 |
| Peak memory | 208556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260363554 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.4260363554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.1574840397 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 73524265122 ps |
| CPU time | 350.1 seconds |
| Started | Oct 12 01:39:37 PM UTC 24 |
| Finished | Oct 12 01:45:32 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574840397 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1574840397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_loopback.80693586 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 6142202579 ps |
| CPU time | 37.37 seconds |
| Started | Oct 12 01:39:35 PM UTC 24 |
| Finished | Oct 12 01:40:13 PM UTC 24 |
| Peak memory | 208740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80693586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 22.uart_loopback.80693586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_noise_filter.3135345695 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 111329324370 ps |
| CPU time | 31.14 seconds |
| Started | Oct 12 01:39:29 PM UTC 24 |
| Finished | Oct 12 01:40:02 PM UTC 24 |
| Peak memory | 208864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135345695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3135345695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_perf.1864180736 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 9668429174 ps |
| CPU time | 287.94 seconds |
| Started | Oct 12 01:39:36 PM UTC 24 |
| Finished | Oct 12 01:44:28 PM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864180736 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1864180736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_rx_oversample.3220624441 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 3249269382 ps |
| CPU time | 8.26 seconds |
| Started | Oct 12 01:39:26 PM UTC 24 |
| Finished | Oct 12 01:39:35 PM UTC 24 |
| Peak memory | 207488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220624441 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3220624441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.1571987531 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 47518299772 ps |
| CPU time | 31.75 seconds |
| Started | Oct 12 01:39:31 PM UTC 24 |
| Finished | Oct 12 01:40:05 PM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571987531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1571987531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.1798077112 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 4815439879 ps |
| CPU time | 2.78 seconds |
| Started | Oct 12 01:39:31 PM UTC 24 |
| Finished | Oct 12 01:39:35 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798077112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1798077112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_smoke.3663859712 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 6215830288 ps |
| CPU time | 13.03 seconds |
| Started | Oct 12 01:39:06 PM UTC 24 |
| Finished | Oct 12 01:39:20 PM UTC 24 |
| Peak memory | 208344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663859712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3663859712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_stress_all.4288218714 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 217086544049 ps |
| CPU time | 390.29 seconds |
| Started | Oct 12 01:39:42 PM UTC 24 |
| Finished | Oct 12 01:46:17 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288218714 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.4288218714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.2397601772 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3217050574 ps |
| CPU time | 51.57 seconds |
| Started | Oct 12 01:39:40 PM UTC 24 |
| Finished | Oct 12 01:40:33 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2397601772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all _with_rand_reset.2397601772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.984601257 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2053973973 ps |
| CPU time | 4.01 seconds |
| Started | Oct 12 01:39:33 PM UTC 24 |
| Finished | Oct 12 01:39:39 PM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984601257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.984601257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_tx_rx.2373992460 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 90177548361 ps |
| CPU time | 311.08 seconds |
| Started | Oct 12 01:39:09 PM UTC 24 |
| Finished | Oct 12 01:44:24 PM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373992460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2373992460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/22.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/220.uart_fifo_reset.1521051842 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 11381920115 ps |
| CPU time | 22.14 seconds |
| Started | Oct 12 02:05:35 PM UTC 24 |
| Finished | Oct 12 02:05:59 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521051842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1521051842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/220.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/222.uart_fifo_reset.2898100704 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 95011317664 ps |
| CPU time | 67.37 seconds |
| Started | Oct 12 02:05:40 PM UTC 24 |
| Finished | Oct 12 02:06:49 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898100704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2898100704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/222.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/223.uart_fifo_reset.3819051254 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 136966596717 ps |
| CPU time | 62.48 seconds |
| Started | Oct 12 02:05:42 PM UTC 24 |
| Finished | Oct 12 02:06:46 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819051254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3819051254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/223.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/224.uart_fifo_reset.2182219074 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 53745845933 ps |
| CPU time | 36.57 seconds |
| Started | Oct 12 02:05:45 PM UTC 24 |
| Finished | Oct 12 02:06:22 PM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182219074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2182219074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/224.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/225.uart_fifo_reset.1146866563 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 67003761186 ps |
| CPU time | 116.88 seconds |
| Started | Oct 12 02:05:46 PM UTC 24 |
| Finished | Oct 12 02:07:44 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146866563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1146866563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/225.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/226.uart_fifo_reset.4184716381 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 103018775233 ps |
| CPU time | 56.83 seconds |
| Started | Oct 12 02:05:47 PM UTC 24 |
| Finished | Oct 12 02:06:45 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184716381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.4184716381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/226.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/228.uart_fifo_reset.2364231043 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 43380031942 ps |
| CPU time | 35.28 seconds |
| Started | Oct 12 02:05:48 PM UTC 24 |
| Finished | Oct 12 02:06:25 PM UTC 24 |
| Peak memory | 208960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364231043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2364231043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/228.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/229.uart_fifo_reset.2394972472 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 84958478650 ps |
| CPU time | 31 seconds |
| Started | Oct 12 02:05:48 PM UTC 24 |
| Finished | Oct 12 02:06:20 PM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394972472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2394972472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/229.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_alert_test.625445322 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 48576986 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 01:40:25 PM UTC 24 |
| Finished | Oct 12 01:40:27 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625445322 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.625445322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_fifo_full.323530784 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 89112408158 ps |
| CPU time | 103.07 seconds |
| Started | Oct 12 01:39:48 PM UTC 24 |
| Finished | Oct 12 01:41:33 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323530784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.323530784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.2976008856 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 102102796457 ps |
| CPU time | 98.08 seconds |
| Started | Oct 12 01:39:53 PM UTC 24 |
| Finished | Oct 12 01:41:33 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976008856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2976008856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_fifo_reset.2781275905 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 258770831202 ps |
| CPU time | 92.95 seconds |
| Started | Oct 12 01:39:57 PM UTC 24 |
| Finished | Oct 12 01:41:32 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781275905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2781275905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_intr.1284963314 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 33327433596 ps |
| CPU time | 16.68 seconds |
| Started | Oct 12 01:40:03 PM UTC 24 |
| Finished | Oct 12 01:40:21 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284963314 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1284963314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.332791547 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 147430267173 ps |
| CPU time | 307.44 seconds |
| Started | Oct 12 01:40:20 PM UTC 24 |
| Finished | Oct 12 01:45:32 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332791547 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.332791547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_loopback.2471445740 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 7033132839 ps |
| CPU time | 13.26 seconds |
| Started | Oct 12 01:40:19 PM UTC 24 |
| Finished | Oct 12 01:40:34 PM UTC 24 |
| Peak memory | 208284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471445740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2471445740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_noise_filter.3543777427 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 72184676143 ps |
| CPU time | 65.95 seconds |
| Started | Oct 12 01:40:06 PM UTC 24 |
| Finished | Oct 12 01:41:13 PM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543777427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3543777427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_perf.413923085 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 18692632422 ps |
| CPU time | 257.14 seconds |
| Started | Oct 12 01:40:19 PM UTC 24 |
| Finished | Oct 12 01:44:40 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413923085 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.413923085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_rx_oversample.1323051782 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 3690353289 ps |
| CPU time | 43.08 seconds |
| Started | Oct 12 01:40:02 PM UTC 24 |
| Finished | Oct 12 01:40:46 PM UTC 24 |
| Peak memory | 207488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323051782 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1323051782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.2490931626 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 44066530331 ps |
| CPU time | 68.61 seconds |
| Started | Oct 12 01:40:14 PM UTC 24 |
| Finished | Oct 12 01:41:24 PM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490931626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2490931626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.2797376188 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1482358828 ps |
| CPU time | 6.34 seconds |
| Started | Oct 12 01:40:11 PM UTC 24 |
| Finished | Oct 12 01:40:18 PM UTC 24 |
| Peak memory | 205240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797376188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2797376188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_smoke.2689945665 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 557260392 ps |
| CPU time | 2.63 seconds |
| Started | Oct 12 01:39:44 PM UTC 24 |
| Finished | Oct 12 01:39:48 PM UTC 24 |
| Peak memory | 207408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689945665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2689945665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_stress_all.625944748 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 176629622264 ps |
| CPU time | 1509.4 seconds |
| Started | Oct 12 01:40:23 PM UTC 24 |
| Finished | Oct 12 02:05:51 PM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625944748 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.625944748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.1962246133 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 23683007730 ps |
| CPU time | 51.08 seconds |
| Started | Oct 12 01:40:21 PM UTC 24 |
| Finished | Oct 12 01:41:14 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1962246133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all _with_rand_reset.1962246133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.4269768420 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 12334740318 ps |
| CPU time | 24.05 seconds |
| Started | Oct 12 01:40:17 PM UTC 24 |
| Finished | Oct 12 01:40:43 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269768420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.4269768420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/23.uart_tx_rx.3242557333 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 64194952551 ps |
| CPU time | 32.36 seconds |
| Started | Oct 12 01:39:46 PM UTC 24 |
| Finished | Oct 12 01:40:20 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242557333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3242557333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/23.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3216028066 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 141885426642 ps |
| CPU time | 229.43 seconds |
| Started | Oct 12 02:05:50 PM UTC 24 |
| Finished | Oct 12 02:09:43 PM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216028066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3216028066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/230.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/231.uart_fifo_reset.2310840486 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 150017978901 ps |
| CPU time | 51.34 seconds |
| Started | Oct 12 02:05:50 PM UTC 24 |
| Finished | Oct 12 02:06:43 PM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310840486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2310840486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/231.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/232.uart_fifo_reset.2480175427 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 47219704922 ps |
| CPU time | 134.36 seconds |
| Started | Oct 12 02:05:51 PM UTC 24 |
| Finished | Oct 12 02:08:08 PM UTC 24 |
| Peak memory | 208520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480175427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2480175427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/232.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2365516569 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 157207887221 ps |
| CPU time | 251.72 seconds |
| Started | Oct 12 02:05:51 PM UTC 24 |
| Finished | Oct 12 02:10:06 PM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365516569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2365516569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/233.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/234.uart_fifo_reset.1766809447 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 104451323834 ps |
| CPU time | 134.4 seconds |
| Started | Oct 12 02:05:51 PM UTC 24 |
| Finished | Oct 12 02:08:08 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766809447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1766809447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/234.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/235.uart_fifo_reset.6888098 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 47717722472 ps |
| CPU time | 31.19 seconds |
| Started | Oct 12 02:05:53 PM UTC 24 |
| Finished | Oct 12 02:06:26 PM UTC 24 |
| Peak memory | 207388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6888098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.6888098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/235.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/236.uart_fifo_reset.2097331924 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 58717986033 ps |
| CPU time | 49.21 seconds |
| Started | Oct 12 02:05:54 PM UTC 24 |
| Finished | Oct 12 02:06:45 PM UTC 24 |
| Peak memory | 208580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097331924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2097331924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/236.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/237.uart_fifo_reset.2307069813 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 108531617506 ps |
| CPU time | 53.54 seconds |
| Started | Oct 12 02:05:57 PM UTC 24 |
| Finished | Oct 12 02:06:51 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307069813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2307069813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/237.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/238.uart_fifo_reset.3236816990 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 6784809595 ps |
| CPU time | 18.06 seconds |
| Started | Oct 12 02:05:57 PM UTC 24 |
| Finished | Oct 12 02:06:16 PM UTC 24 |
| Peak memory | 208408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236816990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3236816990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/238.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1373795820 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 25943701830 ps |
| CPU time | 70.18 seconds |
| Started | Oct 12 02:05:58 PM UTC 24 |
| Finished | Oct 12 02:07:10 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373795820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1373795820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/239.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_alert_test.3818024561 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 43207630 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 01:41:08 PM UTC 24 |
| Finished | Oct 12 01:41:10 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818024561 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3818024561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_fifo_full.901461094 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 148057143932 ps |
| CPU time | 93.62 seconds |
| Started | Oct 12 01:40:34 PM UTC 24 |
| Finished | Oct 12 01:42:09 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901461094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.901461094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.3400075419 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 13529569038 ps |
| CPU time | 38.51 seconds |
| Started | Oct 12 01:40:35 PM UTC 24 |
| Finished | Oct 12 01:41:15 PM UTC 24 |
| Peak memory | 208336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400075419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3400075419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_fifo_reset.3764409324 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 77125255243 ps |
| CPU time | 145.36 seconds |
| Started | Oct 12 01:40:35 PM UTC 24 |
| Finished | Oct 12 01:43:03 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764409324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3764409324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_intr.156704393 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 14934218889 ps |
| CPU time | 14.88 seconds |
| Started | Oct 12 01:40:39 PM UTC 24 |
| Finished | Oct 12 01:40:55 PM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156704393 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.156704393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.2841429767 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 197851642637 ps |
| CPU time | 453.11 seconds |
| Started | Oct 12 01:40:56 PM UTC 24 |
| Finished | Oct 12 01:48:34 PM UTC 24 |
| Peak memory | 208624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841429767 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2841429767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_loopback.3175687709 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 3040123620 ps |
| CPU time | 4.5 seconds |
| Started | Oct 12 01:40:53 PM UTC 24 |
| Finished | Oct 12 01:40:58 PM UTC 24 |
| Peak memory | 207480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175687709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3175687709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_noise_filter.4135117106 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 7962319099 ps |
| CPU time | 25.46 seconds |
| Started | Oct 12 01:40:40 PM UTC 24 |
| Finished | Oct 12 01:41:07 PM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135117106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4135117106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_perf.2368121435 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 18261751843 ps |
| CPU time | 1427.31 seconds |
| Started | Oct 12 01:40:56 PM UTC 24 |
| Finished | Oct 12 02:04:59 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368121435 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2368121435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_rx_oversample.1226989822 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1475080415 ps |
| CPU time | 9.24 seconds |
| Started | Oct 12 01:40:37 PM UTC 24 |
| Finished | Oct 12 01:40:47 PM UTC 24 |
| Peak memory | 207348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226989822 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1226989822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.592575155 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 95141137432 ps |
| CPU time | 214.1 seconds |
| Started | Oct 12 01:40:47 PM UTC 24 |
| Finished | Oct 12 01:44:25 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592575155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.592575155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.341468025 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1541153673 ps |
| CPU time | 7.23 seconds |
| Started | Oct 12 01:40:43 PM UTC 24 |
| Finished | Oct 12 01:40:52 PM UTC 24 |
| Peak memory | 205248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341468025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.341468025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_smoke.1294303403 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 407550281 ps |
| CPU time | 3 seconds |
| Started | Oct 12 01:40:28 PM UTC 24 |
| Finished | Oct 12 01:40:32 PM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294303403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1294303403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_stress_all.3253259966 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 291376437341 ps |
| CPU time | 450.31 seconds |
| Started | Oct 12 01:40:59 PM UTC 24 |
| Finished | Oct 12 01:48:35 PM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253259966 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3253259966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.35302305 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3366634619 ps |
| CPU time | 60.88 seconds |
| Started | Oct 12 01:40:56 PM UTC 24 |
| Finished | Oct 12 01:41:58 PM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=35302305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all_w ith_rand_reset.35302305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.4202778487 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 6923559031 ps |
| CPU time | 36.27 seconds |
| Started | Oct 12 01:40:49 PM UTC 24 |
| Finished | Oct 12 01:41:26 PM UTC 24 |
| Peak memory | 208216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202778487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.4202778487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/24.uart_tx_rx.2699045153 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 19374211448 ps |
| CPU time | 38.3 seconds |
| Started | Oct 12 01:40:33 PM UTC 24 |
| Finished | Oct 12 01:41:12 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699045153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2699045153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/24.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/241.uart_fifo_reset.2028486389 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 156907196735 ps |
| CPU time | 83.18 seconds |
| Started | Oct 12 02:06:00 PM UTC 24 |
| Finished | Oct 12 02:07:25 PM UTC 24 |
| Peak memory | 208960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028486389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2028486389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/241.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/242.uart_fifo_reset.1506871131 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 115165792276 ps |
| CPU time | 177.02 seconds |
| Started | Oct 12 02:06:01 PM UTC 24 |
| Finished | Oct 12 02:09:01 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506871131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1506871131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/242.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1425902875 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 85194626125 ps |
| CPU time | 65.85 seconds |
| Started | Oct 12 02:06:03 PM UTC 24 |
| Finished | Oct 12 02:07:11 PM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425902875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1425902875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/243.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/244.uart_fifo_reset.1191392199 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 62611209873 ps |
| CPU time | 13.62 seconds |
| Started | Oct 12 02:06:04 PM UTC 24 |
| Finished | Oct 12 02:06:19 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191392199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1191392199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/244.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3732862872 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 36375436645 ps |
| CPU time | 37.8 seconds |
| Started | Oct 12 02:06:05 PM UTC 24 |
| Finished | Oct 12 02:06:44 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732862872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3732862872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/245.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/246.uart_fifo_reset.1232769385 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 91706252699 ps |
| CPU time | 146.2 seconds |
| Started | Oct 12 02:06:06 PM UTC 24 |
| Finished | Oct 12 02:08:35 PM UTC 24 |
| Peak memory | 208492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232769385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1232769385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/246.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/247.uart_fifo_reset.3767275559 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 179637471140 ps |
| CPU time | 65.45 seconds |
| Started | Oct 12 02:06:06 PM UTC 24 |
| Finished | Oct 12 02:07:13 PM UTC 24 |
| Peak memory | 208488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767275559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3767275559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/247.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/248.uart_fifo_reset.4081115734 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 24035359311 ps |
| CPU time | 61.62 seconds |
| Started | Oct 12 02:06:07 PM UTC 24 |
| Finished | Oct 12 02:07:11 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081115734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.4081115734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/248.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/249.uart_fifo_reset.2087895545 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 214249756542 ps |
| CPU time | 49.37 seconds |
| Started | Oct 12 02:06:08 PM UTC 24 |
| Finished | Oct 12 02:06:58 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087895545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2087895545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/249.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_alert_test.695009314 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 25650604 ps |
| CPU time | 0.87 seconds |
| Started | Oct 12 01:41:35 PM UTC 24 |
| Finished | Oct 12 01:41:37 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695009314 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.695009314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_fifo_full.2093485983 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 68247500154 ps |
| CPU time | 83.69 seconds |
| Started | Oct 12 01:41:13 PM UTC 24 |
| Finished | Oct 12 01:42:39 PM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093485983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2093485983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.1276112829 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 273701088739 ps |
| CPU time | 213.16 seconds |
| Started | Oct 12 01:41:14 PM UTC 24 |
| Finished | Oct 12 01:44:51 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276112829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1276112829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_fifo_reset.1170113733 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 29407958682 ps |
| CPU time | 34.39 seconds |
| Started | Oct 12 01:41:14 PM UTC 24 |
| Finished | Oct 12 01:41:50 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170113733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1170113733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_intr.4193528866 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 7484659651 ps |
| CPU time | 7.8 seconds |
| Started | Oct 12 01:41:16 PM UTC 24 |
| Finished | Oct 12 01:41:25 PM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193528866 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.4193528866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.3669931874 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 109820101518 ps |
| CPU time | 174.02 seconds |
| Started | Oct 12 01:41:34 PM UTC 24 |
| Finished | Oct 12 01:44:31 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669931874 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3669931874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_loopback.3694671680 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 6158701520 ps |
| CPU time | 6.14 seconds |
| Started | Oct 12 01:41:27 PM UTC 24 |
| Finished | Oct 12 01:41:34 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694671680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3694671680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_noise_filter.4163797316 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 89211643225 ps |
| CPU time | 310.59 seconds |
| Started | Oct 12 01:41:16 PM UTC 24 |
| Finished | Oct 12 01:46:30 PM UTC 24 |
| Peak memory | 208864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163797316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.4163797316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_perf.2885101725 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 27885217527 ps |
| CPU time | 1072.69 seconds |
| Started | Oct 12 01:41:33 PM UTC 24 |
| Finished | Oct 12 01:59:37 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885101725 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2885101725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_rx_oversample.1546729158 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 2178919220 ps |
| CPU time | 18.08 seconds |
| Started | Oct 12 01:41:15 PM UTC 24 |
| Finished | Oct 12 01:41:34 PM UTC 24 |
| Peak memory | 207336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546729158 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1546729158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.3339661240 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 15322375717 ps |
| CPU time | 61.05 seconds |
| Started | Oct 12 01:41:25 PM UTC 24 |
| Finished | Oct 12 01:42:28 PM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339661240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3339661240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.691141731 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 4094754372 ps |
| CPU time | 16.33 seconds |
| Started | Oct 12 01:41:22 PM UTC 24 |
| Finished | Oct 12 01:41:39 PM UTC 24 |
| Peak memory | 205248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691141731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.691141731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_smoke.696577323 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 473507799 ps |
| CPU time | 3.71 seconds |
| Started | Oct 12 01:41:09 PM UTC 24 |
| Finished | Oct 12 01:41:14 PM UTC 24 |
| Peak memory | 207520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696577323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 25.uart_smoke.696577323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_stress_all.985760660 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 301530482504 ps |
| CPU time | 747.55 seconds |
| Started | Oct 12 01:41:34 PM UTC 24 |
| Finished | Oct 12 01:54:12 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985760660 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.985760660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.2789943522 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3527727723 ps |
| CPU time | 36.32 seconds |
| Started | Oct 12 01:41:34 PM UTC 24 |
| Finished | Oct 12 01:42:12 PM UTC 24 |
| Peak memory | 217988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2789943522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all _with_rand_reset.2789943522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.1610998469 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 9952735770 ps |
| CPU time | 20.37 seconds |
| Started | Oct 12 01:41:25 PM UTC 24 |
| Finished | Oct 12 01:41:46 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610998469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1610998469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/25.uart_tx_rx.4210672808 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 96140097512 ps |
| CPU time | 113.44 seconds |
| Started | Oct 12 01:41:11 PM UTC 24 |
| Finished | Oct 12 01:43:07 PM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210672808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.4210672808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/25.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/250.uart_fifo_reset.3998610715 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 167658470424 ps |
| CPU time | 29.32 seconds |
| Started | Oct 12 02:06:11 PM UTC 24 |
| Finished | Oct 12 02:06:41 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998610715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3998610715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/250.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/252.uart_fifo_reset.2084521860 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 37509778113 ps |
| CPU time | 37.36 seconds |
| Started | Oct 12 02:06:15 PM UTC 24 |
| Finished | Oct 12 02:06:54 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084521860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2084521860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/252.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/253.uart_fifo_reset.916335232 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 15181148892 ps |
| CPU time | 27.41 seconds |
| Started | Oct 12 02:06:17 PM UTC 24 |
| Finished | Oct 12 02:06:46 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916335232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.916335232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/253.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/254.uart_fifo_reset.654375990 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 19872467604 ps |
| CPU time | 44.96 seconds |
| Started | Oct 12 02:06:17 PM UTC 24 |
| Finished | Oct 12 02:07:03 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654375990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.654375990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/254.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/255.uart_fifo_reset.1539159501 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 117893553527 ps |
| CPU time | 107.81 seconds |
| Started | Oct 12 02:06:18 PM UTC 24 |
| Finished | Oct 12 02:08:08 PM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539159501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1539159501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/255.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/256.uart_fifo_reset.528474897 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 26564754718 ps |
| CPU time | 57.67 seconds |
| Started | Oct 12 02:06:20 PM UTC 24 |
| Finished | Oct 12 02:07:19 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528474897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.528474897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/256.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/257.uart_fifo_reset.2923469165 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 138996802471 ps |
| CPU time | 72.97 seconds |
| Started | Oct 12 02:06:21 PM UTC 24 |
| Finished | Oct 12 02:07:36 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923469165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2923469165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/257.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/258.uart_fifo_reset.456778250 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 39681805026 ps |
| CPU time | 17.24 seconds |
| Started | Oct 12 02:06:23 PM UTC 24 |
| Finished | Oct 12 02:06:42 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456778250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.456778250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/258.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/259.uart_fifo_reset.598988601 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 31752687383 ps |
| CPU time | 42.74 seconds |
| Started | Oct 12 02:06:25 PM UTC 24 |
| Finished | Oct 12 02:07:10 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598988601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.598988601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/259.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_alert_test.539948107 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 69758436 ps |
| CPU time | 0.82 seconds |
| Started | Oct 12 01:42:28 PM UTC 24 |
| Finished | Oct 12 01:42:30 PM UTC 24 |
| Peak memory | 202340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539948107 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.539948107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_fifo_full.2708924152 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 18468988806 ps |
| CPU time | 28.93 seconds |
| Started | Oct 12 01:41:44 PM UTC 24 |
| Finished | Oct 12 01:42:14 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708924152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2708924152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.2176831769 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 72337297359 ps |
| CPU time | 118.57 seconds |
| Started | Oct 12 01:41:48 PM UTC 24 |
| Finished | Oct 12 01:43:49 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176831769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2176831769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_fifo_reset.2774863553 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 9531404681 ps |
| CPU time | 33.61 seconds |
| Started | Oct 12 01:41:51 PM UTC 24 |
| Finished | Oct 12 01:42:27 PM UTC 24 |
| Peak memory | 208360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774863553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2774863553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_intr.2368025844 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 7990931850 ps |
| CPU time | 15.56 seconds |
| Started | Oct 12 01:42:04 PM UTC 24 |
| Finished | Oct 12 01:42:21 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368025844 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2368025844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.3964553267 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 62842024457 ps |
| CPU time | 139.06 seconds |
| Started | Oct 12 01:42:22 PM UTC 24 |
| Finished | Oct 12 01:44:44 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964553267 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3964553267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_loopback.1161650655 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 846032357 ps |
| CPU time | 2.52 seconds |
| Started | Oct 12 01:42:18 PM UTC 24 |
| Finished | Oct 12 01:42:21 PM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161650655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1161650655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_noise_filter.1475455081 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 53102615362 ps |
| CPU time | 92.65 seconds |
| Started | Oct 12 01:42:10 PM UTC 24 |
| Finished | Oct 12 01:43:45 PM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475455081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1475455081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_perf.3741948622 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 12647592038 ps |
| CPU time | 398.86 seconds |
| Started | Oct 12 01:42:19 PM UTC 24 |
| Finished | Oct 12 01:49:03 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741948622 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3741948622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_rx_oversample.2645114470 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 5881893388 ps |
| CPU time | 16.19 seconds |
| Started | Oct 12 01:41:59 PM UTC 24 |
| Finished | Oct 12 01:42:17 PM UTC 24 |
| Peak memory | 208008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645114470 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2645114470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.1074617347 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 86603667428 ps |
| CPU time | 29.53 seconds |
| Started | Oct 12 01:42:13 PM UTC 24 |
| Finished | Oct 12 01:42:45 PM UTC 24 |
| Peak memory | 208552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074617347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1074617347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.2323563140 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 3693404924 ps |
| CPU time | 4.13 seconds |
| Started | Oct 12 01:42:12 PM UTC 24 |
| Finished | Oct 12 01:42:18 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323563140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2323563140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_smoke.1532457691 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 454824355 ps |
| CPU time | 2.89 seconds |
| Started | Oct 12 01:41:39 PM UTC 24 |
| Finished | Oct 12 01:41:42 PM UTC 24 |
| Peak memory | 208624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532457691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1532457691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_stress_all.2102770032 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 218223702261 ps |
| CPU time | 294.86 seconds |
| Started | Oct 12 01:42:27 PM UTC 24 |
| Finished | Oct 12 01:47:26 PM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102770032 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2102770032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.2082217209 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 394018938 ps |
| CPU time | 9.97 seconds |
| Started | Oct 12 01:42:22 PM UTC 24 |
| Finished | Oct 12 01:42:33 PM UTC 24 |
| Peak memory | 209012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2082217209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all _with_rand_reset.2082217209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.2567112456 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 6770551813 ps |
| CPU time | 39.24 seconds |
| Started | Oct 12 01:42:15 PM UTC 24 |
| Finished | Oct 12 01:42:55 PM UTC 24 |
| Peak memory | 208672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567112456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2567112456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/26.uart_tx_rx.885184328 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 61102844851 ps |
| CPU time | 89.86 seconds |
| Started | Oct 12 01:41:40 PM UTC 24 |
| Finished | Oct 12 01:43:11 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885184328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.885184328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/26.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/260.uart_fifo_reset.3442848151 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 48757071870 ps |
| CPU time | 30.14 seconds |
| Started | Oct 12 02:06:25 PM UTC 24 |
| Finished | Oct 12 02:06:57 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442848151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3442848151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/260.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/261.uart_fifo_reset.353943367 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 27487814632 ps |
| CPU time | 59.01 seconds |
| Started | Oct 12 02:06:27 PM UTC 24 |
| Finished | Oct 12 02:07:27 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353943367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.353943367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/261.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/262.uart_fifo_reset.2541751555 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 29035493667 ps |
| CPU time | 48.25 seconds |
| Started | Oct 12 02:06:38 PM UTC 24 |
| Finished | Oct 12 02:07:27 PM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541751555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2541751555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/262.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/263.uart_fifo_reset.260030785 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 107549672398 ps |
| CPU time | 284.22 seconds |
| Started | Oct 12 02:06:39 PM UTC 24 |
| Finished | Oct 12 02:11:27 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260030785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.260030785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/263.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/264.uart_fifo_reset.3771994726 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 180060352410 ps |
| CPU time | 65.18 seconds |
| Started | Oct 12 02:06:42 PM UTC 24 |
| Finished | Oct 12 02:07:49 PM UTC 24 |
| Peak memory | 208732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771994726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3771994726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/264.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/265.uart_fifo_reset.1219589845 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 72035777588 ps |
| CPU time | 138.84 seconds |
| Started | Oct 12 02:06:43 PM UTC 24 |
| Finished | Oct 12 02:09:04 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219589845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1219589845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/265.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/266.uart_fifo_reset.3197014113 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 30684214897 ps |
| CPU time | 38.24 seconds |
| Started | Oct 12 02:06:44 PM UTC 24 |
| Finished | Oct 12 02:07:24 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197014113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3197014113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/266.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/267.uart_fifo_reset.1680123331 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 137370518134 ps |
| CPU time | 469.44 seconds |
| Started | Oct 12 02:06:45 PM UTC 24 |
| Finished | Oct 12 02:14:41 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680123331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1680123331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/267.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/268.uart_fifo_reset.2468085529 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 83928816860 ps |
| CPU time | 164.16 seconds |
| Started | Oct 12 02:06:46 PM UTC 24 |
| Finished | Oct 12 02:09:33 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468085529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2468085529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/268.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/269.uart_fifo_reset.3671194185 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 126033555828 ps |
| CPU time | 71.05 seconds |
| Started | Oct 12 02:06:46 PM UTC 24 |
| Finished | Oct 12 02:07:59 PM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671194185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3671194185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/269.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_alert_test.3674634892 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 18938549 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 01:43:25 PM UTC 24 |
| Finished | Oct 12 01:43:27 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674634892 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3674634892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_fifo_full.4026256411 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 37846483538 ps |
| CPU time | 34.75 seconds |
| Started | Oct 12 01:42:38 PM UTC 24 |
| Finished | Oct 12 01:43:14 PM UTC 24 |
| Peak memory | 208964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026256411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.4026256411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.1423161714 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 128739141298 ps |
| CPU time | 174.42 seconds |
| Started | Oct 12 01:42:40 PM UTC 24 |
| Finished | Oct 12 01:45:37 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423161714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1423161714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_fifo_reset.2219834365 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 184529719849 ps |
| CPU time | 163.98 seconds |
| Started | Oct 12 01:42:46 PM UTC 24 |
| Finished | Oct 12 01:45:32 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219834365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2219834365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_intr.4187025362 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 72683800308 ps |
| CPU time | 122.51 seconds |
| Started | Oct 12 01:42:56 PM UTC 24 |
| Finished | Oct 12 01:45:00 PM UTC 24 |
| Peak memory | 207380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187025362 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.4187025362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.2188451559 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 36545163801 ps |
| CPU time | 184.51 seconds |
| Started | Oct 12 01:43:14 PM UTC 24 |
| Finished | Oct 12 01:46:21 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188451559 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2188451559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_loopback.3547312177 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 3349920625 ps |
| CPU time | 12.25 seconds |
| Started | Oct 12 01:43:12 PM UTC 24 |
| Finished | Oct 12 01:43:26 PM UTC 24 |
| Peak memory | 207352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547312177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3547312177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_noise_filter.2507517990 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 168937014052 ps |
| CPU time | 90.99 seconds |
| Started | Oct 12 01:43:03 PM UTC 24 |
| Finished | Oct 12 01:44:36 PM UTC 24 |
| Peak memory | 208076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507517990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2507517990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_perf.2139527184 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 10357727754 ps |
| CPU time | 573.58 seconds |
| Started | Oct 12 01:43:13 PM UTC 24 |
| Finished | Oct 12 01:52:54 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139527184 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2139527184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_rx_oversample.3887908402 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 3812404443 ps |
| CPU time | 32.65 seconds |
| Started | Oct 12 01:42:50 PM UTC 24 |
| Finished | Oct 12 01:43:24 PM UTC 24 |
| Peak memory | 207336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887908402 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3887908402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.3145474891 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 101912083786 ps |
| CPU time | 86.11 seconds |
| Started | Oct 12 01:43:07 PM UTC 24 |
| Finished | Oct 12 01:44:35 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145474891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3145474891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.2838002157 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3014000253 ps |
| CPU time | 7.06 seconds |
| Started | Oct 12 01:43:04 PM UTC 24 |
| Finished | Oct 12 01:43:12 PM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838002157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2838002157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_smoke.4264895312 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 804391101 ps |
| CPU time | 4.14 seconds |
| Started | Oct 12 01:42:31 PM UTC 24 |
| Finished | Oct 12 01:42:37 PM UTC 24 |
| Peak memory | 208288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264895312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.uart_smoke.4264895312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.2013858569 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 5371888072 ps |
| CPU time | 78.16 seconds |
| Started | Oct 12 01:43:15 PM UTC 24 |
| Finished | Oct 12 01:44:35 PM UTC 24 |
| Peak memory | 225312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2013858569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all _with_rand_reset.2013858569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.3291648813 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 877068615 ps |
| CPU time | 2.12 seconds |
| Started | Oct 12 01:43:09 PM UTC 24 |
| Finished | Oct 12 01:43:12 PM UTC 24 |
| Peak memory | 207408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291648813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3291648813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_tx_rx.1953802724 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 68596868440 ps |
| CPU time | 44.51 seconds |
| Started | Oct 12 01:42:33 PM UTC 24 |
| Finished | Oct 12 01:43:20 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953802724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1953802724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/27.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/270.uart_fifo_reset.3659404713 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 86893658067 ps |
| CPU time | 58.44 seconds |
| Started | Oct 12 02:06:46 PM UTC 24 |
| Finished | Oct 12 02:07:46 PM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659404713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3659404713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/270.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/271.uart_fifo_reset.135256523 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 23062243990 ps |
| CPU time | 50.02 seconds |
| Started | Oct 12 02:06:47 PM UTC 24 |
| Finished | Oct 12 02:07:39 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135256523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.135256523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/271.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/272.uart_fifo_reset.3733213761 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 81294809530 ps |
| CPU time | 63.37 seconds |
| Started | Oct 12 02:06:50 PM UTC 24 |
| Finished | Oct 12 02:07:55 PM UTC 24 |
| Peak memory | 208536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733213761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3733213761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/272.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/273.uart_fifo_reset.1878105317 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 44638992864 ps |
| CPU time | 19.19 seconds |
| Started | Oct 12 02:06:50 PM UTC 24 |
| Finished | Oct 12 02:07:10 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878105317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1878105317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/273.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/274.uart_fifo_reset.1716783625 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 126872333598 ps |
| CPU time | 266.98 seconds |
| Started | Oct 12 02:06:50 PM UTC 24 |
| Finished | Oct 12 02:11:21 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716783625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1716783625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/274.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/275.uart_fifo_reset.3445699984 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 11295308835 ps |
| CPU time | 27.41 seconds |
| Started | Oct 12 02:06:51 PM UTC 24 |
| Finished | Oct 12 02:07:20 PM UTC 24 |
| Peak memory | 208684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445699984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3445699984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/275.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/277.uart_fifo_reset.1887956413 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 19785456921 ps |
| CPU time | 36.64 seconds |
| Started | Oct 12 02:06:53 PM UTC 24 |
| Finished | Oct 12 02:07:31 PM UTC 24 |
| Peak memory | 208452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887956413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1887956413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/277.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/278.uart_fifo_reset.1418989060 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 111886618913 ps |
| CPU time | 99.47 seconds |
| Started | Oct 12 02:06:55 PM UTC 24 |
| Finished | Oct 12 02:08:37 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418989060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1418989060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/278.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/279.uart_fifo_reset.1864004766 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 13946706116 ps |
| CPU time | 40.4 seconds |
| Started | Oct 12 02:06:58 PM UTC 24 |
| Finished | Oct 12 02:07:40 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864004766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1864004766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/279.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_alert_test.4076891070 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 29664421 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 01:44:17 PM UTC 24 |
| Finished | Oct 12 01:44:19 PM UTC 24 |
| Peak memory | 204388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076891070 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.4076891070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_fifo_full.2011206952 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 26253137595 ps |
| CPU time | 17.41 seconds |
| Started | Oct 12 01:43:34 PM UTC 24 |
| Finished | Oct 12 01:43:53 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011206952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2011206952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.2456392822 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 40209642329 ps |
| CPU time | 46.22 seconds |
| Started | Oct 12 01:43:34 PM UTC 24 |
| Finished | Oct 12 01:44:22 PM UTC 24 |
| Peak memory | 208344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456392822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2456392822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_fifo_reset.2367724166 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 252547379770 ps |
| CPU time | 49.76 seconds |
| Started | Oct 12 01:43:37 PM UTC 24 |
| Finished | Oct 12 01:44:29 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367724166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2367724166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_intr.2816551586 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 18583993611 ps |
| CPU time | 55.51 seconds |
| Started | Oct 12 01:43:45 PM UTC 24 |
| Finished | Oct 12 01:44:43 PM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816551586 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2816551586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.2170321016 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 82508784717 ps |
| CPU time | 231.91 seconds |
| Started | Oct 12 01:44:03 PM UTC 24 |
| Finished | Oct 12 01:47:59 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170321016 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2170321016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_loopback.3116231844 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 6004159542 ps |
| CPU time | 4.14 seconds |
| Started | Oct 12 01:43:57 PM UTC 24 |
| Finished | Oct 12 01:44:02 PM UTC 24 |
| Peak memory | 207752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116231844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3116231844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_noise_filter.2488235555 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 101099529538 ps |
| CPU time | 68.64 seconds |
| Started | Oct 12 01:43:50 PM UTC 24 |
| Finished | Oct 12 01:45:00 PM UTC 24 |
| Peak memory | 209040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488235555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2488235555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_perf.1665229887 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 6353775551 ps |
| CPU time | 89.19 seconds |
| Started | Oct 12 01:43:58 PM UTC 24 |
| Finished | Oct 12 01:45:29 PM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665229887 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1665229887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_rx_oversample.1856222645 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 3911543311 ps |
| CPU time | 13.49 seconds |
| Started | Oct 12 01:43:42 PM UTC 24 |
| Finished | Oct 12 01:43:57 PM UTC 24 |
| Peak memory | 208040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856222645 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1856222645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.2611277252 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 108162923721 ps |
| CPU time | 51.16 seconds |
| Started | Oct 12 01:43:54 PM UTC 24 |
| Finished | Oct 12 01:44:46 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611277252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2611277252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.1316180595 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 5540481143 ps |
| CPU time | 13.81 seconds |
| Started | Oct 12 01:43:50 PM UTC 24 |
| Finished | Oct 12 01:44:05 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316180595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1316180595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_smoke.4034954711 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 895687923 ps |
| CPU time | 4.95 seconds |
| Started | Oct 12 01:43:27 PM UTC 24 |
| Finished | Oct 12 01:43:33 PM UTC 24 |
| Peak memory | 207828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034954711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 28.uart_smoke.4034954711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_stress_all.1673863405 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 42502264553 ps |
| CPU time | 87.56 seconds |
| Started | Oct 12 01:44:05 PM UTC 24 |
| Finished | Oct 12 01:45:35 PM UTC 24 |
| Peak memory | 208952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673863405 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1673863405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.2683946724 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 9953254720 ps |
| CPU time | 36.8 seconds |
| Started | Oct 12 01:44:04 PM UTC 24 |
| Finished | Oct 12 01:44:42 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2683946724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all _with_rand_reset.2683946724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.2530962902 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1021357075 ps |
| CPU time | 6.31 seconds |
| Started | Oct 12 01:43:56 PM UTC 24 |
| Finished | Oct 12 01:44:03 PM UTC 24 |
| Peak memory | 208452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530962902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2530962902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/28.uart_tx_rx.1693363416 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 111153996734 ps |
| CPU time | 26.65 seconds |
| Started | Oct 12 01:43:28 PM UTC 24 |
| Finished | Oct 12 01:43:56 PM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693363416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1693363416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/28.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/280.uart_fifo_reset.3771917678 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 53093660713 ps |
| CPU time | 101.88 seconds |
| Started | Oct 12 02:06:59 PM UTC 24 |
| Finished | Oct 12 02:08:43 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771917678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3771917678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/280.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/281.uart_fifo_reset.3514692006 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 140851125043 ps |
| CPU time | 48.28 seconds |
| Started | Oct 12 02:07:00 PM UTC 24 |
| Finished | Oct 12 02:07:50 PM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514692006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3514692006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/281.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2938038284 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 26226621570 ps |
| CPU time | 27.37 seconds |
| Started | Oct 12 02:07:04 PM UTC 24 |
| Finished | Oct 12 02:07:33 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938038284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2938038284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/282.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/283.uart_fifo_reset.2000337151 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 37668830134 ps |
| CPU time | 65.75 seconds |
| Started | Oct 12 02:07:11 PM UTC 24 |
| Finished | Oct 12 02:08:18 PM UTC 24 |
| Peak memory | 208488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000337151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2000337151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/283.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/284.uart_fifo_reset.2967814566 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 8219365015 ps |
| CPU time | 22.55 seconds |
| Started | Oct 12 02:07:11 PM UTC 24 |
| Finished | Oct 12 02:07:34 PM UTC 24 |
| Peak memory | 207668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967814566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2967814566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/284.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/285.uart_fifo_reset.3894594240 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 9592103217 ps |
| CPU time | 20.79 seconds |
| Started | Oct 12 02:07:11 PM UTC 24 |
| Finished | Oct 12 02:07:33 PM UTC 24 |
| Peak memory | 208812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894594240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3894594240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/285.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/286.uart_fifo_reset.2233796703 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 88932757504 ps |
| CPU time | 139.28 seconds |
| Started | Oct 12 02:07:12 PM UTC 24 |
| Finished | Oct 12 02:09:33 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233796703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2233796703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/286.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/287.uart_fifo_reset.4239603151 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 118564914943 ps |
| CPU time | 55.3 seconds |
| Started | Oct 12 02:07:12 PM UTC 24 |
| Finished | Oct 12 02:08:09 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239603151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.4239603151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/287.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/288.uart_fifo_reset.2107542968 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 16987522798 ps |
| CPU time | 15.71 seconds |
| Started | Oct 12 02:07:12 PM UTC 24 |
| Finished | Oct 12 02:07:29 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107542968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2107542968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/288.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/289.uart_fifo_reset.369328741 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 154760680517 ps |
| CPU time | 33.9 seconds |
| Started | Oct 12 02:07:12 PM UTC 24 |
| Finished | Oct 12 02:07:47 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369328741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.369328741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/289.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_alert_test.1674217703 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 15143063 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 01:44:43 PM UTC 24 |
| Finished | Oct 12 01:44:45 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674217703 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1674217703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_fifo_full.2543609335 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 236976566178 ps |
| CPU time | 173.01 seconds |
| Started | Oct 12 01:44:25 PM UTC 24 |
| Finished | Oct 12 01:47:21 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543609335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2543609335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.2908421649 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 110595502920 ps |
| CPU time | 95.22 seconds |
| Started | Oct 12 01:44:26 PM UTC 24 |
| Finished | Oct 12 01:46:03 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908421649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2908421649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_fifo_reset.3432309526 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 15120221996 ps |
| CPU time | 35.25 seconds |
| Started | Oct 12 01:44:26 PM UTC 24 |
| Finished | Oct 12 01:45:02 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432309526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3432309526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_intr.4148330948 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 19055673682 ps |
| CPU time | 9.37 seconds |
| Started | Oct 12 01:44:30 PM UTC 24 |
| Finished | Oct 12 01:44:40 PM UTC 24 |
| Peak memory | 207668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148330948 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.4148330948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.2062112780 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 126073952334 ps |
| CPU time | 848.45 seconds |
| Started | Oct 12 01:44:41 PM UTC 24 |
| Finished | Oct 12 01:58:58 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062112780 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2062112780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_loopback.476576233 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 4696350725 ps |
| CPU time | 19.52 seconds |
| Started | Oct 12 01:44:39 PM UTC 24 |
| Finished | Oct 12 01:45:00 PM UTC 24 |
| Peak memory | 207504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476576233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 29.uart_loopback.476576233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_noise_filter.355395505 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 150448790121 ps |
| CPU time | 74.73 seconds |
| Started | Oct 12 01:44:32 PM UTC 24 |
| Finished | Oct 12 01:45:48 PM UTC 24 |
| Peak memory | 217856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355395505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.355395505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_perf.3562812747 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 15741644545 ps |
| CPU time | 656.51 seconds |
| Started | Oct 12 01:44:39 PM UTC 24 |
| Finished | Oct 12 01:55:44 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562812747 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3562812747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_rx_oversample.2498936297 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 3971307239 ps |
| CPU time | 33.23 seconds |
| Started | Oct 12 01:44:29 PM UTC 24 |
| Finished | Oct 12 01:45:03 PM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498936297 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2498936297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.2201617433 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 37227705692 ps |
| CPU time | 60.81 seconds |
| Started | Oct 12 01:44:36 PM UTC 24 |
| Finished | Oct 12 01:45:39 PM UTC 24 |
| Peak memory | 208656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201617433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2201617433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.2012873339 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 4760431691 ps |
| CPU time | 6.12 seconds |
| Started | Oct 12 01:44:35 PM UTC 24 |
| Finished | Oct 12 01:44:42 PM UTC 24 |
| Peak memory | 205104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012873339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2012873339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_smoke.1063330807 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 480558001 ps |
| CPU time | 2.91 seconds |
| Started | Oct 12 01:44:20 PM UTC 24 |
| Finished | Oct 12 01:44:24 PM UTC 24 |
| Peak memory | 208148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063330807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1063330807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_stress_all.1894589587 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 25726904901 ps |
| CPU time | 99.21 seconds |
| Started | Oct 12 01:44:43 PM UTC 24 |
| Finished | Oct 12 01:46:24 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894589587 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1894589587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.893595007 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 3339623306 ps |
| CPU time | 53.68 seconds |
| Started | Oct 12 01:44:42 PM UTC 24 |
| Finished | Oct 12 01:45:37 PM UTC 24 |
| Peak memory | 222068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=893595007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all_ with_rand_reset.893595007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.2339739485 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 11933476359 ps |
| CPU time | 45.49 seconds |
| Started | Oct 12 01:44:37 PM UTC 24 |
| Finished | Oct 12 01:45:24 PM UTC 24 |
| Peak memory | 208664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339739485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2339739485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/29.uart_tx_rx.1021498745 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 56401772195 ps |
| CPU time | 29.46 seconds |
| Started | Oct 12 01:44:23 PM UTC 24 |
| Finished | Oct 12 01:44:53 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021498745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1021498745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/29.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2028651934 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 28218177776 ps |
| CPU time | 55.81 seconds |
| Started | Oct 12 02:07:13 PM UTC 24 |
| Finished | Oct 12 02:08:10 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028651934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2028651934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/290.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/291.uart_fifo_reset.2913045287 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 203212033708 ps |
| CPU time | 51.41 seconds |
| Started | Oct 12 02:07:14 PM UTC 24 |
| Finished | Oct 12 02:08:07 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913045287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2913045287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/291.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/292.uart_fifo_reset.606732817 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 179415662485 ps |
| CPU time | 76.66 seconds |
| Started | Oct 12 02:07:19 PM UTC 24 |
| Finished | Oct 12 02:08:38 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606732817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.606732817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/292.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/293.uart_fifo_reset.3430124495 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 236972349664 ps |
| CPU time | 125.86 seconds |
| Started | Oct 12 02:07:20 PM UTC 24 |
| Finished | Oct 12 02:09:29 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430124495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3430124495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/293.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/294.uart_fifo_reset.2131378109 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 17195126099 ps |
| CPU time | 38.12 seconds |
| Started | Oct 12 02:07:20 PM UTC 24 |
| Finished | Oct 12 02:08:00 PM UTC 24 |
| Peak memory | 207932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131378109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2131378109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/294.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/295.uart_fifo_reset.3574506116 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 114384157171 ps |
| CPU time | 143.69 seconds |
| Started | Oct 12 02:07:21 PM UTC 24 |
| Finished | Oct 12 02:09:48 PM UTC 24 |
| Peak memory | 208872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574506116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3574506116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/295.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/296.uart_fifo_reset.1517724451 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 87170467975 ps |
| CPU time | 88.51 seconds |
| Started | Oct 12 02:07:24 PM UTC 24 |
| Finished | Oct 12 02:08:55 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517724451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1517724451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/296.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/297.uart_fifo_reset.4282855414 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 157034042889 ps |
| CPU time | 78.2 seconds |
| Started | Oct 12 02:07:26 PM UTC 24 |
| Finished | Oct 12 02:08:46 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282855414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.4282855414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/297.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/298.uart_fifo_reset.3224367339 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 69964425431 ps |
| CPU time | 70.52 seconds |
| Started | Oct 12 02:07:28 PM UTC 24 |
| Finished | Oct 12 02:08:40 PM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224367339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3224367339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/298.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/299.uart_fifo_reset.3371814427 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 43735614009 ps |
| CPU time | 18.69 seconds |
| Started | Oct 12 02:07:29 PM UTC 24 |
| Finished | Oct 12 02:07:49 PM UTC 24 |
| Peak memory | 208672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371814427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3371814427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/299.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_alert_test.1739362619 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 242862223 ps |
| CPU time | 0.79 seconds |
| Started | Oct 12 01:29:31 PM UTC 24 |
| Finished | Oct 12 01:29:32 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739362619 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1739362619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.2823417562 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 250224406248 ps |
| CPU time | 187.46 seconds |
| Started | Oct 12 01:29:19 PM UTC 24 |
| Finished | Oct 12 01:32:30 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823417562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2823417562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_intr.596956490 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 184965028351 ps |
| CPU time | 56.25 seconds |
| Started | Oct 12 01:29:21 PM UTC 24 |
| Finished | Oct 12 01:30:18 PM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596956490 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.596956490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.2520902582 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 92571038414 ps |
| CPU time | 309.39 seconds |
| Started | Oct 12 01:29:28 PM UTC 24 |
| Finished | Oct 12 01:34:42 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520902582 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2520902582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_loopback.1707086477 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3504628170 ps |
| CPU time | 8.04 seconds |
| Started | Oct 12 01:29:27 PM UTC 24 |
| Finished | Oct 12 01:29:36 PM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707086477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1707086477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_noise_filter.2420432643 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 71109655793 ps |
| CPU time | 69.43 seconds |
| Started | Oct 12 01:29:21 PM UTC 24 |
| Finished | Oct 12 01:30:32 PM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420432643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2420432643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_rx_oversample.1630055559 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2014133511 ps |
| CPU time | 5.46 seconds |
| Started | Oct 12 01:29:20 PM UTC 24 |
| Finished | Oct 12 01:29:26 PM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630055559 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1630055559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.1113888562 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 17986224502 ps |
| CPU time | 48.5 seconds |
| Started | Oct 12 01:29:26 PM UTC 24 |
| Finished | Oct 12 01:30:16 PM UTC 24 |
| Peak memory | 208344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113888562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1113888562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.367541384 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2073522138 ps |
| CPU time | 6.84 seconds |
| Started | Oct 12 01:29:21 PM UTC 24 |
| Finished | Oct 12 01:29:29 PM UTC 24 |
| Peak memory | 205240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367541384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.367541384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_sec_cm.940105421 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 64955466 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 01:29:29 PM UTC 24 |
| Finished | Oct 12 01:29:32 PM UTC 24 |
| Peak memory | 237600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940105421 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.940105421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_smoke.426724989 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 11051002516 ps |
| CPU time | 27.99 seconds |
| Started | Oct 12 01:29:18 PM UTC 24 |
| Finished | Oct 12 01:29:47 PM UTC 24 |
| Peak memory | 208460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426724989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 3.uart_smoke.426724989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_stress_all.1348332261 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 117605434018 ps |
| CPU time | 179.6 seconds |
| Started | Oct 12 01:29:29 PM UTC 24 |
| Finished | Oct 12 01:32:32 PM UTC 24 |
| Peak memory | 217732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348332261 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1348332261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.2776181562 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7630782102 ps |
| CPU time | 25.78 seconds |
| Started | Oct 12 01:29:28 PM UTC 24 |
| Finished | Oct 12 01:29:55 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2776181562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_ with_rand_reset.2776181562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.2667137166 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 491707179 ps |
| CPU time | 2.49 seconds |
| Started | Oct 12 01:29:26 PM UTC 24 |
| Finished | Oct 12 01:29:29 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667137166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2667137166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_tx_rx.1377142449 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 67463488908 ps |
| CPU time | 64.09 seconds |
| Started | Oct 12 01:29:18 PM UTC 24 |
| Finished | Oct 12 01:30:24 PM UTC 24 |
| Peak memory | 208404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377142449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1377142449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/3.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_alert_test.3435697558 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 48001298 ps |
| CPU time | 0.83 seconds |
| Started | Oct 12 01:45:12 PM UTC 24 |
| Finished | Oct 12 01:45:14 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435697558 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3435697558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_fifo_full.3861390074 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 91249144860 ps |
| CPU time | 96.7 seconds |
| Started | Oct 12 01:44:45 PM UTC 24 |
| Finished | Oct 12 01:46:24 PM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861390074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3861390074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.1198673850 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 156628740564 ps |
| CPU time | 67.4 seconds |
| Started | Oct 12 01:44:47 PM UTC 24 |
| Finished | Oct 12 01:45:56 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198673850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1198673850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_intr.2423445533 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 29327648012 ps |
| CPU time | 8.33 seconds |
| Started | Oct 12 01:44:54 PM UTC 24 |
| Finished | Oct 12 01:45:04 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423445533 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2423445533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.3097339416 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 47848901870 ps |
| CPU time | 370.81 seconds |
| Started | Oct 12 01:45:05 PM UTC 24 |
| Finished | Oct 12 01:51:21 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097339416 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3097339416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_loopback.4238973841 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 8515123023 ps |
| CPU time | 16.79 seconds |
| Started | Oct 12 01:45:04 PM UTC 24 |
| Finished | Oct 12 01:45:22 PM UTC 24 |
| Peak memory | 207472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238973841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 30.uart_loopback.4238973841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_noise_filter.325216971 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 220041450837 ps |
| CPU time | 41.75 seconds |
| Started | Oct 12 01:45:02 PM UTC 24 |
| Finished | Oct 12 01:45:45 PM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325216971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.325216971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_perf.1850983120 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 7393559672 ps |
| CPU time | 447.49 seconds |
| Started | Oct 12 01:45:05 PM UTC 24 |
| Finished | Oct 12 01:52:38 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850983120 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1850983120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_rx_oversample.2089904493 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 2442175444 ps |
| CPU time | 12.1 seconds |
| Started | Oct 12 01:44:51 PM UTC 24 |
| Finished | Oct 12 01:45:05 PM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089904493 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2089904493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.1986788532 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 65680487346 ps |
| CPU time | 30.04 seconds |
| Started | Oct 12 01:45:02 PM UTC 24 |
| Finished | Oct 12 01:45:33 PM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986788532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1986788532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.2774395761 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 591067614 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 01:45:02 PM UTC 24 |
| Finished | Oct 12 01:45:04 PM UTC 24 |
| Peak memory | 204300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774395761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2774395761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_smoke.1089258008 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 284946401 ps |
| CPU time | 2.41 seconds |
| Started | Oct 12 01:44:44 PM UTC 24 |
| Finished | Oct 12 01:44:47 PM UTC 24 |
| Peak memory | 207612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089258008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1089258008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_stress_all.946449035 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 332088351015 ps |
| CPU time | 837.19 seconds |
| Started | Oct 12 01:45:08 PM UTC 24 |
| Finished | Oct 12 01:59:14 PM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946449035 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.946449035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.2903764274 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 16844761750 ps |
| CPU time | 86.02 seconds |
| Started | Oct 12 01:45:06 PM UTC 24 |
| Finished | Oct 12 01:46:34 PM UTC 24 |
| Peak memory | 224556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2903764274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all _with_rand_reset.2903764274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.3741019940 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 8735723458 ps |
| CPU time | 6.76 seconds |
| Started | Oct 12 01:45:04 PM UTC 24 |
| Finished | Oct 12 01:45:12 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741019940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3741019940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_tx_rx.1901002562 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 35045339833 ps |
| CPU time | 22.41 seconds |
| Started | Oct 12 01:44:44 PM UTC 24 |
| Finished | Oct 12 01:45:08 PM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901002562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1901002562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/30.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_alert_test.2987697920 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 45405454 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 01:45:45 PM UTC 24 |
| Finished | Oct 12 01:45:47 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987697920 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2987697920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_fifo_full.3000731327 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 45602086348 ps |
| CPU time | 79.46 seconds |
| Started | Oct 12 01:45:23 PM UTC 24 |
| Finished | Oct 12 01:46:44 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000731327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3000731327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.2497132869 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 59435163594 ps |
| CPU time | 93.23 seconds |
| Started | Oct 12 01:45:25 PM UTC 24 |
| Finished | Oct 12 01:47:00 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497132869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2497132869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_fifo_reset.4093684202 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 107029690630 ps |
| CPU time | 188.37 seconds |
| Started | Oct 12 01:45:30 PM UTC 24 |
| Finished | Oct 12 01:48:41 PM UTC 24 |
| Peak memory | 208936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093684202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.4093684202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.3903407741 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 164254552253 ps |
| CPU time | 403.93 seconds |
| Started | Oct 12 01:45:40 PM UTC 24 |
| Finished | Oct 12 01:52:29 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903407741 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3903407741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_loopback.535192301 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 7246302209 ps |
| CPU time | 26.8 seconds |
| Started | Oct 12 01:45:37 PM UTC 24 |
| Finished | Oct 12 01:46:06 PM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535192301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 31.uart_loopback.535192301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_noise_filter.3703169205 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 170488331057 ps |
| CPU time | 153.84 seconds |
| Started | Oct 12 01:45:33 PM UTC 24 |
| Finished | Oct 12 01:48:10 PM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703169205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3703169205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_perf.581035805 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 29582025487 ps |
| CPU time | 1729.77 seconds |
| Started | Oct 12 01:45:37 PM UTC 24 |
| Finished | Oct 12 02:14:46 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581035805 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.581035805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_rx_oversample.1589326535 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 4957061732 ps |
| CPU time | 15.39 seconds |
| Started | Oct 12 01:45:31 PM UTC 24 |
| Finished | Oct 12 01:45:48 PM UTC 24 |
| Peak memory | 207440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589326535 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1589326535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.1881572183 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 129468353876 ps |
| CPU time | 306.73 seconds |
| Started | Oct 12 01:45:34 PM UTC 24 |
| Finished | Oct 12 01:50:45 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881572183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1881572183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.3157401368 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 3309849356 ps |
| CPU time | 7.35 seconds |
| Started | Oct 12 01:45:33 PM UTC 24 |
| Finished | Oct 12 01:45:42 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157401368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3157401368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_smoke.2407382598 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 695911556 ps |
| CPU time | 4.43 seconds |
| Started | Oct 12 01:45:15 PM UTC 24 |
| Finished | Oct 12 01:45:21 PM UTC 24 |
| Peak memory | 207948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407382598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2407382598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_stress_all.672845004 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 111556135384 ps |
| CPU time | 213.19 seconds |
| Started | Oct 12 01:45:43 PM UTC 24 |
| Finished | Oct 12 01:49:19 PM UTC 24 |
| Peak memory | 208880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672845004 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.672845004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.2955173177 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 9563916773 ps |
| CPU time | 14.11 seconds |
| Started | Oct 12 01:45:43 PM UTC 24 |
| Finished | Oct 12 01:45:58 PM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2955173177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all _with_rand_reset.2955173177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.1761190046 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1071269538 ps |
| CPU time | 4.97 seconds |
| Started | Oct 12 01:45:35 PM UTC 24 |
| Finished | Oct 12 01:45:41 PM UTC 24 |
| Peak memory | 207900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761190046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1761190046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/31.uart_tx_rx.3996615731 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 35693090824 ps |
| CPU time | 21.43 seconds |
| Started | Oct 12 01:45:21 PM UTC 24 |
| Finished | Oct 12 01:45:44 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996615731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3996615731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_alert_test.36525104 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 14903948 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 01:46:25 PM UTC 24 |
| Finished | Oct 12 01:46:27 PM UTC 24 |
| Peak memory | 204316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36525104 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.36525104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_fifo_full.1293365773 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 127988369573 ps |
| CPU time | 73.1 seconds |
| Started | Oct 12 01:45:48 PM UTC 24 |
| Finished | Oct 12 01:47:03 PM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293365773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1293365773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.558173580 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 53471294523 ps |
| CPU time | 16.2 seconds |
| Started | Oct 12 01:45:49 PM UTC 24 |
| Finished | Oct 12 01:46:06 PM UTC 24 |
| Peak memory | 208356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558173580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.558173580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_fifo_reset.1668323130 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 27814365776 ps |
| CPU time | 61.63 seconds |
| Started | Oct 12 01:45:49 PM UTC 24 |
| Finished | Oct 12 01:46:52 PM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668323130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1668323130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_intr.3750704765 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 48872384617 ps |
| CPU time | 83.62 seconds |
| Started | Oct 12 01:45:58 PM UTC 24 |
| Finished | Oct 12 01:47:24 PM UTC 24 |
| Peak memory | 208020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750704765 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3750704765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.2269009172 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 112439909890 ps |
| CPU time | 880.16 seconds |
| Started | Oct 12 01:46:22 PM UTC 24 |
| Finished | Oct 12 02:01:13 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269009172 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2269009172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_loopback.1505882918 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 3613867808 ps |
| CPU time | 7.59 seconds |
| Started | Oct 12 01:46:18 PM UTC 24 |
| Finished | Oct 12 01:46:27 PM UTC 24 |
| Peak memory | 207488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505882918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1505882918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_noise_filter.3563673377 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 246126409962 ps |
| CPU time | 115.84 seconds |
| Started | Oct 12 01:46:04 PM UTC 24 |
| Finished | Oct 12 01:48:02 PM UTC 24 |
| Peak memory | 208916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563673377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3563673377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_perf.2434919287 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 12881943414 ps |
| CPU time | 875.67 seconds |
| Started | Oct 12 01:46:18 PM UTC 24 |
| Finished | Oct 12 02:01:04 PM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434919287 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2434919287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_rx_oversample.898359533 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 3381810892 ps |
| CPU time | 15.24 seconds |
| Started | Oct 12 01:45:57 PM UTC 24 |
| Finished | Oct 12 01:46:14 PM UTC 24 |
| Peak memory | 207508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898359533 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.898359533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.2765861596 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 168391322231 ps |
| CPU time | 96.51 seconds |
| Started | Oct 12 01:46:08 PM UTC 24 |
| Finished | Oct 12 01:47:46 PM UTC 24 |
| Peak memory | 208348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765861596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2765861596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.1535560236 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 4925971673 ps |
| CPU time | 16.24 seconds |
| Started | Oct 12 01:46:07 PM UTC 24 |
| Finished | Oct 12 01:46:24 PM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535560236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1535560236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_smoke.640507003 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 118502752 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 01:45:46 PM UTC 24 |
| Finished | Oct 12 01:45:48 PM UTC 24 |
| Peak memory | 206316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640507003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 32.uart_smoke.640507003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_stress_all.1783155904 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 226007518306 ps |
| CPU time | 221.7 seconds |
| Started | Oct 12 01:46:25 PM UTC 24 |
| Finished | Oct 12 01:50:10 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783155904 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1783155904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.2399866193 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 5245444926 ps |
| CPU time | 66.19 seconds |
| Started | Oct 12 01:46:24 PM UTC 24 |
| Finished | Oct 12 01:47:32 PM UTC 24 |
| Peak memory | 217840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2399866193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all _with_rand_reset.2399866193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.2960839860 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 502488862 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 01:46:15 PM UTC 24 |
| Finished | Oct 12 01:46:18 PM UTC 24 |
| Peak memory | 207792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960839860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2960839860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/32.uart_tx_rx.3581534222 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 177541030525 ps |
| CPU time | 132.21 seconds |
| Started | Oct 12 01:45:48 PM UTC 24 |
| Finished | Oct 12 01:48:02 PM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581534222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3581534222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/32.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_alert_test.2760343765 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 11650599 ps |
| CPU time | 0.77 seconds |
| Started | Oct 12 01:47:22 PM UTC 24 |
| Finished | Oct 12 01:47:24 PM UTC 24 |
| Peak memory | 202340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760343765 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2760343765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_fifo_full.2134690769 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 206721437035 ps |
| CPU time | 187.6 seconds |
| Started | Oct 12 01:46:29 PM UTC 24 |
| Finished | Oct 12 01:49:39 PM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134690769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2134690769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.4242779126 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 19332816650 ps |
| CPU time | 16.1 seconds |
| Started | Oct 12 01:46:31 PM UTC 24 |
| Finished | Oct 12 01:46:48 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242779126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4242779126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_fifo_reset.3294096812 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 16411595336 ps |
| CPU time | 40.98 seconds |
| Started | Oct 12 01:46:32 PM UTC 24 |
| Finished | Oct 12 01:47:14 PM UTC 24 |
| Peak memory | 208244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294096812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3294096812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.4294788201 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 68529151200 ps |
| CPU time | 166.22 seconds |
| Started | Oct 12 01:47:04 PM UTC 24 |
| Finished | Oct 12 01:49:52 PM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294788201 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.4294788201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_loopback.251479515 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 6007066967 ps |
| CPU time | 13.66 seconds |
| Started | Oct 12 01:46:57 PM UTC 24 |
| Finished | Oct 12 01:47:12 PM UTC 24 |
| Peak memory | 207996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251479515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 33.uart_loopback.251479515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_noise_filter.382439294 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 89137475700 ps |
| CPU time | 234.4 seconds |
| Started | Oct 12 01:46:45 PM UTC 24 |
| Finished | Oct 12 01:50:43 PM UTC 24 |
| Peak memory | 208916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382439294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.382439294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_perf.198256826 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 12891707016 ps |
| CPU time | 427.41 seconds |
| Started | Oct 12 01:47:01 PM UTC 24 |
| Finished | Oct 12 01:54:13 PM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198256826 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.198256826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_rx_oversample.491255116 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 3585390545 ps |
| CPU time | 20.8 seconds |
| Started | Oct 12 01:46:35 PM UTC 24 |
| Finished | Oct 12 01:46:57 PM UTC 24 |
| Peak memory | 207408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491255116 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.491255116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.1913205227 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 49367661156 ps |
| CPU time | 121.06 seconds |
| Started | Oct 12 01:46:53 PM UTC 24 |
| Finished | Oct 12 01:48:57 PM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913205227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1913205227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.4013901426 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 3022705375 ps |
| CPU time | 5.54 seconds |
| Started | Oct 12 01:46:49 PM UTC 24 |
| Finished | Oct 12 01:46:56 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013901426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.4013901426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_smoke.2543269508 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 319614720 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 01:46:27 PM UTC 24 |
| Finished | Oct 12 01:46:30 PM UTC 24 |
| Peak memory | 206252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543269508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2543269508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_stress_all.2101343669 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 169728769030 ps |
| CPU time | 599.76 seconds |
| Started | Oct 12 01:47:15 PM UTC 24 |
| Finished | Oct 12 01:57:22 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101343669 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2101343669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.460825994 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 16698636780 ps |
| CPU time | 84.57 seconds |
| Started | Oct 12 01:47:13 PM UTC 24 |
| Finished | Oct 12 01:48:39 PM UTC 24 |
| Peak memory | 220004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=460825994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all_ with_rand_reset.460825994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.2227649859 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 6873761082 ps |
| CPU time | 24.25 seconds |
| Started | Oct 12 01:46:56 PM UTC 24 |
| Finished | Oct 12 01:47:22 PM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227649859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2227649859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_tx_rx.3967522823 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 76058055413 ps |
| CPU time | 172.72 seconds |
| Started | Oct 12 01:46:28 PM UTC 24 |
| Finished | Oct 12 01:49:23 PM UTC 24 |
| Peak memory | 208616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967522823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3967522823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/33.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_alert_test.2454359656 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 23639264 ps |
| CPU time | 0.87 seconds |
| Started | Oct 12 01:48:14 PM UTC 24 |
| Finished | Oct 12 01:48:15 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454359656 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2454359656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_fifo_full.2237909801 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 44740492257 ps |
| CPU time | 89.83 seconds |
| Started | Oct 12 01:47:25 PM UTC 24 |
| Finished | Oct 12 01:48:57 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237909801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2237909801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.2736794062 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 9385180287 ps |
| CPU time | 28.19 seconds |
| Started | Oct 12 01:47:26 PM UTC 24 |
| Finished | Oct 12 01:47:56 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736794062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2736794062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_fifo_reset.3053467380 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 16857963992 ps |
| CPU time | 34.01 seconds |
| Started | Oct 12 01:47:27 PM UTC 24 |
| Finished | Oct 12 01:48:03 PM UTC 24 |
| Peak memory | 208416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053467380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3053467380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_intr.2868976131 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 228556176402 ps |
| CPU time | 387.89 seconds |
| Started | Oct 12 01:47:34 PM UTC 24 |
| Finished | Oct 12 01:54:06 PM UTC 24 |
| Peak memory | 207196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868976131 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2868976131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.3057479475 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 217368636605 ps |
| CPU time | 140.35 seconds |
| Started | Oct 12 01:48:03 PM UTC 24 |
| Finished | Oct 12 01:50:26 PM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057479475 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3057479475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_loopback.1496668081 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 5455992153 ps |
| CPU time | 13.79 seconds |
| Started | Oct 12 01:47:59 PM UTC 24 |
| Finished | Oct 12 01:48:14 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496668081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1496668081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_noise_filter.2230702146 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 69796225130 ps |
| CPU time | 58.52 seconds |
| Started | Oct 12 01:47:45 PM UTC 24 |
| Finished | Oct 12 01:48:45 PM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230702146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2230702146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_perf.4084401743 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 17505924282 ps |
| CPU time | 545.59 seconds |
| Started | Oct 12 01:48:02 PM UTC 24 |
| Finished | Oct 12 01:57:15 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084401743 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.4084401743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_rx_oversample.2042574739 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 7279691479 ps |
| CPU time | 41.07 seconds |
| Started | Oct 12 01:47:31 PM UTC 24 |
| Finished | Oct 12 01:48:13 PM UTC 24 |
| Peak memory | 207592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042574739 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2042574739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.1163663452 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 67722804379 ps |
| CPU time | 159.71 seconds |
| Started | Oct 12 01:47:55 PM UTC 24 |
| Finished | Oct 12 01:50:37 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163663452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1163663452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.1342582936 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 1725247079 ps |
| CPU time | 6.03 seconds |
| Started | Oct 12 01:47:47 PM UTC 24 |
| Finished | Oct 12 01:47:54 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342582936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1342582936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_smoke.1052367049 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 467298513 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 01:47:23 PM UTC 24 |
| Finished | Oct 12 01:47:26 PM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052367049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1052367049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_stress_all.617675641 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 175322384835 ps |
| CPU time | 702.22 seconds |
| Started | Oct 12 01:48:10 PM UTC 24 |
| Finished | Oct 12 02:00:00 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617675641 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.617675641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.2776265677 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 5605003596 ps |
| CPU time | 108.63 seconds |
| Started | Oct 12 01:48:03 PM UTC 24 |
| Finished | Oct 12 01:49:54 PM UTC 24 |
| Peak memory | 225388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2776265677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all _with_rand_reset.2776265677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.2913139874 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 8629611219 ps |
| CPU time | 19.61 seconds |
| Started | Oct 12 01:47:57 PM UTC 24 |
| Finished | Oct 12 01:48:18 PM UTC 24 |
| Peak memory | 208004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913139874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2913139874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/34.uart_tx_rx.3893770214 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 27842919729 ps |
| CPU time | 59.06 seconds |
| Started | Oct 12 01:47:24 PM UTC 24 |
| Finished | Oct 12 01:48:25 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893770214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3893770214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/34.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_alert_test.2941963440 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 22443832 ps |
| CPU time | 0.83 seconds |
| Started | Oct 12 01:48:57 PM UTC 24 |
| Finished | Oct 12 01:48:59 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941963440 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2941963440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_fifo_full.1563196840 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 11159813621 ps |
| CPU time | 19.13 seconds |
| Started | Oct 12 01:48:19 PM UTC 24 |
| Finished | Oct 12 01:48:39 PM UTC 24 |
| Peak memory | 207484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563196840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1563196840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.1623762381 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 55426033529 ps |
| CPU time | 40.4 seconds |
| Started | Oct 12 01:48:26 PM UTC 24 |
| Finished | Oct 12 01:49:08 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623762381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1623762381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_fifo_reset.3454004287 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 29330684675 ps |
| CPU time | 24.93 seconds |
| Started | Oct 12 01:48:29 PM UTC 24 |
| Finished | Oct 12 01:48:56 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454004287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3454004287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_intr.553024431 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 31603183523 ps |
| CPU time | 29.07 seconds |
| Started | Oct 12 01:48:35 PM UTC 24 |
| Finished | Oct 12 01:49:06 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553024431 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.553024431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.3004094951 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 109049209581 ps |
| CPU time | 432.49 seconds |
| Started | Oct 12 01:48:50 PM UTC 24 |
| Finished | Oct 12 01:56:08 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004094951 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3004094951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_loopback.1509460852 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1482579809 ps |
| CPU time | 2.19 seconds |
| Started | Oct 12 01:48:46 PM UTC 24 |
| Finished | Oct 12 01:48:49 PM UTC 24 |
| Peak memory | 207084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509460852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1509460852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_noise_filter.3199480109 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 75667853006 ps |
| CPU time | 42.08 seconds |
| Started | Oct 12 01:48:35 PM UTC 24 |
| Finished | Oct 12 01:49:19 PM UTC 24 |
| Peak memory | 208528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199480109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3199480109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_perf.3259402130 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 6053183556 ps |
| CPU time | 327.24 seconds |
| Started | Oct 12 01:48:48 PM UTC 24 |
| Finished | Oct 12 01:54:20 PM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259402130 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3259402130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_rx_oversample.1063245650 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 5245844964 ps |
| CPU time | 55.91 seconds |
| Started | Oct 12 01:48:32 PM UTC 24 |
| Finished | Oct 12 01:49:30 PM UTC 24 |
| Peak memory | 207548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063245650 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1063245650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.1209106197 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 111511299688 ps |
| CPU time | 47.04 seconds |
| Started | Oct 12 01:48:40 PM UTC 24 |
| Finished | Oct 12 01:49:29 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209106197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1209106197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.2347433540 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 69801062564 ps |
| CPU time | 114.54 seconds |
| Started | Oct 12 01:48:40 PM UTC 24 |
| Finished | Oct 12 01:50:37 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347433540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2347433540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_smoke.1721469605 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 10612264571 ps |
| CPU time | 12.47 seconds |
| Started | Oct 12 01:48:15 PM UTC 24 |
| Finished | Oct 12 01:48:28 PM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721469605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1721469605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_stress_all.2648615919 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 633208497086 ps |
| CPU time | 222.91 seconds |
| Started | Oct 12 01:48:56 PM UTC 24 |
| Finished | Oct 12 01:52:42 PM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648615919 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2648615919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.2938801359 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 630020110 ps |
| CPU time | 8.97 seconds |
| Started | Oct 12 01:48:52 PM UTC 24 |
| Finished | Oct 12 01:49:02 PM UTC 24 |
| Peak memory | 208912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2938801359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all _with_rand_reset.2938801359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.1050387807 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3860154125 ps |
| CPU time | 2.62 seconds |
| Started | Oct 12 01:48:43 PM UTC 24 |
| Finished | Oct 12 01:48:46 PM UTC 24 |
| Peak memory | 207628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050387807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1050387807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/35.uart_tx_rx.2356000832 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 45983155522 ps |
| CPU time | 73.68 seconds |
| Started | Oct 12 01:48:16 PM UTC 24 |
| Finished | Oct 12 01:49:31 PM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356000832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2356000832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/35.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_alert_test.3221362982 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 26221959 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 01:49:29 PM UTC 24 |
| Finished | Oct 12 01:49:31 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221362982 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3221362982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_fifo_full.3646985930 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 113803427269 ps |
| CPU time | 245.44 seconds |
| Started | Oct 12 01:49:02 PM UTC 24 |
| Finished | Oct 12 01:53:11 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646985930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3646985930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.2640981490 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 11475977273 ps |
| CPU time | 22.88 seconds |
| Started | Oct 12 01:49:02 PM UTC 24 |
| Finished | Oct 12 01:49:26 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640981490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2640981490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_fifo_reset.1530794679 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 93121513514 ps |
| CPU time | 56.06 seconds |
| Started | Oct 12 01:49:04 PM UTC 24 |
| Finished | Oct 12 01:50:01 PM UTC 24 |
| Peak memory | 208200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530794679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1530794679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_intr.1036289113 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 41929415979 ps |
| CPU time | 77.51 seconds |
| Started | Oct 12 01:49:09 PM UTC 24 |
| Finished | Oct 12 01:50:28 PM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036289113 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1036289113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.3937948533 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 77516031821 ps |
| CPU time | 370.89 seconds |
| Started | Oct 12 01:49:24 PM UTC 24 |
| Finished | Oct 12 01:55:39 PM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937948533 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3937948533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_loopback.1536032215 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 10753327411 ps |
| CPU time | 7.61 seconds |
| Started | Oct 12 01:49:19 PM UTC 24 |
| Finished | Oct 12 01:49:28 PM UTC 24 |
| Peak memory | 207880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536032215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1536032215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_noise_filter.3259241046 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 145731301508 ps |
| CPU time | 114.31 seconds |
| Started | Oct 12 01:49:13 PM UTC 24 |
| Finished | Oct 12 01:51:10 PM UTC 24 |
| Peak memory | 208924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259241046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3259241046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_perf.2214079262 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 17039236674 ps |
| CPU time | 268 seconds |
| Started | Oct 12 01:49:19 PM UTC 24 |
| Finished | Oct 12 01:53:51 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214079262 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2214079262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_rx_oversample.4160346825 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 1606576398 ps |
| CPU time | 4.13 seconds |
| Started | Oct 12 01:49:07 PM UTC 24 |
| Finished | Oct 12 01:49:12 PM UTC 24 |
| Peak memory | 207296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160346825 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.4160346825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.3205080527 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 72902388214 ps |
| CPU time | 43.18 seconds |
| Started | Oct 12 01:49:14 PM UTC 24 |
| Finished | Oct 12 01:49:59 PM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205080527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3205080527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.3292655514 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3904147925 ps |
| CPU time | 4.04 seconds |
| Started | Oct 12 01:49:13 PM UTC 24 |
| Finished | Oct 12 01:49:18 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292655514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3292655514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_smoke.2497100250 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 292716810 ps |
| CPU time | 2.58 seconds |
| Started | Oct 12 01:48:58 PM UTC 24 |
| Finished | Oct 12 01:49:02 PM UTC 24 |
| Peak memory | 207420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497100250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2497100250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_stress_all.2720666228 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 333252178340 ps |
| CPU time | 525.03 seconds |
| Started | Oct 12 01:49:29 PM UTC 24 |
| Finished | Oct 12 01:58:21 PM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720666228 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2720666228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.2762696661 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 8182498059 ps |
| CPU time | 24.99 seconds |
| Started | Oct 12 01:49:28 PM UTC 24 |
| Finished | Oct 12 01:49:54 PM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2762696661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all _with_rand_reset.2762696661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.3634103874 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 6093334736 ps |
| CPU time | 18.48 seconds |
| Started | Oct 12 01:49:19 PM UTC 24 |
| Finished | Oct 12 01:49:39 PM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634103874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3634103874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/36.uart_tx_rx.2446355334 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 48240182173 ps |
| CPU time | 26.69 seconds |
| Started | Oct 12 01:48:59 PM UTC 24 |
| Finished | Oct 12 01:49:27 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446355334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2446355334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/36.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_alert_test.1118876303 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 15519053 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 01:50:03 PM UTC 24 |
| Finished | Oct 12 01:50:05 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118876303 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1118876303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_fifo_full.1015007421 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 165176647204 ps |
| CPU time | 25.28 seconds |
| Started | Oct 12 01:49:31 PM UTC 24 |
| Finished | Oct 12 01:49:58 PM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015007421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1015007421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.1139730372 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 159336088876 ps |
| CPU time | 406.61 seconds |
| Started | Oct 12 01:49:32 PM UTC 24 |
| Finished | Oct 12 01:56:24 PM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139730372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1139730372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_fifo_reset.2813931809 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 17594648339 ps |
| CPU time | 64.2 seconds |
| Started | Oct 12 01:49:33 PM UTC 24 |
| Finished | Oct 12 01:50:39 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813931809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2813931809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_intr.1122070035 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 31280973418 ps |
| CPU time | 21.41 seconds |
| Started | Oct 12 01:49:40 PM UTC 24 |
| Finished | Oct 12 01:50:02 PM UTC 24 |
| Peak memory | 208432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122070035 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1122070035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.298708057 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 146745456483 ps |
| CPU time | 493.86 seconds |
| Started | Oct 12 01:49:59 PM UTC 24 |
| Finished | Oct 12 01:58:19 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298708057 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.298708057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_loopback.1585994697 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 293165394 ps |
| CPU time | 1.9 seconds |
| Started | Oct 12 01:49:58 PM UTC 24 |
| Finished | Oct 12 01:50:01 PM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585994697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1585994697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_noise_filter.290458698 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 182581248627 ps |
| CPU time | 178.08 seconds |
| Started | Oct 12 01:49:40 PM UTC 24 |
| Finished | Oct 12 01:52:41 PM UTC 24 |
| Peak memory | 217912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290458698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.290458698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_perf.1168163219 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 8676967588 ps |
| CPU time | 287.05 seconds |
| Started | Oct 12 01:49:58 PM UTC 24 |
| Finished | Oct 12 01:54:50 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168163219 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1168163219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_rx_oversample.1590463534 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 6139860995 ps |
| CPU time | 68.91 seconds |
| Started | Oct 12 01:49:35 PM UTC 24 |
| Finished | Oct 12 01:50:45 PM UTC 24 |
| Peak memory | 207656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590463534 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1590463534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.1445115015 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 74479836435 ps |
| CPU time | 29.05 seconds |
| Started | Oct 12 01:49:55 PM UTC 24 |
| Finished | Oct 12 01:50:25 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445115015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1445115015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.1918761927 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 1709149449 ps |
| CPU time | 3.65 seconds |
| Started | Oct 12 01:49:53 PM UTC 24 |
| Finished | Oct 12 01:49:58 PM UTC 24 |
| Peak memory | 205112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918761927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1918761927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_smoke.3472590303 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 501612682 ps |
| CPU time | 1.93 seconds |
| Started | Oct 12 01:49:30 PM UTC 24 |
| Finished | Oct 12 01:49:33 PM UTC 24 |
| Peak memory | 206256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472590303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3472590303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_stress_all.2610899084 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 187655483075 ps |
| CPU time | 684.91 seconds |
| Started | Oct 12 01:50:03 PM UTC 24 |
| Finished | Oct 12 02:01:36 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610899084 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2610899084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.2651357144 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 11176665495 ps |
| CPU time | 40.29 seconds |
| Started | Oct 12 01:50:02 PM UTC 24 |
| Finished | Oct 12 01:50:45 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2651357144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all _with_rand_reset.2651357144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.4209421472 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 1047046393 ps |
| CPU time | 5.18 seconds |
| Started | Oct 12 01:49:55 PM UTC 24 |
| Finished | Oct 12 01:50:01 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209421472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.4209421472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/37.uart_tx_rx.488179162 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 68644087133 ps |
| CPU time | 66.51 seconds |
| Started | Oct 12 01:49:31 PM UTC 24 |
| Finished | Oct 12 01:50:39 PM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488179162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.488179162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/37.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_alert_test.1073618631 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 20369904 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 01:50:46 PM UTC 24 |
| Finished | Oct 12 01:50:48 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073618631 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1073618631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_fifo_full.1869948583 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 169024638192 ps |
| CPU time | 31.51 seconds |
| Started | Oct 12 01:50:06 PM UTC 24 |
| Finished | Oct 12 01:50:39 PM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869948583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1869948583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.281948740 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 19828117486 ps |
| CPU time | 35.97 seconds |
| Started | Oct 12 01:50:11 PM UTC 24 |
| Finished | Oct 12 01:50:48 PM UTC 24 |
| Peak memory | 207580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281948740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.281948740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_fifo_reset.76093660 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 41752576706 ps |
| CPU time | 109.62 seconds |
| Started | Oct 12 01:50:21 PM UTC 24 |
| Finished | Oct 12 01:52:13 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76093660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.76093660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_intr.3756182355 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 19456786376 ps |
| CPU time | 20.85 seconds |
| Started | Oct 12 01:50:27 PM UTC 24 |
| Finished | Oct 12 01:50:49 PM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756182355 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3756182355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.4030934834 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 160939817619 ps |
| CPU time | 581.87 seconds |
| Started | Oct 12 01:50:41 PM UTC 24 |
| Finished | Oct 12 02:00:30 PM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030934834 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.4030934834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_loopback.1295204710 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 5514398002 ps |
| CPU time | 5.98 seconds |
| Started | Oct 12 01:50:40 PM UTC 24 |
| Finished | Oct 12 01:50:47 PM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295204710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1295204710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_noise_filter.4078462364 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 43384394673 ps |
| CPU time | 33.56 seconds |
| Started | Oct 12 01:50:29 PM UTC 24 |
| Finished | Oct 12 01:51:04 PM UTC 24 |
| Peak memory | 207556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078462364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.4078462364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_perf.3767955077 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 10564150697 ps |
| CPU time | 336.31 seconds |
| Started | Oct 12 01:50:40 PM UTC 24 |
| Finished | Oct 12 01:56:21 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767955077 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3767955077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_rx_oversample.2987680779 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3947795071 ps |
| CPU time | 10.88 seconds |
| Started | Oct 12 01:50:26 PM UTC 24 |
| Finished | Oct 12 01:50:38 PM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987680779 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2987680779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.487717308 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 29118115528 ps |
| CPU time | 27.92 seconds |
| Started | Oct 12 01:50:38 PM UTC 24 |
| Finished | Oct 12 01:51:08 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487717308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.487717308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.3712420616 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1929829094 ps |
| CPU time | 8 seconds |
| Started | Oct 12 01:50:37 PM UTC 24 |
| Finished | Oct 12 01:50:46 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712420616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3712420616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_smoke.1726766339 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 5440473765 ps |
| CPU time | 16.31 seconds |
| Started | Oct 12 01:50:03 PM UTC 24 |
| Finished | Oct 12 01:50:21 PM UTC 24 |
| Peak memory | 207532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726766339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1726766339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_stress_all.1797840866 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 126431545292 ps |
| CPU time | 51.48 seconds |
| Started | Oct 12 01:50:45 PM UTC 24 |
| Finished | Oct 12 01:51:38 PM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797840866 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1797840866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.37605338 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 8258488852 ps |
| CPU time | 100.69 seconds |
| Started | Oct 12 01:50:44 PM UTC 24 |
| Finished | Oct 12 01:52:27 PM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=37605338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all_w ith_rand_reset.37605338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.2501331902 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 7158402035 ps |
| CPU time | 18.8 seconds |
| Started | Oct 12 01:50:40 PM UTC 24 |
| Finished | Oct 12 01:51:00 PM UTC 24 |
| Peak memory | 208360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501331902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2501331902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/38.uart_tx_rx.3832866709 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 55936124298 ps |
| CPU time | 82.06 seconds |
| Started | Oct 12 01:50:04 PM UTC 24 |
| Finished | Oct 12 01:51:27 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832866709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3832866709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/38.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_alert_test.1044659377 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 73021034 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 01:51:22 PM UTC 24 |
| Finished | Oct 12 01:51:23 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044659377 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1044659377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_fifo_full.4004172831 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 50162710654 ps |
| CPU time | 126.75 seconds |
| Started | Oct 12 01:50:47 PM UTC 24 |
| Finished | Oct 12 01:52:56 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004172831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.4004172831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.660936609 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 14038541425 ps |
| CPU time | 24.48 seconds |
| Started | Oct 12 01:50:48 PM UTC 24 |
| Finished | Oct 12 01:51:14 PM UTC 24 |
| Peak memory | 208808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660936609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.660936609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_fifo_reset.2865444179 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 282729600516 ps |
| CPU time | 534.24 seconds |
| Started | Oct 12 01:50:50 PM UTC 24 |
| Finished | Oct 12 01:59:50 PM UTC 24 |
| Peak memory | 208584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865444179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2865444179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_intr.4049416493 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 78869024421 ps |
| CPU time | 43.68 seconds |
| Started | Oct 12 01:50:51 PM UTC 24 |
| Finished | Oct 12 01:51:36 PM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049416493 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.4049416493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.1767158562 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 297126284374 ps |
| CPU time | 355.19 seconds |
| Started | Oct 12 01:51:15 PM UTC 24 |
| Finished | Oct 12 01:57:15 PM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767158562 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1767158562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_loopback.1509790132 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4670635835 ps |
| CPU time | 14.33 seconds |
| Started | Oct 12 01:51:10 PM UTC 24 |
| Finished | Oct 12 01:51:26 PM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509790132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1509790132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_noise_filter.3586270847 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 34484564763 ps |
| CPU time | 59.77 seconds |
| Started | Oct 12 01:51:01 PM UTC 24 |
| Finished | Oct 12 01:52:02 PM UTC 24 |
| Peak memory | 208512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586270847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3586270847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_perf.1799936481 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 13335960648 ps |
| CPU time | 762 seconds |
| Started | Oct 12 01:51:13 PM UTC 24 |
| Finished | Oct 12 02:04:05 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799936481 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1799936481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_rx_oversample.172011432 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 5597773063 ps |
| CPU time | 16.61 seconds |
| Started | Oct 12 01:50:50 PM UTC 24 |
| Finished | Oct 12 01:51:07 PM UTC 24 |
| Peak memory | 207356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172011432 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.172011432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.2669179528 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 30760695878 ps |
| CPU time | 22 seconds |
| Started | Oct 12 01:51:08 PM UTC 24 |
| Finished | Oct 12 01:51:31 PM UTC 24 |
| Peak memory | 208804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669179528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2669179528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.2309479526 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3326303934 ps |
| CPU time | 6.63 seconds |
| Started | Oct 12 01:51:05 PM UTC 24 |
| Finished | Oct 12 01:51:13 PM UTC 24 |
| Peak memory | 205240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309479526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2309479526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_smoke.140786673 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 334011299 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 01:50:46 PM UTC 24 |
| Finished | Oct 12 01:50:49 PM UTC 24 |
| Peak memory | 206188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140786673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 39.uart_smoke.140786673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_stress_all.577905936 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 29902120944 ps |
| CPU time | 564.47 seconds |
| Started | Oct 12 01:51:20 PM UTC 24 |
| Finished | Oct 12 02:00:51 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577905936 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.577905936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.1824079509 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 3296096623 ps |
| CPU time | 29.83 seconds |
| Started | Oct 12 01:51:17 PM UTC 24 |
| Finished | Oct 12 01:51:48 PM UTC 24 |
| Peak memory | 218060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1824079509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all _with_rand_reset.1824079509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1884700312 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 1177722983 ps |
| CPU time | 6.33 seconds |
| Started | Oct 12 01:51:08 PM UTC 24 |
| Finished | Oct 12 01:51:16 PM UTC 24 |
| Peak memory | 207448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884700312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1884700312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/39.uart_tx_rx.313281886 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 12161572010 ps |
| CPU time | 29.87 seconds |
| Started | Oct 12 01:50:47 PM UTC 24 |
| Finished | Oct 12 01:51:18 PM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313281886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.313281886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/39.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_alert_test.1025647519 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 36277016 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 01:29:44 PM UTC 24 |
| Finished | Oct 12 01:29:46 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025647519 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1025647519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_fifo_full.2828519254 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 100785628313 ps |
| CPU time | 23.83 seconds |
| Started | Oct 12 01:29:33 PM UTC 24 |
| Finished | Oct 12 01:29:58 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828519254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2828519254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_intr.940464067 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 19326170735 ps |
| CPU time | 7.57 seconds |
| Started | Oct 12 01:29:34 PM UTC 24 |
| Finished | Oct 12 01:29:43 PM UTC 24 |
| Peak memory | 207232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940464067 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.940464067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.3457634939 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 198364307310 ps |
| CPU time | 1374.13 seconds |
| Started | Oct 12 01:29:39 PM UTC 24 |
| Finished | Oct 12 01:52:49 PM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457634939 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3457634939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_loopback.2720181859 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 7837559607 ps |
| CPU time | 8.37 seconds |
| Started | Oct 12 01:29:38 PM UTC 24 |
| Finished | Oct 12 01:29:47 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720181859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2720181859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_perf.1294570288 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 7179027162 ps |
| CPU time | 46.71 seconds |
| Started | Oct 12 01:29:39 PM UTC 24 |
| Finished | Oct 12 01:30:27 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294570288 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1294570288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_rx_oversample.2794084058 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 6888100355 ps |
| CPU time | 62.76 seconds |
| Started | Oct 12 01:29:34 PM UTC 24 |
| Finished | Oct 12 01:30:38 PM UTC 24 |
| Peak memory | 207408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794084058 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2794084058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.2888642621 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 490946212 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 01:29:35 PM UTC 24 |
| Finished | Oct 12 01:29:38 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888642621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2888642621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_sec_cm.1532851743 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 217443044 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 01:29:41 PM UTC 24 |
| Finished | Oct 12 01:29:43 PM UTC 24 |
| Peak memory | 240120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532851743 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1532851743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_smoke.4280577450 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 474105116 ps |
| CPU time | 1.84 seconds |
| Started | Oct 12 01:29:31 PM UTC 24 |
| Finished | Oct 12 01:29:34 PM UTC 24 |
| Peak memory | 206256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280577450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.uart_smoke.4280577450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.3660482409 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2137809066 ps |
| CPU time | 2.18 seconds |
| Started | Oct 12 01:29:36 PM UTC 24 |
| Finished | Oct 12 01:29:40 PM UTC 24 |
| Peak memory | 207228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660482409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3660482409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_tx_rx.607198528 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 72674271024 ps |
| CPU time | 50.76 seconds |
| Started | Oct 12 01:29:32 PM UTC 24 |
| Finished | Oct 12 01:30:24 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607198528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.607198528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_alert_test.3157388135 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 85818247 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 01:52:25 PM UTC 24 |
| Finished | Oct 12 01:52:27 PM UTC 24 |
| Peak memory | 204388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157388135 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3157388135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_fifo_full.3408686391 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 87208120047 ps |
| CPU time | 72.04 seconds |
| Started | Oct 12 01:51:28 PM UTC 24 |
| Finished | Oct 12 01:52:42 PM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408686391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3408686391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.2245968774 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 175733616815 ps |
| CPU time | 88.94 seconds |
| Started | Oct 12 01:51:29 PM UTC 24 |
| Finished | Oct 12 01:53:00 PM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245968774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2245968774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_fifo_reset.1716141207 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 24727032732 ps |
| CPU time | 34.77 seconds |
| Started | Oct 12 01:51:32 PM UTC 24 |
| Finished | Oct 12 01:52:09 PM UTC 24 |
| Peak memory | 208412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716141207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1716141207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_intr.994738528 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 45497670989 ps |
| CPU time | 51.21 seconds |
| Started | Oct 12 01:51:39 PM UTC 24 |
| Finished | Oct 12 01:52:32 PM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994738528 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.994738528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.3459484692 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 189604310004 ps |
| CPU time | 206.02 seconds |
| Started | Oct 12 01:52:03 PM UTC 24 |
| Finished | Oct 12 01:55:32 PM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459484692 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3459484692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_loopback.1344133635 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 7727011354 ps |
| CPU time | 28.23 seconds |
| Started | Oct 12 01:51:59 PM UTC 24 |
| Finished | Oct 12 01:52:28 PM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344133635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1344133635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_noise_filter.3148468742 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 63524690281 ps |
| CPU time | 47.45 seconds |
| Started | Oct 12 01:51:48 PM UTC 24 |
| Finished | Oct 12 01:52:37 PM UTC 24 |
| Peak memory | 217772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148468742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3148468742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_perf.2946587988 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 13866183109 ps |
| CPU time | 844.29 seconds |
| Started | Oct 12 01:52:03 PM UTC 24 |
| Finished | Oct 12 02:06:17 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946587988 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2946587988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_rx_oversample.3826805663 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 7272120441 ps |
| CPU time | 24.92 seconds |
| Started | Oct 12 01:51:36 PM UTC 24 |
| Finished | Oct 12 01:52:02 PM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826805663 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3826805663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.2567983783 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 19265546627 ps |
| CPU time | 32.3 seconds |
| Started | Oct 12 01:51:51 PM UTC 24 |
| Finished | Oct 12 01:52:25 PM UTC 24 |
| Peak memory | 207228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567983783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2567983783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.2289690808 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4133964957 ps |
| CPU time | 3.63 seconds |
| Started | Oct 12 01:51:50 PM UTC 24 |
| Finished | Oct 12 01:51:54 PM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289690808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2289690808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_smoke.1929059815 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 5469843742 ps |
| CPU time | 23.17 seconds |
| Started | Oct 12 01:51:25 PM UTC 24 |
| Finished | Oct 12 01:51:49 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929059815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1929059815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_stress_all.2617330325 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 296669687752 ps |
| CPU time | 362.69 seconds |
| Started | Oct 12 01:52:14 PM UTC 24 |
| Finished | Oct 12 01:58:21 PM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617330325 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2617330325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.1888979843 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 7641982473 ps |
| CPU time | 27.78 seconds |
| Started | Oct 12 01:52:09 PM UTC 24 |
| Finished | Oct 12 01:52:38 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1888979843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all _with_rand_reset.1888979843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.2755795259 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1158418242 ps |
| CPU time | 2.18 seconds |
| Started | Oct 12 01:51:55 PM UTC 24 |
| Finished | Oct 12 01:51:58 PM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755795259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2755795259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/40.uart_tx_rx.2857236738 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 10086955481 ps |
| CPU time | 21.56 seconds |
| Started | Oct 12 01:51:27 PM UTC 24 |
| Finished | Oct 12 01:51:50 PM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857236738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2857236738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/40.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_alert_test.998324777 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 15263020 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 01:52:54 PM UTC 24 |
| Finished | Oct 12 01:52:55 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998324777 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.998324777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_fifo_full.40288151 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 46413126565 ps |
| CPU time | 90.84 seconds |
| Started | Oct 12 01:52:29 PM UTC 24 |
| Finished | Oct 12 01:54:02 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40288151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.40288151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.1182583956 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 111094744718 ps |
| CPU time | 55.9 seconds |
| Started | Oct 12 01:52:30 PM UTC 24 |
| Finished | Oct 12 01:53:27 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182583956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1182583956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_fifo_reset.3740573508 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 79187252268 ps |
| CPU time | 44.54 seconds |
| Started | Oct 12 01:52:33 PM UTC 24 |
| Finished | Oct 12 01:53:19 PM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740573508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3740573508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_intr.352008382 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 59028465969 ps |
| CPU time | 74 seconds |
| Started | Oct 12 01:52:38 PM UTC 24 |
| Finished | Oct 12 01:53:54 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352008382 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.352008382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.380995862 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 69030606320 ps |
| CPU time | 519.44 seconds |
| Started | Oct 12 01:52:47 PM UTC 24 |
| Finished | Oct 12 02:01:33 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380995862 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.380995862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_loopback.3708830012 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3831192089 ps |
| CPU time | 4.43 seconds |
| Started | Oct 12 01:52:43 PM UTC 24 |
| Finished | Oct 12 01:52:49 PM UTC 24 |
| Peak memory | 208324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708830012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3708830012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_noise_filter.1563389141 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 21762916793 ps |
| CPU time | 40.91 seconds |
| Started | Oct 12 01:52:39 PM UTC 24 |
| Finished | Oct 12 01:53:21 PM UTC 24 |
| Peak memory | 207952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563389141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1563389141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_perf.2220377493 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 13768078669 ps |
| CPU time | 845.89 seconds |
| Started | Oct 12 01:52:43 PM UTC 24 |
| Finished | Oct 12 02:06:59 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220377493 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2220377493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_rx_oversample.1877439568 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 6120808166 ps |
| CPU time | 8.6 seconds |
| Started | Oct 12 01:52:33 PM UTC 24 |
| Finished | Oct 12 01:52:42 PM UTC 24 |
| Peak memory | 207432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877439568 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1877439568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.3979305890 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 283222320553 ps |
| CPU time | 32.44 seconds |
| Started | Oct 12 01:52:42 PM UTC 24 |
| Finished | Oct 12 01:53:16 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979305890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3979305890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.3815850073 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 4507702757 ps |
| CPU time | 12.56 seconds |
| Started | Oct 12 01:52:39 PM UTC 24 |
| Finished | Oct 12 01:52:53 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815850073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3815850073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_smoke.4156365269 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 959640136 ps |
| CPU time | 3.1 seconds |
| Started | Oct 12 01:52:27 PM UTC 24 |
| Finished | Oct 12 01:52:32 PM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156365269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.uart_smoke.4156365269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_stress_all.698705075 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 529731418783 ps |
| CPU time | 392.22 seconds |
| Started | Oct 12 01:52:50 PM UTC 24 |
| Finished | Oct 12 01:59:27 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698705075 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.698705075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.3051774838 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 526600341 ps |
| CPU time | 10.06 seconds |
| Started | Oct 12 01:52:50 PM UTC 24 |
| Finished | Oct 12 01:53:01 PM UTC 24 |
| Peak memory | 224320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3051774838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all _with_rand_reset.3051774838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.3061486956 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 868090786 ps |
| CPU time | 3.5 seconds |
| Started | Oct 12 01:52:42 PM UTC 24 |
| Finished | Oct 12 01:52:47 PM UTC 24 |
| Peak memory | 207300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061486956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3061486956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/41.uart_tx_rx.3582743847 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 30773512450 ps |
| CPU time | 28.83 seconds |
| Started | Oct 12 01:52:28 PM UTC 24 |
| Finished | Oct 12 01:52:59 PM UTC 24 |
| Peak memory | 208540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582743847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3582743847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/41.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_alert_test.3515174398 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 65843385 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 01:53:31 PM UTC 24 |
| Finished | Oct 12 01:53:33 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515174398 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3515174398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_fifo_full.3375724416 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 96482956449 ps |
| CPU time | 112.97 seconds |
| Started | Oct 12 01:52:57 PM UTC 24 |
| Finished | Oct 12 01:54:52 PM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375724416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3375724416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.982256326 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 77829751163 ps |
| CPU time | 79.52 seconds |
| Started | Oct 12 01:53:00 PM UTC 24 |
| Finished | Oct 12 01:54:21 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982256326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.982256326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_fifo_reset.2071029615 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 26462583922 ps |
| CPU time | 61.78 seconds |
| Started | Oct 12 01:53:00 PM UTC 24 |
| Finished | Oct 12 01:54:03 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071029615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2071029615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_intr.2267192161 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 27346297038 ps |
| CPU time | 86.33 seconds |
| Started | Oct 12 01:53:01 PM UTC 24 |
| Finished | Oct 12 01:54:29 PM UTC 24 |
| Peak memory | 208540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267192161 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2267192161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.1390780362 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 140878594096 ps |
| CPU time | 505.44 seconds |
| Started | Oct 12 01:53:22 PM UTC 24 |
| Finished | Oct 12 02:01:54 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390780362 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1390780362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_loopback.4028835890 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 10162290563 ps |
| CPU time | 9.24 seconds |
| Started | Oct 12 01:53:20 PM UTC 24 |
| Finished | Oct 12 01:53:31 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028835890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 42.uart_loopback.4028835890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_noise_filter.4035883781 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 250233910315 ps |
| CPU time | 65.75 seconds |
| Started | Oct 12 01:53:04 PM UTC 24 |
| Finished | Oct 12 01:54:12 PM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035883781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.4035883781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_perf.1084854579 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 22508684047 ps |
| CPU time | 629.82 seconds |
| Started | Oct 12 01:53:22 PM UTC 24 |
| Finished | Oct 12 02:04:00 PM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084854579 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1084854579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_rx_oversample.2534011151 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 3292343023 ps |
| CPU time | 10.21 seconds |
| Started | Oct 12 01:53:01 PM UTC 24 |
| Finished | Oct 12 01:53:13 PM UTC 24 |
| Peak memory | 208196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534011151 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2534011151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.2809989390 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 79374800391 ps |
| CPU time | 39.36 seconds |
| Started | Oct 12 01:53:14 PM UTC 24 |
| Finished | Oct 12 01:53:54 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809989390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2809989390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.4097137087 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 4376399182 ps |
| CPU time | 16.55 seconds |
| Started | Oct 12 01:53:12 PM UTC 24 |
| Finished | Oct 12 01:53:30 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097137087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4097137087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_smoke.3011745575 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 881161804 ps |
| CPU time | 2.75 seconds |
| Started | Oct 12 01:52:56 PM UTC 24 |
| Finished | Oct 12 01:52:59 PM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011745575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3011745575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_stress_all.2620580190 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 241354265325 ps |
| CPU time | 287.53 seconds |
| Started | Oct 12 01:53:31 PM UTC 24 |
| Finished | Oct 12 01:58:23 PM UTC 24 |
| Peak memory | 217840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620580190 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2620580190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.2954900667 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 3029812445 ps |
| CPU time | 56.64 seconds |
| Started | Oct 12 01:53:28 PM UTC 24 |
| Finished | Oct 12 01:54:26 PM UTC 24 |
| Peak memory | 221960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2954900667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all _with_rand_reset.2954900667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.1002344710 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 538219847 ps |
| CPU time | 2.99 seconds |
| Started | Oct 12 01:53:17 PM UTC 24 |
| Finished | Oct 12 01:53:21 PM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002344710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1002344710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/42.uart_tx_rx.46434374 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 50126226605 ps |
| CPU time | 32.72 seconds |
| Started | Oct 12 01:52:56 PM UTC 24 |
| Finished | Oct 12 01:53:30 PM UTC 24 |
| Peak memory | 208856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46434374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.46434374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/42.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_alert_test.1564778417 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 18302647 ps |
| CPU time | 0.82 seconds |
| Started | Oct 12 01:54:14 PM UTC 24 |
| Finished | Oct 12 01:54:15 PM UTC 24 |
| Peak memory | 202116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564778417 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1564778417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_fifo_full.1514041600 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 241320909133 ps |
| CPU time | 83.25 seconds |
| Started | Oct 12 01:53:49 PM UTC 24 |
| Finished | Oct 12 01:55:14 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514041600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1514041600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.1415088899 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 17750405939 ps |
| CPU time | 36.12 seconds |
| Started | Oct 12 01:53:52 PM UTC 24 |
| Finished | Oct 12 01:54:29 PM UTC 24 |
| Peak memory | 207608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415088899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1415088899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_fifo_reset.316368733 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 158998225384 ps |
| CPU time | 319.92 seconds |
| Started | Oct 12 01:53:53 PM UTC 24 |
| Finished | Oct 12 01:59:17 PM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316368733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.316368733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_intr.4121569502 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 40171217110 ps |
| CPU time | 81.79 seconds |
| Started | Oct 12 01:53:55 PM UTC 24 |
| Finished | Oct 12 01:55:18 PM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121569502 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.4121569502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.2064243684 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 125586040759 ps |
| CPU time | 1189.78 seconds |
| Started | Oct 12 01:54:12 PM UTC 24 |
| Finished | Oct 12 02:14:17 PM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064243684 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2064243684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_loopback.1120434589 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 4445175084 ps |
| CPU time | 4.79 seconds |
| Started | Oct 12 01:54:07 PM UTC 24 |
| Finished | Oct 12 01:54:13 PM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120434589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1120434589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_noise_filter.3664408337 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 119867262258 ps |
| CPU time | 97.16 seconds |
| Started | Oct 12 01:53:57 PM UTC 24 |
| Finished | Oct 12 01:55:36 PM UTC 24 |
| Peak memory | 208976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664408337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3664408337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_perf.156380370 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 16997738311 ps |
| CPU time | 484.26 seconds |
| Started | Oct 12 01:54:10 PM UTC 24 |
| Finished | Oct 12 02:02:21 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156380370 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.156380370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_rx_oversample.3023713971 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 5183405569 ps |
| CPU time | 21.43 seconds |
| Started | Oct 12 01:53:55 PM UTC 24 |
| Finished | Oct 12 01:54:17 PM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023713971 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3023713971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.352796106 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 31562258709 ps |
| CPU time | 55.15 seconds |
| Started | Oct 12 01:54:04 PM UTC 24 |
| Finished | Oct 12 01:55:01 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352796106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.352796106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.3612026407 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 37251212045 ps |
| CPU time | 51.64 seconds |
| Started | Oct 12 01:54:03 PM UTC 24 |
| Finished | Oct 12 01:54:56 PM UTC 24 |
| Peak memory | 205304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612026407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3612026407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_smoke.1381612738 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 11053414317 ps |
| CPU time | 23.61 seconds |
| Started | Oct 12 01:53:31 PM UTC 24 |
| Finished | Oct 12 01:53:56 PM UTC 24 |
| Peak memory | 208460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381612738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1381612738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_stress_all.2702739587 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 127828935306 ps |
| CPU time | 248.6 seconds |
| Started | Oct 12 01:54:14 PM UTC 24 |
| Finished | Oct 12 01:58:25 PM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702739587 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2702739587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.61735673 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 10731887128 ps |
| CPU time | 32.6 seconds |
| Started | Oct 12 01:54:12 PM UTC 24 |
| Finished | Oct 12 01:54:46 PM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=61735673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all_w ith_rand_reset.61735673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.2620403677 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 438751233 ps |
| CPU time | 2.8 seconds |
| Started | Oct 12 01:54:06 PM UTC 24 |
| Finished | Oct 12 01:54:10 PM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620403677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2620403677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/43.uart_tx_rx.3846943634 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 13354164530 ps |
| CPU time | 12.85 seconds |
| Started | Oct 12 01:53:34 PM UTC 24 |
| Finished | Oct 12 01:53:49 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846943634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3846943634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/43.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_alert_test.3600288826 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 10891413 ps |
| CPU time | 0.83 seconds |
| Started | Oct 12 01:54:58 PM UTC 24 |
| Finished | Oct 12 01:55:00 PM UTC 24 |
| Peak memory | 202340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600288826 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3600288826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.3338982302 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 138094942735 ps |
| CPU time | 247.99 seconds |
| Started | Oct 12 01:54:22 PM UTC 24 |
| Finished | Oct 12 01:58:33 PM UTC 24 |
| Peak memory | 208472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338982302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3338982302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_fifo_reset.1640746454 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 265068898528 ps |
| CPU time | 182.11 seconds |
| Started | Oct 12 01:54:23 PM UTC 24 |
| Finished | Oct 12 01:57:28 PM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640746454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1640746454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_intr.816722685 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 19238653598 ps |
| CPU time | 30.82 seconds |
| Started | Oct 12 01:54:29 PM UTC 24 |
| Finished | Oct 12 01:55:02 PM UTC 24 |
| Peak memory | 207220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816722685 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.816722685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.4097332137 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 219108066649 ps |
| CPU time | 433.96 seconds |
| Started | Oct 12 01:54:50 PM UTC 24 |
| Finished | Oct 12 02:02:10 PM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097332137 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.4097332137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_loopback.2752531051 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 7615989599 ps |
| CPU time | 25.14 seconds |
| Started | Oct 12 01:54:48 PM UTC 24 |
| Finished | Oct 12 01:55:14 PM UTC 24 |
| Peak memory | 207320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752531051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2752531051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_noise_filter.104252866 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 77362395897 ps |
| CPU time | 162.25 seconds |
| Started | Oct 12 01:54:30 PM UTC 24 |
| Finished | Oct 12 01:57:16 PM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104252866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.104252866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_perf.282200134 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 16269099470 ps |
| CPU time | 230.26 seconds |
| Started | Oct 12 01:54:48 PM UTC 24 |
| Finished | Oct 12 01:58:41 PM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282200134 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.282200134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_rx_oversample.2662922526 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 1777318140 ps |
| CPU time | 1.92 seconds |
| Started | Oct 12 01:54:27 PM UTC 24 |
| Finished | Oct 12 01:54:30 PM UTC 24 |
| Peak memory | 206288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662922526 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2662922526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.4260138917 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 60410761319 ps |
| CPU time | 145.39 seconds |
| Started | Oct 12 01:54:31 PM UTC 24 |
| Finished | Oct 12 01:56:58 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260138917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.4260138917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.2030761211 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 40920929371 ps |
| CPU time | 42.18 seconds |
| Started | Oct 12 01:54:30 PM UTC 24 |
| Finished | Oct 12 01:55:14 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030761211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2030761211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_smoke.776671228 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 6292955108 ps |
| CPU time | 11.35 seconds |
| Started | Oct 12 01:54:17 PM UTC 24 |
| Finished | Oct 12 01:54:29 PM UTC 24 |
| Peak memory | 208240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776671228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 44.uart_smoke.776671228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_stress_all.357389223 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 59570242576 ps |
| CPU time | 156.84 seconds |
| Started | Oct 12 01:54:57 PM UTC 24 |
| Finished | Oct 12 01:57:37 PM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357389223 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.357389223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.1580156452 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 6363717783 ps |
| CPU time | 16.38 seconds |
| Started | Oct 12 01:54:53 PM UTC 24 |
| Finished | Oct 12 01:55:11 PM UTC 24 |
| Peak memory | 219876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1580156452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all _with_rand_reset.1580156452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.3390357999 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 10803897910 ps |
| CPU time | 14.26 seconds |
| Started | Oct 12 01:54:32 PM UTC 24 |
| Finished | Oct 12 01:54:47 PM UTC 24 |
| Peak memory | 208668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390357999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3390357999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/44.uart_tx_rx.4191130559 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 30706331428 ps |
| CPU time | 37.8 seconds |
| Started | Oct 12 01:54:18 PM UTC 24 |
| Finished | Oct 12 01:54:57 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191130559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.4191130559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_alert_test.2140216524 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 14413274 ps |
| CPU time | 0.88 seconds |
| Started | Oct 12 01:55:33 PM UTC 24 |
| Finished | Oct 12 01:55:35 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140216524 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2140216524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_fifo_full.2152398691 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 215205333929 ps |
| CPU time | 180.61 seconds |
| Started | Oct 12 01:55:02 PM UTC 24 |
| Finished | Oct 12 01:58:06 PM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152398691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2152398691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.824703336 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 97985234866 ps |
| CPU time | 34.34 seconds |
| Started | Oct 12 01:55:06 PM UTC 24 |
| Finished | Oct 12 01:55:41 PM UTC 24 |
| Peak memory | 208152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824703336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.824703336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_fifo_reset.2133313205 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 53207330797 ps |
| CPU time | 98.59 seconds |
| Started | Oct 12 01:55:12 PM UTC 24 |
| Finished | Oct 12 01:56:52 PM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133313205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2133313205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_intr.1638148642 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 103757534356 ps |
| CPU time | 181.76 seconds |
| Started | Oct 12 01:55:15 PM UTC 24 |
| Finished | Oct 12 01:58:19 PM UTC 24 |
| Peak memory | 208440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638148642 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1638148642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.1962653216 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 110047775958 ps |
| CPU time | 438.37 seconds |
| Started | Oct 12 01:55:32 PM UTC 24 |
| Finished | Oct 12 02:02:56 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962653216 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1962653216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_loopback.2767693263 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 11035825907 ps |
| CPU time | 38.38 seconds |
| Started | Oct 12 01:55:28 PM UTC 24 |
| Finished | Oct 12 01:56:07 PM UTC 24 |
| Peak memory | 207340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767693263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2767693263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_noise_filter.399921459 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 147980773118 ps |
| CPU time | 26.79 seconds |
| Started | Oct 12 01:55:16 PM UTC 24 |
| Finished | Oct 12 01:55:44 PM UTC 24 |
| Peak memory | 208040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399921459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.399921459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_perf.2918492534 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 24238712120 ps |
| CPU time | 131.67 seconds |
| Started | Oct 12 01:55:31 PM UTC 24 |
| Finished | Oct 12 01:57:45 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918492534 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2918492534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_rx_oversample.2681515465 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 2543328493 ps |
| CPU time | 9.77 seconds |
| Started | Oct 12 01:55:15 PM UTC 24 |
| Finished | Oct 12 01:55:26 PM UTC 24 |
| Peak memory | 207272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681515465 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2681515465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.2993586363 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 29295402058 ps |
| CPU time | 30.58 seconds |
| Started | Oct 12 01:55:24 PM UTC 24 |
| Finished | Oct 12 01:55:56 PM UTC 24 |
| Peak memory | 208348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993586363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2993586363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.2981880443 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 4185596980 ps |
| CPU time | 3.31 seconds |
| Started | Oct 12 01:55:19 PM UTC 24 |
| Finished | Oct 12 01:55:24 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981880443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2981880443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_smoke.4157714244 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 428830017 ps |
| CPU time | 2.7 seconds |
| Started | Oct 12 01:55:01 PM UTC 24 |
| Finished | Oct 12 01:55:05 PM UTC 24 |
| Peak memory | 208152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157714244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 45.uart_smoke.4157714244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_stress_all.207669579 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 247410772763 ps |
| CPU time | 1558.68 seconds |
| Started | Oct 12 01:55:33 PM UTC 24 |
| Finished | Oct 12 02:21:50 PM UTC 24 |
| Peak memory | 222420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207669579 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.207669579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.3383503145 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3476542166 ps |
| CPU time | 47.26 seconds |
| Started | Oct 12 01:55:33 PM UTC 24 |
| Finished | Oct 12 01:56:22 PM UTC 24 |
| Peak memory | 217920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3383503145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all _with_rand_reset.3383503145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.753523290 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1736947360 ps |
| CPU time | 3.79 seconds |
| Started | Oct 12 01:55:26 PM UTC 24 |
| Finished | Oct 12 01:55:31 PM UTC 24 |
| Peak memory | 207596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753523290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.753523290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/45.uart_tx_rx.3203598421 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 68001344988 ps |
| CPU time | 26.97 seconds |
| Started | Oct 12 01:55:01 PM UTC 24 |
| Finished | Oct 12 01:55:30 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203598421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3203598421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/45.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_alert_test.4222702618 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 22670927 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 01:56:25 PM UTC 24 |
| Finished | Oct 12 01:56:26 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222702618 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.4222702618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_fifo_full.2756811433 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 137383560342 ps |
| CPU time | 484.04 seconds |
| Started | Oct 12 01:55:40 PM UTC 24 |
| Finished | Oct 12 02:03:50 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756811433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2756811433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.1198293818 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 216721675206 ps |
| CPU time | 199.57 seconds |
| Started | Oct 12 01:55:40 PM UTC 24 |
| Finished | Oct 12 01:59:03 PM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198293818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1198293818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_fifo_reset.2597776419 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 89623381567 ps |
| CPU time | 54.58 seconds |
| Started | Oct 12 01:55:42 PM UTC 24 |
| Finished | Oct 12 01:56:39 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597776419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2597776419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_intr.293066133 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 39312473728 ps |
| CPU time | 71.68 seconds |
| Started | Oct 12 01:55:45 PM UTC 24 |
| Finished | Oct 12 01:56:58 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293066133 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.293066133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.936600330 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 93461884727 ps |
| CPU time | 369.34 seconds |
| Started | Oct 12 01:56:19 PM UTC 24 |
| Finished | Oct 12 02:02:34 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936600330 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.936600330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_loopback.34701236 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 583216166 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 01:56:16 PM UTC 24 |
| Finished | Oct 12 01:56:19 PM UTC 24 |
| Peak memory | 206252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34701236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 46.uart_loopback.34701236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_noise_filter.2255390717 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 347077275086 ps |
| CPU time | 93.87 seconds |
| Started | Oct 12 01:55:57 PM UTC 24 |
| Finished | Oct 12 01:57:32 PM UTC 24 |
| Peak memory | 207960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255390717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2255390717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_perf.4256308096 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 8653675917 ps |
| CPU time | 646.99 seconds |
| Started | Oct 12 01:56:16 PM UTC 24 |
| Finished | Oct 12 02:07:11 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256308096 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.4256308096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_rx_oversample.2823539331 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 5647592580 ps |
| CPU time | 51.69 seconds |
| Started | Oct 12 01:55:45 PM UTC 24 |
| Finished | Oct 12 01:56:38 PM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823539331 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2823539331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.1180965616 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 20337766311 ps |
| CPU time | 44.32 seconds |
| Started | Oct 12 01:56:08 PM UTC 24 |
| Finished | Oct 12 01:56:54 PM UTC 24 |
| Peak memory | 208740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180965616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1180965616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.3617725408 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 36975848235 ps |
| CPU time | 17.43 seconds |
| Started | Oct 12 01:55:57 PM UTC 24 |
| Finished | Oct 12 01:56:15 PM UTC 24 |
| Peak memory | 207352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617725408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3617725408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_smoke.773343426 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 741530282 ps |
| CPU time | 2.88 seconds |
| Started | Oct 12 01:55:36 PM UTC 24 |
| Finished | Oct 12 01:55:40 PM UTC 24 |
| Peak memory | 207412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773343426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 46.uart_smoke.773343426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_stress_all.448648213 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 317814873238 ps |
| CPU time | 462.68 seconds |
| Started | Oct 12 01:56:22 PM UTC 24 |
| Finished | Oct 12 02:04:11 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448648213 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.448648213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.1141420670 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 4524357976 ps |
| CPU time | 110.47 seconds |
| Started | Oct 12 01:56:21 PM UTC 24 |
| Finished | Oct 12 01:58:14 PM UTC 24 |
| Peak memory | 219872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1141420670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all _with_rand_reset.1141420670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.72107558 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 3191655775 ps |
| CPU time | 4.99 seconds |
| Started | Oct 12 01:56:09 PM UTC 24 |
| Finished | Oct 12 01:56:15 PM UTC 24 |
| Peak memory | 207372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72107558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.72107558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/46.uart_tx_rx.2266906721 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 99855145375 ps |
| CPU time | 95.64 seconds |
| Started | Oct 12 01:55:37 PM UTC 24 |
| Finished | Oct 12 01:57:15 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266906721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2266906721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/46.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_alert_test.1251378785 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 13230991 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 01:57:26 PM UTC 24 |
| Finished | Oct 12 01:57:28 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251378785 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1251378785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_fifo_full.2160145037 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 49998787740 ps |
| CPU time | 55.03 seconds |
| Started | Oct 12 01:56:39 PM UTC 24 |
| Finished | Oct 12 01:57:36 PM UTC 24 |
| Peak memory | 208576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160145037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2160145037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.146671023 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 127050866333 ps |
| CPU time | 95.61 seconds |
| Started | Oct 12 01:56:39 PM UTC 24 |
| Finished | Oct 12 01:58:17 PM UTC 24 |
| Peak memory | 208392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146671023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.146671023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_fifo_reset.2780328875 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 161484335332 ps |
| CPU time | 52.81 seconds |
| Started | Oct 12 01:56:53 PM UTC 24 |
| Finished | Oct 12 01:57:47 PM UTC 24 |
| Peak memory | 208596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780328875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2780328875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_intr.1468749366 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 53601317022 ps |
| CPU time | 76.81 seconds |
| Started | Oct 12 01:56:59 PM UTC 24 |
| Finished | Oct 12 01:58:18 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468749366 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1468749366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.1737497400 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 137752286991 ps |
| CPU time | 320.11 seconds |
| Started | Oct 12 01:57:20 PM UTC 24 |
| Finished | Oct 12 02:02:44 PM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737497400 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1737497400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_loopback.3113321188 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 4486690545 ps |
| CPU time | 7.84 seconds |
| Started | Oct 12 01:57:17 PM UTC 24 |
| Finished | Oct 12 01:57:26 PM UTC 24 |
| Peak memory | 207488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113321188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3113321188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_noise_filter.3543242863 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 97051206902 ps |
| CPU time | 160.04 seconds |
| Started | Oct 12 01:56:59 PM UTC 24 |
| Finished | Oct 12 01:59:42 PM UTC 24 |
| Peak memory | 208476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543242863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3543242863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_perf.1819989985 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 6869837520 ps |
| CPU time | 354.48 seconds |
| Started | Oct 12 01:57:17 PM UTC 24 |
| Finished | Oct 12 02:03:16 PM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819989985 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1819989985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_rx_oversample.2987763602 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 2320620091 ps |
| CPU time | 11.09 seconds |
| Started | Oct 12 01:56:54 PM UTC 24 |
| Finished | Oct 12 01:57:06 PM UTC 24 |
| Peak memory | 207528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987763602 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2987763602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.585702504 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 121038495404 ps |
| CPU time | 145.46 seconds |
| Started | Oct 12 01:57:16 PM UTC 24 |
| Finished | Oct 12 01:59:43 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585702504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.585702504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.4165926010 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 3475188764 ps |
| CPU time | 11.35 seconds |
| Started | Oct 12 01:57:07 PM UTC 24 |
| Finished | Oct 12 01:57:20 PM UTC 24 |
| Peak memory | 205240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165926010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4165926010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_smoke.1308688804 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 910278761 ps |
| CPU time | 2.92 seconds |
| Started | Oct 12 01:56:28 PM UTC 24 |
| Finished | Oct 12 01:56:32 PM UTC 24 |
| Peak memory | 208568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308688804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1308688804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_stress_all.2447848687 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 160200930216 ps |
| CPU time | 191.31 seconds |
| Started | Oct 12 01:57:23 PM UTC 24 |
| Finished | Oct 12 02:00:37 PM UTC 24 |
| Peak memory | 217860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447848687 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2447848687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.3501999392 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 13269883164 ps |
| CPU time | 78.95 seconds |
| Started | Oct 12 01:57:21 PM UTC 24 |
| Finished | Oct 12 01:58:42 PM UTC 24 |
| Peak memory | 220024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3501999392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all _with_rand_reset.3501999392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.1457817394 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 3675150982 ps |
| CPU time | 2.69 seconds |
| Started | Oct 12 01:57:16 PM UTC 24 |
| Finished | Oct 12 01:57:19 PM UTC 24 |
| Peak memory | 207500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457817394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1457817394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/47.uart_tx_rx.3907130388 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 126058647882 ps |
| CPU time | 64.34 seconds |
| Started | Oct 12 01:56:33 PM UTC 24 |
| Finished | Oct 12 01:57:39 PM UTC 24 |
| Peak memory | 208956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907130388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3907130388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/47.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_alert_test.784682523 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 37829262 ps |
| CPU time | 0.83 seconds |
| Started | Oct 12 01:58:19 PM UTC 24 |
| Finished | Oct 12 01:58:21 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784682523 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.784682523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_fifo_full.3738450538 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 55297327837 ps |
| CPU time | 86.24 seconds |
| Started | Oct 12 01:57:33 PM UTC 24 |
| Finished | Oct 12 01:59:02 PM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738450538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3738450538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.3232389739 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 54062591428 ps |
| CPU time | 72.63 seconds |
| Started | Oct 12 01:57:33 PM UTC 24 |
| Finished | Oct 12 01:58:48 PM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232389739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3232389739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_fifo_reset.2067767749 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 99247105435 ps |
| CPU time | 181.28 seconds |
| Started | Oct 12 01:57:36 PM UTC 24 |
| Finished | Oct 12 02:00:40 PM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067767749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2067767749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_intr.61372667 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 41712747400 ps |
| CPU time | 38.49 seconds |
| Started | Oct 12 01:57:38 PM UTC 24 |
| Finished | Oct 12 01:58:18 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61372667 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.61372667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.2972969109 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 178089267435 ps |
| CPU time | 243.77 seconds |
| Started | Oct 12 01:58:07 PM UTC 24 |
| Finished | Oct 12 02:02:14 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972969109 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2972969109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_loopback.1512385450 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 17124788531 ps |
| CPU time | 31.09 seconds |
| Started | Oct 12 01:57:52 PM UTC 24 |
| Finished | Oct 12 01:58:25 PM UTC 24 |
| Peak memory | 207148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512385450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1512385450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_noise_filter.594769487 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 10561274058 ps |
| CPU time | 39.4 seconds |
| Started | Oct 12 01:57:40 PM UTC 24 |
| Finished | Oct 12 01:58:21 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594769487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.594769487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_perf.2626218126 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 14841596402 ps |
| CPU time | 268.17 seconds |
| Started | Oct 12 01:57:58 PM UTC 24 |
| Finished | Oct 12 02:02:30 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626218126 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2626218126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_rx_oversample.1312443845 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 5576792239 ps |
| CPU time | 46.38 seconds |
| Started | Oct 12 01:57:37 PM UTC 24 |
| Finished | Oct 12 01:58:25 PM UTC 24 |
| Peak memory | 207476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312443845 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1312443845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.168906116 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 188095850178 ps |
| CPU time | 381.64 seconds |
| Started | Oct 12 01:57:48 PM UTC 24 |
| Finished | Oct 12 02:04:14 PM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168906116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.168906116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.3394457126 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2869665403 ps |
| CPU time | 2.92 seconds |
| Started | Oct 12 01:57:46 PM UTC 24 |
| Finished | Oct 12 01:57:50 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394457126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3394457126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_smoke.3277005181 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 514979625 ps |
| CPU time | 2.57 seconds |
| Started | Oct 12 01:57:29 PM UTC 24 |
| Finished | Oct 12 01:57:33 PM UTC 24 |
| Peak memory | 208012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277005181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3277005181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_stress_all.2809826211 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 163221672571 ps |
| CPU time | 215.59 seconds |
| Started | Oct 12 01:58:18 PM UTC 24 |
| Finished | Oct 12 02:01:56 PM UTC 24 |
| Peak memory | 217732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809826211 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2809826211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.819519130 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 6706764742 ps |
| CPU time | 63.91 seconds |
| Started | Oct 12 01:58:15 PM UTC 24 |
| Finished | Oct 12 01:59:20 PM UTC 24 |
| Peak memory | 217764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=819519130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all_ with_rand_reset.819519130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.3802781969 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 587833705 ps |
| CPU time | 4.11 seconds |
| Started | Oct 12 01:57:51 PM UTC 24 |
| Finished | Oct 12 01:57:56 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802781969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3802781969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/48.uart_tx_rx.3882349458 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 110957358558 ps |
| CPU time | 21.26 seconds |
| Started | Oct 12 01:57:29 PM UTC 24 |
| Finished | Oct 12 01:57:52 PM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882349458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3882349458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/48.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_alert_test.194416243 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 23635576 ps |
| CPU time | 0.83 seconds |
| Started | Oct 12 01:58:40 PM UTC 24 |
| Finished | Oct 12 01:58:42 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194416243 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.194416243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_fifo_full.4116946986 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 47612414749 ps |
| CPU time | 117.89 seconds |
| Started | Oct 12 01:58:20 PM UTC 24 |
| Finished | Oct 12 02:00:21 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116946986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.4116946986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.3533246011 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 20761683012 ps |
| CPU time | 32.64 seconds |
| Started | Oct 12 01:58:21 PM UTC 24 |
| Finished | Oct 12 01:58:55 PM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533246011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3533246011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_fifo_reset.643166202 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 49241193711 ps |
| CPU time | 187.73 seconds |
| Started | Oct 12 01:58:21 PM UTC 24 |
| Finished | Oct 12 02:01:32 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643166202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.643166202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_intr.713560235 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 43166527619 ps |
| CPU time | 106.22 seconds |
| Started | Oct 12 01:58:22 PM UTC 24 |
| Finished | Oct 12 02:00:11 PM UTC 24 |
| Peak memory | 208800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713560235 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.713560235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.3901175076 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 121038230476 ps |
| CPU time | 725.9 seconds |
| Started | Oct 12 01:58:34 PM UTC 24 |
| Finished | Oct 12 02:10:48 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901175076 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3901175076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_loopback.340934641 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 1720731482 ps |
| CPU time | 6.95 seconds |
| Started | Oct 12 01:58:27 PM UTC 24 |
| Finished | Oct 12 01:58:35 PM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340934641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 49.uart_loopback.340934641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_noise_filter.1366336316 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 178300762553 ps |
| CPU time | 160.4 seconds |
| Started | Oct 12 01:58:22 PM UTC 24 |
| Finished | Oct 12 02:01:06 PM UTC 24 |
| Peak memory | 208964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366336316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1366336316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_perf.2690608825 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 13926510717 ps |
| CPU time | 630.83 seconds |
| Started | Oct 12 01:58:31 PM UTC 24 |
| Finished | Oct 12 02:09:09 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690608825 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2690608825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_rx_oversample.2396053713 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 4342386199 ps |
| CPU time | 15.22 seconds |
| Started | Oct 12 01:58:22 PM UTC 24 |
| Finished | Oct 12 01:58:39 PM UTC 24 |
| Peak memory | 207628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396053713 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2396053713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.1959791733 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 263644416149 ps |
| CPU time | 79.41 seconds |
| Started | Oct 12 01:58:26 PM UTC 24 |
| Finished | Oct 12 01:59:47 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959791733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1959791733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.2017233953 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2798198197 ps |
| CPU time | 9.09 seconds |
| Started | Oct 12 01:58:24 PM UTC 24 |
| Finished | Oct 12 01:58:34 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017233953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2017233953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_smoke.1044436871 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 281214240 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 01:58:19 PM UTC 24 |
| Finished | Oct 12 01:58:22 PM UTC 24 |
| Peak memory | 207108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044436871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1044436871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_stress_all.1637953635 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 221289588592 ps |
| CPU time | 411.03 seconds |
| Started | Oct 12 01:58:36 PM UTC 24 |
| Finished | Oct 12 02:05:32 PM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637953635 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1637953635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.1043200271 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3815681462 ps |
| CPU time | 32.95 seconds |
| Started | Oct 12 01:58:35 PM UTC 24 |
| Finished | Oct 12 01:59:09 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1043200271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all _with_rand_reset.1043200271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.2359557699 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 1205445255 ps |
| CPU time | 3.34 seconds |
| Started | Oct 12 01:58:26 PM UTC 24 |
| Finished | Oct 12 01:58:30 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359557699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2359557699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/49.uart_tx_rx.413540263 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 62940322391 ps |
| CPU time | 36.11 seconds |
| Started | Oct 12 01:58:20 PM UTC 24 |
| Finished | Oct 12 01:58:58 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413540263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.413540263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/49.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_alert_test.2714127073 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 15152858 ps |
| CPU time | 0.88 seconds |
| Started | Oct 12 01:30:06 PM UTC 24 |
| Finished | Oct 12 01:30:08 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714127073 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2714127073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_fifo_full.1532717246 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 21551475156 ps |
| CPU time | 38.08 seconds |
| Started | Oct 12 01:29:46 PM UTC 24 |
| Finished | Oct 12 01:30:26 PM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532717246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1532717246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_intr.3338473645 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 10665637626 ps |
| CPU time | 9.02 seconds |
| Started | Oct 12 01:29:48 PM UTC 24 |
| Finished | Oct 12 01:29:59 PM UTC 24 |
| Peak memory | 208492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338473645 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3338473645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.2077280600 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 173581076776 ps |
| CPU time | 1115.07 seconds |
| Started | Oct 12 01:30:03 PM UTC 24 |
| Finished | Oct 12 01:48:51 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077280600 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2077280600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_loopback.1721816951 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1286843557 ps |
| CPU time | 5.55 seconds |
| Started | Oct 12 01:30:00 PM UTC 24 |
| Finished | Oct 12 01:30:07 PM UTC 24 |
| Peak memory | 207276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721816951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1721816951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_noise_filter.3896473212 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 14956382717 ps |
| CPU time | 42.86 seconds |
| Started | Oct 12 01:29:53 PM UTC 24 |
| Finished | Oct 12 01:30:37 PM UTC 24 |
| Peak memory | 207740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896473212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3896473212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_perf.3263702888 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 11299929199 ps |
| CPU time | 117.51 seconds |
| Started | Oct 12 01:30:03 PM UTC 24 |
| Finished | Oct 12 01:32:03 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263702888 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3263702888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_rx_oversample.3362682949 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 7576838423 ps |
| CPU time | 82.36 seconds |
| Started | Oct 12 01:29:48 PM UTC 24 |
| Finished | Oct 12 01:31:13 PM UTC 24 |
| Peak memory | 207420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362682949 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3362682949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.580079062 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 28465442178 ps |
| CPU time | 39.35 seconds |
| Started | Oct 12 01:29:59 PM UTC 24 |
| Finished | Oct 12 01:30:39 PM UTC 24 |
| Peak memory | 208728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580079062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.580079062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.320506663 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 2647012686 ps |
| CPU time | 8.55 seconds |
| Started | Oct 12 01:29:57 PM UTC 24 |
| Finished | Oct 12 01:30:07 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320506663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.320506663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_smoke.711125718 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 689754930 ps |
| CPU time | 2.76 seconds |
| Started | Oct 12 01:29:44 PM UTC 24 |
| Finished | Oct 12 01:29:48 PM UTC 24 |
| Peak memory | 207688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711125718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 5.uart_smoke.711125718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.1928679535 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1663300792 ps |
| CPU time | 2.64 seconds |
| Started | Oct 12 01:30:00 PM UTC 24 |
| Finished | Oct 12 01:30:04 PM UTC 24 |
| Peak memory | 207420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928679535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1928679535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_tx_rx.4228558883 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 4452023876 ps |
| CPU time | 13.39 seconds |
| Started | Oct 12 01:29:44 PM UTC 24 |
| Finished | Oct 12 01:29:59 PM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228558883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.4228558883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/50.uart_fifo_reset.309508839 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 37676943754 ps |
| CPU time | 20.75 seconds |
| Started | Oct 12 01:58:42 PM UTC 24 |
| Finished | Oct 12 01:59:05 PM UTC 24 |
| Peak memory | 207936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309508839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.309508839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/50.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.2143305839 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 12179734512 ps |
| CPU time | 74.43 seconds |
| Started | Oct 12 01:58:42 PM UTC 24 |
| Finished | Oct 12 01:59:59 PM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2143305839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all _with_rand_reset.2143305839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/51.uart_fifo_reset.1190345257 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 21605593614 ps |
| CPU time | 53.28 seconds |
| Started | Oct 12 01:58:43 PM UTC 24 |
| Finished | Oct 12 01:59:39 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190345257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1190345257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/51.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.4150155244 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 4751444463 ps |
| CPU time | 56.84 seconds |
| Started | Oct 12 01:58:49 PM UTC 24 |
| Finished | Oct 12 01:59:47 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4150155244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all _with_rand_reset.4150155244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/52.uart_fifo_reset.3852908350 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 120490644436 ps |
| CPU time | 54.43 seconds |
| Started | Oct 12 01:58:57 PM UTC 24 |
| Finished | Oct 12 01:59:53 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852908350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3852908350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/52.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.426611321 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 3855208030 ps |
| CPU time | 32.27 seconds |
| Started | Oct 12 01:58:59 PM UTC 24 |
| Finished | Oct 12 01:59:32 PM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=426611321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all_ with_rand_reset.426611321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.4169226336 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 4982016426 ps |
| CPU time | 66.44 seconds |
| Started | Oct 12 01:59:01 PM UTC 24 |
| Finished | Oct 12 02:00:09 PM UTC 24 |
| Peak memory | 220036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4169226336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all _with_rand_reset.4169226336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/54.uart_fifo_reset.2136044507 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 54549176749 ps |
| CPU time | 44.04 seconds |
| Started | Oct 12 01:59:02 PM UTC 24 |
| Finished | Oct 12 01:59:47 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136044507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2136044507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/54.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.583253569 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 3124048923 ps |
| CPU time | 11.55 seconds |
| Started | Oct 12 01:59:04 PM UTC 24 |
| Finished | Oct 12 01:59:17 PM UTC 24 |
| Peak memory | 217732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=583253569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all_ with_rand_reset.583253569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/55.uart_fifo_reset.1748264917 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 51831848233 ps |
| CPU time | 44.91 seconds |
| Started | Oct 12 01:59:05 PM UTC 24 |
| Finished | Oct 12 01:59:52 PM UTC 24 |
| Peak memory | 208492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748264917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1748264917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/55.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.1816212203 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 4337771637 ps |
| CPU time | 87.85 seconds |
| Started | Oct 12 01:59:10 PM UTC 24 |
| Finished | Oct 12 02:00:40 PM UTC 24 |
| Peak memory | 217904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1816212203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all _with_rand_reset.1816212203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/56.uart_fifo_reset.3636820719 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 104385315374 ps |
| CPU time | 232.56 seconds |
| Started | Oct 12 01:59:15 PM UTC 24 |
| Finished | Oct 12 02:03:11 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636820719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3636820719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/56.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.3453375522 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 2340209239 ps |
| CPU time | 53.36 seconds |
| Started | Oct 12 01:59:17 PM UTC 24 |
| Finished | Oct 12 02:00:12 PM UTC 24 |
| Peak memory | 220020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3453375522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all _with_rand_reset.3453375522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/57.uart_fifo_reset.1865909047 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 58106543923 ps |
| CPU time | 62.92 seconds |
| Started | Oct 12 01:59:18 PM UTC 24 |
| Finished | Oct 12 02:00:22 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865909047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1865909047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/57.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.1756502460 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 2874718820 ps |
| CPU time | 46.12 seconds |
| Started | Oct 12 01:59:22 PM UTC 24 |
| Finished | Oct 12 02:00:09 PM UTC 24 |
| Peak memory | 217724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1756502460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all _with_rand_reset.1756502460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/58.uart_fifo_reset.1466303506 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 38233798062 ps |
| CPU time | 14.74 seconds |
| Started | Oct 12 01:59:28 PM UTC 24 |
| Finished | Oct 12 01:59:44 PM UTC 24 |
| Peak memory | 208472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466303506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1466303506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/58.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.1254639441 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 2941928753 ps |
| CPU time | 35.21 seconds |
| Started | Oct 12 01:59:33 PM UTC 24 |
| Finished | Oct 12 02:00:09 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1254639441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all _with_rand_reset.1254639441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/59.uart_fifo_reset.3433836091 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 157669133152 ps |
| CPU time | 21.91 seconds |
| Started | Oct 12 01:59:38 PM UTC 24 |
| Finished | Oct 12 02:00:01 PM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433836091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3433836091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/59.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.536991944 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 9376328897 ps |
| CPU time | 83.4 seconds |
| Started | Oct 12 01:59:39 PM UTC 24 |
| Finished | Oct 12 02:01:04 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=536991944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all_ with_rand_reset.536991944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_alert_test.141382317 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 36677161 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 01:30:27 PM UTC 24 |
| Finished | Oct 12 01:30:28 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141382317 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.141382317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_fifo_full.2055427836 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 70242915460 ps |
| CPU time | 90.08 seconds |
| Started | Oct 12 01:30:09 PM UTC 24 |
| Finished | Oct 12 01:31:41 PM UTC 24 |
| Peak memory | 208384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055427836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2055427836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_fifo_reset.1667022385 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 38734968439 ps |
| CPU time | 27.19 seconds |
| Started | Oct 12 01:30:12 PM UTC 24 |
| Finished | Oct 12 01:30:40 PM UTC 24 |
| Peak memory | 208740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667022385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1667022385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_intr.2619459614 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 263813372323 ps |
| CPU time | 209.79 seconds |
| Started | Oct 12 01:30:13 PM UTC 24 |
| Finished | Oct 12 01:33:45 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619459614 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2619459614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.2918162803 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 107101367220 ps |
| CPU time | 133.89 seconds |
| Started | Oct 12 01:30:21 PM UTC 24 |
| Finished | Oct 12 01:32:37 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918162803 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2918162803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_loopback.334877464 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 10563524354 ps |
| CPU time | 7.66 seconds |
| Started | Oct 12 01:30:19 PM UTC 24 |
| Finished | Oct 12 01:30:28 PM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334877464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 6.uart_loopback.334877464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_noise_filter.2469759962 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 34835879843 ps |
| CPU time | 19.91 seconds |
| Started | Oct 12 01:30:14 PM UTC 24 |
| Finished | Oct 12 01:30:35 PM UTC 24 |
| Peak memory | 207616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469759962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2469759962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_perf.2637691464 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 12874981836 ps |
| CPU time | 176.13 seconds |
| Started | Oct 12 01:30:20 PM UTC 24 |
| Finished | Oct 12 01:33:19 PM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637691464 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2637691464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_rx_oversample.196795817 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2421962981 ps |
| CPU time | 5.71 seconds |
| Started | Oct 12 01:30:13 PM UTC 24 |
| Finished | Oct 12 01:30:19 PM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196795817 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.196795817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.2413224746 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 12583407044 ps |
| CPU time | 32.52 seconds |
| Started | Oct 12 01:30:16 PM UTC 24 |
| Finished | Oct 12 01:30:50 PM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413224746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2413224746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.1770559984 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1844350393 ps |
| CPU time | 3.3 seconds |
| Started | Oct 12 01:30:16 PM UTC 24 |
| Finished | Oct 12 01:30:20 PM UTC 24 |
| Peak memory | 205112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770559984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1770559984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_smoke.2044547836 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 454663602 ps |
| CPU time | 3.51 seconds |
| Started | Oct 12 01:30:07 PM UTC 24 |
| Finished | Oct 12 01:30:12 PM UTC 24 |
| Peak memory | 207180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044547836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2044547836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.838274120 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1655020707 ps |
| CPU time | 30.22 seconds |
| Started | Oct 12 01:30:24 PM UTC 24 |
| Finished | Oct 12 01:30:56 PM UTC 24 |
| Peak memory | 217860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=838274120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_w ith_rand_reset.838274120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.2887370958 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 7160238470 ps |
| CPU time | 17.88 seconds |
| Started | Oct 12 01:30:17 PM UTC 24 |
| Finished | Oct 12 01:30:36 PM UTC 24 |
| Peak memory | 208292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887370958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2887370958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_tx_rx.2491665252 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 7722610909 ps |
| CPU time | 6.46 seconds |
| Started | Oct 12 01:30:07 PM UTC 24 |
| Finished | Oct 12 01:30:15 PM UTC 24 |
| Peak memory | 207064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491665252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2491665252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/60.uart_fifo_reset.1396694783 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 118077906181 ps |
| CPU time | 46.39 seconds |
| Started | Oct 12 01:59:42 PM UTC 24 |
| Finished | Oct 12 02:00:30 PM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396694783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1396694783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/60.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.73515399 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 3277325491 ps |
| CPU time | 52.74 seconds |
| Started | Oct 12 01:59:44 PM UTC 24 |
| Finished | Oct 12 02:00:38 PM UTC 24 |
| Peak memory | 221988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=73515399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all_w ith_rand_reset.73515399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/61.uart_fifo_reset.2624121775 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 39702426571 ps |
| CPU time | 71.35 seconds |
| Started | Oct 12 01:59:44 PM UTC 24 |
| Finished | Oct 12 02:00:57 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624121775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2624121775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/61.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.3117374967 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 3665197603 ps |
| CPU time | 47.48 seconds |
| Started | Oct 12 01:59:47 PM UTC 24 |
| Finished | Oct 12 02:00:36 PM UTC 24 |
| Peak memory | 219816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3117374967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all _with_rand_reset.3117374967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/62.uart_fifo_reset.1196651244 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 119630149623 ps |
| CPU time | 133.05 seconds |
| Started | Oct 12 01:59:48 PM UTC 24 |
| Finished | Oct 12 02:02:04 PM UTC 24 |
| Peak memory | 208096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196651244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1196651244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/62.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.1433917946 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 1815874589 ps |
| CPU time | 23.04 seconds |
| Started | Oct 12 01:59:49 PM UTC 24 |
| Finished | Oct 12 02:00:13 PM UTC 24 |
| Peak memory | 224884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1433917946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all _with_rand_reset.1433917946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/63.uart_fifo_reset.3161464433 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 115377095307 ps |
| CPU time | 87.89 seconds |
| Started | Oct 12 01:59:51 PM UTC 24 |
| Finished | Oct 12 02:01:20 PM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161464433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3161464433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/63.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.1875693372 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 1708951713 ps |
| CPU time | 26.14 seconds |
| Started | Oct 12 01:59:53 PM UTC 24 |
| Finished | Oct 12 02:00:20 PM UTC 24 |
| Peak memory | 208876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1875693372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all _with_rand_reset.1875693372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/64.uart_fifo_reset.3667489499 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 43364883539 ps |
| CPU time | 43.47 seconds |
| Started | Oct 12 01:59:54 PM UTC 24 |
| Finished | Oct 12 02:00:39 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667489499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3667489499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/64.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.1511128196 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2629744096 ps |
| CPU time | 52.74 seconds |
| Started | Oct 12 02:00:00 PM UTC 24 |
| Finished | Oct 12 02:00:54 PM UTC 24 |
| Peak memory | 208960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1511128196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all _with_rand_reset.1511128196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/65.uart_fifo_reset.3216372122 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 129336516159 ps |
| CPU time | 18.79 seconds |
| Started | Oct 12 02:00:01 PM UTC 24 |
| Finished | Oct 12 02:00:25 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216372122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3216372122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/65.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.790978922 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 5509143472 ps |
| CPU time | 75.92 seconds |
| Started | Oct 12 02:00:02 PM UTC 24 |
| Finished | Oct 12 02:01:24 PM UTC 24 |
| Peak memory | 217980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=790978922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all_ with_rand_reset.790978922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/66.uart_fifo_reset.3479412207 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 27975956235 ps |
| CPU time | 43.34 seconds |
| Started | Oct 12 02:00:10 PM UTC 24 |
| Finished | Oct 12 02:00:55 PM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479412207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3479412207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/66.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.924147044 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 9873777594 ps |
| CPU time | 120.66 seconds |
| Started | Oct 12 02:00:10 PM UTC 24 |
| Finished | Oct 12 02:02:14 PM UTC 24 |
| Peak memory | 217748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=924147044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all_ with_rand_reset.924147044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/67.uart_fifo_reset.42851643 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 20289081608 ps |
| CPU time | 34.73 seconds |
| Started | Oct 12 02:00:10 PM UTC 24 |
| Finished | Oct 12 02:00:47 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42851643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.42851643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/67.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.34803081 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 1053947544 ps |
| CPU time | 10.88 seconds |
| Started | Oct 12 02:00:11 PM UTC 24 |
| Finished | Oct 12 02:00:24 PM UTC 24 |
| Peak memory | 217680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=34803081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all_w ith_rand_reset.34803081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/68.uart_fifo_reset.2362164674 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 187238300567 ps |
| CPU time | 47.14 seconds |
| Started | Oct 12 02:00:14 PM UTC 24 |
| Finished | Oct 12 02:01:02 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362164674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2362164674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/68.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.3150924172 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 1781855895 ps |
| CPU time | 33.23 seconds |
| Started | Oct 12 02:00:14 PM UTC 24 |
| Finished | Oct 12 02:00:48 PM UTC 24 |
| Peak memory | 224256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3150924172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all _with_rand_reset.3150924172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/69.uart_fifo_reset.858329201 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 113039559025 ps |
| CPU time | 249.49 seconds |
| Started | Oct 12 02:00:21 PM UTC 24 |
| Finished | Oct 12 02:04:34 PM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858329201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.858329201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/69.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.3785023172 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 4283018325 ps |
| CPU time | 64.9 seconds |
| Started | Oct 12 02:00:22 PM UTC 24 |
| Finished | Oct 12 02:01:28 PM UTC 24 |
| Peak memory | 221924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3785023172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all _with_rand_reset.3785023172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_alert_test.2725234231 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 23645194 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 01:30:42 PM UTC 24 |
| Finished | Oct 12 01:30:44 PM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725234231 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2725234231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_fifo_full.4081451542 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 134288190393 ps |
| CPU time | 97.36 seconds |
| Started | Oct 12 01:30:28 PM UTC 24 |
| Finished | Oct 12 01:32:07 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081451542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.4081451542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.2894432912 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 18041298618 ps |
| CPU time | 42.91 seconds |
| Started | Oct 12 01:30:29 PM UTC 24 |
| Finished | Oct 12 01:31:13 PM UTC 24 |
| Peak memory | 208276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894432912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2894432912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_intr.3993175194 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 29638061516 ps |
| CPU time | 97.78 seconds |
| Started | Oct 12 01:30:33 PM UTC 24 |
| Finished | Oct 12 01:32:13 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993175194 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3993175194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_loopback.3404784960 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2875242674 ps |
| CPU time | 5.73 seconds |
| Started | Oct 12 01:30:39 PM UTC 24 |
| Finished | Oct 12 01:30:46 PM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404784960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3404784960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_noise_filter.2313462503 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 80362413542 ps |
| CPU time | 151.47 seconds |
| Started | Oct 12 01:30:34 PM UTC 24 |
| Finished | Oct 12 01:33:08 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313462503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2313462503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_perf.4155036321 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 10027413578 ps |
| CPU time | 344.86 seconds |
| Started | Oct 12 01:30:39 PM UTC 24 |
| Finished | Oct 12 01:36:29 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155036321 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.4155036321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_rx_oversample.2055961421 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1798961164 ps |
| CPU time | 7.74 seconds |
| Started | Oct 12 01:30:30 PM UTC 24 |
| Finished | Oct 12 01:30:39 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055961421 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2055961421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.4205804036 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 78260626908 ps |
| CPU time | 188.78 seconds |
| Started | Oct 12 01:30:37 PM UTC 24 |
| Finished | Oct 12 01:33:49 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205804036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.4205804036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.1022805616 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2655586363 ps |
| CPU time | 11.02 seconds |
| Started | Oct 12 01:30:36 PM UTC 24 |
| Finished | Oct 12 01:30:48 PM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022805616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1022805616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_smoke.1933760888 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 933151260 ps |
| CPU time | 5.24 seconds |
| Started | Oct 12 01:30:27 PM UTC 24 |
| Finished | Oct 12 01:30:33 PM UTC 24 |
| Peak memory | 207468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933760888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1933760888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_stress_all.1189787119 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 46856287502 ps |
| CPU time | 1499.14 seconds |
| Started | Oct 12 01:30:41 PM UTC 24 |
| Finished | Oct 12 01:55:56 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189787119 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1189787119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.3617744898 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 7250205667 ps |
| CPU time | 24.81 seconds |
| Started | Oct 12 01:30:41 PM UTC 24 |
| Finished | Oct 12 01:31:07 PM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3617744898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_ with_rand_reset.3617744898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.3630989639 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 851472642 ps |
| CPU time | 2.72 seconds |
| Started | Oct 12 01:30:37 PM UTC 24 |
| Finished | Oct 12 01:30:41 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630989639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3630989639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_tx_rx.1941240807 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 122238413901 ps |
| CPU time | 24.73 seconds |
| Started | Oct 12 01:30:28 PM UTC 24 |
| Finished | Oct 12 01:30:54 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941240807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1941240807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/7.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.30658623 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 11781328550 ps |
| CPU time | 78.22 seconds |
| Started | Oct 12 02:00:25 PM UTC 24 |
| Finished | Oct 12 02:01:45 PM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=30658623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all_w ith_rand_reset.30658623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/71.uart_fifo_reset.3562229023 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 138921629317 ps |
| CPU time | 230.72 seconds |
| Started | Oct 12 02:00:26 PM UTC 24 |
| Finished | Oct 12 02:04:20 PM UTC 24 |
| Peak memory | 208912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562229023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3562229023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/71.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.1290127536 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 4154175991 ps |
| CPU time | 28.77 seconds |
| Started | Oct 12 02:00:31 PM UTC 24 |
| Finished | Oct 12 02:01:01 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1290127536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all _with_rand_reset.1290127536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/72.uart_fifo_reset.1305483566 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 64365872879 ps |
| CPU time | 66.97 seconds |
| Started | Oct 12 02:00:31 PM UTC 24 |
| Finished | Oct 12 02:01:40 PM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305483566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1305483566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/72.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.521719654 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 8609376007 ps |
| CPU time | 25.9 seconds |
| Started | Oct 12 02:00:37 PM UTC 24 |
| Finished | Oct 12 02:01:05 PM UTC 24 |
| Peak memory | 217732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=521719654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all_ with_rand_reset.521719654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/73.uart_fifo_reset.2935823424 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 4008801185 ps |
| CPU time | 11.82 seconds |
| Started | Oct 12 02:00:38 PM UTC 24 |
| Finished | Oct 12 02:00:51 PM UTC 24 |
| Peak memory | 207688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935823424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2935823424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/73.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.1401180147 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 5829026401 ps |
| CPU time | 44.45 seconds |
| Started | Oct 12 02:00:40 PM UTC 24 |
| Finished | Oct 12 02:01:25 PM UTC 24 |
| Peak memory | 217760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1401180147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all _with_rand_reset.1401180147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/74.uart_fifo_reset.4086308762 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 103220179992 ps |
| CPU time | 183.44 seconds |
| Started | Oct 12 02:00:40 PM UTC 24 |
| Finished | Oct 12 02:03:46 PM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086308762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.4086308762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/74.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.2695353776 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 11405337854 ps |
| CPU time | 42.15 seconds |
| Started | Oct 12 02:00:41 PM UTC 24 |
| Finished | Oct 12 02:01:25 PM UTC 24 |
| Peak memory | 225460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2695353776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all _with_rand_reset.2695353776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/75.uart_fifo_reset.1042268842 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 133316545796 ps |
| CPU time | 307.69 seconds |
| Started | Oct 12 02:00:41 PM UTC 24 |
| Finished | Oct 12 02:05:53 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042268842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1042268842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/75.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.2058456803 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 15599909044 ps |
| CPU time | 39.75 seconds |
| Started | Oct 12 02:00:41 PM UTC 24 |
| Finished | Oct 12 02:01:22 PM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2058456803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all _with_rand_reset.2058456803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/76.uart_fifo_reset.1493464858 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 19030464288 ps |
| CPU time | 36.15 seconds |
| Started | Oct 12 02:00:47 PM UTC 24 |
| Finished | Oct 12 02:01:25 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493464858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1493464858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/76.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.2403046124 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 2523112066 ps |
| CPU time | 52.88 seconds |
| Started | Oct 12 02:00:50 PM UTC 24 |
| Finished | Oct 12 02:01:44 PM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2403046124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all _with_rand_reset.2403046124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/77.uart_fifo_reset.3732067724 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 14475441844 ps |
| CPU time | 40.66 seconds |
| Started | Oct 12 02:00:52 PM UTC 24 |
| Finished | Oct 12 02:01:34 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732067724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3732067724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/77.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.220796743 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 11719962817 ps |
| CPU time | 45.45 seconds |
| Started | Oct 12 02:00:53 PM UTC 24 |
| Finished | Oct 12 02:01:40 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=220796743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all_ with_rand_reset.220796743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/78.uart_fifo_reset.791907345 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 135249998899 ps |
| CPU time | 54.11 seconds |
| Started | Oct 12 02:00:55 PM UTC 24 |
| Finished | Oct 12 02:01:51 PM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791907345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.791907345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/78.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.1322635358 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 2181782852 ps |
| CPU time | 22.26 seconds |
| Started | Oct 12 02:00:56 PM UTC 24 |
| Finished | Oct 12 02:01:19 PM UTC 24 |
| Peak memory | 224072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1322635358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all _with_rand_reset.1322635358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/79.uart_fifo_reset.3234767463 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 201148153827 ps |
| CPU time | 181.85 seconds |
| Started | Oct 12 02:00:58 PM UTC 24 |
| Finished | Oct 12 02:04:03 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234767463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3234767463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/79.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.1351640487 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 2641678176 ps |
| CPU time | 45.04 seconds |
| Started | Oct 12 02:01:02 PM UTC 24 |
| Finished | Oct 12 02:01:49 PM UTC 24 |
| Peak memory | 217904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1351640487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all _with_rand_reset.1351640487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_alert_test.67262792 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 15101371 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 01:31:24 PM UTC 24 |
| Finished | Oct 12 01:31:26 PM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67262792 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.67262792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_fifo_full.4184600064 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 83416019244 ps |
| CPU time | 133.85 seconds |
| Started | Oct 12 01:30:49 PM UTC 24 |
| Finished | Oct 12 01:33:05 PM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184600064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.4184600064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_fifo_reset.2490289916 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 11824127118 ps |
| CPU time | 29.88 seconds |
| Started | Oct 12 01:30:52 PM UTC 24 |
| Finished | Oct 12 01:31:23 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490289916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2490289916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.2795612956 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 116846625153 ps |
| CPU time | 732.77 seconds |
| Started | Oct 12 01:31:20 PM UTC 24 |
| Finished | Oct 12 01:43:41 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795612956 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2795612956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_loopback.824961329 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3886538582 ps |
| CPU time | 3.33 seconds |
| Started | Oct 12 01:31:18 PM UTC 24 |
| Finished | Oct 12 01:31:22 PM UTC 24 |
| Peak memory | 207228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824961329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 8.uart_loopback.824961329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_noise_filter.1185603 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 81663917209 ps |
| CPU time | 62.57 seconds |
| Started | Oct 12 01:30:56 PM UTC 24 |
| Finished | Oct 12 01:32:01 PM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1185603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_perf.1930271314 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 19595637525 ps |
| CPU time | 583.32 seconds |
| Started | Oct 12 01:31:18 PM UTC 24 |
| Finished | Oct 12 01:41:09 PM UTC 24 |
| Peak memory | 208628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930271314 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1930271314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_rx_oversample.3983871779 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 5907033097 ps |
| CPU time | 54.09 seconds |
| Started | Oct 12 01:30:54 PM UTC 24 |
| Finished | Oct 12 01:31:50 PM UTC 24 |
| Peak memory | 207940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983871779 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3983871779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.2243567586 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 3164626141 ps |
| CPU time | 8.71 seconds |
| Started | Oct 12 01:31:08 PM UTC 24 |
| Finished | Oct 12 01:31:17 PM UTC 24 |
| Peak memory | 205240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243567586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2243567586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_smoke.2728080550 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5336791620 ps |
| CPU time | 9.08 seconds |
| Started | Oct 12 01:30:45 PM UTC 24 |
| Finished | Oct 12 01:30:55 PM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728080550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2728080550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_stress_all.1549791307 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 169804686795 ps |
| CPU time | 835.96 seconds |
| Started | Oct 12 01:31:24 PM UTC 24 |
| Finished | Oct 12 01:45:30 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549791307 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1549791307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.1921788985 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2580503999 ps |
| CPU time | 30.93 seconds |
| Started | Oct 12 01:31:23 PM UTC 24 |
| Finished | Oct 12 01:31:55 PM UTC 24 |
| Peak memory | 217876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1921788985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_ with_rand_reset.1921788985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.1015252685 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 6693261491 ps |
| CPU time | 24 seconds |
| Started | Oct 12 01:31:14 PM UTC 24 |
| Finished | Oct 12 01:31:39 PM UTC 24 |
| Peak memory | 208452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015252685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1015252685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_tx_rx.1046963050 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 95647310869 ps |
| CPU time | 258.51 seconds |
| Started | Oct 12 01:30:47 PM UTC 24 |
| Finished | Oct 12 01:35:09 PM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046963050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1046963050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/8.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/80.uart_fifo_reset.3565133482 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 41959305681 ps |
| CPU time | 11.86 seconds |
| Started | Oct 12 02:01:03 PM UTC 24 |
| Finished | Oct 12 02:01:16 PM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565133482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3565133482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/80.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.3558576488 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 2456441216 ps |
| CPU time | 39.36 seconds |
| Started | Oct 12 02:01:04 PM UTC 24 |
| Finished | Oct 12 02:01:45 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3558576488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all _with_rand_reset.3558576488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/81.uart_fifo_reset.2250401150 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 11820047808 ps |
| CPU time | 40.38 seconds |
| Started | Oct 12 02:01:05 PM UTC 24 |
| Finished | Oct 12 02:01:47 PM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250401150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2250401150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/81.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.2651006540 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 13570976731 ps |
| CPU time | 64.3 seconds |
| Started | Oct 12 02:01:05 PM UTC 24 |
| Finished | Oct 12 02:02:11 PM UTC 24 |
| Peak memory | 219948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2651006540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all _with_rand_reset.2651006540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/82.uart_fifo_reset.1441628367 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 22066010307 ps |
| CPU time | 37.41 seconds |
| Started | Oct 12 02:01:06 PM UTC 24 |
| Finished | Oct 12 02:01:45 PM UTC 24 |
| Peak memory | 208152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441628367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1441628367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/82.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.640009103 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 3409617844 ps |
| CPU time | 45.14 seconds |
| Started | Oct 12 02:01:14 PM UTC 24 |
| Finished | Oct 12 02:02:00 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=640009103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all_ with_rand_reset.640009103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/83.uart_fifo_reset.2825166723 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 41272128095 ps |
| CPU time | 68.86 seconds |
| Started | Oct 12 02:01:17 PM UTC 24 |
| Finished | Oct 12 02:02:27 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825166723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2825166723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/83.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.3788174834 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 14148319075 ps |
| CPU time | 55.34 seconds |
| Started | Oct 12 02:01:20 PM UTC 24 |
| Finished | Oct 12 02:02:17 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3788174834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all _with_rand_reset.3788174834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/84.uart_fifo_reset.596217924 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 143303149316 ps |
| CPU time | 166.63 seconds |
| Started | Oct 12 02:01:21 PM UTC 24 |
| Finished | Oct 12 02:04:10 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596217924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.596217924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/84.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.4236824615 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 17510500527 ps |
| CPU time | 30.87 seconds |
| Started | Oct 12 02:01:23 PM UTC 24 |
| Finished | Oct 12 02:01:55 PM UTC 24 |
| Peak memory | 225104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4236824615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all _with_rand_reset.4236824615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/85.uart_fifo_reset.384640306 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 39830876886 ps |
| CPU time | 94.35 seconds |
| Started | Oct 12 02:01:24 PM UTC 24 |
| Finished | Oct 12 02:03:00 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384640306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.384640306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/85.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.1922596010 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 2884317554 ps |
| CPU time | 53.29 seconds |
| Started | Oct 12 02:01:26 PM UTC 24 |
| Finished | Oct 12 02:02:21 PM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1922596010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all _with_rand_reset.1922596010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/86.uart_fifo_reset.1946393857 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 79287679563 ps |
| CPU time | 17.15 seconds |
| Started | Oct 12 02:01:26 PM UTC 24 |
| Finished | Oct 12 02:01:45 PM UTC 24 |
| Peak memory | 208476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946393857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1946393857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/86.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.2771601981 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 8803530009 ps |
| CPU time | 63.75 seconds |
| Started | Oct 12 02:01:26 PM UTC 24 |
| Finished | Oct 12 02:02:32 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2771601981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all _with_rand_reset.2771601981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/87.uart_fifo_reset.2125307936 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 11155765013 ps |
| CPU time | 23.64 seconds |
| Started | Oct 12 02:01:29 PM UTC 24 |
| Finished | Oct 12 02:01:55 PM UTC 24 |
| Peak memory | 208580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125307936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2125307936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/87.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.2698878451 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 4325116631 ps |
| CPU time | 17.05 seconds |
| Started | Oct 12 02:01:34 PM UTC 24 |
| Finished | Oct 12 02:01:52 PM UTC 24 |
| Peak memory | 217728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2698878451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all _with_rand_reset.2698878451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/88.uart_fifo_reset.4264247177 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 20765514409 ps |
| CPU time | 18.6 seconds |
| Started | Oct 12 02:01:35 PM UTC 24 |
| Finished | Oct 12 02:01:54 PM UTC 24 |
| Peak memory | 208200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264247177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.4264247177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/88.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.797301144 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 2922952508 ps |
| CPU time | 12.45 seconds |
| Started | Oct 12 02:01:35 PM UTC 24 |
| Finished | Oct 12 02:01:48 PM UTC 24 |
| Peak memory | 208948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=797301144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all_ with_rand_reset.797301144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/89.uart_fifo_reset.2652848935 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 19017766109 ps |
| CPU time | 14.48 seconds |
| Started | Oct 12 02:01:37 PM UTC 24 |
| Finished | Oct 12 02:01:52 PM UTC 24 |
| Peak memory | 207296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652848935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2652848935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/89.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.3041050410 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 3116439107 ps |
| CPU time | 25.92 seconds |
| Started | Oct 12 02:01:41 PM UTC 24 |
| Finished | Oct 12 02:02:08 PM UTC 24 |
| Peak memory | 217760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3041050410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all _with_rand_reset.3041050410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_alert_test.3486021285 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 30531343 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 01:32:09 PM UTC 24 |
| Finished | Oct 12 01:32:10 PM UTC 24 |
| Peak memory | 204388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486021285 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3486021285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_fifo_full.3728671241 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 77587091886 ps |
| CPU time | 181.8 seconds |
| Started | Oct 12 01:31:36 PM UTC 24 |
| Finished | Oct 12 01:34:41 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728671241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3728671241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.3576355995 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 149366198646 ps |
| CPU time | 175.31 seconds |
| Started | Oct 12 01:31:38 PM UTC 24 |
| Finished | Oct 12 01:34:36 PM UTC 24 |
| Peak memory | 208364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576355995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3576355995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_intr.707749106 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 17994763266 ps |
| CPU time | 62.13 seconds |
| Started | Oct 12 01:31:43 PM UTC 24 |
| Finished | Oct 12 01:32:47 PM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707749106 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.707749106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.1944076153 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 131237174307 ps |
| CPU time | 526.27 seconds |
| Started | Oct 12 01:32:02 PM UTC 24 |
| Finished | Oct 12 01:40:55 PM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944076153 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1944076153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_loopback.3619476084 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1511883349 ps |
| CPU time | 6.38 seconds |
| Started | Oct 12 01:32:00 PM UTC 24 |
| Finished | Oct 12 01:32:08 PM UTC 24 |
| Peak memory | 207620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619476084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3619476084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_noise_filter.2897454122 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 150259349218 ps |
| CPU time | 96.22 seconds |
| Started | Oct 12 01:31:44 PM UTC 24 |
| Finished | Oct 12 01:33:22 PM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897454122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2897454122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_perf.978200640 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 34909968522 ps |
| CPU time | 1325.8 seconds |
| Started | Oct 12 01:32:01 PM UTC 24 |
| Finished | Oct 12 01:54:22 PM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978200640 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.978200640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_rx_oversample.2184920025 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 5117642750 ps |
| CPU time | 48.73 seconds |
| Started | Oct 12 01:31:42 PM UTC 24 |
| Finished | Oct 12 01:32:32 PM UTC 24 |
| Peak memory | 207480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184920025 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2184920025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.1091741367 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 27211772532 ps |
| CPU time | 50.02 seconds |
| Started | Oct 12 01:31:53 PM UTC 24 |
| Finished | Oct 12 01:32:45 PM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091741367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1091741367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.2739452264 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 6352634412 ps |
| CPU time | 13.64 seconds |
| Started | Oct 12 01:31:51 PM UTC 24 |
| Finished | Oct 12 01:32:06 PM UTC 24 |
| Peak memory | 207352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739452264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2739452264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_smoke.1196478991 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 523338915 ps |
| CPU time | 1.84 seconds |
| Started | Oct 12 01:31:27 PM UTC 24 |
| Finished | Oct 12 01:31:30 PM UTC 24 |
| Peak memory | 207244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196478991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1196478991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_stress_all.1881873365 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 226972302749 ps |
| CPU time | 91.19 seconds |
| Started | Oct 12 01:32:06 PM UTC 24 |
| Finished | Oct 12 01:33:39 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881873365 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1881873365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.3073299342 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5857277670 ps |
| CPU time | 13.42 seconds |
| Started | Oct 12 01:32:03 PM UTC 24 |
| Finished | Oct 12 01:32:18 PM UTC 24 |
| Peak memory | 217928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3073299342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_ with_rand_reset.3073299342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.2390614055 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2418641342 ps |
| CPU time | 4.64 seconds |
| Started | Oct 12 01:31:56 PM UTC 24 |
| Finished | Oct 12 01:32:02 PM UTC 24 |
| Peak memory | 207968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390614055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2390614055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_tx_rx.2858196195 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 71945499864 ps |
| CPU time | 205.4 seconds |
| Started | Oct 12 01:31:31 PM UTC 24 |
| Finished | Oct 12 01:35:00 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858196195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2858196195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/9.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/90.uart_fifo_reset.2698378052 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 90634894733 ps |
| CPU time | 136.04 seconds |
| Started | Oct 12 02:01:41 PM UTC 24 |
| Finished | Oct 12 02:03:59 PM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698378052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2698378052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/90.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.783973318 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 16684792344 ps |
| CPU time | 59.37 seconds |
| Started | Oct 12 02:01:45 PM UTC 24 |
| Finished | Oct 12 02:02:46 PM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=783973318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all_ with_rand_reset.783973318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/91.uart_fifo_reset.788216153 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 84386107537 ps |
| CPU time | 74.04 seconds |
| Started | Oct 12 02:01:45 PM UTC 24 |
| Finished | Oct 12 02:03:01 PM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788216153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.788216153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/91.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.3645658136 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 3311010515 ps |
| CPU time | 30.84 seconds |
| Started | Oct 12 02:01:46 PM UTC 24 |
| Finished | Oct 12 02:02:19 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3645658136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all _with_rand_reset.3645658136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/92.uart_fifo_reset.3058889618 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 148079698473 ps |
| CPU time | 154.7 seconds |
| Started | Oct 12 02:01:46 PM UTC 24 |
| Finished | Oct 12 02:04:24 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058889618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3058889618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/92.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.2897526368 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 1463096359 ps |
| CPU time | 18.16 seconds |
| Started | Oct 12 02:01:46 PM UTC 24 |
| Finished | Oct 12 02:02:06 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2897526368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all _with_rand_reset.2897526368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/93.uart_fifo_reset.2152097832 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 16184498604 ps |
| CPU time | 39.94 seconds |
| Started | Oct 12 02:01:48 PM UTC 24 |
| Finished | Oct 12 02:02:30 PM UTC 24 |
| Peak memory | 208576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152097832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2152097832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/93.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.1186680340 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 3549854538 ps |
| CPU time | 25.41 seconds |
| Started | Oct 12 02:01:50 PM UTC 24 |
| Finished | Oct 12 02:02:16 PM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1186680340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all _with_rand_reset.1186680340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/94.uart_fifo_reset.3144570262 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 81936393952 ps |
| CPU time | 63.87 seconds |
| Started | Oct 12 02:01:50 PM UTC 24 |
| Finished | Oct 12 02:02:55 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144570262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3144570262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/94.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.2318513563 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 9613160616 ps |
| CPU time | 62.15 seconds |
| Started | Oct 12 02:01:52 PM UTC 24 |
| Finished | Oct 12 02:02:56 PM UTC 24 |
| Peak memory | 217724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2318513563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all _with_rand_reset.2318513563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/95.uart_fifo_reset.706250431 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 92905419883 ps |
| CPU time | 239.86 seconds |
| Started | Oct 12 02:01:53 PM UTC 24 |
| Finished | Oct 12 02:05:56 PM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706250431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.706250431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/95.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.1577186000 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 11502021577 ps |
| CPU time | 94.62 seconds |
| Started | Oct 12 02:01:53 PM UTC 24 |
| Finished | Oct 12 02:03:30 PM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1577186000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all _with_rand_reset.1577186000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/96.uart_fifo_reset.1946512150 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 104505348509 ps |
| CPU time | 179.44 seconds |
| Started | Oct 12 02:01:55 PM UTC 24 |
| Finished | Oct 12 02:04:57 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946512150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1946512150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/96.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.68638299 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 8444019275 ps |
| CPU time | 64.97 seconds |
| Started | Oct 12 02:01:55 PM UTC 24 |
| Finished | Oct 12 02:03:02 PM UTC 24 |
| Peak memory | 225320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=68638299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all_w ith_rand_reset.68638299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/97.uart_fifo_reset.225653074 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 44610143054 ps |
| CPU time | 47.25 seconds |
| Started | Oct 12 02:01:55 PM UTC 24 |
| Finished | Oct 12 02:02:44 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225653074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.225653074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/97.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.3164769184 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 33271095989 ps |
| CPU time | 45.97 seconds |
| Started | Oct 12 02:01:56 PM UTC 24 |
| Finished | Oct 12 02:02:44 PM UTC 24 |
| Peak memory | 225532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3164769184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all _with_rand_reset.3164769184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/98.uart_fifo_reset.1201794517 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 8320949330 ps |
| CPU time | 18.92 seconds |
| Started | Oct 12 02:01:57 PM UTC 24 |
| Finished | Oct 12 02:02:18 PM UTC 24 |
| Peak memory | 208512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201794517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1201794517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/98.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.3796970072 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 13311093618 ps |
| CPU time | 64.72 seconds |
| Started | Oct 12 02:02:01 PM UTC 24 |
| Finished | Oct 12 02:03:08 PM UTC 24 |
| Peak memory | 209012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3796970072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all _with_rand_reset.3796970072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.1014227930 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 1232791235 ps |
| CPU time | 19.77 seconds |
| Started | Oct 12 02:02:07 PM UTC 24 |
| Finished | Oct 12 02:02:28 PM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1014227930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all _with_rand_reset.1014227930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest |
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