| T423 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_noise_filter.4065325011 |
|
|
Feb 09 06:51:26 AM UTC 25 |
Feb 09 06:51:46 AM UTC 25 |
8202966397 ps |
| T476 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.2266723295 |
|
|
Feb 09 06:51:43 AM UTC 25 |
Feb 09 06:51:47 AM UTC 25 |
380357431 ps |
| T391 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_smoke.618228495 |
|
|
Feb 09 06:51:13 AM UTC 25 |
Feb 09 06:51:58 AM UTC 25 |
5909506212 ps |
| T282 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_fifo_reset.422017112 |
|
|
Feb 09 06:49:40 AM UTC 25 |
Feb 09 06:53:24 AM UTC 25 |
147502610951 ps |
| T162 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_stress_all.3682204357 |
|
|
Feb 09 06:47:35 AM UTC 25 |
Feb 09 06:52:01 AM UTC 25 |
463501734838 ps |
| T26 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.1697813552 |
|
|
Feb 09 06:40:39 AM UTC 25 |
Feb 09 06:52:01 AM UTC 25 |
36695449916 ps |
| T477 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_alert_test.3263860219 |
|
|
Feb 09 06:52:02 AM UTC 25 |
Feb 09 06:52:04 AM UTC 25 |
14078349 ps |
| T166 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.3767614721 |
|
|
Feb 09 06:51:22 AM UTC 25 |
Feb 09 06:52:04 AM UTC 25 |
45413892740 ps |
| T478 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_rx_oversample.2736955891 |
|
|
Feb 09 06:51:23 AM UTC 25 |
Feb 09 06:52:06 AM UTC 25 |
4333450969 ps |
| T479 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.985500 |
|
|
Feb 09 06:47:31 AM UTC 25 |
Feb 09 06:52:10 AM UTC 25 |
80504074670 ps |
| T480 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_loopback.2414126287 |
|
|
Feb 09 06:51:45 AM UTC 25 |
Feb 09 06:52:11 AM UTC 25 |
6027622233 ps |
| T348 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_tx_rx.1889574243 |
|
|
Feb 09 06:50:36 AM UTC 25 |
Feb 09 06:52:13 AM UTC 25 |
40988103888 ps |
| T373 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.2817345305 |
|
|
Feb 09 06:45:38 AM UTC 25 |
Feb 09 06:52:16 AM UTC 25 |
88707920290 ps |
| T481 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_smoke.332083872 |
|
|
Feb 09 06:52:05 AM UTC 25 |
Feb 09 06:52:16 AM UTC 25 |
6250736418 ps |
| T482 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_rx_oversample.1054876484 |
|
|
Feb 09 06:52:13 AM UTC 25 |
Feb 09 06:52:31 AM UTC 25 |
6136379603 ps |
| T483 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.4002948602 |
|
|
Feb 09 06:52:32 AM UTC 25 |
Feb 09 06:52:37 AM UTC 25 |
3917980317 ps |
| T177 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_fifo_full.1806645851 |
|
|
Feb 09 06:52:07 AM UTC 25 |
Feb 09 06:52:44 AM UTC 25 |
63641268949 ps |
| T368 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.1863221404 |
|
|
Feb 09 06:52:45 AM UTC 25 |
Feb 09 06:52:49 AM UTC 25 |
3737854958 ps |
| T484 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_loopback.2296129008 |
|
|
Feb 09 06:52:50 AM UTC 25 |
Feb 09 06:52:56 AM UTC 25 |
3037063824 ps |
| T485 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_tx_rx.262003711 |
|
|
Feb 09 06:52:05 AM UTC 25 |
Feb 09 06:53:02 AM UTC 25 |
33349075050 ps |
| T337 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.4043367214 |
|
|
Feb 09 06:52:10 AM UTC 25 |
Feb 09 06:53:10 AM UTC 25 |
146788465752 ps |
| T358 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_intr.907304310 |
|
|
Feb 09 06:52:16 AM UTC 25 |
Feb 09 06:53:23 AM UTC 25 |
14238541081 ps |
| T486 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_alert_test.2020651285 |
|
|
Feb 09 06:53:23 AM UTC 25 |
Feb 09 06:53:25 AM UTC 25 |
10848664 ps |
| T392 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_noise_filter.3723363617 |
|
|
Feb 09 06:52:17 AM UTC 25 |
Feb 09 06:53:25 AM UTC 25 |
54329516570 ps |
| T487 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_smoke.1376858269 |
|
|
Feb 09 06:53:25 AM UTC 25 |
Feb 09 06:53:27 AM UTC 25 |
338809809 ps |
| T382 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.3335153183 |
|
|
Feb 09 06:51:48 AM UTC 25 |
Feb 09 06:53:35 AM UTC 25 |
29900849317 ps |
| T27 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.585623898 |
|
|
Feb 09 06:42:24 AM UTC 25 |
Feb 09 06:53:37 AM UTC 25 |
61888279399 ps |
| T120 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_fifo_reset.1688704177 |
|
|
Feb 09 06:51:22 AM UTC 25 |
Feb 09 06:53:45 AM UTC 25 |
113493399790 ps |
| T121 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.1683667102 |
|
|
Feb 09 06:52:38 AM UTC 25 |
Feb 09 06:53:53 AM UTC 25 |
90024156180 ps |
| T122 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.577887639 |
|
|
Feb 09 06:48:55 AM UTC 25 |
Feb 09 06:53:56 AM UTC 25 |
211579801507 ps |
| T123 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_tx_rx.361022546 |
|
|
Feb 09 06:49:09 AM UTC 25 |
Feb 09 06:53:57 AM UTC 25 |
179332076448 ps |
| T124 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.4093308386 |
|
|
Feb 09 06:53:58 AM UTC 25 |
Feb 09 06:54:01 AM UTC 25 |
954343548 ps |
| T125 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.1640376074 |
|
|
Feb 09 06:53:54 AM UTC 25 |
Feb 09 06:54:09 AM UTC 25 |
40055364626 ps |
| T126 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_rx_oversample.2520396080 |
|
|
Feb 09 06:53:38 AM UTC 25 |
Feb 09 06:54:11 AM UTC 25 |
3304378590 ps |
| T127 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.3617853395 |
|
|
Feb 09 06:51:42 AM UTC 25 |
Feb 09 06:54:12 AM UTC 25 |
174568590416 ps |
| T128 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_perf.3910346324 |
|
|
Feb 09 06:50:21 AM UTC 25 |
Feb 09 06:54:14 AM UTC 25 |
17550150826 ps |
| T488 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_loopback.4035976154 |
|
|
Feb 09 06:54:02 AM UTC 25 |
Feb 09 06:54:14 AM UTC 25 |
8299977443 ps |
| T489 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_alert_test.2382071375 |
|
|
Feb 09 06:54:14 AM UTC 25 |
Feb 09 06:54:16 AM UTC 25 |
56310265 ps |
| T381 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_stress_all.201446080 |
|
|
Feb 09 06:51:06 AM UTC 25 |
Feb 09 06:54:24 AM UTC 25 |
97634425697 ps |
| T490 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.1522625495 |
|
|
Feb 09 06:53:57 AM UTC 25 |
Feb 09 06:54:28 AM UTC 25 |
29550676417 ps |
| T491 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_smoke.4073915208 |
|
|
Feb 09 06:54:17 AM UTC 25 |
Feb 09 06:54:32 AM UTC 25 |
5684204276 ps |
| T492 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_noise_filter.1664703554 |
|
|
Feb 09 06:50:48 AM UTC 25 |
Feb 09 06:54:41 AM UTC 25 |
87550261887 ps |
| T34 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.1082751323 |
|
|
Feb 09 06:41:25 AM UTC 25 |
Feb 09 06:54:44 AM UTC 25 |
60545640141 ps |
| T35 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.1871714962 |
|
|
Feb 09 06:37:35 AM UTC 25 |
Feb 09 06:54:46 AM UTC 25 |
145575045335 ps |
| T493 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_perf.1595248774 |
|
|
Feb 09 06:51:01 AM UTC 25 |
Feb 09 06:54:58 AM UTC 25 |
14243493025 ps |
| T494 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_tx_rx.3194153774 |
|
|
Feb 09 06:51:13 AM UTC 25 |
Feb 09 06:54:59 AM UTC 25 |
54177539095 ps |
| T495 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_rx_oversample.2573091044 |
|
|
Feb 09 06:54:45 AM UTC 25 |
Feb 09 06:55:03 AM UTC 25 |
5928003341 ps |
| T496 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.1428969825 |
|
|
Feb 09 06:54:59 AM UTC 25 |
Feb 09 06:55:03 AM UTC 25 |
2198547495 ps |
| T386 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.1853993036 |
|
|
Feb 09 06:55:04 AM UTC 25 |
Feb 09 06:55:08 AM UTC 25 |
6329754398 ps |
| T497 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_tx_rx.4204717126 |
|
|
Feb 09 06:53:26 AM UTC 25 |
Feb 09 06:55:09 AM UTC 25 |
41328966851 ps |
| T138 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_stress_all.728836701 |
|
|
Feb 09 06:45:51 AM UTC 25 |
Feb 09 06:55:10 AM UTC 25 |
253742122815 ps |
| T498 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.2652658771 |
|
|
Feb 09 06:39:25 AM UTC 25 |
Feb 09 06:55:10 AM UTC 25 |
124261069957 ps |
| T390 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_perf.2446555203 |
|
|
Feb 09 06:35:21 AM UTC 25 |
Feb 09 06:55:13 AM UTC 25 |
17630084573 ps |
| T499 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.2168791494 |
|
|
Feb 09 06:53:28 AM UTC 25 |
Feb 09 06:55:14 AM UTC 25 |
55478197926 ps |
| T500 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_alert_test.2125748823 |
|
|
Feb 09 06:55:14 AM UTC 25 |
Feb 09 06:55:16 AM UTC 25 |
15607022 ps |
| T501 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_loopback.1467679898 |
|
|
Feb 09 06:55:04 AM UTC 25 |
Feb 09 06:55:25 AM UTC 25 |
7342174333 ps |
| T502 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_smoke.3148119358 |
|
|
Feb 09 06:55:16 AM UTC 25 |
Feb 09 06:55:28 AM UTC 25 |
5479257962 ps |
| T36 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.465201681 |
|
|
Feb 09 06:35:21 AM UTC 25 |
Feb 09 06:55:29 AM UTC 25 |
284855543132 ps |
| T503 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.3086512076 |
|
|
Feb 09 06:54:33 AM UTC 25 |
Feb 09 06:55:30 AM UTC 25 |
76796718847 ps |
| T387 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_stress_all.4048977990 |
|
|
Feb 09 06:53:11 AM UTC 25 |
Feb 09 06:55:45 AM UTC 25 |
176561580890 ps |
| T504 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_noise_filter.4167350077 |
|
|
Feb 09 06:53:46 AM UTC 25 |
Feb 09 06:55:46 AM UTC 25 |
185736554233 ps |
| T129 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_stress_all.922693445 |
|
|
Feb 09 06:49:01 AM UTC 25 |
Feb 09 06:55:49 AM UTC 25 |
214862788479 ps |
| T505 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_tx_rx.226139457 |
|
|
Feb 09 06:55:17 AM UTC 25 |
Feb 09 06:55:54 AM UTC 25 |
70169314879 ps |
| T506 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.2825441872 |
|
|
Feb 09 06:55:47 AM UTC 25 |
Feb 09 06:55:55 AM UTC 25 |
2583091059 ps |
| T507 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.4162243197 |
|
|
Feb 09 06:55:51 AM UTC 25 |
Feb 09 06:55:56 AM UTC 25 |
1238755871 ps |
| T508 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_rx_oversample.370946954 |
|
|
Feb 09 06:55:31 AM UTC 25 |
Feb 09 06:55:56 AM UTC 25 |
6937798004 ps |
| T340 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_fifo_full.2550747526 |
|
|
Feb 09 06:54:29 AM UTC 25 |
Feb 09 06:55:57 AM UTC 25 |
74896975891 ps |
| T509 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_loopback.3760556831 |
|
|
Feb 09 06:55:55 AM UTC 25 |
Feb 09 06:55:58 AM UTC 25 |
5181177054 ps |
| T510 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_alert_test.1211361515 |
|
|
Feb 09 06:55:59 AM UTC 25 |
Feb 09 06:56:01 AM UTC 25 |
18852495 ps |
| T511 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.543232389 |
|
|
Feb 09 06:55:00 AM UTC 25 |
Feb 09 06:56:01 AM UTC 25 |
80657576655 ps |
| T512 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_smoke.871739525 |
|
|
Feb 09 06:56:02 AM UTC 25 |
Feb 09 06:56:05 AM UTC 25 |
124591805 ps |
| T273 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_fifo_reset.3053820202 |
|
|
Feb 09 06:55:30 AM UTC 25 |
Feb 09 06:56:09 AM UTC 25 |
51478866127 ps |
| T513 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_fifo_full.2716416594 |
|
|
Feb 09 06:55:26 AM UTC 25 |
Feb 09 06:56:14 AM UTC 25 |
98431015277 ps |
| T37 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.3345002499 |
|
|
Feb 09 06:36:05 AM UTC 25 |
Feb 09 06:56:14 AM UTC 25 |
437179404615 ps |
| T514 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_tx_rx.39212030 |
|
|
Feb 09 06:56:02 AM UTC 25 |
Feb 09 06:56:18 AM UTC 25 |
12841851306 ps |
| T515 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_perf.2651862445 |
|
|
Feb 09 06:55:56 AM UTC 25 |
Feb 09 06:56:18 AM UTC 25 |
7266478236 ps |
| T516 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_intr.2809552447 |
|
|
Feb 09 06:56:19 AM UTC 25 |
Feb 09 06:56:27 AM UTC 25 |
31723525445 ps |
| T517 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.2129340872 |
|
|
Feb 09 06:56:27 AM UTC 25 |
Feb 09 06:56:32 AM UTC 25 |
1919834707 ps |
| T38 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.2312868866 |
|
|
Feb 09 06:44:53 AM UTC 25 |
Feb 09 06:56:38 AM UTC 25 |
744465573640 ps |
| T518 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.4105071230 |
|
|
Feb 09 06:56:39 AM UTC 25 |
Feb 09 06:56:43 AM UTC 25 |
1575806141 ps |
| T519 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_loopback.3132725889 |
|
|
Feb 09 06:56:44 AM UTC 25 |
Feb 09 06:56:52 AM UTC 25 |
6826974845 ps |
| T520 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_fifo_full.2403558317 |
|
|
Feb 09 06:56:05 AM UTC 25 |
Feb 09 06:56:54 AM UTC 25 |
45124352023 ps |
| T521 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_noise_filter.818374693 |
|
|
Feb 09 06:55:46 AM UTC 25 |
Feb 09 06:56:56 AM UTC 25 |
17461959588 ps |
| T522 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.337708373 |
|
|
Feb 09 06:56:34 AM UTC 25 |
Feb 09 06:56:57 AM UTC 25 |
74288994995 ps |
| T139 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_stress_all.2375730079 |
|
|
Feb 09 06:52:02 AM UTC 25 |
Feb 09 06:57:13 AM UTC 25 |
340264725846 ps |
| T523 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_alert_test.2655207578 |
|
|
Feb 09 06:57:13 AM UTC 25 |
Feb 09 06:57:15 AM UTC 25 |
104031743 ps |
| T524 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_stress_all.2332785715 |
|
|
Feb 09 06:56:58 AM UTC 25 |
Feb 09 06:57:15 AM UTC 25 |
8395248959 ps |
| T525 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_smoke.4005418238 |
|
|
Feb 09 06:57:16 AM UTC 25 |
Feb 09 06:57:19 AM UTC 25 |
447018075 ps |
| T526 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.1652686356 |
|
|
Feb 09 06:55:29 AM UTC 25 |
Feb 09 06:57:37 AM UTC 25 |
119242449862 ps |
| T527 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_perf.1363466433 |
|
|
Feb 09 06:55:09 AM UTC 25 |
Feb 09 06:57:43 AM UTC 25 |
18895670575 ps |
| T528 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_rx_oversample.3005591614 |
|
|
Feb 09 06:56:15 AM UTC 25 |
Feb 09 06:57:44 AM UTC 25 |
7377755374 ps |
| T196 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_fifo_full.3073168200 |
|
|
Feb 09 06:57:20 AM UTC 25 |
Feb 09 06:57:50 AM UTC 25 |
40342084500 ps |
| T416 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_fifo_reset.3024365376 |
|
|
Feb 09 06:53:37 AM UTC 25 |
Feb 09 06:57:55 AM UTC 25 |
205671995225 ps |
| T529 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_noise_filter.1004057370 |
|
|
Feb 09 06:56:19 AM UTC 25 |
Feb 09 06:58:01 AM UTC 25 |
85353041751 ps |
| T530 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.1213331829 |
|
|
Feb 09 06:57:57 AM UTC 25 |
Feb 09 06:58:05 AM UTC 25 |
4664297308 ps |
| T202 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_fifo_reset.1118730029 |
|
|
Feb 09 06:56:15 AM UTC 25 |
Feb 09 06:58:11 AM UTC 25 |
31794568012 ps |
| T531 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.1265747627 |
|
|
Feb 09 06:58:06 AM UTC 25 |
Feb 09 06:58:13 AM UTC 25 |
1750502956 ps |
| T378 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_tx_rx.2169390270 |
|
|
Feb 09 06:54:25 AM UTC 25 |
Feb 09 06:59:22 AM UTC 25 |
104710578518 ps |
| T532 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.2298148476 |
|
|
Feb 09 06:54:12 AM UTC 25 |
Feb 09 06:58:14 AM UTC 25 |
149124850015 ps |
| T533 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_loopback.1638865159 |
|
|
Feb 09 06:58:12 AM UTC 25 |
Feb 09 06:58:22 AM UTC 25 |
4184894865 ps |
| T534 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_perf.2421339012 |
|
|
Feb 09 06:52:52 AM UTC 25 |
Feb 09 06:58:24 AM UTC 25 |
10333315366 ps |
| T535 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.509470087 |
|
|
Feb 09 06:40:37 AM UTC 25 |
Feb 09 06:58:27 AM UTC 25 |
191171893248 ps |
| T536 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_intr.2812651813 |
|
|
Feb 09 06:57:51 AM UTC 25 |
Feb 09 06:58:27 AM UTC 25 |
42408273906 ps |
| T537 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_alert_test.1898108522 |
|
|
Feb 09 06:58:28 AM UTC 25 |
Feb 09 06:58:30 AM UTC 25 |
20465445 ps |
| T538 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_smoke.2408838600 |
|
|
Feb 09 06:58:28 AM UTC 25 |
Feb 09 06:58:32 AM UTC 25 |
672127344 ps |
| T539 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_fifo_reset.2541797643 |
|
|
Feb 09 06:54:42 AM UTC 25 |
Feb 09 06:58:45 AM UTC 25 |
57816794247 ps |
| T540 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_tx_rx.3414355845 |
|
|
Feb 09 06:57:16 AM UTC 25 |
Feb 09 06:58:58 AM UTC 25 |
63767399391 ps |
| T541 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_fifo_full.2440467185 |
|
|
Feb 09 06:53:27 AM UTC 25 |
Feb 09 06:58:58 AM UTC 25 |
105287022611 ps |
| T542 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.613552198 |
|
|
Feb 09 06:50:52 AM UTC 25 |
Feb 09 06:59:00 AM UTC 25 |
113252170790 ps |
| T543 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_rx_oversample.4167051877 |
|
|
Feb 09 06:57:45 AM UTC 25 |
Feb 09 06:59:04 AM UTC 25 |
8012608687 ps |
| T407 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_stress_all.4273463060 |
|
|
Feb 09 06:42:27 AM UTC 25 |
Feb 09 06:59:05 AM UTC 25 |
162780512038 ps |
| T544 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.2827615193 |
|
|
Feb 09 06:59:06 AM UTC 25 |
Feb 09 06:59:14 AM UTC 25 |
7026947856 ps |
| T545 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.596658696 |
|
|
Feb 09 06:56:55 AM UTC 25 |
Feb 09 06:59:16 AM UTC 25 |
66970620917 ps |
| T546 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.2568470047 |
|
|
Feb 09 06:59:17 AM UTC 25 |
Feb 09 06:59:22 AM UTC 25 |
1291710912 ps |
| T547 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_noise_filter.3967193905 |
|
|
Feb 09 06:57:57 AM UTC 25 |
Feb 09 06:59:28 AM UTC 25 |
190798609861 ps |
| T245 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_fifo_reset.3108611994 |
|
|
Feb 09 06:57:45 AM UTC 25 |
Feb 09 06:59:31 AM UTC 25 |
66625100526 ps |
| T548 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_loopback.3065978692 |
|
|
Feb 09 06:59:22 AM UTC 25 |
Feb 09 06:59:40 AM UTC 25 |
8640591311 ps |
| T549 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_perf.2586839039 |
|
|
Feb 09 06:47:26 AM UTC 25 |
Feb 09 06:59:46 AM UTC 25 |
15066333724 ps |
| T130 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_stress_all.1819072122 |
|
|
Feb 09 06:48:19 AM UTC 25 |
Feb 09 06:59:48 AM UTC 25 |
233106984542 ps |
| T550 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_alert_test.275277498 |
|
|
Feb 09 06:59:47 AM UTC 25 |
Feb 09 06:59:49 AM UTC 25 |
12383474 ps |
| T551 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_noise_filter.1723249165 |
|
|
Feb 09 06:59:05 AM UTC 25 |
Feb 09 06:59:50 AM UTC 25 |
45763684065 ps |
| T552 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.3902552583 |
|
|
Feb 09 06:58:45 AM UTC 25 |
Feb 09 06:59:50 AM UTC 25 |
12655334765 ps |
| T553 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_tx_rx.990647591 |
|
|
Feb 09 06:58:31 AM UTC 25 |
Feb 09 06:59:50 AM UTC 25 |
46335287516 ps |
| T554 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_fifo_full.331592763 |
|
|
Feb 09 06:58:32 AM UTC 25 |
Feb 09 06:59:51 AM UTC 25 |
69690786939 ps |
| T555 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_smoke.2921825050 |
|
|
Feb 09 06:59:49 AM UTC 25 |
Feb 09 06:59:53 AM UTC 25 |
635523320 ps |
| T556 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.3381584969 |
|
|
Feb 09 06:50:25 AM UTC 25 |
Feb 09 06:59:55 AM UTC 25 |
132838114523 ps |
| T557 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_perf.287894081 |
|
|
Feb 09 06:48:47 AM UTC 25 |
Feb 09 06:59:58 AM UTC 25 |
11397361753 ps |
| T558 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_rx_oversample.2898962984 |
|
|
Feb 09 06:58:59 AM UTC 25 |
Feb 09 07:00:01 AM UTC 25 |
6558565913 ps |
| T559 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.2424014018 |
|
|
Feb 09 06:59:59 AM UTC 25 |
Feb 09 07:00:06 AM UTC 25 |
5119100784 ps |
| T560 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_intr.3784217701 |
|
|
Feb 09 06:54:47 AM UTC 25 |
Feb 09 07:00:13 AM UTC 25 |
258051764534 ps |
| T561 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_intr.2293341302 |
|
|
Feb 09 06:59:01 AM UTC 25 |
Feb 09 07:00:16 AM UTC 25 |
95798653832 ps |
| T411 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_noise_filter.2154366711 |
|
|
Feb 09 06:59:56 AM UTC 25 |
Feb 09 07:00:16 AM UTC 25 |
20823681464 ps |
| T427 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_perf.280687832 |
|
|
Feb 09 06:41:16 AM UTC 25 |
Feb 09 07:00:17 AM UTC 25 |
21786301084 ps |
| T562 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_noise_filter.3476715757 |
|
|
Feb 09 06:54:59 AM UTC 25 |
Feb 09 07:00:19 AM UTC 25 |
160686781782 ps |
| T563 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_intr.86112971 |
|
|
Feb 09 06:59:55 AM UTC 25 |
Feb 09 07:00:26 AM UTC 25 |
25719619094 ps |
| T564 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_alert_test.4056822704 |
|
|
Feb 09 07:00:27 AM UTC 25 |
Feb 09 07:00:28 AM UTC 25 |
51475527 ps |
| T565 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_loopback.1116243729 |
|
|
Feb 09 07:00:15 AM UTC 25 |
Feb 09 07:00:30 AM UTC 25 |
3129341629 ps |
| T566 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_rx_oversample.624664010 |
|
|
Feb 09 06:59:52 AM UTC 25 |
Feb 09 07:00:31 AM UTC 25 |
6596835478 ps |
| T567 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.3869765877 |
|
|
Feb 09 06:59:51 AM UTC 25 |
Feb 09 07:00:35 AM UTC 25 |
58396777875 ps |
| T568 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_intr.1383821419 |
|
|
Feb 09 06:53:44 AM UTC 25 |
Feb 09 07:00:40 AM UTC 25 |
271841333719 ps |
| T569 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.1451917875 |
|
|
Feb 09 07:00:15 AM UTC 25 |
Feb 09 07:00:42 AM UTC 25 |
12421083538 ps |
| T570 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_intr.1661398173 |
|
|
Feb 09 06:55:40 AM UTC 25 |
Feb 09 07:00:46 AM UTC 25 |
334034649038 ps |
| T571 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_smoke.3958598705 |
|
|
Feb 09 07:00:30 AM UTC 25 |
Feb 09 07:00:46 AM UTC 25 |
5393260165 ps |
| T572 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_stress_all.2414062501 |
|
|
Feb 09 06:58:25 AM UTC 25 |
Feb 09 07:01:02 AM UTC 25 |
159917164037 ps |
| T573 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_tx_rx.3556066534 |
|
|
Feb 09 06:59:51 AM UTC 25 |
Feb 09 07:01:05 AM UTC 25 |
31845704593 ps |
| T178 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_fifo_full.4203286720 |
|
|
Feb 09 06:59:51 AM UTC 25 |
Feb 09 07:01:07 AM UTC 25 |
87374280003 ps |
| T574 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.2072841996 |
|
|
Feb 09 07:01:05 AM UTC 25 |
Feb 09 07:01:09 AM UTC 25 |
492643355 ps |
| T575 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_loopback.967885190 |
|
|
Feb 09 07:01:07 AM UTC 25 |
Feb 09 07:01:10 AM UTC 25 |
1056690703 ps |
| T576 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.176137730 |
|
|
Feb 09 07:00:02 AM UTC 25 |
Feb 09 07:01:10 AM UTC 25 |
96694444786 ps |
| T39 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.2278021576 |
|
|
Feb 09 06:51:04 AM UTC 25 |
Feb 09 07:01:13 AM UTC 25 |
317894132410 ps |
| T577 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.1564191388 |
|
|
Feb 09 06:56:10 AM UTC 25 |
Feb 09 07:01:14 AM UTC 25 |
233796277965 ps |
| T578 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_alert_test.3269890024 |
|
|
Feb 09 07:01:15 AM UTC 25 |
Feb 09 07:01:17 AM UTC 25 |
14220850 ps |
| T211 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_fifo_reset.4114183268 |
|
|
Feb 09 06:58:59 AM UTC 25 |
Feb 09 07:01:26 AM UTC 25 |
98106074081 ps |
| T579 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.987312447 |
|
|
Feb 09 06:52:57 AM UTC 25 |
Feb 09 07:01:32 AM UTC 25 |
49438218526 ps |
| T580 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_smoke.2552651693 |
|
|
Feb 09 07:01:18 AM UTC 25 |
Feb 09 07:01:38 AM UTC 25 |
6012536077 ps |
| T581 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_fifo_reset.972505876 |
|
|
Feb 09 06:59:51 AM UTC 25 |
Feb 09 07:01:40 AM UTC 25 |
27762698986 ps |
| T40 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.3064535620 |
|
|
Feb 09 06:43:52 AM UTC 25 |
Feb 09 07:01:41 AM UTC 25 |
85803536837 ps |
| T175 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_fifo_full.2986290590 |
|
|
Feb 09 07:00:32 AM UTC 25 |
Feb 09 07:01:43 AM UTC 25 |
84537586478 ps |
| T198 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.2255998995 |
|
|
Feb 09 07:01:39 AM UTC 25 |
Feb 09 07:01:51 AM UTC 25 |
62306401632 ps |
| T582 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.2404488475 |
|
|
Feb 09 06:57:37 AM UTC 25 |
Feb 09 07:01:52 AM UTC 25 |
159293144923 ps |
| T409 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_stress_all.3572086951 |
|
|
Feb 09 06:50:32 AM UTC 25 |
Feb 09 07:01:52 AM UTC 25 |
240593191378 ps |
| T583 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_rx_oversample.3738913795 |
|
|
Feb 09 07:01:42 AM UTC 25 |
Feb 09 07:01:52 AM UTC 25 |
3363450464 ps |
| T222 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_fifo_reset.3764853656 |
|
|
Feb 09 07:00:41 AM UTC 25 |
Feb 09 07:01:55 AM UTC 25 |
44663766144 ps |
| T584 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.2833971254 |
|
|
Feb 09 06:55:57 AM UTC 25 |
Feb 09 07:01:56 AM UTC 25 |
116839743312 ps |
| T585 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.3079602871 |
|
|
Feb 09 07:01:53 AM UTC 25 |
Feb 09 07:01:57 AM UTC 25 |
1241183417 ps |
| T586 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.3130877545 |
|
|
Feb 09 07:01:53 AM UTC 25 |
Feb 09 07:02:03 AM UTC 25 |
1266398557 ps |
| T587 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_rx_oversample.2478865220 |
|
|
Feb 09 07:00:43 AM UTC 25 |
Feb 09 07:02:05 AM UTC 25 |
6271167772 ps |
| T588 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_loopback.3804312294 |
|
|
Feb 09 07:01:56 AM UTC 25 |
Feb 09 07:02:05 AM UTC 25 |
1816528677 ps |
| T589 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_noise_filter.1322968018 |
|
|
Feb 09 07:00:47 AM UTC 25 |
Feb 09 07:02:07 AM UTC 25 |
151888637883 ps |
| T590 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_alert_test.2180578650 |
|
|
Feb 09 07:02:06 AM UTC 25 |
Feb 09 07:02:08 AM UTC 25 |
20161361 ps |
| T591 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_tx_rx.2428889556 |
|
|
Feb 09 07:01:27 AM UTC 25 |
Feb 09 07:02:09 AM UTC 25 |
65351463783 ps |
| T592 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.797789783 |
|
|
Feb 09 07:01:53 AM UTC 25 |
Feb 09 07:02:20 AM UTC 25 |
37205210899 ps |
| T593 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_smoke.3281437737 |
|
|
Feb 09 07:02:08 AM UTC 25 |
Feb 09 07:02:25 AM UTC 25 |
11633538854 ps |
| T192 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_fifo_full.2894719280 |
|
|
Feb 09 07:02:10 AM UTC 25 |
Feb 09 07:02:30 AM UTC 25 |
32062883516 ps |
| T594 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.1835635431 |
|
|
Feb 09 06:59:29 AM UTC 25 |
Feb 09 07:02:36 AM UTC 25 |
56493766205 ps |
| T595 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_tx_rx.3049832423 |
|
|
Feb 09 07:00:31 AM UTC 25 |
Feb 09 07:02:40 AM UTC 25 |
81343761156 ps |
| T412 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_noise_filter.963404653 |
|
|
Feb 09 07:01:52 AM UTC 25 |
Feb 09 07:02:42 AM UTC 25 |
85476956979 ps |
| T596 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_stress_all.3026718354 |
|
|
Feb 09 06:59:41 AM UTC 25 |
Feb 09 07:02:43 AM UTC 25 |
44650046289 ps |
| T597 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_rx_oversample.1237534199 |
|
|
Feb 09 07:02:30 AM UTC 25 |
Feb 09 07:02:46 AM UTC 25 |
2801983230 ps |
| T598 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_intr.1788182155 |
|
|
Feb 09 07:02:37 AM UTC 25 |
Feb 09 07:02:48 AM UTC 25 |
7717797951 ps |
| T599 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_tx_rx.1985471052 |
|
|
Feb 09 07:02:09 AM UTC 25 |
Feb 09 07:02:50 AM UTC 25 |
45009886949 ps |
| T600 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_stress_all.1666027822 |
|
|
Feb 09 06:55:58 AM UTC 25 |
Feb 09 07:02:51 AM UTC 25 |
386748098747 ps |
| T601 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_loopback.3909885227 |
|
|
Feb 09 07:03:29 AM UTC 25 |
Feb 09 07:03:42 AM UTC 25 |
1772950218 ps |
| T602 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.4207854283 |
|
|
Feb 09 07:02:48 AM UTC 25 |
Feb 09 07:02:53 AM UTC 25 |
1118171453 ps |
| T603 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_intr.4286248692 |
|
|
Feb 09 07:01:43 AM UTC 25 |
Feb 09 07:02:54 AM UTC 25 |
45306470963 ps |
| T604 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.3548248070 |
|
|
Feb 09 07:02:43 AM UTC 25 |
Feb 09 07:02:57 AM UTC 25 |
5492388984 ps |
| T605 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_alert_test.504786181 |
|
|
Feb 09 07:02:58 AM UTC 25 |
Feb 09 07:03:00 AM UTC 25 |
111683771 ps |
| T606 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_loopback.1024325158 |
|
|
Feb 09 07:02:49 AM UTC 25 |
Feb 09 07:03:00 AM UTC 25 |
3799724137 ps |
| T395 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.2033322352 |
|
|
Feb 09 06:53:02 AM UTC 25 |
Feb 09 07:03:03 AM UTC 25 |
143793136322 ps |
| T607 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.148894554 |
|
|
Feb 09 07:00:56 AM UTC 25 |
Feb 09 07:03:07 AM UTC 25 |
50070221812 ps |
| T253 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_fifo_reset.2926267498 |
|
|
Feb 09 07:02:26 AM UTC 25 |
Feb 09 07:03:08 AM UTC 25 |
23994965477 ps |
| T608 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_fifo_full.3761335064 |
|
|
Feb 09 07:01:33 AM UTC 25 |
Feb 09 07:03:09 AM UTC 25 |
149016955851 ps |
| T182 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_fifo_reset.551600702 |
|
|
Feb 09 07:01:41 AM UTC 25 |
Feb 09 07:03:17 AM UTC 25 |
162935847752 ps |
| T609 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_rx_oversample.3122555855 |
|
|
Feb 09 07:03:09 AM UTC 25 |
Feb 09 07:03:18 AM UTC 25 |
4681318623 ps |
| T610 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_perf.2643680580 |
|
|
Feb 09 06:59:23 AM UTC 25 |
Feb 09 07:03:22 AM UTC 25 |
22215856974 ps |
| T398 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.1393586725 |
|
|
Feb 09 06:51:59 AM UTC 25 |
Feb 09 07:03:26 AM UTC 25 |
59540944106 ps |
| T611 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_smoke.3021200318 |
|
|
Feb 09 07:03:01 AM UTC 25 |
Feb 09 07:03:27 AM UTC 25 |
5975862591 ps |
| T612 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_intr.923815382 |
|
|
Feb 09 07:03:17 AM UTC 25 |
Feb 09 07:03:28 AM UTC 25 |
15740528347 ps |
| T613 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.995306102 |
|
|
Feb 09 07:02:44 AM UTC 25 |
Feb 09 07:03:30 AM UTC 25 |
54211332347 ps |
| T614 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.2463683861 |
|
|
Feb 09 06:59:15 AM UTC 25 |
Feb 09 07:03:37 AM UTC 25 |
324562214062 ps |
| T165 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.3611738823 |
|
|
Feb 09 06:55:50 AM UTC 25 |
Feb 09 07:03:42 AM UTC 25 |
130052320846 ps |
| T167 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_fifo_full.3626412653 |
|
|
Feb 09 07:03:03 AM UTC 25 |
Feb 09 07:03:47 AM UTC 25 |
21060788496 ps |
| T615 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_alert_test.509309989 |
|
|
Feb 09 07:03:47 AM UTC 25 |
Feb 09 07:03:49 AM UTC 25 |
30722897 ps |
| T616 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.3845771885 |
|
|
Feb 09 07:03:23 AM UTC 25 |
Feb 09 07:03:56 AM UTC 25 |
39744463044 ps |
| T617 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.2455590808 |
|
|
Feb 09 07:03:27 AM UTC 25 |
Feb 09 07:04:05 AM UTC 25 |
60524823510 ps |
| T618 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.3901318187 |
|
|
Feb 09 07:03:28 AM UTC 25 |
Feb 09 07:04:11 AM UTC 25 |
6029486767 ps |
| T619 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.3827215659 |
|
|
Feb 09 06:51:04 AM UTC 25 |
Feb 09 07:04:11 AM UTC 25 |
133203549121 ps |
| T620 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_smoke.4272409534 |
|
|
Feb 09 07:03:50 AM UTC 25 |
Feb 09 07:04:14 AM UTC 25 |
5838050749 ps |
| T621 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_stress_all.1719318580 |
|
|
Feb 09 07:03:43 AM UTC 25 |
Feb 09 07:04:17 AM UTC 25 |
19135522333 ps |
| T397 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.927400408 |
|
|
Feb 09 07:02:54 AM UTC 25 |
Feb 09 07:04:19 AM UTC 25 |
4973339837 ps |
| T622 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_tx_rx.4234477603 |
|
|
Feb 09 07:03:01 AM UTC 25 |
Feb 09 07:04:20 AM UTC 25 |
55334551314 ps |
| T415 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_stress_all.665270805 |
|
|
Feb 09 06:55:12 AM UTC 25 |
Feb 09 07:04:22 AM UTC 25 |
516107553158 ps |
| T623 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_tx_rx.3094391713 |
|
|
Feb 09 07:03:57 AM UTC 25 |
Feb 09 07:04:26 AM UTC 25 |
10830780878 ps |
| T624 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.3816944556 |
|
|
Feb 09 07:04:21 AM UTC 25 |
Feb 09 07:04:28 AM UTC 25 |
3555967029 ps |
| T625 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_noise_filter.2845675671 |
|
|
Feb 09 07:03:18 AM UTC 25 |
Feb 09 07:04:31 AM UTC 25 |
26063818182 ps |
| T626 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.3054908117 |
|
|
Feb 09 07:04:27 AM UTC 25 |
Feb 09 07:04:33 AM UTC 25 |
2388880508 ps |
| T627 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.985001342 |
|
|
Feb 09 07:00:36 AM UTC 25 |
Feb 09 07:04:36 AM UTC 25 |
135983865170 ps |
| T628 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_rx_oversample.2031901733 |
|
|
Feb 09 07:04:15 AM UTC 25 |
Feb 09 07:04:37 AM UTC 25 |
7244834854 ps |
| T629 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_perf.1742455034 |
|
|
Feb 09 06:48:11 AM UTC 25 |
Feb 09 07:04:38 AM UTC 25 |
19765108370 ps |
| T630 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_noise_filter.2823169207 |
|
|
Feb 09 07:04:21 AM UTC 25 |
Feb 09 07:04:40 AM UTC 25 |
6192183962 ps |
| T631 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_alert_test.4039775369 |
|
|
Feb 09 07:04:39 AM UTC 25 |
Feb 09 07:04:41 AM UTC 25 |
24332949 ps |
| T632 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_loopback.910065174 |
|
|
Feb 09 07:04:29 AM UTC 25 |
Feb 09 07:04:43 AM UTC 25 |
6419384884 ps |
| T633 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_noise_filter.1468028160 |
|
|
Feb 09 07:02:40 AM UTC 25 |
Feb 09 07:04:51 AM UTC 25 |
77142981435 ps |
| T634 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_intr.726499912 |
|
|
Feb 09 07:04:18 AM UTC 25 |
Feb 09 07:04:56 AM UTC 25 |
15463294855 ps |
| T179 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_fifo_full.2580193111 |
|
|
Feb 09 07:04:05 AM UTC 25 |
Feb 09 07:04:58 AM UTC 25 |
49113006872 ps |
| T635 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.3965700140 |
|
|
Feb 09 07:04:23 AM UTC 25 |
Feb 09 07:05:00 AM UTC 25 |
117853999671 ps |
| T214 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_fifo_reset.3109612471 |
|
|
Feb 09 07:04:11 AM UTC 25 |
Feb 09 07:05:00 AM UTC 25 |
34677259153 ps |
| T636 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_stress_all.2723215571 |
|
|
Feb 09 07:04:37 AM UTC 25 |
Feb 09 07:05:00 AM UTC 25 |
18550170444 ps |
| T637 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.404514948 |
|
|
Feb 09 07:01:10 AM UTC 25 |
Feb 09 07:05:01 AM UTC 25 |
106864124957 ps |
| T638 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_smoke.847115057 |
|
|
Feb 09 07:04:41 AM UTC 25 |
Feb 09 07:05:06 AM UTC 25 |
5543964639 ps |
| T639 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.3597205222 |
|
|
Feb 09 07:03:08 AM UTC 25 |
Feb 09 07:05:10 AM UTC 25 |
56309785275 ps |
| T640 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.1949269798 |
|
|
Feb 09 07:05:07 AM UTC 25 |
Feb 09 07:05:11 AM UTC 25 |
448704536 ps |
| T641 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_rx_oversample.1778272382 |
|
|
Feb 09 07:05:00 AM UTC 25 |
Feb 09 07:05:14 AM UTC 25 |
2449606048 ps |
| T642 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_perf.4099198382 |
|
|
Feb 09 06:56:53 AM UTC 25 |
Feb 09 07:05:15 AM UTC 25 |
9634223995 ps |
| T643 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_stress_all.3270310051 |
|
|
Feb 09 07:02:55 AM UTC 25 |
Feb 09 07:05:18 AM UTC 25 |
69356448623 ps |
| T219 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_fifo_reset.1862401331 |
|
|
Feb 09 07:04:58 AM UTC 25 |
Feb 09 07:05:22 AM UTC 25 |
32883405598 ps |
| T114 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.540934638 |
|
|
Feb 09 06:48:57 AM UTC 25 |
Feb 09 07:05:24 AM UTC 25 |
228787138573 ps |
| T644 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_alert_test.1909523755 |
|
|
Feb 09 07:05:23 AM UTC 25 |
Feb 09 07:05:25 AM UTC 25 |
42207211 ps |
| T645 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_loopback.2977439531 |
|
|
Feb 09 07:05:10 AM UTC 25 |
Feb 09 07:05:27 AM UTC 25 |
7214115254 ps |
| T417 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.1513303180 |
|
|
Feb 09 07:04:51 AM UTC 25 |
Feb 09 07:05:29 AM UTC 25 |
25132122815 ps |
| T646 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_smoke.3337353645 |
|
|
Feb 09 07:05:26 AM UTC 25 |
Feb 09 07:05:29 AM UTC 25 |
459987496 ps |
| T647 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_noise_filter.2918017423 |
|
|
Feb 09 07:05:01 AM UTC 25 |
Feb 09 07:05:31 AM UTC 25 |
12982214152 ps |
| T648 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_intr.2523034246 |
|
|
Feb 09 07:05:01 AM UTC 25 |
Feb 09 07:05:35 AM UTC 25 |
30967021158 ps |
| T649 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_rx_oversample.3977330022 |
|
|
Feb 09 07:05:32 AM UTC 25 |
Feb 09 07:05:36 AM UTC 25 |
2267716965 ps |
| T650 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_intr.784005766 |
|
|
Feb 09 07:05:35 AM UTC 25 |
Feb 09 07:05:44 AM UTC 25 |
4709268054 ps |
| T651 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_tx_rx.1796404560 |
|
|
Feb 09 07:05:27 AM UTC 25 |
Feb 09 07:05:48 AM UTC 25 |
13885814969 ps |
| T115 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.750675200 |
|
|
Feb 09 06:58:23 AM UTC 25 |
Feb 09 07:05:49 AM UTC 25 |
47178115644 ps |
| T652 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.4193768469 |
|
|
Feb 09 07:05:45 AM UTC 25 |
Feb 09 07:05:55 AM UTC 25 |
2173189032 ps |
| T653 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.729273482 |
|
|
Feb 09 07:05:50 AM UTC 25 |
Feb 09 07:05:56 AM UTC 25 |
1776710872 ps |
| T654 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.2274245867 |
|
|
Feb 09 07:00:17 AM UTC 25 |
Feb 09 07:06:02 AM UTC 25 |
59429673701 ps |