| T388 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.2783706878 |
|
|
Oct 15 10:51:02 AM UTC 24 |
Oct 15 10:51:22 AM UTC 24 |
7896871245 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_perf.242467205 |
|
|
Oct 15 10:49:17 AM UTC 24 |
Oct 15 10:51:24 AM UTC 24 |
13088949070 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.455021499 |
|
|
Oct 15 10:49:17 AM UTC 24 |
Oct 15 10:51:33 AM UTC 24 |
67207946820 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_alert_test.4080125585 |
|
|
Oct 15 10:51:34 AM UTC 24 |
Oct 15 10:51:36 AM UTC 24 |
31633103 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_smoke.4095762980 |
|
|
Oct 15 10:51:37 AM UTC 24 |
Oct 15 10:51:41 AM UTC 24 |
472849296 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.522388783 |
|
|
Oct 15 10:49:54 AM UTC 24 |
Oct 15 10:51:49 AM UTC 24 |
54185171585 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_tx_rx.184375214 |
|
|
Oct 15 10:51:42 AM UTC 24 |
Oct 15 10:51:55 AM UTC 24 |
8934751462 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.2322064666 |
|
|
Oct 15 10:51:23 AM UTC 24 |
Oct 15 10:52:05 AM UTC 24 |
2649115734 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_fifo_full.1884984340 |
|
|
Oct 15 10:51:50 AM UTC 24 |
Oct 15 10:52:26 AM UTC 24 |
58263444599 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.2422681652 |
|
|
Oct 15 10:51:55 AM UTC 24 |
Oct 15 10:52:33 AM UTC 24 |
63107572221 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_intr.2470993857 |
|
|
Oct 15 10:52:33 AM UTC 24 |
Oct 15 10:52:36 AM UTC 24 |
570355560 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_perf.2853114253 |
|
|
Oct 15 10:45:41 AM UTC 24 |
Oct 15 10:52:37 AM UTC 24 |
22141832962 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.3746003179 |
|
|
Oct 15 10:52:38 AM UTC 24 |
Oct 15 10:52:48 AM UTC 24 |
3226282952 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.1452786234 |
|
|
Oct 15 10:45:42 AM UTC 24 |
Oct 15 10:52:53 AM UTC 24 |
135542643849 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.2065257380 |
|
|
Oct 15 10:35:21 AM UTC 24 |
Oct 15 10:52:54 AM UTC 24 |
98365862952 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_loopback.374973403 |
|
|
Oct 15 10:52:55 AM UTC 24 |
Oct 15 10:52:59 AM UTC 24 |
1803447388 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.4283549925 |
|
|
Oct 15 10:50:54 AM UTC 24 |
Oct 15 10:53:10 AM UTC 24 |
58505196786 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_fifo_reset.1838860704 |
|
|
Oct 15 10:52:06 AM UTC 24 |
Oct 15 10:53:16 AM UTC 24 |
12409897709 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_perf.2874300666 |
|
|
Oct 15 10:37:37 AM UTC 24 |
Oct 15 10:53:23 AM UTC 24 |
16453150187 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_stress_all.973609253 |
|
|
Oct 15 10:45:46 AM UTC 24 |
Oct 15 10:53:28 AM UTC 24 |
206408464007 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_alert_test.3542259872 |
|
|
Oct 15 10:53:29 AM UTC 24 |
Oct 15 10:53:31 AM UTC 24 |
13290584 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_fifo_reset.390409856 |
|
|
Oct 15 10:48:13 AM UTC 24 |
Oct 15 10:53:31 AM UTC 24 |
130469914449 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_smoke.1868668496 |
|
|
Oct 15 10:53:31 AM UTC 24 |
Oct 15 10:53:35 AM UTC 24 |
508845999 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.1151475340 |
|
|
Oct 15 10:52:49 AM UTC 24 |
Oct 15 10:53:39 AM UTC 24 |
70268092937 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_rx_oversample.3673573293 |
|
|
Oct 15 10:52:26 AM UTC 24 |
Oct 15 10:53:40 AM UTC 24 |
6695354606 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_perf.3593645787 |
|
|
Oct 15 10:44:40 AM UTC 24 |
Oct 15 10:53:40 AM UTC 24 |
9618232777 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.1272998628 |
|
|
Oct 15 10:52:54 AM UTC 24 |
Oct 15 10:53:43 AM UTC 24 |
11832518565 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_rx_oversample.1945258757 |
|
|
Oct 15 10:53:42 AM UTC 24 |
Oct 15 10:53:50 AM UTC 24 |
1479427829 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_noise_filter.1578400232 |
|
|
Oct 15 10:52:36 AM UTC 24 |
Oct 15 10:53:57 AM UTC 24 |
159227404485 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_noise_filter.1460623856 |
|
|
Oct 15 10:53:51 AM UTC 24 |
Oct 15 10:54:00 AM UTC 24 |
3108054934 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_stress_all.3872029595 |
|
|
Oct 15 10:31:34 AM UTC 24 |
Oct 15 10:54:09 AM UTC 24 |
392490636279 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.1870136049 |
|
|
Oct 15 10:54:10 AM UTC 24 |
Oct 15 10:54:13 AM UTC 24 |
1771778513 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_tx_rx.3328997058 |
|
|
Oct 15 10:53:32 AM UTC 24 |
Oct 15 10:54:17 AM UTC 24 |
194503696055 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.2304884383 |
|
|
Oct 15 10:53:58 AM UTC 24 |
Oct 15 10:54:22 AM UTC 24 |
43467601383 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_fifo_full.3766367845 |
|
|
Oct 15 10:48:04 AM UTC 24 |
Oct 15 10:54:23 AM UTC 24 |
109582340029 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.1764974199 |
|
|
Oct 15 10:53:17 AM UTC 24 |
Oct 15 10:54:23 AM UTC 24 |
57995867072 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_loopback.3789812513 |
|
|
Oct 15 10:54:14 AM UTC 24 |
Oct 15 10:54:24 AM UTC 24 |
3012701192 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_alert_test.4083464761 |
|
|
Oct 15 10:54:25 AM UTC 24 |
Oct 15 10:54:27 AM UTC 24 |
138310701 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_perf.3797217609 |
|
|
Oct 15 10:51:10 AM UTC 24 |
Oct 15 10:54:32 AM UTC 24 |
11075420410 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_smoke.69794327 |
|
|
Oct 15 10:54:27 AM UTC 24 |
Oct 15 10:54:32 AM UTC 24 |
674532753 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_stress_all.929578496 |
|
|
Oct 15 10:53:24 AM UTC 24 |
Oct 15 10:54:50 AM UTC 24 |
510048233671 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.1449279324 |
|
|
Oct 15 10:49:09 AM UTC 24 |
Oct 15 10:54:52 AM UTC 24 |
138222169847 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_fifo_full.2361036723 |
|
|
Oct 15 10:53:36 AM UTC 24 |
Oct 15 10:55:04 AM UTC 24 |
47929980213 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.368530256 |
|
|
Oct 15 10:54:24 AM UTC 24 |
Oct 15 10:55:10 AM UTC 24 |
11196412827 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.804634448 |
|
|
Oct 15 10:54:51 AM UTC 24 |
Oct 15 10:55:13 AM UTC 24 |
37375915771 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_stress_all.2411073684 |
|
|
Oct 15 10:51:25 AM UTC 24 |
Oct 15 10:55:16 AM UTC 24 |
244229626557 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.1389398208 |
|
|
Oct 15 10:55:16 AM UTC 24 |
Oct 15 10:55:19 AM UTC 24 |
4093330803 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.2229778860 |
|
|
Oct 15 10:40:15 AM UTC 24 |
Oct 15 10:55:19 AM UTC 24 |
138530232886 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.1521467028 |
|
|
Oct 15 10:55:20 AM UTC 24 |
Oct 15 10:55:23 AM UTC 24 |
498637280 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_rx_oversample.1063961433 |
|
|
Oct 15 10:55:05 AM UTC 24 |
Oct 15 10:55:26 AM UTC 24 |
2537573332 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_loopback.1532969336 |
|
|
Oct 15 10:55:24 AM UTC 24 |
Oct 15 10:55:29 AM UTC 24 |
3892683097 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_fifo_reset.2447362686 |
|
|
Oct 15 10:53:40 AM UTC 24 |
Oct 15 10:55:33 AM UTC 24 |
215799810339 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_intr.3762809753 |
|
|
Oct 15 10:55:11 AM UTC 24 |
Oct 15 10:55:41 AM UTC 24 |
45027147553 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_fifo_full.2488282409 |
|
|
Oct 15 10:54:33 AM UTC 24 |
Oct 15 10:55:50 AM UTC 24 |
28678765859 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_fifo_reset.2959127975 |
|
|
Oct 15 10:50:07 AM UTC 24 |
Oct 15 10:55:51 AM UTC 24 |
111128002253 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_alert_test.1977047636 |
|
|
Oct 15 10:55:51 AM UTC 24 |
Oct 15 10:55:52 AM UTC 24 |
34592977 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_fifo_full.1622054645 |
|
|
Oct 15 10:49:32 AM UTC 24 |
Oct 15 10:56:01 AM UTC 24 |
177922093491 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_tx_rx.615096691 |
|
|
Oct 15 10:54:33 AM UTC 24 |
Oct 15 10:56:05 AM UTC 24 |
115217580674 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_smoke.4211883841 |
|
|
Oct 15 10:55:52 AM UTC 24 |
Oct 15 10:56:19 AM UTC 24 |
5885039652 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.2983011863 |
|
|
Oct 15 10:55:20 AM UTC 24 |
Oct 15 10:56:25 AM UTC 24 |
28395113635 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.1443096782 |
|
|
Oct 15 10:56:05 AM UTC 24 |
Oct 15 10:56:34 AM UTC 24 |
48844604195 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_fifo_reset.2348679602 |
|
|
Oct 15 10:56:19 AM UTC 24 |
Oct 15 10:56:36 AM UTC 24 |
15411532586 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_tx_rx.1920287471 |
|
|
Oct 15 10:55:53 AM UTC 24 |
Oct 15 10:56:37 AM UTC 24 |
38287243596 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_rx_oversample.669676613 |
|
|
Oct 15 10:56:26 AM UTC 24 |
Oct 15 10:56:38 AM UTC 24 |
4325521221 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.1749142803 |
|
|
Oct 15 10:55:34 AM UTC 24 |
Oct 15 10:56:44 AM UTC 24 |
11407083746 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.2212039828 |
|
|
Oct 15 10:56:44 AM UTC 24 |
Oct 15 10:56:49 AM UTC 24 |
2628587239 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.3240052943 |
|
|
Oct 15 10:56:37 AM UTC 24 |
Oct 15 10:56:50 AM UTC 24 |
3947908279 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_loopback.2393549959 |
|
|
Oct 15 10:56:50 AM UTC 24 |
Oct 15 10:56:57 AM UTC 24 |
3384912799 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_intr.286935957 |
|
|
Oct 15 10:56:34 AM UTC 24 |
Oct 15 10:57:01 AM UTC 24 |
19509245774 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.3729075819 |
|
|
Oct 15 10:44:40 AM UTC 24 |
Oct 15 10:57:15 AM UTC 24 |
95672016478 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_alert_test.522525573 |
|
|
Oct 15 10:57:44 AM UTC 24 |
Oct 15 10:57:46 AM UTC 24 |
25542106 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_smoke.1498968815 |
|
|
Oct 15 10:57:47 AM UTC 24 |
Oct 15 10:57:50 AM UTC 24 |
514447892 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_fifo_reset.1979584719 |
|
|
Oct 15 10:54:53 AM UTC 24 |
Oct 15 10:58:09 AM UTC 24 |
181973986123 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_stress_all.1610781945 |
|
|
Oct 15 10:54:24 AM UTC 24 |
Oct 15 10:58:13 AM UTC 24 |
399037689519 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_perf.1603436749 |
|
|
Oct 15 10:54:18 AM UTC 24 |
Oct 15 10:58:16 AM UTC 24 |
6656754016 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_noise_filter.720635510 |
|
|
Oct 15 10:55:14 AM UTC 24 |
Oct 15 10:58:16 AM UTC 24 |
66927155119 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_stress_all.3924677864 |
|
|
Oct 15 10:55:42 AM UTC 24 |
Oct 15 10:58:20 AM UTC 24 |
68819482869 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_intr.586733394 |
|
|
Oct 15 10:53:44 AM UTC 24 |
Oct 15 10:58:25 AM UTC 24 |
263158123979 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_intr.3229614687 |
|
|
Oct 15 10:58:21 AM UTC 24 |
Oct 15 10:58:26 AM UTC 24 |
11890810451 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_tx_rx.2291114928 |
|
|
Oct 15 10:57:50 AM UTC 24 |
Oct 15 10:58:31 AM UTC 24 |
30587340524 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.727971430 |
|
|
Oct 15 10:58:27 AM UTC 24 |
Oct 15 10:58:33 AM UTC 24 |
1619992878 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_rx_oversample.1825458751 |
|
|
Oct 15 10:58:17 AM UTC 24 |
Oct 15 10:58:42 AM UTC 24 |
4719890203 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.2842606522 |
|
|
Oct 15 10:57:02 AM UTC 24 |
Oct 15 10:58:45 AM UTC 24 |
19660437982 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.2564764220 |
|
|
Oct 15 10:54:01 AM UTC 24 |
Oct 15 10:58:48 AM UTC 24 |
154734780505 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.1383998797 |
|
|
Oct 15 10:58:14 AM UTC 24 |
Oct 15 10:58:50 AM UTC 24 |
17385631649 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.2508991561 |
|
|
Oct 15 10:58:34 AM UTC 24 |
Oct 15 10:58:55 AM UTC 24 |
7972537859 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_loopback.2807341239 |
|
|
Oct 15 10:58:43 AM UTC 24 |
Oct 15 10:58:58 AM UTC 24 |
6126313535 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_fifo_reset.1417728093 |
|
|
Oct 15 10:58:16 AM UTC 24 |
Oct 15 10:58:58 AM UTC 24 |
70998203347 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_alert_test.3731014967 |
|
|
Oct 15 10:58:58 AM UTC 24 |
Oct 15 10:59:00 AM UTC 24 |
16244280 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_fifo_full.2753745856 |
|
|
Oct 15 10:56:02 AM UTC 24 |
Oct 15 10:59:01 AM UTC 24 |
339302710865 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_smoke.2162354263 |
|
|
Oct 15 10:58:59 AM UTC 24 |
Oct 15 10:59:02 AM UTC 24 |
627088973 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_tx_rx.475183908 |
|
|
Oct 15 10:59:01 AM UTC 24 |
Oct 15 10:59:04 AM UTC 24 |
1987765148 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_noise_filter.3884219857 |
|
|
Oct 15 10:58:26 AM UTC 24 |
Oct 15 10:59:29 AM UTC 24 |
44699301039 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.4000546747 |
|
|
Oct 15 10:56:38 AM UTC 24 |
Oct 15 10:59:43 AM UTC 24 |
131698257973 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_rx_oversample.2786287629 |
|
|
Oct 15 10:59:30 AM UTC 24 |
Oct 15 10:59:44 AM UTC 24 |
4888827631 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.2155489191 |
|
|
Oct 15 10:58:51 AM UTC 24 |
Oct 15 10:59:57 AM UTC 24 |
46885968049 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_perf.3264920778 |
|
|
Oct 15 10:58:46 AM UTC 24 |
Oct 15 10:59:59 AM UTC 24 |
6669640181 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.528559327 |
|
|
Oct 15 10:59:58 AM UTC 24 |
Oct 15 11:00:01 AM UTC 24 |
2295830682 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_perf.1565390134 |
|
|
Oct 15 10:55:27 AM UTC 24 |
Oct 15 11:00:05 AM UTC 24 |
10749049674 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.3052536026 |
|
|
Oct 15 11:00:02 AM UTC 24 |
Oct 15 11:00:08 AM UTC 24 |
986041074 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_loopback.2010086971 |
|
|
Oct 15 11:00:06 AM UTC 24 |
Oct 15 11:00:14 AM UTC 24 |
3652340763 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_perf.1120886944 |
|
|
Oct 15 10:53:00 AM UTC 24 |
Oct 15 11:00:23 AM UTC 24 |
12517587923 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.704610575 |
|
|
Oct 15 11:00:00 AM UTC 24 |
Oct 15 11:00:38 AM UTC 24 |
61854079469 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_stress_all.1101542857 |
|
|
Oct 15 11:00:38 AM UTC 24 |
Oct 15 11:00:45 AM UTC 24 |
19330513971 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.2940242382 |
|
|
Oct 15 10:59:03 AM UTC 24 |
Oct 15 11:00:46 AM UTC 24 |
43957657756 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_alert_test.593235340 |
|
|
Oct 15 11:00:45 AM UTC 24 |
Oct 15 11:00:47 AM UTC 24 |
14378693 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_fifo_full.2411314130 |
|
|
Oct 15 10:58:10 AM UTC 24 |
Oct 15 11:00:50 AM UTC 24 |
62507474789 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_perf.394661382 |
|
|
Oct 15 10:41:29 AM UTC 24 |
Oct 15 11:00:59 AM UTC 24 |
21319497522 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_smoke.3672190429 |
|
|
Oct 15 11:00:48 AM UTC 24 |
Oct 15 11:01:00 AM UTC 24 |
5874611527 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_stress_all.2363487389 |
|
|
Oct 15 10:49:22 AM UTC 24 |
Oct 15 11:01:04 AM UTC 24 |
277626314968 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.3365248605 |
|
|
Oct 15 10:53:11 AM UTC 24 |
Oct 15 11:01:05 AM UTC 24 |
215125029413 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.1840217260 |
|
|
Oct 15 10:55:29 AM UTC 24 |
Oct 15 11:01:06 AM UTC 24 |
52341534314 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_noise_filter.1152890616 |
|
|
Oct 15 10:59:45 AM UTC 24 |
Oct 15 11:01:07 AM UTC 24 |
249468914384 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.532332255 |
|
|
Oct 15 11:01:08 AM UTC 24 |
Oct 15 11:01:22 AM UTC 24 |
5431855019 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_noise_filter.1905020160 |
|
|
Oct 15 10:56:36 AM UTC 24 |
Oct 15 11:01:24 AM UTC 24 |
152913808685 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_fifo_reset.535849114 |
|
|
Oct 15 11:01:01 AM UTC 24 |
Oct 15 11:01:26 AM UTC 24 |
34076835945 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.3241560697 |
|
|
Oct 15 11:00:23 AM UTC 24 |
Oct 15 11:01:27 AM UTC 24 |
11088528591 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.1148416575 |
|
|
Oct 15 11:01:25 AM UTC 24 |
Oct 15 11:01:30 AM UTC 24 |
829290583 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_fifo_full.2601691772 |
|
|
Oct 15 11:00:51 AM UTC 24 |
Oct 15 11:01:31 AM UTC 24 |
58587364227 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_rx_oversample.4278357503 |
|
|
Oct 15 11:01:05 AM UTC 24 |
Oct 15 11:01:33 AM UTC 24 |
5263974470 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_intr.1878263551 |
|
|
Oct 15 11:01:06 AM UTC 24 |
Oct 15 11:01:33 AM UTC 24 |
36542793200 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_loopback.663888502 |
|
|
Oct 15 11:01:26 AM UTC 24 |
Oct 15 11:01:33 AM UTC 24 |
1851647537 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_alert_test.1173823404 |
|
|
Oct 15 11:01:34 AM UTC 24 |
Oct 15 11:01:35 AM UTC 24 |
16934507 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_smoke.4134618315 |
|
|
Oct 15 11:01:34 AM UTC 24 |
Oct 15 11:01:36 AM UTC 24 |
486267454 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.782134575 |
|
|
Oct 15 11:01:31 AM UTC 24 |
Oct 15 11:01:56 AM UTC 24 |
6883998722 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_fifo_full.2350126040 |
|
|
Oct 15 11:01:37 AM UTC 24 |
Oct 15 11:01:56 AM UTC 24 |
86036043612 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.684078213 |
|
|
Oct 15 10:58:32 AM UTC 24 |
Oct 15 11:02:02 AM UTC 24 |
199406106708 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_noise_filter.2628002779 |
|
|
Oct 15 11:01:07 AM UTC 24 |
Oct 15 11:02:07 AM UTC 24 |
61165198101 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.3031683377 |
|
|
Oct 15 11:01:23 AM UTC 24 |
Oct 15 11:02:16 AM UTC 24 |
96514511325 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.911106163 |
|
|
Oct 15 11:01:57 AM UTC 24 |
Oct 15 11:02:18 AM UTC 24 |
86125935043 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_rx_oversample.2370620329 |
|
|
Oct 15 11:02:02 AM UTC 24 |
Oct 15 11:02:18 AM UTC 24 |
3603665953 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_stress_all.2628880089 |
|
|
Oct 15 10:29:08 AM UTC 24 |
Oct 15 11:02:20 AM UTC 24 |
197704615245 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.644168006 |
|
|
Oct 15 11:02:18 AM UTC 24 |
Oct 15 11:02:21 AM UTC 24 |
4513729697 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.2255101451 |
|
|
Oct 15 11:02:20 AM UTC 24 |
Oct 15 11:02:24 AM UTC 24 |
506129653 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_loopback.4092753990 |
|
|
Oct 15 11:02:22 AM UTC 24 |
Oct 15 11:02:30 AM UTC 24 |
8750270765 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.2846630021 |
|
|
Oct 15 11:02:19 AM UTC 24 |
Oct 15 11:02:33 AM UTC 24 |
18837441132 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_fifo_reset.537405859 |
|
|
Oct 15 11:01:57 AM UTC 24 |
Oct 15 11:02:36 AM UTC 24 |
52110835632 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_noise_filter.2501665869 |
|
|
Oct 15 11:02:17 AM UTC 24 |
Oct 15 11:02:52 AM UTC 24 |
17073051032 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_alert_test.4089125874 |
|
|
Oct 15 11:02:53 AM UTC 24 |
Oct 15 11:02:55 AM UTC 24 |
23648750 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_fifo_reset.868886045 |
|
|
Oct 15 10:59:06 AM UTC 24 |
Oct 15 11:02:59 AM UTC 24 |
79207140469 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_intr.4005740443 |
|
|
Oct 15 10:59:44 AM UTC 24 |
Oct 15 11:03:00 AM UTC 24 |
145605974253 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.2948027201 |
|
|
Oct 15 10:56:58 AM UTC 24 |
Oct 15 11:03:03 AM UTC 24 |
133872542457 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.807329519 |
|
|
Oct 15 10:53:40 AM UTC 24 |
Oct 15 11:03:10 AM UTC 24 |
106953344146 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_smoke.2032774291 |
|
|
Oct 15 11:02:55 AM UTC 24 |
Oct 15 11:03:16 AM UTC 24 |
5568710468 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_intr.2812412791 |
|
|
Oct 15 11:02:07 AM UTC 24 |
Oct 15 11:03:22 AM UTC 24 |
32422833436 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_rx_oversample.2733674855 |
|
|
Oct 15 11:03:17 AM UTC 24 |
Oct 15 11:03:30 AM UTC 24 |
4252998183 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.2566507547 |
|
|
Oct 15 11:01:00 AM UTC 24 |
Oct 15 11:03:31 AM UTC 24 |
196605368073 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.2534171784 |
|
|
Oct 15 11:03:31 AM UTC 24 |
Oct 15 11:03:37 AM UTC 24 |
4012527803 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_intr.1281311253 |
|
|
Oct 15 11:03:23 AM UTC 24 |
Oct 15 11:03:38 AM UTC 24 |
21152052644 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.3352868493 |
|
|
Oct 15 11:02:34 AM UTC 24 |
Oct 15 11:03:43 AM UTC 24 |
27189617168 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_loopback.630642016 |
|
|
Oct 15 11:03:44 AM UTC 24 |
Oct 15 11:03:47 AM UTC 24 |
1116225358 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.301121854 |
|
|
Oct 15 11:03:04 AM UTC 24 |
Oct 15 11:03:48 AM UTC 24 |
25566766376 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.1935538862 |
|
|
Oct 15 10:51:21 AM UTC 24 |
Oct 15 11:03:55 AM UTC 24 |
112572538637 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_fifo_full.406990483 |
|
|
Oct 15 10:59:02 AM UTC 24 |
Oct 15 11:04:01 AM UTC 24 |
142660839207 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.2073312640 |
|
|
Oct 15 11:03:40 AM UTC 24 |
Oct 15 11:04:05 AM UTC 24 |
6987947391 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_alert_test.961238204 |
|
|
Oct 15 11:04:05 AM UTC 24 |
Oct 15 11:04:07 AM UTC 24 |
13697629 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_perf.78303422 |
|
|
Oct 15 11:01:27 AM UTC 24 |
Oct 15 11:04:16 AM UTC 24 |
9105915229 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_fifo_reset.286272371 |
|
|
Oct 15 11:03:11 AM UTC 24 |
Oct 15 11:04:23 AM UTC 24 |
219238813892 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_tx_rx.3339750894 |
|
|
Oct 15 11:03:00 AM UTC 24 |
Oct 15 11:04:23 AM UTC 24 |
44687817327 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_tx_rx.692248885 |
|
|
Oct 15 11:00:48 AM UTC 24 |
Oct 15 11:04:26 AM UTC 24 |
75448563930 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_smoke.2347755264 |
|
|
Oct 15 11:04:07 AM UTC 24 |
Oct 15 11:04:42 AM UTC 24 |
6048651818 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_tx_rx.694752747 |
|
|
Oct 15 11:01:36 AM UTC 24 |
Oct 15 11:04:44 AM UTC 24 |
269170309852 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_fifo_full.2428726461 |
|
|
Oct 15 11:03:00 AM UTC 24 |
Oct 15 11:04:46 AM UTC 24 |
162888451826 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_fifo_full.2280117040 |
|
|
Oct 15 11:04:23 AM UTC 24 |
Oct 15 11:04:48 AM UTC 24 |
47591918168 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.1269957698 |
|
|
Oct 15 11:04:47 AM UTC 24 |
Oct 15 11:04:53 AM UTC 24 |
5256666150 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.1401409644 |
|
|
Oct 15 11:03:39 AM UTC 24 |
Oct 15 11:04:55 AM UTC 24 |
32932840496 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_alert_test.2773193018 |
|
|
Oct 15 11:04:54 AM UTC 24 |
Oct 15 11:04:56 AM UTC 24 |
34693384 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.2473945769 |
|
|
Oct 15 11:04:23 AM UTC 24 |
Oct 15 11:04:58 AM UTC 24 |
100008883710 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_loopback.1170762311 |
|
|
Oct 15 11:04:51 AM UTC 24 |
Oct 15 11:04:59 AM UTC 24 |
7795867551 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_intr.547738213 |
|
|
Oct 15 11:04:44 AM UTC 24 |
Oct 15 11:05:04 AM UTC 24 |
26185259311 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.2876669249 |
|
|
Oct 15 11:05:02 AM UTC 24 |
Oct 15 11:05:06 AM UTC 24 |
2590179664 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.1586961577 |
|
|
Oct 15 11:05:01 AM UTC 24 |
Oct 15 11:05:06 AM UTC 24 |
4322051226 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_alert_test.185420446 |
|
|
Oct 15 11:05:07 AM UTC 24 |
Oct 15 11:05:08 AM UTC 24 |
17259020 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.2598565305 |
|
|
Oct 15 11:03:56 AM UTC 24 |
Oct 15 11:05:09 AM UTC 24 |
2705553297 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_loopback.3684943372 |
|
|
Oct 15 11:05:03 AM UTC 24 |
Oct 15 11:05:09 AM UTC 24 |
7550310348 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_smoke.2011184041 |
|
|
Oct 15 11:04:54 AM UTC 24 |
Oct 15 11:05:09 AM UTC 24 |
5800775836 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_smoke.2290474366 |
|
|
Oct 15 11:05:07 AM UTC 24 |
Oct 15 11:05:10 AM UTC 24 |
929812602 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.2366465796 |
|
|
Oct 15 11:05:10 AM UTC 24 |
Oct 15 11:05:14 AM UTC 24 |
1431583203 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.3979395413 |
|
|
Oct 15 11:05:10 AM UTC 24 |
Oct 15 11:05:14 AM UTC 24 |
3059805622 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.3504018171 |
|
|
Oct 15 11:04:50 AM UTC 24 |
Oct 15 11:05:14 AM UTC 24 |
14301128680 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_alert_test.3591825163 |
|
|
Oct 15 11:05:15 AM UTC 24 |
Oct 15 11:05:17 AM UTC 24 |
15372281 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_rx_oversample.1976728045 |
|
|
Oct 15 11:04:42 AM UTC 24 |
Oct 15 11:05:17 AM UTC 24 |
4725695066 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_loopback.1562515413 |
|
|
Oct 15 11:05:10 AM UTC 24 |
Oct 15 11:05:17 AM UTC 24 |
4371493493 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_intr.2049641556 |
|
|
Oct 15 11:05:10 AM UTC 24 |
Oct 15 11:05:20 AM UTC 24 |
3922144093 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_smoke.3522216896 |
|
|
Oct 15 11:05:15 AM UTC 24 |
Oct 15 11:05:22 AM UTC 24 |
712312288 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.3042554798 |
|
|
Oct 15 11:05:18 AM UTC 24 |
Oct 15 11:05:22 AM UTC 24 |
2372762263 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_alert_test.2516403604 |
|
|
Oct 15 11:05:22 AM UTC 24 |
Oct 15 11:05:24 AM UTC 24 |
13671362 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.4099964992 |
|
|
Oct 15 11:05:18 AM UTC 24 |
Oct 15 11:05:25 AM UTC 24 |
3446265217 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_intr.3674621017 |
|
|
Oct 15 11:05:16 AM UTC 24 |
Oct 15 11:05:26 AM UTC 24 |
3030628369 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.401542324 |
|
|
Oct 15 11:04:50 AM UTC 24 |
Oct 15 11:05:29 AM UTC 24 |
31143621659 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.1361190319 |
|
|
Oct 15 11:00:15 AM UTC 24 |
Oct 15 11:05:29 AM UTC 24 |
280711846511 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_smoke.1976381123 |
|
|
Oct 15 11:05:24 AM UTC 24 |
Oct 15 11:05:29 AM UTC 24 |
5620946854 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_noise_filter.2218800976 |
|
|
Oct 15 11:03:30 AM UTC 24 |
Oct 15 11:05:32 AM UTC 24 |
52499834044 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_rx_oversample.3569332544 |
|
|
Oct 15 11:04:59 AM UTC 24 |
Oct 15 11:05:32 AM UTC 24 |
6665361784 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.3063257895 |
|
|
Oct 15 11:05:10 AM UTC 24 |
Oct 15 11:05:33 AM UTC 24 |
38214909511 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_fifo_full.79242648 |
|
|
Oct 15 11:04:55 AM UTC 24 |
Oct 15 11:05:35 AM UTC 24 |
74634984215 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_rx_oversample.339128376 |
|
|
Oct 15 11:05:09 AM UTC 24 |
Oct 15 11:05:35 AM UTC 24 |
2754217075 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_noise_filter.2474243405 |
|
|
Oct 15 11:05:10 AM UTC 24 |
Oct 15 11:05:37 AM UTC 24 |
8128925635 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_loopback.2075941122 |
|
|
Oct 15 11:05:36 AM UTC 24 |
Oct 15 11:05:37 AM UTC 24 |
105453140 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_intr.1609986289 |
|
|
Oct 15 11:05:31 AM UTC 24 |
Oct 15 11:05:38 AM UTC 24 |
15763481173 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_fifo_reset.3439972987 |
|
|
Oct 15 11:04:58 AM UTC 24 |
Oct 15 11:05:40 AM UTC 24 |
67892325612 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_fifo_reset.1411219055 |
|
|
Oct 15 11:07:08 AM UTC 24 |
Oct 15 11:07:57 AM UTC 24 |
87588197156 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_loopback.2356354426 |
|
|
Oct 15 11:05:19 AM UTC 24 |
Oct 15 11:05:42 AM UTC 24 |
9729705040 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_alert_test.3734399634 |
|
|
Oct 15 11:05:41 AM UTC 24 |
Oct 15 11:05:43 AM UTC 24 |
42881676 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.3291123639 |
|
|
Oct 15 11:05:12 AM UTC 24 |
Oct 15 11:05:45 AM UTC 24 |
8284779232 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.3486388578 |
|
|
Oct 15 11:04:56 AM UTC 24 |
Oct 15 11:05:46 AM UTC 24 |
15930640661 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_smoke.1579909235 |
|
|
Oct 15 11:05:43 AM UTC 24 |
Oct 15 11:05:47 AM UTC 24 |
263159939 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.762381561 |
|
|
Oct 15 10:54:22 AM UTC 24 |
Oct 15 11:05:50 AM UTC 24 |
117112678195 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_rx_oversample.2031554063 |
|
|
Oct 15 11:05:47 AM UTC 24 |
Oct 15 11:05:53 AM UTC 24 |
6979998345 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_rx_oversample.611782929 |
|
|
Oct 15 11:05:31 AM UTC 24 |
Oct 15 11:05:54 AM UTC 24 |
4526056095 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.3964791820 |
|
|
Oct 15 11:04:54 AM UTC 24 |
Oct 15 11:05:56 AM UTC 24 |
28095675109 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.3094517069 |
|
|
Oct 15 11:05:33 AM UTC 24 |
Oct 15 11:05:56 AM UTC 24 |
6462350013 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_tx_rx.2091408460 |
|
|
Oct 15 11:05:07 AM UTC 24 |
Oct 15 11:05:58 AM UTC 24 |
96615584959 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.4220703959 |
|
|
Oct 15 11:05:55 AM UTC 24 |
Oct 15 11:05:59 AM UTC 24 |
1602099736 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.1972951844 |
|
|
Oct 15 11:05:33 AM UTC 24 |
Oct 15 11:06:00 AM UTC 24 |
36403511827 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_tx_rx.223206755 |
|
|
Oct 15 11:05:15 AM UTC 24 |
Oct 15 11:06:00 AM UTC 24 |
16818264912 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.1957578559 |
|
|
Oct 15 11:05:57 AM UTC 24 |
Oct 15 11:06:00 AM UTC 24 |
1208187987 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_stress_all.807250819 |
|
|
Oct 15 10:58:55 AM UTC 24 |
Oct 15 11:06:05 AM UTC 24 |
187830376122 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_fifo_full.2353999131 |
|
|
Oct 15 11:05:27 AM UTC 24 |
Oct 15 11:06:05 AM UTC 24 |
28210452082 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_tx_rx.2072868105 |
|
|
Oct 15 11:04:16 AM UTC 24 |
Oct 15 11:06:06 AM UTC 24 |
196441417017 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_stress_all.3358641298 |
|
|
Oct 15 11:05:06 AM UTC 24 |
Oct 15 11:06:06 AM UTC 24 |
115841133752 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_fifo_reset.216983987 |
|
|
Oct 15 11:05:09 AM UTC 24 |
Oct 15 11:06:07 AM UTC 24 |
17940142446 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_alert_test.2447386266 |
|
|
Oct 15 11:06:05 AM UTC 24 |
Oct 15 11:06:07 AM UTC 24 |
22027423 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_smoke.1175981447 |
|
|
Oct 15 11:06:06 AM UTC 24 |
Oct 15 11:06:11 AM UTC 24 |
469819231 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_loopback.984454847 |
|
|
Oct 15 11:05:59 AM UTC 24 |
Oct 15 11:06:12 AM UTC 24 |
12685687330 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_rx_oversample.2619316892 |
|
|
Oct 15 11:05:16 AM UTC 24 |
Oct 15 11:06:13 AM UTC 24 |
5675404091 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.396080576 |
|
|
Oct 15 11:05:46 AM UTC 24 |
Oct 15 11:06:15 AM UTC 24 |
35883369067 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.2115597466 |
|
|
Oct 15 11:05:28 AM UTC 24 |
Oct 15 11:06:16 AM UTC 24 |
26353967655 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_tx_rx.1145854499 |
|
|
Oct 15 11:05:27 AM UTC 24 |
Oct 15 11:06:19 AM UTC 24 |
84654461355 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.2406008557 |
|
|
Oct 15 11:05:39 AM UTC 24 |
Oct 15 11:06:20 AM UTC 24 |
19215017505 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.589860263 |
|
|
Oct 15 11:05:15 AM UTC 24 |
Oct 15 11:06:20 AM UTC 24 |
35137520967 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_noise_filter.2728311245 |
|
|
Oct 15 11:05:32 AM UTC 24 |
Oct 15 11:06:20 AM UTC 24 |
19108974674 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.858843893 |
|
|
Oct 15 11:06:16 AM UTC 24 |
Oct 15 11:06:21 AM UTC 24 |
5665213320 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.2527707485 |
|
|
Oct 15 11:05:21 AM UTC 24 |
Oct 15 11:06:21 AM UTC 24 |
14915118260 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_fifo_reset.1714722147 |
|
|
Oct 15 11:04:27 AM UTC 24 |
Oct 15 11:06:22 AM UTC 24 |
57683016950 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_fifo_reset.2437674502 |
|
|
Oct 15 11:06:08 AM UTC 24 |
Oct 15 11:06:23 AM UTC 24 |
12445235999 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_alert_test.3814389029 |
|
|
Oct 15 11:06:22 AM UTC 24 |
Oct 15 11:06:24 AM UTC 24 |
53810705 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.3819799410 |
|
|
Oct 15 11:06:20 AM UTC 24 |
Oct 15 11:06:25 AM UTC 24 |
1109536324 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_loopback.1597760760 |
|
|
Oct 15 11:06:21 AM UTC 24 |
Oct 15 11:06:26 AM UTC 24 |
3979161737 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_smoke.2715971572 |
|
|
Oct 15 11:06:24 AM UTC 24 |
Oct 15 11:06:27 AM UTC 24 |
322948515 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.1934196794 |
|
|
Oct 15 11:06:07 AM UTC 24 |
Oct 15 11:06:30 AM UTC 24 |
22788501011 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_tx_rx.2938769807 |
|
|
Oct 15 11:05:43 AM UTC 24 |
Oct 15 11:06:31 AM UTC 24 |
114162456444 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_intr.650879241 |
|
|
Oct 15 11:06:14 AM UTC 24 |
Oct 15 11:06:34 AM UTC 24 |
36157860672 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_tx_rx.766894327 |
|
|
Oct 15 11:06:25 AM UTC 24 |
Oct 15 11:06:37 AM UTC 24 |
16538942829 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_rx_oversample.153899149 |
|
|
Oct 15 11:06:31 AM UTC 24 |
Oct 15 11:06:40 AM UTC 24 |
3359367248 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.2817073497 |
|
|
Oct 15 11:07:52 AM UTC 24 |
Oct 15 11:07:57 AM UTC 24 |
2162546031 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.1476269682 |
|
|
Oct 15 11:05:57 AM UTC 24 |
Oct 15 11:06:40 AM UTC 24 |
33560929618 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.1892386629 |
|
|
Oct 15 11:06:38 AM UTC 24 |
Oct 15 11:06:42 AM UTC 24 |
2482345256 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_perf.211232944 |
|
|
Oct 15 10:56:51 AM UTC 24 |
Oct 15 11:06:43 AM UTC 24 |
16164307398 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_loopback.3178481261 |
|
|
Oct 15 11:06:43 AM UTC 24 |
Oct 15 11:06:52 AM UTC 24 |
1818826198 ps |