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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1315
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T1251 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.1166672065 Feb 09 07:35:56 AM UTC 25 Feb 09 07:35:58 AM UTC 25 41438765 ps
T1252 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2910438986 Feb 09 07:35:56 AM UTC 25 Feb 09 07:35:59 AM UTC 25 139336246 ps
T1253 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.2475679120 Feb 09 07:35:56 AM UTC 25 Feb 09 07:35:59 AM UTC 25 18065775 ps
T1254 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.2509171869 Feb 09 07:35:56 AM UTC 25 Feb 09 07:35:59 AM UTC 25 556647397 ps
T1255 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.723678719 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:01 AM UTC 25 54411919 ps
T1256 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.315860988 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:02 AM UTC 25 31083806 ps
T1257 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.1659212622 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:02 AM UTC 25 33662720 ps
T1258 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.410269732 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:02 AM UTC 25 13494362 ps
T1259 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.239806376 Feb 09 07:35:59 AM UTC 25 Feb 09 07:36:02 AM UTC 25 28212210 ps
T1260 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2928045316 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:02 AM UTC 25 22814874 ps
T1261 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1023546545 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:02 AM UTC 25 22644497 ps
T1262 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2257827986 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:02 AM UTC 25 12449131 ps
T1263 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.3644456018 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:02 AM UTC 25 42298703 ps
T1264 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.4115512730 Feb 09 07:35:59 AM UTC 25 Feb 09 07:36:02 AM UTC 25 63646014 ps
T1265 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.2264539282 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:02 AM UTC 25 18360249 ps
T1266 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2959964138 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:02 AM UTC 25 109733645 ps
T1267 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.670273991 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:02 AM UTC 25 30812619 ps
T1268 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.4202418196 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:02 AM UTC 25 176788454 ps
T1269 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.2664745339 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:03 AM UTC 25 379771032 ps
T1270 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.406435520 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:03 AM UTC 25 141178592 ps
T1271 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2554129341 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:03 AM UTC 25 121925156 ps
T1272 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.522840251 Feb 09 07:36:01 AM UTC 25 Feb 09 07:36:04 AM UTC 25 28758701 ps
T1273 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.2386632716 Feb 09 07:36:00 AM UTC 25 Feb 09 07:36:04 AM UTC 25 254403995 ps
T1274 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.3608396943 Feb 09 07:36:01 AM UTC 25 Feb 09 07:36:04 AM UTC 25 88525304 ps
T1275 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.2132653517 Feb 09 07:36:04 AM UTC 25 Feb 09 07:36:06 AM UTC 25 12663976 ps
T1276 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.341315665 Feb 09 07:36:04 AM UTC 25 Feb 09 07:36:06 AM UTC 25 10787294 ps
T1277 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.3411973639 Feb 09 07:36:04 AM UTC 25 Feb 09 07:36:06 AM UTC 25 28723354 ps
T1278 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.423376164 Feb 09 07:36:04 AM UTC 25 Feb 09 07:36:06 AM UTC 25 52729563 ps
T1279 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.556533192 Feb 09 07:36:04 AM UTC 25 Feb 09 07:36:06 AM UTC 25 44909247 ps
T1280 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.1623894410 Feb 09 07:36:05 AM UTC 25 Feb 09 07:36:07 AM UTC 25 14566677 ps
T1281 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.1662666372 Feb 09 07:36:05 AM UTC 25 Feb 09 07:36:07 AM UTC 25 12235869 ps
T1282 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2759423896 Feb 09 07:36:05 AM UTC 25 Feb 09 07:36:07 AM UTC 25 14247020 ps
T1283 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.3329035475 Feb 09 07:36:04 AM UTC 25 Feb 09 07:36:07 AM UTC 25 71465271 ps
T1284 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.3000625623 Feb 09 07:36:05 AM UTC 25 Feb 09 07:36:07 AM UTC 25 24131901 ps
T1285 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.1978219630 Feb 09 07:36:05 AM UTC 25 Feb 09 07:36:07 AM UTC 25 77078991 ps
T1286 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2174186123 Feb 09 07:36:04 AM UTC 25 Feb 09 07:36:07 AM UTC 25 36299094 ps
T1287 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3630459646 Feb 09 07:36:04 AM UTC 25 Feb 09 07:36:07 AM UTC 25 30389301 ps
T1288 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.4034023182 Feb 09 07:36:05 AM UTC 25 Feb 09 07:36:07 AM UTC 25 15681746 ps
T1289 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.1201770138 Feb 09 07:36:04 AM UTC 25 Feb 09 07:36:07 AM UTC 25 63681399 ps
T1290 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.3587843932 Feb 09 07:36:04 AM UTC 25 Feb 09 07:36:07 AM UTC 25 89667658 ps
T1291 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.1593945577 Feb 09 07:36:04 AM UTC 25 Feb 09 07:36:08 AM UTC 25 134123232 ps
T1292 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.2321185993 Feb 09 07:36:08 AM UTC 25 Feb 09 07:36:10 AM UTC 25 31372724 ps
T1293 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.1822034110 Feb 09 07:36:08 AM UTC 25 Feb 09 07:36:10 AM UTC 25 45739815 ps
T1294 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.814250608 Feb 09 07:36:08 AM UTC 25 Feb 09 07:36:10 AM UTC 25 54633390 ps
T1295 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.3126177164 Feb 09 07:36:08 AM UTC 25 Feb 09 07:36:10 AM UTC 25 32323315 ps
T1296 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1946862535 Feb 09 07:36:08 AM UTC 25 Feb 09 07:36:10 AM UTC 25 40291551 ps
T1297 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.703266977 Feb 09 07:36:08 AM UTC 25 Feb 09 07:36:10 AM UTC 25 13783005 ps
T1298 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.278550505 Feb 09 07:36:08 AM UTC 25 Feb 09 07:36:10 AM UTC 25 12099651 ps
T1299 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.699893138 Feb 09 07:36:08 AM UTC 25 Feb 09 07:36:10 AM UTC 25 18819669 ps
T1300 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3471431900 Feb 09 07:36:08 AM UTC 25 Feb 09 07:36:10 AM UTC 25 34617043 ps
T1301 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3195477647 Feb 09 07:36:09 AM UTC 25 Feb 09 07:36:10 AM UTC 25 49130370 ps
T1302 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.2927365426 Feb 09 07:36:09 AM UTC 25 Feb 09 07:36:10 AM UTC 25 41726908 ps
T1303 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.1982682413 Feb 09 07:36:08 AM UTC 25 Feb 09 07:36:11 AM UTC 25 20437270 ps
T1304 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1991121068 Feb 09 07:36:09 AM UTC 25 Feb 09 07:36:11 AM UTC 25 38314515 ps
T1305 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.1990080998 Feb 09 07:36:09 AM UTC 25 Feb 09 07:36:11 AM UTC 25 55471837 ps
T1306 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2944020983 Feb 09 07:36:09 AM UTC 25 Feb 09 07:36:11 AM UTC 25 14750810 ps
T1307 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.801696263 Feb 09 07:36:09 AM UTC 25 Feb 09 07:36:11 AM UTC 25 13382403 ps
T1308 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.674471749 Feb 09 07:36:09 AM UTC 25 Feb 09 07:36:11 AM UTC 25 22143776 ps
T1309 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.4136209058 Feb 09 07:36:09 AM UTC 25 Feb 09 07:36:11 AM UTC 25 26205989 ps
T1310 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.327851972 Feb 09 07:36:15 AM UTC 25 Feb 09 07:36:17 AM UTC 25 12153811 ps
T1311 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.223156111 Feb 09 07:36:15 AM UTC 25 Feb 09 07:36:17 AM UTC 25 39131903 ps
T1312 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.608502722 Feb 09 07:36:15 AM UTC 25 Feb 09 07:36:17 AM UTC 25 48851808 ps
T1313 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.2785094656 Feb 09 07:36:15 AM UTC 25 Feb 09 07:36:17 AM UTC 25 53791172 ps
T1314 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.3186625661 Feb 09 07:36:15 AM UTC 25 Feb 09 07:36:17 AM UTC 25 23493382 ps
T1315 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.4176245401 Feb 09 07:36:15 AM UTC 25 Feb 09 07:36:17 AM UTC 25 22217736 ps

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2574184931
Short name T6
Test name
Test status
Simulation time 47742228771 ps
CPU time 29.77 seconds
Started Feb 09 06:35:18 AM UTC 25
Finished Feb 09 06:35:50 AM UTC 25
Peak memory 208248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574184931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 0.uart_fifo_reset.2574184931
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.448868201
Short name T25
Test name
Test status
Simulation time 93095839699 ps
CPU time 379.95 seconds
Started Feb 09 06:36:54 AM UTC 25
Finished Feb 09 06:43:19 AM UTC 25
Peak memory 224276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=448868201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.448868201
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_stress_all.3783925735
Short name T99
Test name
Test status
Simulation time 344648297362 ps
CPU time 193.68 seconds
Started Feb 09 06:35:21 AM UTC 25
Finished Feb 09 06:38:37 AM UTC 25
Peak memory 217296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783925735 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3783925735
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_stress_all.2058547391
Short name T148
Test name
Test status
Simulation time 438519124578 ps
CPU time 306.31 seconds
Started Feb 09 06:36:05 AM UTC 25
Finished Feb 09 06:41:15 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058547391 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2058547391
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.465201681
Short name T36
Test name
Test status
Simulation time 284855543132 ps
CPU time 1195.14 seconds
Started Feb 09 06:35:21 AM UTC 25
Finished Feb 09 06:55:29 AM UTC 25
Peak memory 237396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=465201681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.465201681
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.254657265
Short name T11
Test name
Test status
Simulation time 15217282845 ps
CPU time 33.3 seconds
Started Feb 09 06:35:29 AM UTC 25
Finished Feb 09 06:36:04 AM UTC 25
Peak memory 208460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254657265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_over
flow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.uart_fifo_overflow.254657265
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_stress_all.3562694716
Short name T100
Test name
Test status
Simulation time 358179800129 ps
CPU time 479.41 seconds
Started Feb 09 06:39:43 AM UTC 25
Finished Feb 09 06:47:48 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562694716 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3562694716
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_stress_all.3682204357
Short name T162
Test name
Test status
Simulation time 463501734838 ps
CPU time 262.44 seconds
Started Feb 09 06:47:35 AM UTC 25
Finished Feb 09 06:52:01 AM UTC 25
Peak memory 217352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682204357 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3682204357
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_intr.3223430604
Short name T12
Test name
Test status
Simulation time 46541058205 ps
CPU time 43.58 seconds
Started Feb 09 06:35:19 AM UTC 25
Finished Feb 09 06:36:05 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223430604 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.uart_intr.3223430604
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.2153107038
Short name T319
Test name
Test status
Simulation time 77405213690 ps
CPU time 166.06 seconds
Started Feb 09 06:44:52 AM UTC 25
Finished Feb 09 06:47:41 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153107038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2153107038
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_intr.2030733717
Short name T135
Test name
Test status
Simulation time 51723594486 ps
CPU time 54.13 seconds
Started Feb 09 06:45:18 AM UTC 25
Finished Feb 09 06:46:13 AM UTC 25
Peak memory 208524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030733717 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.uart_intr.2030733717
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_sec_cm.2307386007
Short name T2
Test name
Test status
Simulation time 103025178 ps
CPU time 1.37 seconds
Started Feb 09 06:35:22 AM UTC 25
Finished Feb 09 06:35:24 AM UTC 25
Peak memory 239176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307386007 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2307386007
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_stress_all.3584844235
Short name T161
Test name
Test status
Simulation time 531030927806 ps
CPU time 304.34 seconds
Started Feb 09 06:44:59 AM UTC 25
Finished Feb 09 06:50:07 AM UTC 25
Peak memory 217496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584844235 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3584844235
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.276736063
Short name T323
Test name
Test status
Simulation time 159067991239 ps
CPU time 218.24 seconds
Started Feb 09 06:42:24 AM UTC 25
Finished Feb 09 06:46:05 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276736063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.276736063
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.2371090422
Short name T155
Test name
Test status
Simulation time 143851500954 ps
CPU time 196 seconds
Started Feb 09 06:41:41 AM UTC 25
Finished Feb 09 06:44:59 AM UTC 25
Peak memory 208620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371090422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.uart_fifo_overflow.2371090422
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.3345002499
Short name T37
Test name
Test status
Simulation time 437179404615 ps
CPU time 1195.87 seconds
Started Feb 09 06:36:05 AM UTC 25
Finished Feb 09 06:56:14 AM UTC 25
Peak memory 242560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3345002499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3345002499
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.4016658739
Short name T68
Test name
Test status
Simulation time 263438874080 ps
CPU time 1697.22 seconds
Started Feb 09 06:48:19 AM UTC 25
Finished Feb 09 07:16:55 AM UTC 25
Peak memory 238956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4016658739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.4016658739
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_stress_all.2704123974
Short name T103
Test name
Test status
Simulation time 150492948507 ps
CPU time 785.32 seconds
Started Feb 09 06:37:37 AM UTC 25
Finished Feb 09 06:50:52 AM UTC 25
Peak memory 208424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704123974 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2704123974
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_intr.3599545668
Short name T18
Test name
Test status
Simulation time 51087335738 ps
CPU time 71.67 seconds
Started Feb 09 06:35:51 AM UTC 25
Finished Feb 09 06:37:04 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599545668 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.uart_intr.3599545668
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_fifo_full.4140090697
Short name T287
Test name
Test status
Simulation time 28651147451 ps
CPU time 121.6 seconds
Started Feb 09 06:45:05 AM UTC 25
Finished Feb 09 06:47:09 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140090697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 11.uart_fifo_full.4140090697
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.3029046450
Short name T105
Test name
Test status
Simulation time 87254124 ps
CPU time 1.93 seconds
Started Feb 09 07:35:32 AM UTC 25
Finished Feb 09 07:35:35 AM UTC 25
Peak memory 203008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029046450 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3029046450
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.913404522
Short name T53
Test name
Test status
Simulation time 90829882980 ps
CPU time 150.31 seconds
Started Feb 09 06:35:18 AM UTC 25
Finished Feb 09 06:37:51 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913404522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_over
flow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.uart_fifo_overflow.913404522
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_loopback.2232801781
Short name T404
Test name
Test status
Simulation time 5180829721 ps
CPU time 11.8 seconds
Started Feb 09 06:40:34 AM UTC 25
Finished Feb 09 06:40:47 AM UTC 25
Peak memory 206940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232801781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 6.uart_loopback.2232801781
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.2726832102
Short name T174
Test name
Test status
Simulation time 105146239023 ps
CPU time 51.32 seconds
Started Feb 09 06:38:50 AM UTC 25
Finished Feb 09 06:39:43 AM UTC 25
Peak memory 208148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726832102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.uart_fifo_overflow.2726832102
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_fifo_reset.4265903909
Short name T160
Test name
Test status
Simulation time 40606899670 ps
CPU time 75.97 seconds
Started Feb 09 06:42:53 AM UTC 25
Finished Feb 09 06:44:12 AM UTC 25
Peak memory 208684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265903909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 9.uart_fifo_reset.4265903909
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_noise_filter.3053545251
Short name T306
Test name
Test status
Simulation time 86976638706 ps
CPU time 237.14 seconds
Started Feb 09 06:36:25 AM UTC 25
Finished Feb 09 06:40:26 AM UTC 25
Peak memory 207556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053545251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.uart_noise_filter.3053545251
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_stress_all.4273463060
Short name T407
Test name
Test status
Simulation time 162780512038 ps
CPU time 986.99 seconds
Started Feb 09 06:42:27 AM UTC 25
Finished Feb 09 06:59:05 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273463060 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4273463060
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_alert_test.2284860007
Short name T1
Test name
Test status
Simulation time 47285630 ps
CPU time 0.84 seconds
Started Feb 09 06:35:22 AM UTC 25
Finished Feb 09 06:35:24 AM UTC 25
Peak memory 204252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284860007 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2284860007
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.3682740130
Short name T77
Test name
Test status
Simulation time 14959413 ps
CPU time 0.92 seconds
Started Feb 09 07:35:29 AM UTC 25
Finished Feb 09 07:35:31 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682740130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3682740130
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_fifo_full.776460711
Short name T131
Test name
Test status
Simulation time 173324987743 ps
CPU time 164.01 seconds
Started Feb 09 06:35:27 AM UTC 25
Finished Feb 09 06:38:14 AM UTC 25
Peak memory 208416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776460711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 1.uart_fifo_full.776460711
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.3011883664
Short name T49
Test name
Test status
Simulation time 74053923136 ps
CPU time 430.92 seconds
Started Feb 09 06:36:52 AM UTC 25
Finished Feb 09 06:44:08 AM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011883664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3011883664
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_stress_all.728836701
Short name T138
Test name
Test status
Simulation time 253742122815 ps
CPU time 552.51 seconds
Started Feb 09 06:45:51 AM UTC 25
Finished Feb 09 06:55:10 AM UTC 25
Peak memory 217336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728836701 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.728836701
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.1871714962
Short name T35
Test name
Test status
Simulation time 145575045335 ps
CPU time 1019.56 seconds
Started Feb 09 06:37:35 AM UTC 25
Finished Feb 09 06:54:46 AM UTC 25
Peak memory 239388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1871714962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1871714962
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_noise_filter.537352905
Short name T296
Test name
Test status
Simulation time 152038328787 ps
CPU time 161.76 seconds
Started Feb 09 06:40:25 AM UTC 25
Finished Feb 09 06:43:10 AM UTC 25
Peak memory 208188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537352905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fil
ter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.uart_noise_filter.537352905
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.540934638
Short name T114
Test name
Test status
Simulation time 228787138573 ps
CPU time 976.65 seconds
Started Feb 09 06:48:57 AM UTC 25
Finished Feb 09 07:05:24 AM UTC 25
Peak memory 234040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=540934638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.540934638
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_fifo_full.723615982
Short name T151
Test name
Test status
Simulation time 32302165710 ps
CPU time 49.37 seconds
Started Feb 09 06:38:47 AM UTC 25
Finished Feb 09 06:39:38 AM UTC 25
Peak memory 208444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723615982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 5.uart_fifo_full.723615982
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_noise_filter.2166444328
Short name T332
Test name
Test status
Simulation time 108215350020 ps
CPU time 63 seconds
Started Feb 09 06:47:49 AM UTC 25
Finished Feb 09 06:48:54 AM UTC 25
Peak memory 208572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166444328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 13.uart_noise_filter.2166444328
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_fifo_reset.2647581758
Short name T16
Test name
Test status
Simulation time 36230990174 ps
CPU time 41.5 seconds
Started Feb 09 06:35:30 AM UTC 25
Finished Feb 09 06:36:14 AM UTC 25
Peak memory 208496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647581758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 1.uart_fifo_reset.2647581758
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_tx_rx.2218535269
Short name T285
Test name
Test status
Simulation time 84357123942 ps
CPU time 290.77 seconds
Started Feb 09 06:39:49 AM UTC 25
Finished Feb 09 06:44:44 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218535269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.uart_tx_rx.2218535269
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_tx_rx.2024540246
Short name T29
Test name
Test status
Simulation time 136257773179 ps
CPU time 97.83 seconds
Started Feb 09 06:35:25 AM UTC 25
Finished Feb 09 06:37:05 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024540246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.uart_tx_rx.2024540246
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.2846993520
Short name T259
Test name
Test status
Simulation time 316843889035 ps
CPU time 724.07 seconds
Started Feb 09 07:25:01 AM UTC 25
Finished Feb 09 07:37:13 AM UTC 25
Peak memory 231908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2846993520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2846993520
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/96.uart_fifo_reset.82145565
Short name T191
Test name
Test status
Simulation time 61711184043 ps
CPU time 92.75 seconds
Started Feb 09 07:25:35 AM UTC 25
Finished Feb 09 07:27:10 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82145565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 96.uart_fifo_reset.82145565
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/96.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.1921072573
Short name T339
Test name
Test status
Simulation time 160306393089 ps
CPU time 411.52 seconds
Started Feb 09 06:44:12 AM UTC 25
Finished Feb 09 06:51:09 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921072573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.uart_fifo_overflow.1921072573
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_fifo_reset.4114183268
Short name T211
Test name
Test status
Simulation time 98106074081 ps
CPU time 145.11 seconds
Started Feb 09 06:58:59 AM UTC 25
Finished Feb 09 07:01:26 AM UTC 25
Peak memory 208496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114183268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 24.uart_fifo_reset.4114183268
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_fifo_reset.551600702
Short name T182
Test name
Test status
Simulation time 162935847752 ps
CPU time 93.79 seconds
Started Feb 09 07:01:41 AM UTC 25
Finished Feb 09 07:03:17 AM UTC 25
Peak memory 208300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551600702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 27.uart_fifo_reset.551600702
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_fifo_reset.3465510017
Short name T220
Test name
Test status
Simulation time 72683225619 ps
CPU time 232.05 seconds
Started Feb 09 07:15:47 AM UTC 25
Finished Feb 09 07:19:42 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465510017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 46.uart_fifo_reset.3465510017
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.2312868866
Short name T38
Test name
Test status
Simulation time 744465573640 ps
CPU time 697.8 seconds
Started Feb 09 06:44:53 AM UTC 25
Finished Feb 09 06:56:38 AM UTC 25
Peak memory 235436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2312868866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2312868866
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_noise_filter.1393552820
Short name T322
Test name
Test status
Simulation time 169263283865 ps
CPU time 189.12 seconds
Started Feb 09 06:42:09 AM UTC 25
Finished Feb 09 06:45:21 AM UTC 25
Peak memory 207356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393552820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.uart_noise_filter.1393552820
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/164.uart_fifo_reset.3558832618
Short name T229
Test name
Test status
Simulation time 27814108524 ps
CPU time 57.32 seconds
Started Feb 09 07:30:20 AM UTC 25
Finished Feb 09 07:31:19 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558832618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 164.uart_fifo_reset.3558832618
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/164.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/166.uart_fifo_reset.3476646592
Short name T266
Test name
Test status
Simulation time 244196774896 ps
CPU time 504.43 seconds
Started Feb 09 07:30:26 AM UTC 25
Finished Feb 09 07:38:56 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476646592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 166.uart_fifo_reset.3476646592
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/166.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.3611738823
Short name T165
Test name
Test status
Simulation time 130052320846 ps
CPU time 465.74 seconds
Started Feb 09 06:55:50 AM UTC 25
Finished Feb 09 07:03:42 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611738823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.uart_rx_parity_err.3611738823
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/57.uart_fifo_reset.2362932332
Short name T233
Test name
Test status
Simulation time 228950415070 ps
CPU time 94.38 seconds
Started Feb 09 07:19:32 AM UTC 25
Finished Feb 09 07:21:09 AM UTC 25
Peak memory 208528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362932332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 57.uart_fifo_reset.2362932332
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/57.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/65.uart_fifo_reset.3476929287
Short name T244
Test name
Test status
Simulation time 124949382104 ps
CPU time 62.73 seconds
Started Feb 09 07:20:23 AM UTC 25
Finished Feb 09 07:21:28 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476929287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 65.uart_fifo_reset.3476929287
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/65.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.2974403774
Short name T110
Test name
Test status
Simulation time 251004313 ps
CPU time 1.9 seconds
Started Feb 09 07:35:40 AM UTC 25
Finished Feb 09 07:35:43 AM UTC 25
Peak memory 203008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974403774 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2974403774
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_tx_rx.1977096511
Short name T310
Test name
Test status
Simulation time 55965298683 ps
CPU time 130.64 seconds
Started Feb 09 06:44:07 AM UTC 25
Finished Feb 09 06:46:20 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977096511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.uart_tx_rx.1977096511
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_fifo_reset.798012332
Short name T200
Test name
Test status
Simulation time 88633886548 ps
CPU time 207.37 seconds
Started Feb 09 06:45:08 AM UTC 25
Finished Feb 09 06:48:39 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798012332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 11.uart_fifo_reset.798012332
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/116.uart_fifo_reset.2771655849
Short name T224
Test name
Test status
Simulation time 131510105169 ps
CPU time 109.36 seconds
Started Feb 09 07:27:19 AM UTC 25
Finished Feb 09 07:29:10 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771655849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 116.uart_fifo_reset.2771655849
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/116.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_fifo_reset.1471184525
Short name T235
Test name
Test status
Simulation time 15683546384 ps
CPU time 30.15 seconds
Started Feb 09 06:48:24 AM UTC 25
Finished Feb 09 06:48:56 AM UTC 25
Peak memory 208448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471184525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 14.uart_fifo_reset.1471184525
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/148.uart_fifo_reset.359779513
Short name T270
Test name
Test status
Simulation time 70985320919 ps
CPU time 158.62 seconds
Started Feb 09 07:29:33 AM UTC 25
Finished Feb 09 07:32:15 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359779513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 148.uart_fifo_reset.359779513
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/148.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.2936592675
Short name T383
Test name
Test status
Simulation time 52832953431 ps
CPU time 63.51 seconds
Started Feb 09 06:50:38 AM UTC 25
Finished Feb 09 06:51:43 AM UTC 25
Peak memory 208584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936592675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.uart_fifo_overflow.2936592675
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/162.uart_fifo_reset.593545758
Short name T263
Test name
Test status
Simulation time 91379966335 ps
CPU time 48.97 seconds
Started Feb 09 07:30:18 AM UTC 25
Finished Feb 09 07:31:09 AM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593545758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 162.uart_fifo_reset.593545758
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/162.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/285.uart_fifo_reset.1827174361
Short name T265
Test name
Test status
Simulation time 62585986990 ps
CPU time 43.94 seconds
Started Feb 09 07:34:58 AM UTC 25
Finished Feb 09 07:35:43 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827174361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 285.uart_fifo_reset.1827174361
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/285.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.1907258992
Short name T59
Test name
Test status
Simulation time 83888884831 ps
CPU time 275.68 seconds
Started Feb 09 07:05:16 AM UTC 25
Finished Feb 09 07:09:56 AM UTC 25
Peak memory 223660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1907258992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1907258992
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.2133333969
Short name T933
Test name
Test status
Simulation time 66186600201 ps
CPU time 623.17 seconds
Started Feb 09 07:11:11 AM UTC 25
Finished Feb 09 07:21:41 AM UTC 25
Peak memory 221528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2133333969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2133333969
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/73.uart_fifo_reset.448382939
Short name T954
Test name
Test status
Simulation time 85454474019 ps
CPU time 157.34 seconds
Started Feb 09 07:21:29 AM UTC 25
Finished Feb 09 07:24:09 AM UTC 25
Peak memory 208580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448382939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 73.uart_fifo_reset.448382939
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/73.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_loopback.957613390
Short name T10
Test name
Test status
Simulation time 5634697187 ps
CPU time 34.57 seconds
Started Feb 09 06:35:21 AM UTC 25
Finished Feb 09 06:35:57 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957613390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.uart_loopback.957613390
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_fifo_reset.942055303
Short name T205
Test name
Test status
Simulation time 182187050441 ps
CPU time 326.24 seconds
Started Feb 09 06:44:12 AM UTC 25
Finished Feb 09 06:49:43 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942055303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 10.uart_fifo_reset.942055303
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/100.uart_fifo_reset.4153218526
Short name T231
Test name
Test status
Simulation time 14176266458 ps
CPU time 15.9 seconds
Started Feb 09 07:26:12 AM UTC 25
Finished Feb 09 07:26:29 AM UTC 25
Peak memory 208580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153218526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 100.uart_fifo_reset.4153218526
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/100.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/111.uart_fifo_reset.4210932681
Short name T247
Test name
Test status
Simulation time 142904837382 ps
CPU time 139.64 seconds
Started Feb 09 07:27:11 AM UTC 25
Finished Feb 09 07:29:33 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210932681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 111.uart_fifo_reset.4210932681
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/111.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/115.uart_fifo_reset.1299278367
Short name T238
Test name
Test status
Simulation time 18521546947 ps
CPU time 44.33 seconds
Started Feb 09 07:27:19 AM UTC 25
Finished Feb 09 07:28:05 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299278367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 115.uart_fifo_reset.1299278367
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/115.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/118.uart_fifo_reset.3344670421
Short name T248
Test name
Test status
Simulation time 31809088487 ps
CPU time 66.54 seconds
Started Feb 09 07:27:41 AM UTC 25
Finished Feb 09 07:28:50 AM UTC 25
Peak memory 208172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344670421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 118.uart_fifo_reset.3344670421
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/118.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_fifo_full.1571093734
Short name T336
Test name
Test status
Simulation time 74939746013 ps
CPU time 129.78 seconds
Started Feb 09 06:48:23 AM UTC 25
Finished Feb 09 06:50:35 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571093734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 14.uart_fifo_full.1571093734
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_intr.2731794425
Short name T136
Test name
Test status
Simulation time 36737626981 ps
CPU time 146.86 seconds
Started Feb 09 06:48:26 AM UTC 25
Finished Feb 09 06:50:56 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731794425 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.uart_intr.2731794425
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/141.uart_fifo_reset.3715709987
Short name T279
Test name
Test status
Simulation time 83858251687 ps
CPU time 166.55 seconds
Started Feb 09 07:29:17 AM UTC 25
Finished Feb 09 07:32:06 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715709987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 141.uart_fifo_reset.3715709987
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/141.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/143.uart_fifo_reset.354529783
Short name T241
Test name
Test status
Simulation time 40298049856 ps
CPU time 32.75 seconds
Started Feb 09 07:29:23 AM UTC 25
Finished Feb 09 07:29:57 AM UTC 25
Peak memory 208324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354529783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 143.uart_fifo_reset.354529783
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/143.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_noise_filter.1925476754
Short name T419
Test name
Test status
Simulation time 111832431635 ps
CPU time 74.57 seconds
Started Feb 09 06:49:49 AM UTC 25
Finished Feb 09 06:51:05 AM UTC 25
Peak memory 217356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925476754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 15.uart_noise_filter.1925476754
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_fifo_reset.1688704177
Short name T120
Test name
Test status
Simulation time 113493399790 ps
CPU time 140.22 seconds
Started Feb 09 06:51:22 AM UTC 25
Finished Feb 09 06:53:45 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688704177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 17.uart_fifo_reset.1688704177
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/186.uart_fifo_reset.955116584
Short name T261
Test name
Test status
Simulation time 132552997120 ps
CPU time 88.45 seconds
Started Feb 09 07:31:22 AM UTC 25
Finished Feb 09 07:32:53 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955116584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 186.uart_fifo_reset.955116584
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/186.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/214.uart_fifo_reset.1830342725
Short name T264
Test name
Test status
Simulation time 18121233235 ps
CPU time 34.52 seconds
Started Feb 09 07:32:30 AM UTC 25
Finished Feb 09 07:33:06 AM UTC 25
Peak memory 208424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830342725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 214.uart_fifo_reset.1830342725
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/214.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/231.uart_fifo_reset.1498752483
Short name T267
Test name
Test status
Simulation time 100363328495 ps
CPU time 48.74 seconds
Started Feb 09 07:33:14 AM UTC 25
Finished Feb 09 07:34:05 AM UTC 25
Peak memory 208296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498752483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 231.uart_fifo_reset.1498752483
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/231.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/234.uart_fifo_reset.116790189
Short name T280
Test name
Test status
Simulation time 90689687907 ps
CPU time 221.53 seconds
Started Feb 09 07:33:17 AM UTC 25
Finished Feb 09 07:37:02 AM UTC 25
Peak memory 208684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116790189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 234.uart_fifo_reset.116790189
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/234.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_fifo_reset.2394804882
Short name T271
Test name
Test status
Simulation time 274472803608 ps
CPU time 238.76 seconds
Started Feb 09 07:06:32 AM UTC 25
Finished Feb 09 07:10:34 AM UTC 25
Peak memory 208440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394804882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 33.uart_fifo_reset.2394804882
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.651995232
Short name T1183
Test name
Test status
Simulation time 79929054 ps
CPU time 1.01 seconds
Started Feb 09 07:35:30 AM UTC 25
Finished Feb 09 07:35:32 AM UTC 25
Peak memory 201916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651995232 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.651995232
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.434696277
Short name T1184
Test name
Test status
Simulation time 445789335 ps
CPU time 2.3 seconds
Started Feb 09 07:35:29 AM UTC 25
Finished Feb 09 07:35:33 AM UTC 25
Peak memory 204312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434696277 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.434696277
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.1392127817
Short name T1182
Test name
Test status
Simulation time 16373291 ps
CPU time 0.84 seconds
Started Feb 09 07:35:28 AM UTC 25
Finished Feb 09 07:35:30 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392127817 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1392127817
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2778293449
Short name T1185
Test name
Test status
Simulation time 28340533 ps
CPU time 1.95 seconds
Started Feb 09 07:35:31 AM UTC 25
Finished Feb 09 07:35:34 AM UTC 25
Peak memory 205072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277829344
9 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2778293449
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.1358196796
Short name T1181
Test name
Test status
Simulation time 55095371 ps
CPU time 0.86 seconds
Started Feb 09 07:35:27 AM UTC 25
Finished Feb 09 07:35:29 AM UTC 25
Peak memory 202948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358196796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1358196796
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3809620522
Short name T90
Test name
Test status
Simulation time 124916095 ps
CPU time 1.19 seconds
Started Feb 09 07:35:30 AM UTC 25
Finished Feb 09 07:35:32 AM UTC 25
Peak memory 202784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809620522 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.3809620522
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2088037488
Short name T1180
Test name
Test status
Simulation time 295813993 ps
CPU time 3.27 seconds
Started Feb 09 07:35:21 AM UTC 25
Finished Feb 09 07:35:25 AM UTC 25
Peak memory 206416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088037488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2088037488
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.3686660520
Short name T104
Test name
Test status
Simulation time 138702659 ps
CPU time 1.98 seconds
Started Feb 09 07:35:26 AM UTC 25
Finished Feb 09 07:35:29 AM UTC 25
Peak memory 203012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686660520 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3686660520
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.806699457
Short name T88
Test name
Test status
Simulation time 47580222 ps
CPU time 1.15 seconds
Started Feb 09 07:35:36 AM UTC 25
Finished Feb 09 07:35:38 AM UTC 25
Peak memory 202820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806699457 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.806699457
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.4045979972
Short name T1191
Test name
Test status
Simulation time 1746620934 ps
CPU time 3.74 seconds
Started Feb 09 07:35:36 AM UTC 25
Finished Feb 09 07:35:41 AM UTC 25
Peak memory 204096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045979972 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.4045979972
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3698094083
Short name T87
Test name
Test status
Simulation time 45882990 ps
CPU time 0.9 seconds
Started Feb 09 07:35:33 AM UTC 25
Finished Feb 09 07:35:35 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698094083 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3698094083
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2768348818
Short name T1189
Test name
Test status
Simulation time 234785233 ps
CPU time 1.1 seconds
Started Feb 09 07:35:37 AM UTC 25
Finished Feb 09 07:35:39 AM UTC 25
Peak memory 202884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276834881
8 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2768348818
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.1191106604
Short name T78
Test name
Test status
Simulation time 16793628 ps
CPU time 0.92 seconds
Started Feb 09 07:35:33 AM UTC 25
Finished Feb 09 07:35:36 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191106604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1191106604
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.3569326131
Short name T1186
Test name
Test status
Simulation time 45526097 ps
CPU time 0.84 seconds
Started Feb 09 07:35:33 AM UTC 25
Finished Feb 09 07:35:35 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569326131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3569326131
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.2502096782
Short name T91
Test name
Test status
Simulation time 15272064 ps
CPU time 0.96 seconds
Started Feb 09 07:35:36 AM UTC 25
Finished Feb 09 07:35:38 AM UTC 25
Peak memory 203016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502096782 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.2502096782
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1888694860
Short name T1187
Test name
Test status
Simulation time 50763413 ps
CPU time 3.57 seconds
Started Feb 09 07:35:31 AM UTC 25
Finished Feb 09 07:35:36 AM UTC 25
Peak memory 206356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888694860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1888694860
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4003176442
Short name T1239
Test name
Test status
Simulation time 85412892 ps
CPU time 1.32 seconds
Started Feb 09 07:35:52 AM UTC 25
Finished Feb 09 07:35:54 AM UTC 25
Peak memory 203020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400317644
2 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.4003176442
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.3291326040
Short name T1228
Test name
Test status
Simulation time 14132113 ps
CPU time 0.75 seconds
Started Feb 09 07:35:50 AM UTC 25
Finished Feb 09 07:35:52 AM UTC 25
Peak memory 202916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291326040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3291326040
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.356446922
Short name T1227
Test name
Test status
Simulation time 20263289 ps
CPU time 0.76 seconds
Started Feb 09 07:35:50 AM UTC 25
Finished Feb 09 07:35:52 AM UTC 25
Peak memory 202868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356446922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.356446922
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.2795671033
Short name T1236
Test name
Test status
Simulation time 115797665 ps
CPU time 1.07 seconds
Started Feb 09 07:35:52 AM UTC 25
Finished Feb 09 07:35:54 AM UTC 25
Peak memory 203016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795671033 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.2795671033
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.2351209030
Short name T1233
Test name
Test status
Simulation time 45626569 ps
CPU time 2.1 seconds
Started Feb 09 07:35:50 AM UTC 25
Finished Feb 09 07:35:53 AM UTC 25
Peak memory 206684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351209030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2351209030
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.3686218218
Short name T1231
Test name
Test status
Simulation time 155495924 ps
CPU time 1.35 seconds
Started Feb 09 07:35:50 AM UTC 25
Finished Feb 09 07:35:53 AM UTC 25
Peak memory 203016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686218218 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3686218218
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2725828
Short name T1240
Test name
Test status
Simulation time 20396045 ps
CPU time 1.13 seconds
Started Feb 09 07:35:54 AM UTC 25
Finished Feb 09 07:35:56 AM UTC 25
Peak memory 203024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725828 -
assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2725828
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.2833816551
Short name T1234
Test name
Test status
Simulation time 26453703 ps
CPU time 0.72 seconds
Started Feb 09 07:35:52 AM UTC 25
Finished Feb 09 07:35:54 AM UTC 25
Peak memory 202948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833816551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2833816551
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.391743141
Short name T1235
Test name
Test status
Simulation time 27174526 ps
CPU time 0.86 seconds
Started Feb 09 07:35:52 AM UTC 25
Finished Feb 09 07:35:54 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391743141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.391743141
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.701831732
Short name T1237
Test name
Test status
Simulation time 46287491 ps
CPU time 0.92 seconds
Started Feb 09 07:35:52 AM UTC 25
Finished Feb 09 07:35:54 AM UTC 25
Peak memory 203084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701831732 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.701831732
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3213425968
Short name T1238
Test name
Test status
Simulation time 36063035 ps
CPU time 2.41 seconds
Started Feb 09 07:35:52 AM UTC 25
Finished Feb 09 07:35:56 AM UTC 25
Peak memory 204380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213425968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3213425968
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.679374597
Short name T109
Test name
Test status
Simulation time 487114968 ps
CPU time 1.46 seconds
Started Feb 09 07:35:52 AM UTC 25
Finished Feb 09 07:35:55 AM UTC 25
Peak memory 203008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679374597 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.679374597
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.4066338993
Short name T1244
Test name
Test status
Simulation time 49835894 ps
CPU time 0.95 seconds
Started Feb 09 07:35:54 AM UTC 25
Finished Feb 09 07:35:56 AM UTC 25
Peak memory 202900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406633899
3 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.4066338993
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.545646214
Short name T86
Test name
Test status
Simulation time 143308486 ps
CPU time 0.85 seconds
Started Feb 09 07:35:54 AM UTC 25
Finished Feb 09 07:35:56 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545646214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM
_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.545646214
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.1885514829
Short name T1216
Test name
Test status
Simulation time 14065776 ps
CPU time 0.75 seconds
Started Feb 09 07:35:54 AM UTC 25
Finished Feb 09 07:35:56 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885514829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1885514829
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.929756013
Short name T1241
Test name
Test status
Simulation time 114142681 ps
CPU time 0.87 seconds
Started Feb 09 07:35:54 AM UTC 25
Finished Feb 09 07:35:56 AM UTC 25
Peak memory 203092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929756013 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.929756013
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.290078415
Short name T1242
Test name
Test status
Simulation time 83713089 ps
CPU time 1.24 seconds
Started Feb 09 07:35:54 AM UTC 25
Finished Feb 09 07:35:56 AM UTC 25
Peak memory 203020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290078415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.290078415
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.1740230293
Short name T141
Test name
Test status
Simulation time 76784276 ps
CPU time 1.37 seconds
Started Feb 09 07:35:54 AM UTC 25
Finished Feb 09 07:35:57 AM UTC 25
Peak memory 203012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740230293 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1740230293
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1795610031
Short name T1250
Test name
Test status
Simulation time 17567038 ps
CPU time 0.98 seconds
Started Feb 09 07:35:56 AM UTC 25
Finished Feb 09 07:35:58 AM UTC 25
Peak memory 203020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179561003
1 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1795610031
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.2136816420
Short name T1247
Test name
Test status
Simulation time 27218002 ps
CPU time 0.8 seconds
Started Feb 09 07:35:56 AM UTC 25
Finished Feb 09 07:35:58 AM UTC 25
Peak memory 202948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136816420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2136816420
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.2223675276
Short name T1243
Test name
Test status
Simulation time 14806153 ps
CPU time 0.87 seconds
Started Feb 09 07:35:54 AM UTC 25
Finished Feb 09 07:35:56 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223675276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2223675276
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2910438986
Short name T1252
Test name
Test status
Simulation time 139336246 ps
CPU time 1.13 seconds
Started Feb 09 07:35:56 AM UTC 25
Finished Feb 09 07:35:59 AM UTC 25
Peak memory 203016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910438986 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.2910438986
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.3911406026
Short name T1246
Test name
Test status
Simulation time 104301664 ps
CPU time 2.2 seconds
Started Feb 09 07:35:54 AM UTC 25
Finished Feb 09 07:35:58 AM UTC 25
Peak memory 204636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911406026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3911406026
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.1925686549
Short name T1245
Test name
Test status
Simulation time 89583720 ps
CPU time 1.33 seconds
Started Feb 09 07:35:54 AM UTC 25
Finished Feb 09 07:35:57 AM UTC 25
Peak memory 203012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925686549 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1925686549
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.239806376
Short name T1259
Test name
Test status
Simulation time 28212210 ps
CPU time 1.15 seconds
Started Feb 09 07:35:59 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 202640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239806376
-assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.239806376
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.2475679120
Short name T1253
Test name
Test status
Simulation time 18065775 ps
CPU time 0.88 seconds
Started Feb 09 07:35:56 AM UTC 25
Finished Feb 09 07:35:59 AM UTC 25
Peak memory 202948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475679120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2475679120
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.749761444
Short name T1249
Test name
Test status
Simulation time 92971664 ps
CPU time 0.79 seconds
Started Feb 09 07:35:56 AM UTC 25
Finished Feb 09 07:35:58 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749761444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.749761444
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.4026509253
Short name T1248
Test name
Test status
Simulation time 29039832 ps
CPU time 0.66 seconds
Started Feb 09 07:35:56 AM UTC 25
Finished Feb 09 07:35:58 AM UTC 25
Peak memory 203016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026509253 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.4026509253
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.2509171869
Short name T1254
Test name
Test status
Simulation time 556647397 ps
CPU time 1.48 seconds
Started Feb 09 07:35:56 AM UTC 25
Finished Feb 09 07:35:59 AM UTC 25
Peak memory 203016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509171869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2509171869
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.1166672065
Short name T1251
Test name
Test status
Simulation time 41438765 ps
CPU time 0.93 seconds
Started Feb 09 07:35:56 AM UTC 25
Finished Feb 09 07:35:58 AM UTC 25
Peak memory 203016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166672065 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1166672065
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2959964138
Short name T1266
Test name
Test status
Simulation time 109733645 ps
CPU time 1.4 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 203020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295996413
8 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2959964138
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.315860988
Short name T1256
Test name
Test status
Simulation time 31083806 ps
CPU time 0.73 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315860988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM
_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.315860988
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.723678719
Short name T1255
Test name
Test status
Simulation time 54411919 ps
CPU time 0.66 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:01 AM UTC 25
Peak memory 202636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723678719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.723678719
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2928045316
Short name T1260
Test name
Test status
Simulation time 22814874 ps
CPU time 0.94 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 202880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928045316 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.2928045316
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.4115512730
Short name T1264
Test name
Test status
Simulation time 63646014 ps
CPU time 1.39 seconds
Started Feb 09 07:35:59 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 203016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115512730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.4115512730
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.2664745339
Short name T1269
Test name
Test status
Simulation time 379771032 ps
CPU time 1.97 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:03 AM UTC 25
Peak memory 202960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664745339 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2664745339
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1023546545
Short name T1261
Test name
Test status
Simulation time 22644497 ps
CPU time 0.82 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 203020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102354654
5 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1023546545
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.410269732
Short name T1258
Test name
Test status
Simulation time 13494362 ps
CPU time 0.69 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410269732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM
_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.410269732
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.1659212622
Short name T1257
Test name
Test status
Simulation time 33662720 ps
CPU time 0.75 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 202904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659212622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1659212622
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.2264539282
Short name T1265
Test name
Test status
Simulation time 18360249 ps
CPU time 1.11 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 203092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264539282 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.2264539282
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2554129341
Short name T1271
Test name
Test status
Simulation time 121925156 ps
CPU time 2.02 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:03 AM UTC 25
Peak memory 204636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554129341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2554129341
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.406435520
Short name T1270
Test name
Test status
Simulation time 141178592 ps
CPU time 1.72 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:03 AM UTC 25
Peak memory 203008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406435520 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.406435520
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.522840251
Short name T1272
Test name
Test status
Simulation time 28758701 ps
CPU time 1.17 seconds
Started Feb 09 07:36:01 AM UTC 25
Finished Feb 09 07:36:04 AM UTC 25
Peak memory 203024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522840251
-assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.522840251
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2257827986
Short name T1262
Test name
Test status
Simulation time 12449131 ps
CPU time 0.66 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 202948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257827986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2257827986
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.3644456018
Short name T1263
Test name
Test status
Simulation time 42298703 ps
CPU time 0.79 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644456018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3644456018
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.670273991
Short name T1267
Test name
Test status
Simulation time 30812619 ps
CPU time 1 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 203092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670273991 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.670273991
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.2386632716
Short name T1273
Test name
Test status
Simulation time 254403995 ps
CPU time 2.49 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:04 AM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386632716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2386632716
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.4202418196
Short name T1268
Test name
Test status
Simulation time 176788454 ps
CPU time 1.3 seconds
Started Feb 09 07:36:00 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 203012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202418196 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.4202418196
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3630459646
Short name T1287
Test name
Test status
Simulation time 30389301 ps
CPU time 1.19 seconds
Started Feb 09 07:36:04 AM UTC 25
Finished Feb 09 07:36:07 AM UTC 25
Peak memory 203020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363045964
6 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3630459646
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.2132653517
Short name T1275
Test name
Test status
Simulation time 12663976 ps
CPU time 0.65 seconds
Started Feb 09 07:36:04 AM UTC 25
Finished Feb 09 07:36:06 AM UTC 25
Peak memory 202948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132653517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2132653517
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.341315665
Short name T1276
Test name
Test status
Simulation time 10787294 ps
CPU time 0.68 seconds
Started Feb 09 07:36:04 AM UTC 25
Finished Feb 09 07:36:06 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341315665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.341315665
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.3411973639
Short name T1277
Test name
Test status
Simulation time 28723354 ps
CPU time 0.73 seconds
Started Feb 09 07:36:04 AM UTC 25
Finished Feb 09 07:36:06 AM UTC 25
Peak memory 203092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411973639 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.3411973639
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.3608396943
Short name T1274
Test name
Test status
Simulation time 88525304 ps
CPU time 1.75 seconds
Started Feb 09 07:36:01 AM UTC 25
Finished Feb 09 07:36:04 AM UTC 25
Peak memory 203016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608396943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3608396943
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.3587843932
Short name T1290
Test name
Test status
Simulation time 89667658 ps
CPU time 1.58 seconds
Started Feb 09 07:36:04 AM UTC 25
Finished Feb 09 07:36:07 AM UTC 25
Peak memory 203012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587843932 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3587843932
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2174186123
Short name T1286
Test name
Test status
Simulation time 36299094 ps
CPU time 1.05 seconds
Started Feb 09 07:36:04 AM UTC 25
Finished Feb 09 07:36:07 AM UTC 25
Peak memory 203020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217418612
3 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2174186123
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.423376164
Short name T1278
Test name
Test status
Simulation time 52729563 ps
CPU time 0.71 seconds
Started Feb 09 07:36:04 AM UTC 25
Finished Feb 09 07:36:06 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423376164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM
_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.423376164
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.556533192
Short name T1279
Test name
Test status
Simulation time 44909247 ps
CPU time 0.79 seconds
Started Feb 09 07:36:04 AM UTC 25
Finished Feb 09 07:36:06 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556533192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.556533192
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.3329035475
Short name T1283
Test name
Test status
Simulation time 71465271 ps
CPU time 0.87 seconds
Started Feb 09 07:36:04 AM UTC 25
Finished Feb 09 07:36:07 AM UTC 25
Peak memory 203092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329035475 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.3329035475
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.1593945577
Short name T1291
Test name
Test status
Simulation time 134123232 ps
CPU time 2.14 seconds
Started Feb 09 07:36:04 AM UTC 25
Finished Feb 09 07:36:08 AM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593945577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1593945577
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.1201770138
Short name T1289
Test name
Test status
Simulation time 63681399 ps
CPU time 1.17 seconds
Started Feb 09 07:36:04 AM UTC 25
Finished Feb 09 07:36:07 AM UTC 25
Peak memory 203012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201770138 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1201770138
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.2955149507
Short name T80
Test name
Test status
Simulation time 21383804 ps
CPU time 1.01 seconds
Started Feb 09 07:35:38 AM UTC 25
Finished Feb 09 07:35:40 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955149507 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2955149507
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.1090986231
Short name T82
Test name
Test status
Simulation time 265061514 ps
CPU time 3.88 seconds
Started Feb 09 07:35:38 AM UTC 25
Finished Feb 09 07:35:43 AM UTC 25
Peak memory 204252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090986231 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1090986231
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.2210785393
Short name T79
Test name
Test status
Simulation time 48659689 ps
CPU time 0.89 seconds
Started Feb 09 07:35:37 AM UTC 25
Finished Feb 09 07:35:39 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210785393 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2210785393
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.259197650
Short name T1192
Test name
Test status
Simulation time 118531880 ps
CPU time 1.13 seconds
Started Feb 09 07:35:38 AM UTC 25
Finished Feb 09 07:35:41 AM UTC 25
Peak memory 203024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259197650
-assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.259197650
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.2716433503
Short name T92
Test name
Test status
Simulation time 74806969 ps
CPU time 0.93 seconds
Started Feb 09 07:35:38 AM UTC 25
Finished Feb 09 07:35:40 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716433503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2716433503
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.3516491755
Short name T1188
Test name
Test status
Simulation time 11627001 ps
CPU time 0.85 seconds
Started Feb 09 07:35:37 AM UTC 25
Finished Feb 09 07:35:39 AM UTC 25
Peak memory 202916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516491755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3516491755
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.3323335185
Short name T93
Test name
Test status
Simulation time 71284930 ps
CPU time 0.94 seconds
Started Feb 09 07:35:38 AM UTC 25
Finished Feb 09 07:35:40 AM UTC 25
Peak memory 203032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323335185 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.3323335185
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.2638985004
Short name T1190
Test name
Test status
Simulation time 233063894 ps
CPU time 1.9 seconds
Started Feb 09 07:35:37 AM UTC 25
Finished Feb 09 07:35:40 AM UTC 25
Peak memory 203012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638985004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2638985004
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.4015733321
Short name T106
Test name
Test status
Simulation time 171347833 ps
CPU time 1.42 seconds
Started Feb 09 07:35:37 AM UTC 25
Finished Feb 09 07:35:40 AM UTC 25
Peak memory 203012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015733321 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.4015733321
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2759423896
Short name T1282
Test name
Test status
Simulation time 14247020 ps
CPU time 0.76 seconds
Started Feb 09 07:36:05 AM UTC 25
Finished Feb 09 07:36:07 AM UTC 25
Peak memory 202380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759423896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2759423896
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.1623894410
Short name T1280
Test name
Test status
Simulation time 14566677 ps
CPU time 0.74 seconds
Started Feb 09 07:36:05 AM UTC 25
Finished Feb 09 07:36:07 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623894410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1623894410
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.4034023182
Short name T1288
Test name
Test status
Simulation time 15681746 ps
CPU time 0.85 seconds
Started Feb 09 07:36:05 AM UTC 25
Finished Feb 09 07:36:07 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034023182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.4034023182
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.3000625623
Short name T1284
Test name
Test status
Simulation time 24131901 ps
CPU time 0.7 seconds
Started Feb 09 07:36:05 AM UTC 25
Finished Feb 09 07:36:07 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000625623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3000625623
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.1978219630
Short name T1285
Test name
Test status
Simulation time 77078991 ps
CPU time 0.74 seconds
Started Feb 09 07:36:05 AM UTC 25
Finished Feb 09 07:36:07 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978219630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1978219630
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.1662666372
Short name T1281
Test name
Test status
Simulation time 12235869 ps
CPU time 0.65 seconds
Started Feb 09 07:36:05 AM UTC 25
Finished Feb 09 07:36:07 AM UTC 25
Peak memory 202364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662666372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1662666372
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.3126177164
Short name T1295
Test name
Test status
Simulation time 32323315 ps
CPU time 0.66 seconds
Started Feb 09 07:36:08 AM UTC 25
Finished Feb 09 07:36:10 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126177164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3126177164
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.2321185993
Short name T1292
Test name
Test status
Simulation time 31372724 ps
CPU time 0.59 seconds
Started Feb 09 07:36:08 AM UTC 25
Finished Feb 09 07:36:10 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321185993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2321185993
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.1822034110
Short name T1293
Test name
Test status
Simulation time 45739815 ps
CPU time 0.53 seconds
Started Feb 09 07:36:08 AM UTC 25
Finished Feb 09 07:36:10 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822034110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1822034110
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.814250608
Short name T1294
Test name
Test status
Simulation time 54633390 ps
CPU time 0.66 seconds
Started Feb 09 07:36:08 AM UTC 25
Finished Feb 09 07:36:10 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814250608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.814250608
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.3944602384
Short name T81
Test name
Test status
Simulation time 70177530 ps
CPU time 1.1 seconds
Started Feb 09 07:35:41 AM UTC 25
Finished Feb 09 07:35:43 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944602384 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3944602384
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.1603641873
Short name T1198
Test name
Test status
Simulation time 111305673 ps
CPU time 2.49 seconds
Started Feb 09 07:35:41 AM UTC 25
Finished Feb 09 07:35:45 AM UTC 25
Peak memory 204256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603641873 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1603641873
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.18198305
Short name T89
Test name
Test status
Simulation time 25264058 ps
CPU time 0.79 seconds
Started Feb 09 07:35:40 AM UTC 25
Finished Feb 09 07:35:42 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18198305 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.18198305
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2415851483
Short name T1194
Test name
Test status
Simulation time 87178433 ps
CPU time 0.97 seconds
Started Feb 09 07:35:41 AM UTC 25
Finished Feb 09 07:35:43 AM UTC 25
Peak memory 202800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241585148
3 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2415851483
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2878872694
Short name T94
Test name
Test status
Simulation time 70949137 ps
CPU time 0.9 seconds
Started Feb 09 07:35:41 AM UTC 25
Finished Feb 09 07:35:43 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878872694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2878872694
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.298768831
Short name T1193
Test name
Test status
Simulation time 17907100 ps
CPU time 0.84 seconds
Started Feb 09 07:35:40 AM UTC 25
Finished Feb 09 07:35:42 AM UTC 25
Peak memory 202948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298768831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.298768831
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.3396854962
Short name T95
Test name
Test status
Simulation time 29722523 ps
CPU time 1.09 seconds
Started Feb 09 07:35:41 AM UTC 25
Finished Feb 09 07:35:43 AM UTC 25
Peak memory 203092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396854962 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.3396854962
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.2161897325
Short name T1195
Test name
Test status
Simulation time 430733386 ps
CPU time 3.08 seconds
Started Feb 09 07:35:40 AM UTC 25
Finished Feb 09 07:35:44 AM UTC 25
Peak memory 204352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161897325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2161897325
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1946862535
Short name T1296
Test name
Test status
Simulation time 40291551 ps
CPU time 0.67 seconds
Started Feb 09 07:36:08 AM UTC 25
Finished Feb 09 07:36:10 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946862535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1946862535
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.278550505
Short name T1298
Test name
Test status
Simulation time 12099651 ps
CPU time 0.69 seconds
Started Feb 09 07:36:08 AM UTC 25
Finished Feb 09 07:36:10 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278550505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.278550505
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.1982682413
Short name T1303
Test name
Test status
Simulation time 20437270 ps
CPU time 0.76 seconds
Started Feb 09 07:36:08 AM UTC 25
Finished Feb 09 07:36:11 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982682413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1982682413
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.703266977
Short name T1297
Test name
Test status
Simulation time 13783005 ps
CPU time 0.57 seconds
Started Feb 09 07:36:08 AM UTC 25
Finished Feb 09 07:36:10 AM UTC 25
Peak memory 202960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703266977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.703266977
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3471431900
Short name T1300
Test name
Test status
Simulation time 34617043 ps
CPU time 0.68 seconds
Started Feb 09 07:36:08 AM UTC 25
Finished Feb 09 07:36:10 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471431900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3471431900
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.699893138
Short name T1299
Test name
Test status
Simulation time 18819669 ps
CPU time 0.66 seconds
Started Feb 09 07:36:08 AM UTC 25
Finished Feb 09 07:36:10 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699893138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.699893138
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.1990080998
Short name T1305
Test name
Test status
Simulation time 55471837 ps
CPU time 0.69 seconds
Started Feb 09 07:36:09 AM UTC 25
Finished Feb 09 07:36:11 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990080998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1990080998
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2944020983
Short name T1306
Test name
Test status
Simulation time 14750810 ps
CPU time 0.67 seconds
Started Feb 09 07:36:09 AM UTC 25
Finished Feb 09 07:36:11 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944020983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2944020983
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.2927365426
Short name T1302
Test name
Test status
Simulation time 41726908 ps
CPU time 0.55 seconds
Started Feb 09 07:36:09 AM UTC 25
Finished Feb 09 07:36:10 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927365426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2927365426
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3195477647
Short name T1301
Test name
Test status
Simulation time 49130370 ps
CPU time 0.56 seconds
Started Feb 09 07:36:09 AM UTC 25
Finished Feb 09 07:36:10 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195477647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3195477647
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.873558691
Short name T1202
Test name
Test status
Simulation time 70453533 ps
CPU time 0.96 seconds
Started Feb 09 07:35:44 AM UTC 25
Finished Feb 09 07:35:46 AM UTC 25
Peak memory 202948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873558691 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.873558691
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.1182694626
Short name T84
Test name
Test status
Simulation time 291396377 ps
CPU time 3.06 seconds
Started Feb 09 07:35:44 AM UTC 25
Finished Feb 09 07:35:48 AM UTC 25
Peak memory 204248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182694626 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1182694626
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.2588803404
Short name T1197
Test name
Test status
Simulation time 38447270 ps
CPU time 0.89 seconds
Started Feb 09 07:35:42 AM UTC 25
Finished Feb 09 07:35:44 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588803404 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2588803404
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1740894580
Short name T1200
Test name
Test status
Simulation time 23195309 ps
CPU time 0.93 seconds
Started Feb 09 07:35:44 AM UTC 25
Finished Feb 09 07:35:46 AM UTC 25
Peak memory 202904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174089458
0 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1740894580
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.3120924891
Short name T96
Test name
Test status
Simulation time 39307190 ps
CPU time 0.85 seconds
Started Feb 09 07:35:42 AM UTC 25
Finished Feb 09 07:35:44 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120924891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3120924891
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.3645706491
Short name T1196
Test name
Test status
Simulation time 45048248 ps
CPU time 0.86 seconds
Started Feb 09 07:35:42 AM UTC 25
Finished Feb 09 07:35:44 AM UTC 25
Peak memory 202804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645706491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3645706491
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2254905108
Short name T97
Test name
Test status
Simulation time 82992075 ps
CPU time 1.11 seconds
Started Feb 09 07:35:44 AM UTC 25
Finished Feb 09 07:35:46 AM UTC 25
Peak memory 203084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254905108 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.2254905108
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.980548302
Short name T1199
Test name
Test status
Simulation time 41813427 ps
CPU time 1.27 seconds
Started Feb 09 07:35:42 AM UTC 25
Finished Feb 09 07:35:45 AM UTC 25
Peak memory 202988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980548302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.980548302
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.4263986317
Short name T140
Test name
Test status
Simulation time 253741770 ps
CPU time 1.41 seconds
Started Feb 09 07:35:42 AM UTC 25
Finished Feb 09 07:35:45 AM UTC 25
Peak memory 202924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263986317 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.4263986317
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1991121068
Short name T1304
Test name
Test status
Simulation time 38314515 ps
CPU time 0.6 seconds
Started Feb 09 07:36:09 AM UTC 25
Finished Feb 09 07:36:11 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991121068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1991121068
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.801696263
Short name T1307
Test name
Test status
Simulation time 13382403 ps
CPU time 0.66 seconds
Started Feb 09 07:36:09 AM UTC 25
Finished Feb 09 07:36:11 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801696263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.801696263
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.674471749
Short name T1308
Test name
Test status
Simulation time 22143776 ps
CPU time 0.64 seconds
Started Feb 09 07:36:09 AM UTC 25
Finished Feb 09 07:36:11 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674471749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.674471749
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.4136209058
Short name T1309
Test name
Test status
Simulation time 26205989 ps
CPU time 0.61 seconds
Started Feb 09 07:36:09 AM UTC 25
Finished Feb 09 07:36:11 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136209058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.4136209058
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.2785094656
Short name T1313
Test name
Test status
Simulation time 53791172 ps
CPU time 0.68 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:36:17 AM UTC 25
Peak memory 202936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785094656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2785094656
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.327851972
Short name T1310
Test name
Test status
Simulation time 12153811 ps
CPU time 0.62 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:36:17 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327851972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.327851972
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.608502722
Short name T1312
Test name
Test status
Simulation time 48851808 ps
CPU time 0.67 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:36:17 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608502722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.608502722
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.3186625661
Short name T1314
Test name
Test status
Simulation time 23493382 ps
CPU time 0.71 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:36:17 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186625661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3186625661
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.4176245401
Short name T1315
Test name
Test status
Simulation time 22217736 ps
CPU time 0.72 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:36:17 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176245401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.4176245401
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.223156111
Short name T1311
Test name
Test status
Simulation time 39131903 ps
CPU time 0.59 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:36:17 AM UTC 25
Peak memory 202956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223156111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.223156111
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3103504375
Short name T1207
Test name
Test status
Simulation time 107734736 ps
CPU time 1.02 seconds
Started Feb 09 07:35:45 AM UTC 25
Finished Feb 09 07:35:47 AM UTC 25
Peak memory 202904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310350437
5 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3103504375
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.1954163211
Short name T1203
Test name
Test status
Simulation time 32392757 ps
CPU time 0.9 seconds
Started Feb 09 07:35:44 AM UTC 25
Finished Feb 09 07:35:46 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954163211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1954163211
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.2432282669
Short name T1201
Test name
Test status
Simulation time 29097216 ps
CPU time 0.75 seconds
Started Feb 09 07:35:44 AM UTC 25
Finished Feb 09 07:35:46 AM UTC 25
Peak memory 202948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432282669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2432282669
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.252245894
Short name T1205
Test name
Test status
Simulation time 26062590 ps
CPU time 0.91 seconds
Started Feb 09 07:35:45 AM UTC 25
Finished Feb 09 07:35:47 AM UTC 25
Peak memory 203088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252245894 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.252245894
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.1344673456
Short name T1206
Test name
Test status
Simulation time 42459918 ps
CPU time 2.27 seconds
Started Feb 09 07:35:44 AM UTC 25
Finished Feb 09 07:35:47 AM UTC 25
Peak memory 204352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344673456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1344673456
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.1041207716
Short name T111
Test name
Test status
Simulation time 108116074 ps
CPU time 1.84 seconds
Started Feb 09 07:35:44 AM UTC 25
Finished Feb 09 07:35:47 AM UTC 25
Peak memory 203012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041207716 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1041207716
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.258168843
Short name T1211
Test name
Test status
Simulation time 96110473 ps
CPU time 0.96 seconds
Started Feb 09 07:35:47 AM UTC 25
Finished Feb 09 07:35:49 AM UTC 25
Peak memory 202616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258168843
-assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.258168843
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.4085211060
Short name T83
Test name
Test status
Simulation time 20438771 ps
CPU time 0.86 seconds
Started Feb 09 07:35:45 AM UTC 25
Finished Feb 09 07:35:47 AM UTC 25
Peak memory 202920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085211060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.4085211060
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.1930460167
Short name T1204
Test name
Test status
Simulation time 15115397 ps
CPU time 0.86 seconds
Started Feb 09 07:35:45 AM UTC 25
Finished Feb 09 07:35:47 AM UTC 25
Peak memory 202940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930460167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1930460167
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.1140339423
Short name T1212
Test name
Test status
Simulation time 27150275 ps
CPU time 0.99 seconds
Started Feb 09 07:35:47 AM UTC 25
Finished Feb 09 07:35:49 AM UTC 25
Peak memory 202884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140339423 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.1140339423
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.2017400756
Short name T1209
Test name
Test status
Simulation time 190637263 ps
CPU time 1.57 seconds
Started Feb 09 07:35:45 AM UTC 25
Finished Feb 09 07:35:48 AM UTC 25
Peak memory 203012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017400756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2017400756
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.1640057907
Short name T1208
Test name
Test status
Simulation time 163158328 ps
CPU time 1.41 seconds
Started Feb 09 07:35:45 AM UTC 25
Finished Feb 09 07:35:48 AM UTC 25
Peak memory 203012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640057907 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1640057907
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1431954191
Short name T1220
Test name
Test status
Simulation time 34042897 ps
CPU time 1.17 seconds
Started Feb 09 07:35:48 AM UTC 25
Finished Feb 09 07:35:51 AM UTC 25
Peak memory 202968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143195419
1 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1431954191
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.4034597707
Short name T1213
Test name
Test status
Simulation time 18074992 ps
CPU time 0.92 seconds
Started Feb 09 07:35:47 AM UTC 25
Finished Feb 09 07:35:49 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034597707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4034597707
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.736135528
Short name T1210
Test name
Test status
Simulation time 45117200 ps
CPU time 0.72 seconds
Started Feb 09 07:35:47 AM UTC 25
Finished Feb 09 07:35:49 AM UTC 25
Peak memory 202948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736135528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.736135528
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.290467942
Short name T1214
Test name
Test status
Simulation time 155234295 ps
CPU time 0.85 seconds
Started Feb 09 07:35:47 AM UTC 25
Finished Feb 09 07:35:49 AM UTC 25
Peak memory 207184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290467942 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.290467942
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.367683268
Short name T1217
Test name
Test status
Simulation time 99975957 ps
CPU time 2.2 seconds
Started Feb 09 07:35:47 AM UTC 25
Finished Feb 09 07:35:50 AM UTC 25
Peak memory 204416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367683268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.367683268
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.823623693
Short name T1215
Test name
Test status
Simulation time 133133845 ps
CPU time 1.04 seconds
Started Feb 09 07:35:47 AM UTC 25
Finished Feb 09 07:35:49 AM UTC 25
Peak memory 203008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823623693 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.823623693
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2604410261
Short name T1221
Test name
Test status
Simulation time 43292287 ps
CPU time 1 seconds
Started Feb 09 07:35:48 AM UTC 25
Finished Feb 09 07:35:51 AM UTC 25
Peak memory 203024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260441026
1 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2604410261
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.1257689681
Short name T85
Test name
Test status
Simulation time 53193458 ps
CPU time 0.8 seconds
Started Feb 09 07:35:48 AM UTC 25
Finished Feb 09 07:35:50 AM UTC 25
Peak memory 202908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257689681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1257689681
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.2185508759
Short name T1218
Test name
Test status
Simulation time 41452389 ps
CPU time 0.86 seconds
Started Feb 09 07:35:48 AM UTC 25
Finished Feb 09 07:35:50 AM UTC 25
Peak memory 202948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185508759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2185508759
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.1997157040
Short name T1219
Test name
Test status
Simulation time 97196671 ps
CPU time 0.97 seconds
Started Feb 09 07:35:48 AM UTC 25
Finished Feb 09 07:35:51 AM UTC 25
Peak memory 207180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997157040 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.1997157040
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1529483365
Short name T1223
Test name
Test status
Simulation time 414065683 ps
CPU time 2.02 seconds
Started Feb 09 07:35:48 AM UTC 25
Finished Feb 09 07:35:51 AM UTC 25
Peak memory 206332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529483365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1529483365
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.234395430
Short name T1222
Test name
Test status
Simulation time 49833382 ps
CPU time 1.33 seconds
Started Feb 09 07:35:48 AM UTC 25
Finished Feb 09 07:35:51 AM UTC 25
Peak memory 203008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234395430 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.234395430
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.4066575713
Short name T1229
Test name
Test status
Simulation time 83761113 ps
CPU time 1.07 seconds
Started Feb 09 07:35:50 AM UTC 25
Finished Feb 09 07:35:53 AM UTC 25
Peak memory 202796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406657571
3 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.4066575713
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.3476519255
Short name T1226
Test name
Test status
Simulation time 32719089 ps
CPU time 0.91 seconds
Started Feb 09 07:35:50 AM UTC 25
Finished Feb 09 07:35:52 AM UTC 25
Peak memory 202952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476519255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3476519255
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.2434652586
Short name T1224
Test name
Test status
Simulation time 40088181 ps
CPU time 0.83 seconds
Started Feb 09 07:35:50 AM UTC 25
Finished Feb 09 07:35:52 AM UTC 25
Peak memory 202948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434652586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_T
EST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2434652586
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.1516700491
Short name T1225
Test name
Test status
Simulation time 20418463 ps
CPU time 0.94 seconds
Started Feb 09 07:35:50 AM UTC 25
Finished Feb 09 07:35:52 AM UTC 25
Peak memory 203092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516700491 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.1516700491
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.225982597
Short name T1232
Test name
Test status
Simulation time 184876438 ps
CPU time 2.17 seconds
Started Feb 09 07:35:50 AM UTC 25
Finished Feb 09 07:35:53 AM UTC 25
Peak memory 204632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225982597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TE
ST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.225982597
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.3959115583
Short name T1230
Test name
Test status
Simulation time 92139530 ps
CPU time 1.45 seconds
Started Feb 09 07:35:50 AM UTC 25
Finished Feb 09 07:35:53 AM UTC 25
Peak memory 203008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959115583 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3959115583
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_fifo_full.3781720464
Short name T28
Test name
Test status
Simulation time 81151712206 ps
CPU time 64.23 seconds
Started Feb 09 06:35:18 AM UTC 25
Finished Feb 09 06:36:24 AM UTC 25
Peak memory 208012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781720464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 0.uart_fifo_full.3781720464
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.634899060
Short name T50
Test name
Test status
Simulation time 64018842852 ps
CPU time 119.03 seconds
Started Feb 09 06:35:21 AM UTC 25
Finished Feb 09 06:37:22 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634899060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.634899060
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_noise_filter.1355335622
Short name T51
Test name
Test status
Simulation time 461326823460 ps
CPU time 130.98 seconds
Started Feb 09 06:35:19 AM UTC 25
Finished Feb 09 06:37:33 AM UTC 25
Peak memory 217372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355335622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.uart_noise_filter.1355335622
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_perf.2446555203
Short name T390
Test name
Test status
Simulation time 17630084573 ps
CPU time 1179.97 seconds
Started Feb 09 06:35:21 AM UTC 25
Finished Feb 09 06:55:13 AM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446555203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 0.uart_perf.2446555203
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_rx_oversample.3851847711
Short name T9
Test name
Test status
Simulation time 3902052067 ps
CPU time 32.75 seconds
Started Feb 09 06:35:19 AM UTC 25
Finished Feb 09 06:35:54 AM UTC 25
Peak memory 206984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851847711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3851847711
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.1638254869
Short name T7
Test name
Test status
Simulation time 6969470380 ps
CPU time 28.84 seconds
Started Feb 09 06:35:20 AM UTC 25
Finished Feb 09 06:35:50 AM UTC 25
Peak memory 208608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638254869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.uart_rx_parity_err.1638254869
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.3479344851
Short name T3
Test name
Test status
Simulation time 2252286388 ps
CPU time 5.26 seconds
Started Feb 09 06:35:19 AM UTC 25
Finished Feb 09 06:35:26 AM UTC 25
Peak memory 204860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479344851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3479344851
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_smoke.1386812412
Short name T5
Test name
Test status
Simulation time 5283057286 ps
CPU time 13.91 seconds
Started Feb 09 06:35:18 AM UTC 25
Finished Feb 09 06:35:33 AM UTC 25
Peak memory 207420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386812412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.uart_smoke.1386812412
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.1079284405
Short name T13
Test name
Test status
Simulation time 6918684699 ps
CPU time 36.72 seconds
Started Feb 09 06:35:20 AM UTC 25
Finished Feb 09 06:35:58 AM UTC 25
Peak memory 208232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079284405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.uart_tx_ovrd.1079284405
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_tx_rx.2071446906
Short name T142
Test name
Test status
Simulation time 32940022078 ps
CPU time 94.56 seconds
Started Feb 09 06:35:18 AM UTC 25
Finished Feb 09 06:36:55 AM UTC 25
Peak memory 208572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071446906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.uart_tx_rx.2071446906
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/0.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_alert_test.3622952866
Short name T32
Test name
Test status
Simulation time 19211746 ps
CPU time 0.83 seconds
Started Feb 09 06:36:08 AM UTC 25
Finished Feb 09 06:36:10 AM UTC 25
Peak memory 204404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622952866 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3622952866
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.2316202248
Short name T291
Test name
Test status
Simulation time 90786895432 ps
CPU time 398.26 seconds
Started Feb 09 06:36:04 AM UTC 25
Finished Feb 09 06:42:47 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316202248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2316202248
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_loopback.845755969
Short name T24
Test name
Test status
Simulation time 1438513714 ps
CPU time 3.87 seconds
Started Feb 09 06:35:59 AM UTC 25
Finished Feb 09 06:36:04 AM UTC 25
Peak memory 204736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845755969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.uart_loopback.845755969
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_noise_filter.2811989805
Short name T52
Test name
Test status
Simulation time 277400932548 ps
CPU time 103.56 seconds
Started Feb 09 06:35:51 AM UTC 25
Finished Feb 09 06:37:36 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811989805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.uart_noise_filter.2811989805
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_perf.968181146
Short name T298
Test name
Test status
Simulation time 16567407789 ps
CPU time 834.64 seconds
Started Feb 09 06:36:04 AM UTC 25
Finished Feb 09 06:50:08 AM UTC 25
Peak memory 208444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968181146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 1.uart_perf.968181146
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_rx_oversample.94521898
Short name T8
Test name
Test status
Simulation time 1797102770 ps
CPU time 14.67 seconds
Started Feb 09 06:35:35 AM UTC 25
Finished Feb 09 06:35:50 AM UTC 25
Peak memory 206996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94521898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=
uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.94521898
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.3456142429
Short name T102
Test name
Test status
Simulation time 35213274682 ps
CPU time 38.52 seconds
Started Feb 09 06:35:55 AM UTC 25
Finished Feb 09 06:36:35 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456142429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.uart_rx_parity_err.3456142429
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.1008913359
Short name T14
Test name
Test status
Simulation time 4396369310 ps
CPU time 9.93 seconds
Started Feb 09 06:35:52 AM UTC 25
Finished Feb 09 06:36:03 AM UTC 25
Peak memory 204796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008913359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1008913359
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_sec_cm.8002825
Short name T30
Test name
Test status
Simulation time 120236246 ps
CPU time 1.36 seconds
Started Feb 09 06:36:05 AM UTC 25
Finished Feb 09 06:36:08 AM UTC 25
Peak memory 237656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8002825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_
TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.8002825
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_smoke.1197969159
Short name T4
Test name
Test status
Simulation time 273544589 ps
CPU time 1.95 seconds
Started Feb 09 06:35:25 AM UTC 25
Finished Feb 09 06:35:28 AM UTC 25
Peak memory 206408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197969159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.uart_smoke.1197969159
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.1357627256
Short name T15
Test name
Test status
Simulation time 3772024232 ps
CPU time 4.11 seconds
Started Feb 09 06:35:58 AM UTC 25
Finished Feb 09 06:36:03 AM UTC 25
Peak memory 207376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357627256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.uart_tx_ovrd.1357627256
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/1.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_alert_test.3829319913
Short name T442
Test name
Test status
Simulation time 78023740 ps
CPU time 0.83 seconds
Started Feb 09 06:44:59 AM UTC 25
Finished Feb 09 06:45:01 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829319913 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3829319913
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_fifo_full.1571879852
Short name T394
Test name
Test status
Simulation time 14179241065 ps
CPU time 41.57 seconds
Started Feb 09 06:44:09 AM UTC 25
Finished Feb 09 06:44:52 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571879852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 10.uart_fifo_full.1571879852
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_intr.1919224003
Short name T134
Test name
Test status
Simulation time 37053152828 ps
CPU time 29.34 seconds
Started Feb 09 06:44:27 AM UTC 25
Finished Feb 09 06:44:58 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919224003 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.uart_intr.1919224003
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_loopback.362538509
Short name T443
Test name
Test status
Simulation time 5489091641 ps
CPU time 26 seconds
Started Feb 09 06:44:49 AM UTC 25
Finished Feb 09 06:45:17 AM UTC 25
Peak memory 207872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362538509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.uart_loopback.362538509
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_noise_filter.3620637629
Short name T304
Test name
Test status
Simulation time 116438256048 ps
CPU time 172.43 seconds
Started Feb 09 06:44:29 AM UTC 25
Finished Feb 09 06:47:25 AM UTC 25
Peak memory 207768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620637629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 10.uart_noise_filter.3620637629
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_perf.534266071
Short name T666
Test name
Test status
Simulation time 28593570637 ps
CPU time 1325.21 seconds
Started Feb 09 06:44:49 AM UTC 25
Finished Feb 09 07:07:09 AM UTC 25
Peak memory 212076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534266071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 10.uart_perf.534266071
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_rx_oversample.1652106799
Short name T441
Test name
Test status
Simulation time 7086319755 ps
CPU time 42.97 seconds
Started Feb 09 06:44:13 AM UTC 25
Finished Feb 09 06:44:58 AM UTC 25
Peak memory 207056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652106799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1652106799
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.3227946642
Short name T308
Test name
Test status
Simulation time 15668940710 ps
CPU time 32.77 seconds
Started Feb 09 06:44:46 AM UTC 25
Finished Feb 09 06:45:20 AM UTC 25
Peak memory 208452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227946642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.uart_rx_parity_err.3227946642
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.377799295
Short name T374
Test name
Test status
Simulation time 4741842909 ps
CPU time 17.51 seconds
Started Feb 09 06:44:31 AM UTC 25
Finished Feb 09 06:44:50 AM UTC 25
Peak memory 204800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377799295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_
bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 10.uart_rx_start_bit_filter.377799295
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_smoke.2127483250
Short name T48
Test name
Test status
Simulation time 510825081 ps
CPU time 1.63 seconds
Started Feb 09 06:44:03 AM UTC 25
Finished Feb 09 06:44:06 AM UTC 25
Peak memory 206468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127483250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.uart_smoke.2127483250
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.1927956561
Short name T375
Test name
Test status
Simulation time 6628727065 ps
CPU time 26.94 seconds
Started Feb 09 06:44:48 AM UTC 25
Finished Feb 09 06:45:16 AM UTC 25
Peak memory 208196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927956561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.uart_tx_ovrd.1927956561
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/10.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/101.uart_fifo_reset.2157227563
Short name T983
Test name
Test status
Simulation time 66540724850 ps
CPU time 59.4 seconds
Started Feb 09 07:26:17 AM UTC 25
Finished Feb 09 07:27:18 AM UTC 25
Peak memory 207948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157227563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 101.uart_fifo_reset.2157227563
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/101.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/102.uart_fifo_reset.3898618192
Short name T276
Test name
Test status
Simulation time 60277553390 ps
CPU time 56.51 seconds
Started Feb 09 07:26:20 AM UTC 25
Finished Feb 09 07:27:18 AM UTC 25
Peak memory 208464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898618192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 102.uart_fifo_reset.3898618192
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/102.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/103.uart_fifo_reset.2870390865
Short name T979
Test name
Test status
Simulation time 9697445312 ps
CPU time 36.62 seconds
Started Feb 09 07:26:28 AM UTC 25
Finished Feb 09 07:27:06 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870390865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 103.uart_fifo_reset.2870390865
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/103.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/104.uart_fifo_reset.3568933479
Short name T994
Test name
Test status
Simulation time 142131277907 ps
CPU time 125.66 seconds
Started Feb 09 07:26:30 AM UTC 25
Finished Feb 09 07:28:38 AM UTC 25
Peak memory 208428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568933479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 104.uart_fifo_reset.3568933479
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/104.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/105.uart_fifo_reset.1653851780
Short name T1020
Test name
Test status
Simulation time 227543798675 ps
CPU time 219.54 seconds
Started Feb 09 07:26:38 AM UTC 25
Finished Feb 09 07:30:21 AM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653851780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 105.uart_fifo_reset.1653851780
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/105.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/106.uart_fifo_reset.3169158665
Short name T978
Test name
Test status
Simulation time 21426029243 ps
CPU time 19.88 seconds
Started Feb 09 07:26:43 AM UTC 25
Finished Feb 09 07:27:05 AM UTC 25
Peak memory 208608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169158665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 106.uart_fifo_reset.3169158665
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/106.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/107.uart_fifo_reset.2752144445
Short name T980
Test name
Test status
Simulation time 31402938141 ps
CPU time 16.63 seconds
Started Feb 09 07:26:56 AM UTC 25
Finished Feb 09 07:27:14 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752144445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 107.uart_fifo_reset.2752144445
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/107.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/108.uart_fifo_reset.446872951
Short name T985
Test name
Test status
Simulation time 96032330986 ps
CPU time 41.77 seconds
Started Feb 09 07:26:57 AM UTC 25
Finished Feb 09 07:27:41 AM UTC 25
Peak memory 208392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446872951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 108.uart_fifo_reset.446872951
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/108.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/109.uart_fifo_reset.2319104426
Short name T987
Test name
Test status
Simulation time 29438558560 ps
CPU time 51.83 seconds
Started Feb 09 07:27:06 AM UTC 25
Finished Feb 09 07:27:59 AM UTC 25
Peak memory 208436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319104426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 109.uart_fifo_reset.2319104426
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/109.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_alert_test.82936589
Short name T446
Test name
Test status
Simulation time 97721598 ps
CPU time 0.85 seconds
Started Feb 09 06:46:02 AM UTC 25
Finished Feb 09 06:46:04 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82936589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.82936589
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.4024449856
Short name T150
Test name
Test status
Simulation time 90044056830 ps
CPU time 190.52 seconds
Started Feb 09 06:45:06 AM UTC 25
Finished Feb 09 06:48:20 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024449856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.uart_fifo_overflow.4024449856
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.2817345305
Short name T373
Test name
Test status
Simulation time 88707920290 ps
CPU time 393.09 seconds
Started Feb 09 06:45:38 AM UTC 25
Finished Feb 09 06:52:16 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817345305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2817345305
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_loopback.1460708268
Short name T445
Test name
Test status
Simulation time 8663971382 ps
CPU time 30.63 seconds
Started Feb 09 06:45:29 AM UTC 25
Finished Feb 09 06:46:01 AM UTC 25
Peak memory 208504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460708268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 11.uart_loopback.1460708268
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_noise_filter.326862372
Short name T320
Test name
Test status
Simulation time 80170592308 ps
CPU time 179.98 seconds
Started Feb 09 06:45:21 AM UTC 25
Finished Feb 09 06:48:24 AM UTC 25
Peak memory 208648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326862372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fil
ter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.uart_noise_filter.326862372
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_perf.2095362483
Short name T350
Test name
Test status
Simulation time 18603378795 ps
CPU time 311.2 seconds
Started Feb 09 06:45:32 AM UTC 25
Finished Feb 09 06:50:47 AM UTC 25
Peak memory 208384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095362483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 11.uart_perf.2095362483
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_rx_oversample.598319137
Short name T444
Test name
Test status
Simulation time 2434576580 ps
CPU time 6.22 seconds
Started Feb 09 06:45:17 AM UTC 25
Finished Feb 09 06:45:25 AM UTC 25
Peak memory 207108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598319137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.598319137
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.1046157784
Short name T156
Test name
Test status
Simulation time 11831271229 ps
CPU time 23.37 seconds
Started Feb 09 06:45:26 AM UTC 25
Finished Feb 09 06:45:50 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046157784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.uart_rx_parity_err.1046157784
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.363257004
Short name T393
Test name
Test status
Simulation time 35153412690 ps
CPU time 14.07 seconds
Started Feb 09 06:45:22 AM UTC 25
Finished Feb 09 06:45:37 AM UTC 25
Peak memory 204864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363257004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_
bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 11.uart_rx_start_bit_filter.363257004
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_smoke.786009845
Short name T372
Test name
Test status
Simulation time 554222226 ps
CPU time 2.72 seconds
Started Feb 09 06:45:00 AM UTC 25
Finished Feb 09 06:45:04 AM UTC 25
Peak memory 207428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786009845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 11.uart_smoke.786009845
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.1044221258
Short name T58
Test name
Test status
Simulation time 114177392474 ps
CPU time 1432.71 seconds
Started Feb 09 06:45:45 AM UTC 25
Finished Feb 09 07:09:53 AM UTC 25
Peak memory 245080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1044221258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1044221258
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.96700306
Short name T334
Test name
Test status
Simulation time 6485036594 ps
CPU time 13.57 seconds
Started Feb 09 06:45:29 AM UTC 25
Finished Feb 09 06:45:44 AM UTC 25
Peak memory 208136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96700306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.uart_tx_ovrd.96700306
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_tx_rx.3356410360
Short name T338
Test name
Test status
Simulation time 12945768532 ps
CPU time 25.21 seconds
Started Feb 09 06:45:02 AM UTC 25
Finished Feb 09 06:45:28 AM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356410360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.uart_tx_rx.3356410360
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/11.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/110.uart_fifo_reset.3678125048
Short name T1014
Test name
Test status
Simulation time 166753780440 ps
CPU time 163.45 seconds
Started Feb 09 07:27:08 AM UTC 25
Finished Feb 09 07:29:54 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678125048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 110.uart_fifo_reset.3678125048
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/110.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/112.uart_fifo_reset.2898003084
Short name T1026
Test name
Test status
Simulation time 107652133846 ps
CPU time 203.21 seconds
Started Feb 09 07:27:15 AM UTC 25
Finished Feb 09 07:30:41 AM UTC 25
Peak memory 208152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898003084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 112.uart_fifo_reset.2898003084
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/112.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/113.uart_fifo_reset.267354892
Short name T217
Test name
Test status
Simulation time 194945543087 ps
CPU time 84.64 seconds
Started Feb 09 07:27:15 AM UTC 25
Finished Feb 09 07:28:42 AM UTC 25
Peak memory 208576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267354892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 113.uart_fifo_reset.267354892
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/113.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/114.uart_fifo_reset.2127077373
Short name T223
Test name
Test status
Simulation time 92226662978 ps
CPU time 252.95 seconds
Started Feb 09 07:27:18 AM UTC 25
Finished Feb 09 07:31:34 AM UTC 25
Peak memory 208460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127077373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 114.uart_fifo_reset.2127077373
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/114.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/117.uart_fifo_reset.1160417491
Short name T1110
Test name
Test status
Simulation time 215442576479 ps
CPU time 443.36 seconds
Started Feb 09 07:27:21 AM UTC 25
Finished Feb 09 07:34:50 AM UTC 25
Peak memory 208648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160417491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 117.uart_fifo_reset.1160417491
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/117.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/119.uart_fifo_reset.437673951
Short name T991
Test name
Test status
Simulation time 24448536793 ps
CPU time 42.74 seconds
Started Feb 09 07:27:45 AM UTC 25
Finished Feb 09 07:28:30 AM UTC 25
Peak memory 208620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437673951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 119.uart_fifo_reset.437673951
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/119.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_alert_test.2956252162
Short name T448
Test name
Test status
Simulation time 12847031 ps
CPU time 0.86 seconds
Started Feb 09 06:47:38 AM UTC 25
Finished Feb 09 06:47:40 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956252162 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2956252162
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_fifo_full.52298285
Short name T355
Test name
Test status
Simulation time 57687321549 ps
CPU time 82.03 seconds
Started Feb 09 06:46:09 AM UTC 25
Finished Feb 09 06:47:33 AM UTC 25
Peak memory 208516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52298285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.uart_fifo_full.52298285
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.2400206704
Short name T152
Test name
Test status
Simulation time 20627838957 ps
CPU time 37.98 seconds
Started Feb 09 06:46:14 AM UTC 25
Finished Feb 09 06:46:54 AM UTC 25
Peak memory 208564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400206704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.uart_fifo_overflow.2400206704
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_fifo_reset.1281633024
Short name T195
Test name
Test status
Simulation time 23851494267 ps
CPU time 42.61 seconds
Started Feb 09 06:46:21 AM UTC 25
Finished Feb 09 06:47:05 AM UTC 25
Peak memory 208524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281633024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 12.uart_fifo_reset.1281633024
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_intr.197399116
Short name T352
Test name
Test status
Simulation time 26491226162 ps
CPU time 42.57 seconds
Started Feb 09 06:46:52 AM UTC 25
Finished Feb 09 06:47:37 AM UTC 25
Peak memory 208456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197399116 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.uart_intr.197399116
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.985500
Short name T479
Test name
Test status
Simulation time 80504074670 ps
CPU time 274.68 seconds
Started Feb 09 06:47:31 AM UTC 25
Finished Feb 09 06:52:10 AM UTC 25
Peak memory 208416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.985500
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_loopback.485840864
Short name T449
Test name
Test status
Simulation time 9232147858 ps
CPU time 17.36 seconds
Started Feb 09 06:47:26 AM UTC 25
Finished Feb 09 06:47:45 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485840864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.uart_loopback.485840864
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_noise_filter.2541122577
Short name T388
Test name
Test status
Simulation time 100193589529 ps
CPU time 52.78 seconds
Started Feb 09 06:46:55 AM UTC 25
Finished Feb 09 06:47:49 AM UTC 25
Peak memory 207236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541122577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 12.uart_noise_filter.2541122577
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_perf.2586839039
Short name T549
Test name
Test status
Simulation time 15066333724 ps
CPU time 731.74 seconds
Started Feb 09 06:47:26 AM UTC 25
Finished Feb 09 06:59:46 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586839039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 12.uart_perf.2586839039
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_rx_oversample.2723006974
Short name T450
Test name
Test status
Simulation time 5864316093 ps
CPU time 75.11 seconds
Started Feb 09 06:46:29 AM UTC 25
Finished Feb 09 06:47:46 AM UTC 25
Peak memory 207184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723006974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2723006974
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.1792631470
Short name T159
Test name
Test status
Simulation time 61117649340 ps
CPU time 72.26 seconds
Started Feb 09 06:47:10 AM UTC 25
Finished Feb 09 06:48:24 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792631470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.uart_rx_parity_err.1792631470
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.130484286
Short name T351
Test name
Test status
Simulation time 1830579713 ps
CPU time 6.51 seconds
Started Feb 09 06:47:07 AM UTC 25
Finished Feb 09 06:47:14 AM UTC 25
Peak memory 204660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130484286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_
bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 12.uart_rx_start_bit_filter.130484286
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_smoke.2924673910
Short name T328
Test name
Test status
Simulation time 313238369 ps
CPU time 2.24 seconds
Started Feb 09 06:46:05 AM UTC 25
Finished Feb 09 06:46:08 AM UTC 25
Peak memory 206996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924673910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.uart_smoke.2924673910
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.2361777360
Short name T67
Test name
Test status
Simulation time 148777030442 ps
CPU time 1348.83 seconds
Started Feb 09 06:47:34 AM UTC 25
Finished Feb 09 07:10:18 AM UTC 25
Peak memory 228608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2361777360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2361777360
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.161688575
Short name T376
Test name
Test status
Simulation time 7497060412 ps
CPU time 23.45 seconds
Started Feb 09 06:47:16 AM UTC 25
Finished Feb 09 06:47:41 AM UTC 25
Peak memory 208064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161688575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.uart_tx_ovrd.161688575
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_tx_rx.1734263929
Short name T408
Test name
Test status
Simulation time 45939436256 ps
CPU time 139.76 seconds
Started Feb 09 06:46:06 AM UTC 25
Finished Feb 09 06:48:28 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734263929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.uart_tx_rx.1734263929
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/12.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/120.uart_fifo_reset.1651401027
Short name T998
Test name
Test status
Simulation time 23206861958 ps
CPU time 53.54 seconds
Started Feb 09 07:28:00 AM UTC 25
Finished Feb 09 07:28:56 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651401027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 120.uart_fifo_reset.1651401027
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/120.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/121.uart_fifo_reset.3650883419
Short name T239
Test name
Test status
Simulation time 140503919952 ps
CPU time 107.81 seconds
Started Feb 09 07:28:05 AM UTC 25
Finished Feb 09 07:29:55 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650883419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 121.uart_fifo_reset.3650883419
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/121.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/122.uart_fifo_reset.264053881
Short name T996
Test name
Test status
Simulation time 11935806660 ps
CPU time 18.92 seconds
Started Feb 09 07:28:26 AM UTC 25
Finished Feb 09 07:28:46 AM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264053881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 122.uart_fifo_reset.264053881
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/122.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/123.uart_fifo_reset.203442597
Short name T1005
Test name
Test status
Simulation time 52952542796 ps
CPU time 51.06 seconds
Started Feb 09 07:28:30 AM UTC 25
Finished Feb 09 07:29:22 AM UTC 25
Peak memory 208272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203442597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 123.uart_fifo_reset.203442597
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/123.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/124.uart_fifo_reset.1940720939
Short name T1008
Test name
Test status
Simulation time 184865093628 ps
CPU time 59.18 seconds
Started Feb 09 07:28:31 AM UTC 25
Finished Feb 09 07:29:32 AM UTC 25
Peak memory 208528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940720939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 124.uart_fifo_reset.1940720939
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/124.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/125.uart_fifo_reset.3182735461
Short name T260
Test name
Test status
Simulation time 143220813238 ps
CPU time 329.27 seconds
Started Feb 09 07:28:31 AM UTC 25
Finished Feb 09 07:34:04 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182735461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 125.uart_fifo_reset.3182735461
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/125.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/126.uart_fifo_reset.2662096957
Short name T1011
Test name
Test status
Simulation time 28840382943 ps
CPU time 69.04 seconds
Started Feb 09 07:28:32 AM UTC 25
Finished Feb 09 07:29:43 AM UTC 25
Peak memory 208680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662096957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 126.uart_fifo_reset.2662096957
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/126.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/127.uart_fifo_reset.2808761113
Short name T1002
Test name
Test status
Simulation time 7896643627 ps
CPU time 30.89 seconds
Started Feb 09 07:28:37 AM UTC 25
Finished Feb 09 07:29:09 AM UTC 25
Peak memory 208420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808761113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 127.uart_fifo_reset.2808761113
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/127.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/128.uart_fifo_reset.1321977851
Short name T997
Test name
Test status
Simulation time 27799639267 ps
CPU time 11.18 seconds
Started Feb 09 07:28:39 AM UTC 25
Finished Feb 09 07:28:51 AM UTC 25
Peak memory 208316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321977851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 128.uart_fifo_reset.1321977851
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/128.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/129.uart_fifo_reset.3659519196
Short name T1150
Test name
Test status
Simulation time 238373953698 ps
CPU time 449.73 seconds
Started Feb 09 07:28:40 AM UTC 25
Finished Feb 09 07:36:15 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659519196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 129.uart_fifo_reset.3659519196
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/129.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_alert_test.2419422450
Short name T453
Test name
Test status
Simulation time 37809721 ps
CPU time 0.83 seconds
Started Feb 09 06:48:20 AM UTC 25
Finished Feb 09 06:48:22 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419422450 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2419422450
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_fifo_full.4176452381
Short name T335
Test name
Test status
Simulation time 74113731363 ps
CPU time 109.99 seconds
Started Feb 09 06:47:42 AM UTC 25
Finished Feb 09 06:49:34 AM UTC 25
Peak memory 208596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176452381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 13.uart_fifo_full.4176452381
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.1965627413
Short name T173
Test name
Test status
Simulation time 39659154614 ps
CPU time 25.54 seconds
Started Feb 09 06:47:45 AM UTC 25
Finished Feb 09 06:48:12 AM UTC 25
Peak memory 208500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965627413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.uart_fifo_overflow.1965627413
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_fifo_reset.2448066628
Short name T369
Test name
Test status
Simulation time 10011768904 ps
CPU time 46.25 seconds
Started Feb 09 06:47:46 AM UTC 25
Finished Feb 09 06:48:34 AM UTC 25
Peak memory 208584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448066628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 13.uart_fifo_reset.2448066628
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_intr.3742415668
Short name T384
Test name
Test status
Simulation time 16563530542 ps
CPU time 14.49 seconds
Started Feb 09 06:47:49 AM UTC 25
Finished Feb 09 06:48:05 AM UTC 25
Peak memory 208572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742415668 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.uart_intr.3742415668
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.3574545486
Short name T473
Test name
Test status
Simulation time 288263871223 ps
CPU time 185.18 seconds
Started Feb 09 06:48:13 AM UTC 25
Finished Feb 09 06:51:21 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574545486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3574545486
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_loopback.3470833093
Short name T452
Test name
Test status
Simulation time 2759956662 ps
CPU time 6.08 seconds
Started Feb 09 06:48:11 AM UTC 25
Finished Feb 09 06:48:18 AM UTC 25
Peak memory 207336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470833093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 13.uart_loopback.3470833093
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_perf.1742455034
Short name T629
Test name
Test status
Simulation time 19765108370 ps
CPU time 976.59 seconds
Started Feb 09 06:48:11 AM UTC 25
Finished Feb 09 07:04:38 AM UTC 25
Peak memory 209968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742455034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 13.uart_perf.1742455034
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_rx_oversample.3723104916
Short name T455
Test name
Test status
Simulation time 4463097750 ps
CPU time 51.83 seconds
Started Feb 09 06:47:47 AM UTC 25
Finished Feb 09 06:48:41 AM UTC 25
Peak memory 207684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723104916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3723104916
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.4209514915
Short name T367
Test name
Test status
Simulation time 157086235029 ps
CPU time 26.73 seconds
Started Feb 09 06:47:50 AM UTC 25
Finished Feb 09 06:48:18 AM UTC 25
Peak memory 208368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209514915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.uart_rx_parity_err.4209514915
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.289528282
Short name T354
Test name
Test status
Simulation time 39501473285 ps
CPU time 34.83 seconds
Started Feb 09 06:47:49 AM UTC 25
Finished Feb 09 06:48:26 AM UTC 25
Peak memory 204800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289528282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_
bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 13.uart_rx_start_bit_filter.289528282
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_smoke.1330761399
Short name T343
Test name
Test status
Simulation time 712487937 ps
CPU time 6.35 seconds
Started Feb 09 06:47:41 AM UTC 25
Finished Feb 09 06:47:49 AM UTC 25
Peak memory 207460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330761399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.uart_smoke.1330761399
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_stress_all.1819072122
Short name T130
Test name
Test status
Simulation time 233106984542 ps
CPU time 681.63 seconds
Started Feb 09 06:48:19 AM UTC 25
Finished Feb 09 06:59:48 AM UTC 25
Peak memory 217428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819072122 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1819072122
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.2519725407
Short name T451
Test name
Test status
Simulation time 1100768066 ps
CPU time 3.14 seconds
Started Feb 09 06:48:06 AM UTC 25
Finished Feb 09 06:48:10 AM UTC 25
Peak memory 206848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519725407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.uart_tx_ovrd.2519725407
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_tx_rx.3074311588
Short name T454
Test name
Test status
Simulation time 18233069354 ps
CPU time 39.58 seconds
Started Feb 09 06:47:41 AM UTC 25
Finished Feb 09 06:48:22 AM UTC 25
Peak memory 208336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074311588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.uart_tx_rx.3074311588
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/13.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/130.uart_fifo_reset.2293019736
Short name T234
Test name
Test status
Simulation time 50224891617 ps
CPU time 65.69 seconds
Started Feb 09 07:28:42 AM UTC 25
Finished Feb 09 07:29:50 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293019736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 130.uart_fifo_reset.2293019736
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/130.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/131.uart_fifo_reset.1723601075
Short name T1013
Test name
Test status
Simulation time 70047474222 ps
CPU time 58.31 seconds
Started Feb 09 07:28:46 AM UTC 25
Finished Feb 09 07:29:46 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723601075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 131.uart_fifo_reset.1723601075
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/131.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/132.uart_fifo_reset.3348261915
Short name T1017
Test name
Test status
Simulation time 100065765698 ps
CPU time 85.91 seconds
Started Feb 09 07:28:50 AM UTC 25
Finished Feb 09 07:30:18 AM UTC 25
Peak memory 208680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348261915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 132.uart_fifo_reset.3348261915
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/132.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/133.uart_fifo_reset.2958735983
Short name T1010
Test name
Test status
Simulation time 29894149645 ps
CPU time 45.28 seconds
Started Feb 09 07:28:52 AM UTC 25
Finished Feb 09 07:29:39 AM UTC 25
Peak memory 208420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958735983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 133.uart_fifo_reset.2958735983
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/133.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/134.uart_fifo_reset.3654809736
Short name T254
Test name
Test status
Simulation time 165749284942 ps
CPU time 63.53 seconds
Started Feb 09 07:28:56 AM UTC 25
Finished Feb 09 07:30:02 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654809736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 134.uart_fifo_reset.3654809736
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/134.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/135.uart_fifo_reset.306574578
Short name T1009
Test name
Test status
Simulation time 26603127547 ps
CPU time 27.73 seconds
Started Feb 09 07:29:03 AM UTC 25
Finished Feb 09 07:29:33 AM UTC 25
Peak memory 208620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306574578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 135.uart_fifo_reset.306574578
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/135.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/136.uart_fifo_reset.1254201117
Short name T236
Test name
Test status
Simulation time 33628517134 ps
CPU time 50.62 seconds
Started Feb 09 07:29:07 AM UTC 25
Finished Feb 09 07:29:59 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254201117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 136.uart_fifo_reset.1254201117
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/136.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/137.uart_fifo_reset.1525628949
Short name T1027
Test name
Test status
Simulation time 45120829599 ps
CPU time 96.33 seconds
Started Feb 09 07:29:09 AM UTC 25
Finished Feb 09 07:30:47 AM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525628949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 137.uart_fifo_reset.1525628949
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/137.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/138.uart_fifo_reset.4052209307
Short name T1040
Test name
Test status
Simulation time 88104123686 ps
CPU time 151.98 seconds
Started Feb 09 07:29:10 AM UTC 25
Finished Feb 09 07:31:44 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052209307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 138.uart_fifo_reset.4052209307
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/138.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/139.uart_fifo_reset.3544418174
Short name T1012
Test name
Test status
Simulation time 11015650956 ps
CPU time 32.54 seconds
Started Feb 09 07:29:12 AM UTC 25
Finished Feb 09 07:29:46 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544418174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 139.uart_fifo_reset.3544418174
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/139.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_alert_test.1017880729
Short name T458
Test name
Test status
Simulation time 46597720 ps
CPU time 0.84 seconds
Started Feb 09 06:49:02 AM UTC 25
Finished Feb 09 06:49:04 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017880729 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1017880729
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.3066680515
Short name T385
Test name
Test status
Simulation time 30278849503 ps
CPU time 82.58 seconds
Started Feb 09 06:48:23 AM UTC 25
Finished Feb 09 06:49:48 AM UTC 25
Peak memory 208448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066680515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.uart_fifo_overflow.3066680515
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.577887639
Short name T122
Test name
Test status
Simulation time 211579801507 ps
CPU time 296.69 seconds
Started Feb 09 06:48:55 AM UTC 25
Finished Feb 09 06:53:56 AM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577887639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.577887639
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_loopback.289051972
Short name T456
Test name
Test status
Simulation time 1253605143 ps
CPU time 3.09 seconds
Started Feb 09 06:48:42 AM UTC 25
Finished Feb 09 06:48:46 AM UTC 25
Peak memory 207124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289051972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.uart_loopback.289051972
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_noise_filter.3543409961
Short name T366
Test name
Test status
Simulation time 21594090416 ps
CPU time 51.04 seconds
Started Feb 09 06:48:30 AM UTC 25
Finished Feb 09 06:49:22 AM UTC 25
Peak memory 208168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543409961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 14.uart_noise_filter.3543409961
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_perf.287894081
Short name T557
Test name
Test status
Simulation time 11397361753 ps
CPU time 664.03 seconds
Started Feb 09 06:48:47 AM UTC 25
Finished Feb 09 06:59:58 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287894081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 14.uart_perf.287894081
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_rx_oversample.1056080744
Short name T457
Test name
Test status
Simulation time 3931967206 ps
CPU time 33.14 seconds
Started Feb 09 06:48:25 AM UTC 25
Finished Feb 09 06:49:00 AM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056080744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1056080744
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.4267625796
Short name T341
Test name
Test status
Simulation time 67791248747 ps
CPU time 71.3 seconds
Started Feb 09 06:48:35 AM UTC 25
Finished Feb 09 06:49:48 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267625796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.uart_rx_parity_err.4267625796
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.877731574
Short name T377
Test name
Test status
Simulation time 47354914841 ps
CPU time 25.63 seconds
Started Feb 09 06:48:35 AM UTC 25
Finished Feb 09 06:49:02 AM UTC 25
Peak memory 204724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877731574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_
bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 14.uart_rx_start_bit_filter.877731574
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_smoke.563209082
Short name T345
Test name
Test status
Simulation time 5267608102 ps
CPU time 11.91 seconds
Started Feb 09 06:48:21 AM UTC 25
Finished Feb 09 06:48:34 AM UTC 25
Peak memory 208032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563209082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 14.uart_smoke.563209082
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_stress_all.922693445
Short name T129
Test name
Test status
Simulation time 214862788479 ps
CPU time 402.73 seconds
Started Feb 09 06:49:01 AM UTC 25
Finished Feb 09 06:55:49 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922693445 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.922693445
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.1981064245
Short name T363
Test name
Test status
Simulation time 13192212929 ps
CPU time 76.53 seconds
Started Feb 09 06:48:40 AM UTC 25
Finished Feb 09 06:49:58 AM UTC 25
Peak memory 208256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981064245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.uart_tx_ovrd.1981064245
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_tx_rx.2166956319
Short name T469
Test name
Test status
Simulation time 67163226992 ps
CPU time 158.54 seconds
Started Feb 09 06:48:22 AM UTC 25
Finished Feb 09 06:51:03 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166956319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.uart_tx_rx.2166956319
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/14.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/140.uart_fifo_reset.3593286359
Short name T1041
Test name
Test status
Simulation time 57554434956 ps
CPU time 148.79 seconds
Started Feb 09 07:29:14 AM UTC 25
Finished Feb 09 07:31:45 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593286359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 140.uart_fifo_reset.3593286359
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/140.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/142.uart_fifo_reset.184237489
Short name T1032
Test name
Test status
Simulation time 202575991333 ps
CPU time 111.06 seconds
Started Feb 09 07:29:19 AM UTC 25
Finished Feb 09 07:31:12 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184237489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 142.uart_fifo_reset.184237489
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/142.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/144.uart_fifo_reset.3012550564
Short name T197
Test name
Test status
Simulation time 93872501292 ps
CPU time 204.65 seconds
Started Feb 09 07:29:29 AM UTC 25
Finished Feb 09 07:32:57 AM UTC 25
Peak memory 208564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012550564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 144.uart_fifo_reset.3012550564
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/144.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/145.uart_fifo_reset.607375752
Short name T1022
Test name
Test status
Simulation time 33298716513 ps
CPU time 58.3 seconds
Started Feb 09 07:29:30 AM UTC 25
Finished Feb 09 07:30:30 AM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607375752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 145.uart_fifo_reset.607375752
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/145.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/146.uart_fifo_reset.3125682281
Short name T1018
Test name
Test status
Simulation time 32370330205 ps
CPU time 45.51 seconds
Started Feb 09 07:29:32 AM UTC 25
Finished Feb 09 07:30:19 AM UTC 25
Peak memory 208280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125682281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 146.uart_fifo_reset.3125682281
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/146.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/147.uart_fifo_reset.1184957552
Short name T1074
Test name
Test status
Simulation time 124450743748 ps
CPU time 227.39 seconds
Started Feb 09 07:29:33 AM UTC 25
Finished Feb 09 07:33:24 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184957552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 147.uart_fifo_reset.1184957552
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/147.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/149.uart_fifo_reset.3084720520
Short name T1036
Test name
Test status
Simulation time 34146083115 ps
CPU time 101.27 seconds
Started Feb 09 07:29:39 AM UTC 25
Finished Feb 09 07:31:23 AM UTC 25
Peak memory 208592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084720520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 149.uart_fifo_reset.3084720520
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/149.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_alert_test.867616521
Short name T462
Test name
Test status
Simulation time 14350525 ps
CPU time 0.85 seconds
Started Feb 09 06:50:32 AM UTC 25
Finished Feb 09 06:50:34 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867616521 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.867616521
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_fifo_full.3316302423
Short name T459
Test name
Test status
Simulation time 25000640895 ps
CPU time 44.66 seconds
Started Feb 09 06:49:23 AM UTC 25
Finished Feb 09 06:50:10 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316302423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 15.uart_fifo_full.3316302423
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.2840253268
Short name T327
Test name
Test status
Simulation time 290658517783 ps
CPU time 60.56 seconds
Started Feb 09 06:49:35 AM UTC 25
Finished Feb 09 06:50:38 AM UTC 25
Peak memory 208672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840253268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.uart_fifo_overflow.2840253268
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_fifo_reset.422017112
Short name T282
Test name
Test status
Simulation time 147502610951 ps
CPU time 221.18 seconds
Started Feb 09 06:49:40 AM UTC 25
Finished Feb 09 06:53:24 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422017112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 15.uart_fifo_reset.422017112
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_intr.2041703468
Short name T465
Test name
Test status
Simulation time 17510128218 ps
CPU time 53.83 seconds
Started Feb 09 06:49:49 AM UTC 25
Finished Feb 09 06:50:45 AM UTC 25
Peak memory 207968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041703468 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.uart_intr.2041703468
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.3381584969
Short name T556
Test name
Test status
Simulation time 132838114523 ps
CPU time 563.45 seconds
Started Feb 09 06:50:25 AM UTC 25
Finished Feb 09 06:59:55 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381584969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3381584969
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_loopback.2624328845
Short name T460
Test name
Test status
Simulation time 9798556887 ps
CPU time 9.12 seconds
Started Feb 09 06:50:10 AM UTC 25
Finished Feb 09 06:50:21 AM UTC 25
Peak memory 208668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624328845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 15.uart_loopback.2624328845
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_perf.3910346324
Short name T128
Test name
Test status
Simulation time 17550150826 ps
CPU time 227.83 seconds
Started Feb 09 06:50:21 AM UTC 25
Finished Feb 09 06:54:14 AM UTC 25
Peak memory 208672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910346324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 15.uart_perf.3910346324
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_rx_oversample.2746300986
Short name T461
Test name
Test status
Simulation time 5746612198 ps
CPU time 45.03 seconds
Started Feb 09 06:49:44 AM UTC 25
Finished Feb 09 06:50:31 AM UTC 25
Peak memory 207184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746300986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2746300986
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.3297413108
Short name T471
Test name
Test status
Simulation time 82187380605 ps
CPU time 62.26 seconds
Started Feb 09 06:50:08 AM UTC 25
Finished Feb 09 06:51:12 AM UTC 25
Peak memory 208248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297413108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.uart_rx_parity_err.3297413108
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.2158760240
Short name T346
Test name
Test status
Simulation time 6682916347 ps
CPU time 23.77 seconds
Started Feb 09 06:49:59 AM UTC 25
Finished Feb 09 06:50:24 AM UTC 25
Peak memory 204728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158760240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2158760240
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_smoke.343751974
Short name T389
Test name
Test status
Simulation time 788150160 ps
CPU time 2.26 seconds
Started Feb 09 06:49:05 AM UTC 25
Finished Feb 09 06:49:09 AM UTC 25
Peak memory 207880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343751974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 15.uart_smoke.343751974
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_stress_all.3572086951
Short name T409
Test name
Test status
Simulation time 240593191378 ps
CPU time 672.66 seconds
Started Feb 09 06:50:32 AM UTC 25
Finished Feb 09 07:01:52 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572086951 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3572086951
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.3972249974
Short name T183
Test name
Test status
Simulation time 334854420181 ps
CPU time 1050.38 seconds
Started Feb 09 06:50:31 AM UTC 25
Finished Feb 09 07:08:13 AM UTC 25
Peak memory 241052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3972249974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3972249974
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.3454156003
Short name T464
Test name
Test status
Simulation time 7414570338 ps
CPU time 31.19 seconds
Started Feb 09 06:50:09 AM UTC 25
Finished Feb 09 06:50:42 AM UTC 25
Peak memory 207652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454156003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.uart_tx_ovrd.3454156003
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_tx_rx.361022546
Short name T123
Test name
Test status
Simulation time 179332076448 ps
CPU time 284.36 seconds
Started Feb 09 06:49:09 AM UTC 25
Finished Feb 09 06:53:57 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361022546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 15.uart_tx_rx.361022546
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/15.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/150.uart_fifo_reset.309835913
Short name T1153
Test name
Test status
Simulation time 180846995987 ps
CPU time 395.28 seconds
Started Feb 09 07:29:44 AM UTC 25
Finished Feb 09 07:36:24 AM UTC 25
Peak memory 208608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309835913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 150.uart_fifo_reset.309835913
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/150.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/151.uart_fifo_reset.3024425425
Short name T1019
Test name
Test status
Simulation time 11430583222 ps
CPU time 31.42 seconds
Started Feb 09 07:29:47 AM UTC 25
Finished Feb 09 07:30:19 AM UTC 25
Peak memory 208416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024425425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 151.uart_fifo_reset.3024425425
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/151.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/152.uart_fifo_reset.697653971
Short name T1033
Test name
Test status
Simulation time 20588022825 ps
CPU time 90.31 seconds
Started Feb 09 07:29:47 AM UTC 25
Finished Feb 09 07:31:19 AM UTC 25
Peak memory 208508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697653971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 152.uart_fifo_reset.697653971
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/152.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/153.uart_fifo_reset.1598471717
Short name T1069
Test name
Test status
Simulation time 102714387202 ps
CPU time 204.5 seconds
Started Feb 09 07:29:47 AM UTC 25
Finished Feb 09 07:33:14 AM UTC 25
Peak memory 208372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598471717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 153.uart_fifo_reset.1598471717
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/153.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/154.uart_fifo_reset.4219548645
Short name T1071
Test name
Test status
Simulation time 85558615985 ps
CPU time 202.75 seconds
Started Feb 09 07:29:51 AM UTC 25
Finished Feb 09 07:33:17 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219548645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 154.uart_fifo_reset.4219548645
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/154.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/155.uart_fifo_reset.4145016442
Short name T1048
Test name
Test status
Simulation time 383483688699 ps
CPU time 126.66 seconds
Started Feb 09 07:29:55 AM UTC 25
Finished Feb 09 07:32:04 AM UTC 25
Peak memory 208456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145016442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 155.uart_fifo_reset.4145016442
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/155.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/156.uart_fifo_reset.1426253698
Short name T1023
Test name
Test status
Simulation time 17782172838 ps
CPU time 38.99 seconds
Started Feb 09 07:29:56 AM UTC 25
Finished Feb 09 07:30:36 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426253698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 156.uart_fifo_reset.1426253698
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/156.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/157.uart_fifo_reset.2102990406
Short name T1029
Test name
Test status
Simulation time 85070112086 ps
CPU time 58.62 seconds
Started Feb 09 07:29:58 AM UTC 25
Finished Feb 09 07:30:58 AM UTC 25
Peak memory 208592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102990406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 157.uart_fifo_reset.2102990406
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/157.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/158.uart_fifo_reset.3540766480
Short name T1063
Test name
Test status
Simulation time 125828324598 ps
CPU time 167.18 seconds
Started Feb 09 07:29:58 AM UTC 25
Finished Feb 09 07:32:48 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540766480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 158.uart_fifo_reset.3540766480
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/158.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/159.uart_fifo_reset.2050313367
Short name T1021
Test name
Test status
Simulation time 32151060030 ps
CPU time 23.02 seconds
Started Feb 09 07:30:00 AM UTC 25
Finished Feb 09 07:30:25 AM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050313367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 159.uart_fifo_reset.2050313367
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/159.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_alert_test.3269884276
Short name T472
Test name
Test status
Simulation time 15655126 ps
CPU time 0.86 seconds
Started Feb 09 06:51:10 AM UTC 25
Finished Feb 09 06:51:12 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269884276 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3269884276
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_fifo_full.996225741
Short name T357
Test name
Test status
Simulation time 53639388429 ps
CPU time 43.54 seconds
Started Feb 09 06:50:36 AM UTC 25
Finished Feb 09 06:51:21 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996225741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 16.uart_fifo_full.996225741
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_fifo_reset.2433235002
Short name T181
Test name
Test status
Simulation time 78886401043 ps
CPU time 43.61 seconds
Started Feb 09 06:50:39 AM UTC 25
Finished Feb 09 06:51:24 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433235002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 16.uart_fifo_reset.2433235002
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_intr.3270900061
Short name T468
Test name
Test status
Simulation time 15123518209 ps
CPU time 13.25 seconds
Started Feb 09 06:50:45 AM UTC 25
Finished Feb 09 06:51:00 AM UTC 25
Peak memory 207400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270900061 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.uart_intr.3270900061
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.3827215659
Short name T619
Test name
Test status
Simulation time 133203549121 ps
CPU time 778.21 seconds
Started Feb 09 06:51:04 AM UTC 25
Finished Feb 09 07:04:11 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827215659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3827215659
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_loopback.2277348750
Short name T474
Test name
Test status
Simulation time 9666697504 ps
CPU time 36.94 seconds
Started Feb 09 06:50:59 AM UTC 25
Finished Feb 09 06:51:37 AM UTC 25
Peak memory 208436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277348750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 16.uart_loopback.2277348750
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_noise_filter.1664703554
Short name T492
Test name
Test status
Simulation time 87550261887 ps
CPU time 229.28 seconds
Started Feb 09 06:50:48 AM UTC 25
Finished Feb 09 06:54:41 AM UTC 25
Peak memory 207128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664703554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.uart_noise_filter.1664703554
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_perf.1595248774
Short name T493
Test name
Test status
Simulation time 14243493025 ps
CPU time 234.08 seconds
Started Feb 09 06:51:01 AM UTC 25
Finished Feb 09 06:54:58 AM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595248774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 16.uart_perf.1595248774
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_rx_oversample.713741817
Short name T466
Test name
Test status
Simulation time 3631333271 ps
CPU time 7.89 seconds
Started Feb 09 06:50:42 AM UTC 25
Finished Feb 09 06:50:51 AM UTC 25
Peak memory 207060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713741817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.713741817
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.613552198
Short name T542
Test name
Test status
Simulation time 113252170790 ps
CPU time 481.46 seconds
Started Feb 09 06:50:52 AM UTC 25
Finished Feb 09 06:59:00 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613552198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity
_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.uart_rx_parity_err.613552198
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.916750076
Short name T317
Test name
Test status
Simulation time 2488657256 ps
CPU time 9.06 seconds
Started Feb 09 06:50:52 AM UTC 25
Finished Feb 09 06:51:03 AM UTC 25
Peak memory 204724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916750076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_
bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 16.uart_rx_start_bit_filter.916750076
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_smoke.3402060979
Short name T463
Test name
Test status
Simulation time 709286944 ps
CPU time 2.19 seconds
Started Feb 09 06:50:35 AM UTC 25
Finished Feb 09 06:50:38 AM UTC 25
Peak memory 207324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402060979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.uart_smoke.3402060979
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_stress_all.201446080
Short name T381
Test name
Test status
Simulation time 97634425697 ps
CPU time 194.03 seconds
Started Feb 09 06:51:06 AM UTC 25
Finished Feb 09 06:54:24 AM UTC 25
Peak memory 208516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201446080 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.201446080
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.2278021576
Short name T39
Test name
Test status
Simulation time 317894132410 ps
CPU time 601.35 seconds
Started Feb 09 06:51:04 AM UTC 25
Finished Feb 09 07:01:13 AM UTC 25
Peak memory 235448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2278021576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2278021576
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.2785415672
Short name T470
Test name
Test status
Simulation time 6616699755 ps
CPU time 14.01 seconds
Started Feb 09 06:50:57 AM UTC 25
Finished Feb 09 06:51:12 AM UTC 25
Peak memory 208248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785415672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.uart_tx_ovrd.2785415672
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_tx_rx.1889574243
Short name T348
Test name
Test status
Simulation time 40988103888 ps
CPU time 94.9 seconds
Started Feb 09 06:50:36 AM UTC 25
Finished Feb 09 06:52:13 AM UTC 25
Peak memory 208440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889574243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.uart_tx_rx.1889574243
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/16.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/160.uart_fifo_reset.1535751401
Short name T262
Test name
Test status
Simulation time 106114114963 ps
CPU time 28.21 seconds
Started Feb 09 07:30:02 AM UTC 25
Finished Feb 09 07:30:32 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535751401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 160.uart_fifo_reset.1535751401
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/160.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/161.uart_fifo_reset.2663635528
Short name T281
Test name
Test status
Simulation time 21458021910 ps
CPU time 38.45 seconds
Started Feb 09 07:30:05 AM UTC 25
Finished Feb 09 07:30:45 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663635528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 161.uart_fifo_reset.2663635528
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/161.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/163.uart_fifo_reset.355215229
Short name T1025
Test name
Test status
Simulation time 6980101975 ps
CPU time 17.42 seconds
Started Feb 09 07:30:20 AM UTC 25
Finished Feb 09 07:30:40 AM UTC 25
Peak memory 208088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355215229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 163.uart_fifo_reset.355215229
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/163.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/165.uart_fifo_reset.2499144746
Short name T1098
Test name
Test status
Simulation time 90711785198 ps
CPU time 235.07 seconds
Started Feb 09 07:30:21 AM UTC 25
Finished Feb 09 07:34:20 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499144746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 165.uart_fifo_reset.2499144746
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/165.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/167.uart_fifo_reset.3657080088
Short name T1037
Test name
Test status
Simulation time 53871423097 ps
CPU time 52.69 seconds
Started Feb 09 07:30:31 AM UTC 25
Finished Feb 09 07:31:25 AM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657080088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 167.uart_fifo_reset.3657080088
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/167.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/168.uart_fifo_reset.964533968
Short name T1028
Test name
Test status
Simulation time 12213978150 ps
CPU time 14.47 seconds
Started Feb 09 07:30:33 AM UTC 25
Finished Feb 09 07:30:48 AM UTC 25
Peak memory 208624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964533968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 168.uart_fifo_reset.964533968
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/168.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/169.uart_fifo_reset.3860730226
Short name T1057
Test name
Test status
Simulation time 66500575871 ps
CPU time 110.68 seconds
Started Feb 09 07:30:37 AM UTC 25
Finished Feb 09 07:32:30 AM UTC 25
Peak memory 208448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860730226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 169.uart_fifo_reset.3860730226
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/169.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_alert_test.3263860219
Short name T477
Test name
Test status
Simulation time 14078349 ps
CPU time 0.8 seconds
Started Feb 09 06:52:02 AM UTC 25
Finished Feb 09 06:52:04 AM UTC 25
Peak memory 203836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263860219 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3263860219
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_fifo_full.3493684950
Short name T379
Test name
Test status
Simulation time 28582426540 ps
CPU time 10.86 seconds
Started Feb 09 06:51:13 AM UTC 25
Finished Feb 09 06:51:26 AM UTC 25
Peak memory 208416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493684950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 17.uart_fifo_full.3493684950
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.3767614721
Short name T166
Test name
Test status
Simulation time 45413892740 ps
CPU time 40.43 seconds
Started Feb 09 06:51:22 AM UTC 25
Finished Feb 09 06:52:04 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767614721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.uart_fifo_overflow.3767614721
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_intr.2185283083
Short name T475
Test name
Test status
Simulation time 5581942584 ps
CPU time 15.07 seconds
Started Feb 09 06:51:25 AM UTC 25
Finished Feb 09 06:51:42 AM UTC 25
Peak memory 204864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185283083 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.uart_intr.2185283083
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.3335153183
Short name T382
Test name
Test status
Simulation time 29900849317 ps
CPU time 105.47 seconds
Started Feb 09 06:51:48 AM UTC 25
Finished Feb 09 06:53:35 AM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335153183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3335153183
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_loopback.2414126287
Short name T480
Test name
Test status
Simulation time 6027622233 ps
CPU time 24.81 seconds
Started Feb 09 06:51:45 AM UTC 25
Finished Feb 09 06:52:11 AM UTC 25
Peak memory 207256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414126287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 17.uart_loopback.2414126287
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_noise_filter.4065325011
Short name T423
Test name
Test status
Simulation time 8202966397 ps
CPU time 18.28 seconds
Started Feb 09 06:51:26 AM UTC 25
Finished Feb 09 06:51:46 AM UTC 25
Peak memory 207048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065325011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 17.uart_noise_filter.4065325011
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_perf.3315691752
Short name T975
Test name
Test status
Simulation time 31468707757 ps
CPU time 2074.43 seconds
Started Feb 09 06:51:47 AM UTC 25
Finished Feb 09 07:26:43 AM UTC 25
Peak memory 212204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315691752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 17.uart_perf.3315691752
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_rx_oversample.2736955891
Short name T478
Test name
Test status
Simulation time 4333450969 ps
CPU time 41.48 seconds
Started Feb 09 06:51:23 AM UTC 25
Finished Feb 09 06:52:06 AM UTC 25
Peak memory 207144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736955891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2736955891
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.3617853395
Short name T127
Test name
Test status
Simulation time 174568590416 ps
CPU time 147.99 seconds
Started Feb 09 06:51:42 AM UTC 25
Finished Feb 09 06:54:12 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617853395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.uart_rx_parity_err.3617853395
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.2338682370
Short name T360
Test name
Test status
Simulation time 653189161 ps
CPU time 1.85 seconds
Started Feb 09 06:51:37 AM UTC 25
Finished Feb 09 06:51:41 AM UTC 25
Peak memory 204344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338682370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2338682370
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_smoke.618228495
Short name T391
Test name
Test status
Simulation time 5909506212 ps
CPU time 43.17 seconds
Started Feb 09 06:51:13 AM UTC 25
Finished Feb 09 06:51:58 AM UTC 25
Peak memory 208344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618228495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 17.uart_smoke.618228495
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_stress_all.2375730079
Short name T139
Test name
Test status
Simulation time 340264725846 ps
CPU time 306.66 seconds
Started Feb 09 06:52:02 AM UTC 25
Finished Feb 09 06:57:13 AM UTC 25
Peak memory 217020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375730079 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2375730079
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.1393586725
Short name T398
Test name
Test status
Simulation time 59540944106 ps
CPU time 678.78 seconds
Started Feb 09 06:51:59 AM UTC 25
Finished Feb 09 07:03:26 AM UTC 25
Peak memory 217520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1393586725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1393586725
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.2266723295
Short name T476
Test name
Test status
Simulation time 380357431 ps
CPU time 3.09 seconds
Started Feb 09 06:51:43 AM UTC 25
Finished Feb 09 06:51:47 AM UTC 25
Peak memory 208360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266723295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.uart_tx_ovrd.2266723295
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_tx_rx.3194153774
Short name T494
Test name
Test status
Simulation time 54177539095 ps
CPU time 222.12 seconds
Started Feb 09 06:51:13 AM UTC 25
Finished Feb 09 06:54:59 AM UTC 25
Peak memory 208576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194153774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.uart_tx_rx.3194153774
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/17.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/170.uart_fifo_reset.1833640852
Short name T242
Test name
Test status
Simulation time 17903168835 ps
CPU time 28.46 seconds
Started Feb 09 07:30:39 AM UTC 25
Finished Feb 09 07:31:09 AM UTC 25
Peak memory 208216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833640852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 170.uart_fifo_reset.1833640852
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/170.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/171.uart_fifo_reset.1813752941
Short name T275
Test name
Test status
Simulation time 23654602199 ps
CPU time 27.89 seconds
Started Feb 09 07:30:41 AM UTC 25
Finished Feb 09 07:31:10 AM UTC 25
Peak memory 208384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813752941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 171.uart_fifo_reset.1813752941
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/171.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/172.uart_fifo_reset.1647658522
Short name T218
Test name
Test status
Simulation time 68332283150 ps
CPU time 50.54 seconds
Started Feb 09 07:30:42 AM UTC 25
Finished Feb 09 07:31:34 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647658522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 172.uart_fifo_reset.1647658522
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/172.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/173.uart_fifo_reset.973315456
Short name T1030
Test name
Test status
Simulation time 11177476910 ps
CPU time 20.19 seconds
Started Feb 09 07:30:45 AM UTC 25
Finished Feb 09 07:31:07 AM UTC 25
Peak memory 208660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973315456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 173.uart_fifo_reset.973315456
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/173.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/174.uart_fifo_reset.2870212302
Short name T1038
Test name
Test status
Simulation time 56886925077 ps
CPU time 45.86 seconds
Started Feb 09 07:30:46 AM UTC 25
Finished Feb 09 07:31:34 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870212302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 174.uart_fifo_reset.2870212302
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/174.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/175.uart_fifo_reset.3787658581
Short name T1034
Test name
Test status
Simulation time 15572257758 ps
CPU time 30.6 seconds
Started Feb 09 07:30:48 AM UTC 25
Finished Feb 09 07:31:20 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787658581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 175.uart_fifo_reset.3787658581
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/175.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/176.uart_fifo_reset.413618432
Short name T1047
Test name
Test status
Simulation time 123661120230 ps
CPU time 71.84 seconds
Started Feb 09 07:30:49 AM UTC 25
Finished Feb 09 07:32:03 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413618432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 176.uart_fifo_reset.413618432
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/176.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/177.uart_fifo_reset.293340281
Short name T1077
Test name
Test status
Simulation time 98981994795 ps
CPU time 150.18 seconds
Started Feb 09 07:31:02 AM UTC 25
Finished Feb 09 07:33:34 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293340281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 177.uart_fifo_reset.293340281
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/177.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/178.uart_fifo_reset.750962236
Short name T1035
Test name
Test status
Simulation time 56449286641 ps
CPU time 13.61 seconds
Started Feb 09 07:31:08 AM UTC 25
Finished Feb 09 07:31:23 AM UTC 25
Peak memory 207588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750962236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 178.uart_fifo_reset.750962236
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/178.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/179.uart_fifo_reset.74105750
Short name T1064
Test name
Test status
Simulation time 92163298323 ps
CPU time 109.81 seconds
Started Feb 09 07:31:10 AM UTC 25
Finished Feb 09 07:33:02 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74105750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 179.uart_fifo_reset.74105750
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/179.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_alert_test.2020651285
Short name T486
Test name
Test status
Simulation time 10848664 ps
CPU time 0.84 seconds
Started Feb 09 06:53:23 AM UTC 25
Finished Feb 09 06:53:25 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020651285 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2020651285
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_fifo_full.1806645851
Short name T177
Test name
Test status
Simulation time 63641268949 ps
CPU time 34.83 seconds
Started Feb 09 06:52:07 AM UTC 25
Finished Feb 09 06:52:44 AM UTC 25
Peak memory 208680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806645851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 18.uart_fifo_full.1806645851
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.4043367214
Short name T337
Test name
Test status
Simulation time 146788465752 ps
CPU time 58.08 seconds
Started Feb 09 06:52:10 AM UTC 25
Finished Feb 09 06:53:10 AM UTC 25
Peak memory 208404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043367214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.uart_fifo_overflow.4043367214
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_fifo_reset.2492167730
Short name T660
Test name
Test status
Simulation time 105081744996 ps
CPU time 845.09 seconds
Started Feb 09 06:52:12 AM UTC 25
Finished Feb 09 07:06:27 AM UTC 25
Peak memory 208708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492167730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 18.uart_fifo_reset.2492167730
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_intr.907304310
Short name T358
Test name
Test status
Simulation time 14238541081 ps
CPU time 64.76 seconds
Started Feb 09 06:52:16 AM UTC 25
Finished Feb 09 06:53:23 AM UTC 25
Peak memory 207840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907304310 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.uart_intr.907304310
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.987312447
Short name T579
Test name
Test status
Simulation time 49438218526 ps
CPU time 509.18 seconds
Started Feb 09 06:52:57 AM UTC 25
Finished Feb 09 07:01:32 AM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987312447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.987312447
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_loopback.2296129008
Short name T484
Test name
Test status
Simulation time 3037063824 ps
CPU time 5.52 seconds
Started Feb 09 06:52:50 AM UTC 25
Finished Feb 09 06:52:56 AM UTC 25
Peak memory 207172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296129008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 18.uart_loopback.2296129008
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_noise_filter.3723363617
Short name T392
Test name
Test status
Simulation time 54329516570 ps
CPU time 65.94 seconds
Started Feb 09 06:52:17 AM UTC 25
Finished Feb 09 06:53:25 AM UTC 25
Peak memory 208620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723363617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.uart_noise_filter.3723363617
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_perf.2421339012
Short name T534
Test name
Test status
Simulation time 10333315366 ps
CPU time 327.61 seconds
Started Feb 09 06:52:52 AM UTC 25
Finished Feb 09 06:58:24 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421339012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 18.uart_perf.2421339012
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_rx_oversample.1054876484
Short name T482
Test name
Test status
Simulation time 6136379603 ps
CPU time 16.2 seconds
Started Feb 09 06:52:13 AM UTC 25
Finished Feb 09 06:52:31 AM UTC 25
Peak memory 207412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054876484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1054876484
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.1683667102
Short name T121
Test name
Test status
Simulation time 90024156180 ps
CPU time 73.33 seconds
Started Feb 09 06:52:38 AM UTC 25
Finished Feb 09 06:53:53 AM UTC 25
Peak memory 208252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683667102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.uart_rx_parity_err.1683667102
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.4002948602
Short name T483
Test name
Test status
Simulation time 3917980317 ps
CPU time 4.45 seconds
Started Feb 09 06:52:32 AM UTC 25
Finished Feb 09 06:52:37 AM UTC 25
Peak memory 204800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002948602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 18.uart_rx_start_bit_filter.4002948602
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_smoke.332083872
Short name T481
Test name
Test status
Simulation time 6250736418 ps
CPU time 10.06 seconds
Started Feb 09 06:52:05 AM UTC 25
Finished Feb 09 06:52:16 AM UTC 25
Peak memory 207976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332083872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 18.uart_smoke.332083872
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_stress_all.4048977990
Short name T387
Test name
Test status
Simulation time 176561580890 ps
CPU time 151.42 seconds
Started Feb 09 06:53:11 AM UTC 25
Finished Feb 09 06:55:45 AM UTC 25
Peak memory 208680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048977990 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.4048977990
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.2033322352
Short name T395
Test name
Test status
Simulation time 143793136322 ps
CPU time 593.27 seconds
Started Feb 09 06:53:02 AM UTC 25
Finished Feb 09 07:03:03 AM UTC 25
Peak memory 217524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2033322352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2033322352
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.1863221404
Short name T368
Test name
Test status
Simulation time 3737854958 ps
CPU time 3.46 seconds
Started Feb 09 06:52:45 AM UTC 25
Finished Feb 09 06:52:49 AM UTC 25
Peak memory 207892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863221404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.uart_tx_ovrd.1863221404
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_tx_rx.262003711
Short name T485
Test name
Test status
Simulation time 33349075050 ps
CPU time 55.02 seconds
Started Feb 09 06:52:05 AM UTC 25
Finished Feb 09 06:53:02 AM UTC 25
Peak memory 208432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262003711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 18.uart_tx_rx.262003711
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/18.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/180.uart_fifo_reset.3354971160
Short name T1049
Test name
Test status
Simulation time 30296370655 ps
CPU time 54.15 seconds
Started Feb 09 07:31:10 AM UTC 25
Finished Feb 09 07:32:06 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354971160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 180.uart_fifo_reset.3354971160
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/180.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/181.uart_fifo_reset.650480493
Short name T243
Test name
Test status
Simulation time 73458276827 ps
CPU time 52.25 seconds
Started Feb 09 07:31:12 AM UTC 25
Finished Feb 09 07:32:06 AM UTC 25
Peak memory 208560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650480493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 181.uart_fifo_reset.650480493
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/181.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/182.uart_fifo_reset.956819996
Short name T1043
Test name
Test status
Simulation time 74608489537 ps
CPU time 33.65 seconds
Started Feb 09 07:31:14 AM UTC 25
Finished Feb 09 07:31:49 AM UTC 25
Peak memory 208560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956819996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 182.uart_fifo_reset.956819996
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/182.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/183.uart_fifo_reset.1842612954
Short name T1042
Test name
Test status
Simulation time 29656392699 ps
CPU time 31.5 seconds
Started Feb 09 07:31:14 AM UTC 25
Finished Feb 09 07:31:47 AM UTC 25
Peak memory 206788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842612954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 183.uart_fifo_reset.1842612954
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/183.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/184.uart_fifo_reset.3804742251
Short name T1061
Test name
Test status
Simulation time 153243071927 ps
CPU time 83.85 seconds
Started Feb 09 07:31:20 AM UTC 25
Finished Feb 09 07:32:46 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804742251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 184.uart_fifo_reset.3804742251
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/184.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/185.uart_fifo_reset.4155782291
Short name T1056
Test name
Test status
Simulation time 41759187644 ps
CPU time 66.82 seconds
Started Feb 09 07:31:20 AM UTC 25
Finished Feb 09 07:32:29 AM UTC 25
Peak memory 208352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155782291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 185.uart_fifo_reset.4155782291
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/185.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/187.uart_fifo_reset.337024176
Short name T1072
Test name
Test status
Simulation time 136620256153 ps
CPU time 111.61 seconds
Started Feb 09 07:31:24 AM UTC 25
Finished Feb 09 07:33:18 AM UTC 25
Peak memory 208392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337024176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 187.uart_fifo_reset.337024176
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/187.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/188.uart_fifo_reset.2369243857
Short name T1039
Test name
Test status
Simulation time 72996109435 ps
CPU time 14.5 seconds
Started Feb 09 07:31:24 AM UTC 25
Finished Feb 09 07:31:40 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369243857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 188.uart_fifo_reset.2369243857
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/188.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/189.uart_fifo_reset.3085315217
Short name T1055
Test name
Test status
Simulation time 65418086966 ps
CPU time 58.12 seconds
Started Feb 09 07:31:26 AM UTC 25
Finished Feb 09 07:32:27 AM UTC 25
Peak memory 208584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085315217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 189.uart_fifo_reset.3085315217
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/189.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_alert_test.2382071375
Short name T489
Test name
Test status
Simulation time 56310265 ps
CPU time 0.82 seconds
Started Feb 09 06:54:14 AM UTC 25
Finished Feb 09 06:54:16 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382071375 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2382071375
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_fifo_full.2440467185
Short name T541
Test name
Test status
Simulation time 105287022611 ps
CPU time 326.77 seconds
Started Feb 09 06:53:27 AM UTC 25
Finished Feb 09 06:58:58 AM UTC 25
Peak memory 208416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440467185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 19.uart_fifo_full.2440467185
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.2168791494
Short name T499
Test name
Test status
Simulation time 55478197926 ps
CPU time 104.74 seconds
Started Feb 09 06:53:28 AM UTC 25
Finished Feb 09 06:55:14 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168791494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.uart_fifo_overflow.2168791494
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_fifo_reset.3024365376
Short name T416
Test name
Test status
Simulation time 205671995225 ps
CPU time 254.49 seconds
Started Feb 09 06:53:37 AM UTC 25
Finished Feb 09 06:57:55 AM UTC 25
Peak memory 208588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024365376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 19.uart_fifo_reset.3024365376
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_intr.1383821419
Short name T568
Test name
Test status
Simulation time 271841333719 ps
CPU time 411.86 seconds
Started Feb 09 06:53:44 AM UTC 25
Finished Feb 09 07:00:40 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383821419 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.uart_intr.1383821419
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.2298148476
Short name T532
Test name
Test status
Simulation time 149124850015 ps
CPU time 237.9 seconds
Started Feb 09 06:54:12 AM UTC 25
Finished Feb 09 06:58:14 AM UTC 25
Peak memory 208500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298148476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2298148476
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_loopback.4035976154
Short name T488
Test name
Test status
Simulation time 8299977443 ps
CPU time 10.34 seconds
Started Feb 09 06:54:02 AM UTC 25
Finished Feb 09 06:54:14 AM UTC 25
Peak memory 207032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035976154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 19.uart_loopback.4035976154
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_noise_filter.4167350077
Short name T504
Test name
Test status
Simulation time 185736554233 ps
CPU time 117.99 seconds
Started Feb 09 06:53:46 AM UTC 25
Finished Feb 09 06:55:46 AM UTC 25
Peak memory 208072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167350077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.uart_noise_filter.4167350077
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_perf.284540245
Short name T758
Test name
Test status
Simulation time 20418964186 ps
CPU time 1055.05 seconds
Started Feb 09 06:54:10 AM UTC 25
Finished Feb 09 07:11:57 AM UTC 25
Peak memory 212076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284540245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 19.uart_perf.284540245
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_rx_oversample.2520396080
Short name T126
Test name
Test status
Simulation time 3304378590 ps
CPU time 31.99 seconds
Started Feb 09 06:53:38 AM UTC 25
Finished Feb 09 06:54:11 AM UTC 25
Peak memory 207056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520396080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2520396080
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.1522625495
Short name T490
Test name
Test status
Simulation time 29550676417 ps
CPU time 29.3 seconds
Started Feb 09 06:53:57 AM UTC 25
Finished Feb 09 06:54:28 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522625495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.uart_rx_parity_err.1522625495
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.1640376074
Short name T125
Test name
Test status
Simulation time 40055364626 ps
CPU time 13.96 seconds
Started Feb 09 06:53:54 AM UTC 25
Finished Feb 09 06:54:09 AM UTC 25
Peak memory 204928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640376074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1640376074
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_smoke.1376858269
Short name T487
Test name
Test status
Simulation time 338809809 ps
CPU time 1.47 seconds
Started Feb 09 06:53:25 AM UTC 25
Finished Feb 09 06:53:27 AM UTC 25
Peak memory 206468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376858269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.uart_smoke.1376858269
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_stress_all.3867682842
Short name T170
Test name
Test status
Simulation time 501182255385 ps
CPU time 766.84 seconds
Started Feb 09 06:54:14 AM UTC 25
Finished Feb 09 07:07:10 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867682842 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3867682842
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.775233588
Short name T677
Test name
Test status
Simulation time 64048268527 ps
CPU time 787.03 seconds
Started Feb 09 06:54:13 AM UTC 25
Finished Feb 09 07:07:29 AM UTC 25
Peak memory 225160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=775233588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.775233588
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.4093308386
Short name T124
Test name
Test status
Simulation time 954343548 ps
CPU time 2.09 seconds
Started Feb 09 06:53:58 AM UTC 25
Finished Feb 09 06:54:01 AM UTC 25
Peak memory 206996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093308386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.uart_tx_ovrd.4093308386
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_tx_rx.4204717126
Short name T497
Test name
Test status
Simulation time 41328966851 ps
CPU time 101.8 seconds
Started Feb 09 06:53:26 AM UTC 25
Finished Feb 09 06:55:09 AM UTC 25
Peak memory 208464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204717126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.uart_tx_rx.4204717126
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/19.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/190.uart_fifo_reset.3112811889
Short name T1093
Test name
Test status
Simulation time 49235110385 ps
CPU time 151.96 seconds
Started Feb 09 07:31:34 AM UTC 25
Finished Feb 09 07:34:09 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112811889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 190.uart_fifo_reset.3112811889
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/190.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/191.uart_fifo_reset.1785302357
Short name T1051
Test name
Test status
Simulation time 29044805608 ps
CPU time 31.21 seconds
Started Feb 09 07:31:35 AM UTC 25
Finished Feb 09 07:32:07 AM UTC 25
Peak memory 208400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785302357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 191.uart_fifo_reset.1785302357
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/191.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/192.uart_fifo_reset.4126551325
Short name T1050
Test name
Test status
Simulation time 39275742114 ps
CPU time 28.29 seconds
Started Feb 09 07:31:37 AM UTC 25
Finished Feb 09 07:32:06 AM UTC 25
Peak memory 208580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126551325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 192.uart_fifo_reset.4126551325
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/192.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/193.uart_fifo_reset.4137178950
Short name T1105
Test name
Test status
Simulation time 150424645231 ps
CPU time 178.66 seconds
Started Feb 09 07:31:41 AM UTC 25
Finished Feb 09 07:34:42 AM UTC 25
Peak memory 208400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137178950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 193.uart_fifo_reset.4137178950
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/193.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/194.uart_fifo_reset.2250349013
Short name T1052
Test name
Test status
Simulation time 35204445800 ps
CPU time 25.19 seconds
Started Feb 09 07:31:45 AM UTC 25
Finished Feb 09 07:32:12 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250349013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 194.uart_fifo_reset.2250349013
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/194.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/195.uart_fifo_reset.317709299
Short name T232
Test name
Test status
Simulation time 10781625344 ps
CPU time 23.17 seconds
Started Feb 09 07:31:47 AM UTC 25
Finished Feb 09 07:32:11 AM UTC 25
Peak memory 208420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317709299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 195.uart_fifo_reset.317709299
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/195.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/196.uart_fifo_reset.3286116698
Short name T1053
Test name
Test status
Simulation time 42032187773 ps
CPU time 23.04 seconds
Started Feb 09 07:31:49 AM UTC 25
Finished Feb 09 07:32:14 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286116698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 196.uart_fifo_reset.3286116698
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/196.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/197.uart_fifo_reset.639771268
Short name T1062
Test name
Test status
Simulation time 38402101255 ps
CPU time 54.64 seconds
Started Feb 09 07:31:51 AM UTC 25
Finished Feb 09 07:32:48 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639771268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 197.uart_fifo_reset.639771268
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/197.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/198.uart_fifo_reset.271297751
Short name T1065
Test name
Test status
Simulation time 34550279652 ps
CPU time 68.76 seconds
Started Feb 09 07:31:58 AM UTC 25
Finished Feb 09 07:33:09 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271297751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 198.uart_fifo_reset.271297751
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/198.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/199.uart_fifo_reset.1370346641
Short name T225
Test name
Test status
Simulation time 41693852475 ps
CPU time 88.51 seconds
Started Feb 09 07:32:00 AM UTC 25
Finished Feb 09 07:33:31 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370346641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 199.uart_fifo_reset.1370346641
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/199.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_alert_test.726888324
Short name T33
Test name
Test status
Simulation time 13823035 ps
CPU time 0.84 seconds
Started Feb 09 06:36:59 AM UTC 25
Finished Feb 09 06:37:02 AM UTC 25
Peak memory 204472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726888324 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.726888324
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_fifo_full.2255136470
Short name T108
Test name
Test status
Simulation time 11265118455 ps
CPU time 39.37 seconds
Started Feb 09 06:36:13 AM UTC 25
Finished Feb 09 06:36:54 AM UTC 25
Peak memory 208304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255136470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 2.uart_fifo_full.2255136470
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.3068859718
Short name T143
Test name
Test status
Simulation time 129968031711 ps
CPU time 56.61 seconds
Started Feb 09 06:36:15 AM UTC 25
Finished Feb 09 06:37:13 AM UTC 25
Peak memory 206912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068859718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.uart_fifo_overflow.3068859718
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_intr.2769598341
Short name T17
Test name
Test status
Simulation time 31087902228 ps
CPU time 23.06 seconds
Started Feb 09 06:36:25 AM UTC 25
Finished Feb 09 06:36:50 AM UTC 25
Peak memory 208444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769598341 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.uart_intr.2769598341
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_loopback.3088202143
Short name T22
Test name
Test status
Simulation time 11166382944 ps
CPU time 30.7 seconds
Started Feb 09 06:36:42 AM UTC 25
Finished Feb 09 06:37:15 AM UTC 25
Peak memory 208496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088202143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 2.uart_loopback.3088202143
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_perf.3146463203
Short name T324
Test name
Test status
Simulation time 9962098182 ps
CPU time 671.19 seconds
Started Feb 09 06:36:51 AM UTC 25
Finished Feb 09 06:48:10 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146463203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 2.uart_perf.3146463203
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_rx_oversample.222802637
Short name T19
Test name
Test status
Simulation time 5221442292 ps
CPU time 18.17 seconds
Started Feb 09 06:36:19 AM UTC 25
Finished Feb 09 06:36:39 AM UTC 25
Peak memory 207068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222802637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.222802637
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.3711598537
Short name T284
Test name
Test status
Simulation time 90561655563 ps
CPU time 100.24 seconds
Started Feb 09 06:36:39 AM UTC 25
Finished Feb 09 06:38:22 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711598537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.uart_rx_parity_err.3711598537
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.846469746
Short name T107
Test name
Test status
Simulation time 2692321134 ps
CPU time 3.47 seconds
Started Feb 09 06:36:35 AM UTC 25
Finished Feb 09 06:36:41 AM UTC 25
Peak memory 204800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846469746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_
bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 2.uart_rx_start_bit_filter.846469746
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_sec_cm.5072634
Short name T31
Test name
Test status
Simulation time 246912905 ps
CPU time 1.01 seconds
Started Feb 09 06:36:56 AM UTC 25
Finished Feb 09 06:36:59 AM UTC 25
Peak memory 239200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5072634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_
TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.5072634
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_smoke.363149388
Short name T98
Test name
Test status
Simulation time 741058659 ps
CPU time 2.35 seconds
Started Feb 09 06:36:08 AM UTC 25
Finished Feb 09 06:36:12 AM UTC 25
Peak memory 206992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363149388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 2.uart_smoke.363149388
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_stress_all.2844322922
Short name T406
Test name
Test status
Simulation time 212429076377 ps
CPU time 2129.4 seconds
Started Feb 09 06:36:55 AM UTC 25
Finished Feb 09 07:12:46 AM UTC 25
Peak memory 212012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844322922 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2844322922
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.116547386
Short name T21
Test name
Test status
Simulation time 1199085104 ps
CPU time 8.94 seconds
Started Feb 09 06:36:41 AM UTC 25
Finished Feb 09 06:36:51 AM UTC 25
Peak memory 208152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116547386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.uart_tx_ovrd.116547386
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_tx_rx.2163455650
Short name T289
Test name
Test status
Simulation time 31076726867 ps
CPU time 51.53 seconds
Started Feb 09 06:36:12 AM UTC 25
Finished Feb 09 06:37:05 AM UTC 25
Peak memory 207736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163455650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.uart_tx_rx.2163455650
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_alert_test.2125748823
Short name T500
Test name
Test status
Simulation time 15607022 ps
CPU time 0.82 seconds
Started Feb 09 06:55:14 AM UTC 25
Finished Feb 09 06:55:16 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125748823 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2125748823
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_fifo_full.2550747526
Short name T340
Test name
Test status
Simulation time 74896975891 ps
CPU time 86.07 seconds
Started Feb 09 06:54:29 AM UTC 25
Finished Feb 09 06:55:57 AM UTC 25
Peak memory 208580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550747526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 20.uart_fifo_full.2550747526
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.3086512076
Short name T503
Test name
Test status
Simulation time 76796718847 ps
CPU time 55.26 seconds
Started Feb 09 06:54:33 AM UTC 25
Finished Feb 09 06:55:30 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086512076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 20.uart_fifo_overflow.3086512076
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_fifo_reset.2541797643
Short name T539
Test name
Test status
Simulation time 57816794247 ps
CPU time 239.28 seconds
Started Feb 09 06:54:42 AM UTC 25
Finished Feb 09 06:58:45 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541797643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 20.uart_fifo_reset.2541797643
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_intr.3784217701
Short name T560
Test name
Test status
Simulation time 258051764534 ps
CPU time 322.57 seconds
Started Feb 09 06:54:47 AM UTC 25
Finished Feb 09 07:00:13 AM UTC 25
Peak memory 208460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784217701 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.uart_intr.3784217701
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.4291530742
Short name T710
Test name
Test status
Simulation time 78086123668 ps
CPU time 829.67 seconds
Started Feb 09 06:55:10 AM UTC 25
Finished Feb 09 07:09:10 AM UTC 25
Peak memory 212152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291530742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.4291530742
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_loopback.1467679898
Short name T501
Test name
Test status
Simulation time 7342174333 ps
CPU time 19.35 seconds
Started Feb 09 06:55:04 AM UTC 25
Finished Feb 09 06:55:25 AM UTC 25
Peak memory 207236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467679898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 20.uart_loopback.1467679898
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_noise_filter.3476715757
Short name T562
Test name
Test status
Simulation time 160686781782 ps
CPU time 315.84 seconds
Started Feb 09 06:54:59 AM UTC 25
Finished Feb 09 07:00:19 AM UTC 25
Peak memory 207868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476715757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 20.uart_noise_filter.3476715757
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_perf.1363466433
Short name T527
Test name
Test status
Simulation time 18895670575 ps
CPU time 151.24 seconds
Started Feb 09 06:55:09 AM UTC 25
Finished Feb 09 06:57:43 AM UTC 25
Peak memory 208608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363466433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 20.uart_perf.1363466433
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_rx_oversample.2573091044
Short name T495
Test name
Test status
Simulation time 5928003341 ps
CPU time 17.13 seconds
Started Feb 09 06:54:45 AM UTC 25
Finished Feb 09 06:55:03 AM UTC 25
Peak memory 207636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573091044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2573091044
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.543232389
Short name T511
Test name
Test status
Simulation time 80657576655 ps
CPU time 59.25 seconds
Started Feb 09 06:55:00 AM UTC 25
Finished Feb 09 06:56:01 AM UTC 25
Peak memory 208460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543232389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity
_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 20.uart_rx_parity_err.543232389
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.1428969825
Short name T496
Test name
Test status
Simulation time 2198547495 ps
CPU time 3.11 seconds
Started Feb 09 06:54:59 AM UTC 25
Finished Feb 09 06:55:03 AM UTC 25
Peak memory 204928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428969825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1428969825
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_smoke.4073915208
Short name T491
Test name
Test status
Simulation time 5684204276 ps
CPU time 12.99 seconds
Started Feb 09 06:54:17 AM UTC 25
Finished Feb 09 06:54:32 AM UTC 25
Peak memory 208224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073915208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.uart_smoke.4073915208
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_stress_all.665270805
Short name T415
Test name
Test status
Simulation time 516107553158 ps
CPU time 543.81 seconds
Started Feb 09 06:55:12 AM UTC 25
Finished Feb 09 07:04:22 AM UTC 25
Peak memory 219476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665270805 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.665270805
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.1970259761
Short name T418
Test name
Test status
Simulation time 329800774819 ps
CPU time 1011.96 seconds
Started Feb 09 06:55:10 AM UTC 25
Finished Feb 09 07:12:13 AM UTC 25
Peak memory 238912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1970259761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1970259761
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.1853993036
Short name T386
Test name
Test status
Simulation time 6329754398 ps
CPU time 2.94 seconds
Started Feb 09 06:55:04 AM UTC 25
Finished Feb 09 06:55:08 AM UTC 25
Peak memory 207472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853993036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.uart_tx_ovrd.1853993036
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_tx_rx.2169390270
Short name T378
Test name
Test status
Simulation time 104710578518 ps
CPU time 293.28 seconds
Started Feb 09 06:54:25 AM UTC 25
Finished Feb 09 06:59:22 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169390270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.uart_tx_rx.2169390270
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/20.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/200.uart_fifo_reset.1664042672
Short name T277
Test name
Test status
Simulation time 61776927250 ps
CPU time 68.85 seconds
Started Feb 09 07:32:02 AM UTC 25
Finished Feb 09 07:33:13 AM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664042672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 200.uart_fifo_reset.1664042672
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/200.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/201.uart_fifo_reset.4251983455
Short name T1058
Test name
Test status
Simulation time 14338341042 ps
CPU time 26.32 seconds
Started Feb 09 07:32:04 AM UTC 25
Finished Feb 09 07:32:32 AM UTC 25
Peak memory 208084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251983455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 201.uart_fifo_reset.4251983455
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/201.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3066870272
Short name T1120
Test name
Test status
Simulation time 99268637411 ps
CPU time 182.46 seconds
Started Feb 09 07:32:04 AM UTC 25
Finished Feb 09 07:35:10 AM UTC 25
Peak memory 208036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066870272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 202.uart_fifo_reset.3066870272
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/202.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/203.uart_fifo_reset.3972996599
Short name T1060
Test name
Test status
Simulation time 43993231769 ps
CPU time 29.05 seconds
Started Feb 09 07:32:05 AM UTC 25
Finished Feb 09 07:32:36 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972996599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 203.uart_fifo_reset.3972996599
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/203.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/204.uart_fifo_reset.3747000377
Short name T1112
Test name
Test status
Simulation time 68194112517 ps
CPU time 163.07 seconds
Started Feb 09 07:32:06 AM UTC 25
Finished Feb 09 07:34:52 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747000377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 204.uart_fifo_reset.3747000377
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/204.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/205.uart_fifo_reset.200064153
Short name T1059
Test name
Test status
Simulation time 8913687899 ps
CPU time 25.61 seconds
Started Feb 09 07:32:07 AM UTC 25
Finished Feb 09 07:32:33 AM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200064153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 205.uart_fifo_reset.200064153
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/205.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/206.uart_fifo_reset.4285764653
Short name T1068
Test name
Test status
Simulation time 35370708439 ps
CPU time 64.92 seconds
Started Feb 09 07:32:07 AM UTC 25
Finished Feb 09 07:33:13 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285764653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 206.uart_fifo_reset.4285764653
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/206.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2951213332
Short name T1080
Test name
Test status
Simulation time 37238005436 ps
CPU time 86.62 seconds
Started Feb 09 07:32:08 AM UTC 25
Finished Feb 09 07:33:36 AM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951213332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 207.uart_fifo_reset.2951213332
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/207.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/208.uart_fifo_reset.658873986
Short name T1114
Test name
Test status
Simulation time 88606489749 ps
CPU time 166.31 seconds
Started Feb 09 07:32:09 AM UTC 25
Finished Feb 09 07:34:58 AM UTC 25
Peak memory 208320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658873986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 208.uart_fifo_reset.658873986
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/208.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/209.uart_fifo_reset.2777762565
Short name T1119
Test name
Test status
Simulation time 73222974211 ps
CPU time 175.1 seconds
Started Feb 09 07:32:12 AM UTC 25
Finished Feb 09 07:35:10 AM UTC 25
Peak memory 208580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777762565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 209.uart_fifo_reset.2777762565
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/209.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_alert_test.1211361515
Short name T510
Test name
Test status
Simulation time 18852495 ps
CPU time 0.82 seconds
Started Feb 09 06:55:59 AM UTC 25
Finished Feb 09 06:56:01 AM UTC 25
Peak memory 202484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211361515 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1211361515
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_fifo_full.2716416594
Short name T513
Test name
Test status
Simulation time 98431015277 ps
CPU time 46.6 seconds
Started Feb 09 06:55:26 AM UTC 25
Finished Feb 09 06:56:14 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716416594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 21.uart_fifo_full.2716416594
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.1652686356
Short name T526
Test name
Test status
Simulation time 119242449862 ps
CPU time 125.19 seconds
Started Feb 09 06:55:29 AM UTC 25
Finished Feb 09 06:57:37 AM UTC 25
Peak memory 208428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652686356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.uart_fifo_overflow.1652686356
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_fifo_reset.3053820202
Short name T273
Test name
Test status
Simulation time 51478866127 ps
CPU time 36.86 seconds
Started Feb 09 06:55:30 AM UTC 25
Finished Feb 09 06:56:09 AM UTC 25
Peak memory 208420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053820202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 21.uart_fifo_reset.3053820202
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_intr.1661398173
Short name T570
Test name
Test status
Simulation time 334034649038 ps
CPU time 302.7 seconds
Started Feb 09 06:55:40 AM UTC 25
Finished Feb 09 07:00:46 AM UTC 25
Peak memory 208516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661398173 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.uart_intr.1661398173
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.2833971254
Short name T584
Test name
Test status
Simulation time 116839743312 ps
CPU time 354.92 seconds
Started Feb 09 06:55:57 AM UTC 25
Finished Feb 09 07:01:56 AM UTC 25
Peak memory 208288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833971254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2833971254
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_loopback.3760556831
Short name T509
Test name
Test status
Simulation time 5181177054 ps
CPU time 2.23 seconds
Started Feb 09 06:55:55 AM UTC 25
Finished Feb 09 06:55:58 AM UTC 25
Peak memory 207116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760556831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 21.uart_loopback.3760556831
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_noise_filter.818374693
Short name T521
Test name
Test status
Simulation time 17461959588 ps
CPU time 68.4 seconds
Started Feb 09 06:55:46 AM UTC 25
Finished Feb 09 06:56:56 AM UTC 25
Peak memory 208648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818374693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fil
ter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.uart_noise_filter.818374693
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_perf.2651862445
Short name T515
Test name
Test status
Simulation time 7266478236 ps
CPU time 21.07 seconds
Started Feb 09 06:55:56 AM UTC 25
Finished Feb 09 06:56:18 AM UTC 25
Peak memory 208608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651862445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 21.uart_perf.2651862445
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_rx_oversample.370946954
Short name T508
Test name
Test status
Simulation time 6937798004 ps
CPU time 22.96 seconds
Started Feb 09 06:55:31 AM UTC 25
Finished Feb 09 06:55:56 AM UTC 25
Peak memory 208208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370946954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.370946954
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.2825441872
Short name T506
Test name
Test status
Simulation time 2583091059 ps
CPU time 6.39 seconds
Started Feb 09 06:55:47 AM UTC 25
Finished Feb 09 06:55:55 AM UTC 25
Peak memory 204928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825441872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2825441872
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_smoke.3148119358
Short name T502
Test name
Test status
Simulation time 5479257962 ps
CPU time 10.85 seconds
Started Feb 09 06:55:16 AM UTC 25
Finished Feb 09 06:55:28 AM UTC 25
Peak memory 207600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148119358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.uart_smoke.3148119358
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_stress_all.1666027822
Short name T600
Test name
Test status
Simulation time 386748098747 ps
CPU time 407.76 seconds
Started Feb 09 06:55:58 AM UTC 25
Finished Feb 09 07:02:51 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666027822 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1666027822
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.3958985281
Short name T396
Test name
Test status
Simulation time 410750081395 ps
CPU time 1442.75 seconds
Started Feb 09 06:55:57 AM UTC 25
Finished Feb 09 07:20:16 AM UTC 25
Peak memory 236572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3958985281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3958985281
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.4162243197
Short name T507
Test name
Test status
Simulation time 1238755871 ps
CPU time 2.71 seconds
Started Feb 09 06:55:51 AM UTC 25
Finished Feb 09 06:55:56 AM UTC 25
Peak memory 208508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162243197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.uart_tx_ovrd.4162243197
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_tx_rx.226139457
Short name T505
Test name
Test status
Simulation time 70169314879 ps
CPU time 35.53 seconds
Started Feb 09 06:55:17 AM UTC 25
Finished Feb 09 06:55:54 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226139457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 21.uart_tx_rx.226139457
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/21.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/210.uart_fifo_reset.1640282071
Short name T1066
Test name
Test status
Simulation time 123279452227 ps
CPU time 56.83 seconds
Started Feb 09 07:32:13 AM UTC 25
Finished Feb 09 07:33:11 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640282071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 210.uart_fifo_reset.1640282071
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/210.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/211.uart_fifo_reset.2567786276
Short name T1089
Test name
Test status
Simulation time 59971506598 ps
CPU time 101.77 seconds
Started Feb 09 07:32:14 AM UTC 25
Finished Feb 09 07:33:58 AM UTC 25
Peak memory 208648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567786276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 211.uart_fifo_reset.2567786276
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/211.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/212.uart_fifo_reset.3136824680
Short name T1086
Test name
Test status
Simulation time 143860857849 ps
CPU time 93.62 seconds
Started Feb 09 07:32:15 AM UTC 25
Finished Feb 09 07:33:51 AM UTC 25
Peak memory 208340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136824680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 212.uart_fifo_reset.3136824680
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/212.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/213.uart_fifo_reset.1600215739
Short name T249
Test name
Test status
Simulation time 84581410163 ps
CPU time 139.95 seconds
Started Feb 09 07:32:28 AM UTC 25
Finished Feb 09 07:34:51 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600215739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 213.uart_fifo_reset.1600215739
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/213.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/215.uart_fifo_reset.1635493034
Short name T1067
Test name
Test status
Simulation time 189796045608 ps
CPU time 39.91 seconds
Started Feb 09 07:32:31 AM UTC 25
Finished Feb 09 07:33:13 AM UTC 25
Peak memory 208404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635493034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 215.uart_fifo_reset.1635493034
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/215.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/216.uart_fifo_reset.1618499941
Short name T1082
Test name
Test status
Simulation time 26320878658 ps
CPU time 66.19 seconds
Started Feb 09 07:32:32 AM UTC 25
Finished Feb 09 07:33:40 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618499941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 216.uart_fifo_reset.1618499941
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/216.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/217.uart_fifo_reset.3705060886
Short name T1170
Test name
Test status
Simulation time 265599509195 ps
CPU time 397.98 seconds
Started Feb 09 07:32:33 AM UTC 25
Finished Feb 09 07:39:16 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705060886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 217.uart_fifo_reset.3705060886
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/217.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1993734109
Short name T1073
Test name
Test status
Simulation time 22737993769 ps
CPU time 43.79 seconds
Started Feb 09 07:32:34 AM UTC 25
Finished Feb 09 07:33:20 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993734109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 218.uart_fifo_reset.1993734109
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/218.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/219.uart_fifo_reset.2490683273
Short name T1070
Test name
Test status
Simulation time 35839620387 ps
CPU time 37.53 seconds
Started Feb 09 07:32:36 AM UTC 25
Finished Feb 09 07:33:15 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490683273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 219.uart_fifo_reset.2490683273
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/219.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_alert_test.2655207578
Short name T523
Test name
Test status
Simulation time 104031743 ps
CPU time 0.84 seconds
Started Feb 09 06:57:13 AM UTC 25
Finished Feb 09 06:57:15 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655207578 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2655207578
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_fifo_full.2403558317
Short name T520
Test name
Test status
Simulation time 45124352023 ps
CPU time 47.51 seconds
Started Feb 09 06:56:05 AM UTC 25
Finished Feb 09 06:56:54 AM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403558317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 22.uart_fifo_full.2403558317
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.1564191388
Short name T577
Test name
Test status
Simulation time 233796277965 ps
CPU time 299.64 seconds
Started Feb 09 06:56:10 AM UTC 25
Finished Feb 09 07:01:14 AM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564191388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.uart_fifo_overflow.1564191388
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_fifo_reset.1118730029
Short name T202
Test name
Test status
Simulation time 31794568012 ps
CPU time 113.06 seconds
Started Feb 09 06:56:15 AM UTC 25
Finished Feb 09 06:58:11 AM UTC 25
Peak memory 208588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118730029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 22.uart_fifo_reset.1118730029
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_intr.2809552447
Short name T516
Test name
Test status
Simulation time 31723525445 ps
CPU time 6.08 seconds
Started Feb 09 06:56:19 AM UTC 25
Finished Feb 09 06:56:27 AM UTC 25
Peak memory 206800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809552447 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.uart_intr.2809552447
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.596658696
Short name T545
Test name
Test status
Simulation time 66970620917 ps
CPU time 139.02 seconds
Started Feb 09 06:56:55 AM UTC 25
Finished Feb 09 06:59:16 AM UTC 25
Peak memory 208672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596658696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.596658696
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_loopback.3132725889
Short name T519
Test name
Test status
Simulation time 6826974845 ps
CPU time 7.03 seconds
Started Feb 09 06:56:44 AM UTC 25
Finished Feb 09 06:56:52 AM UTC 25
Peak memory 208464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132725889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 22.uart_loopback.3132725889
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_noise_filter.1004057370
Short name T529
Test name
Test status
Simulation time 85353041751 ps
CPU time 100.02 seconds
Started Feb 09 06:56:19 AM UTC 25
Finished Feb 09 06:58:01 AM UTC 25
Peak memory 217448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004057370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 22.uart_noise_filter.1004057370
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_perf.4099198382
Short name T642
Test name
Test status
Simulation time 9634223995 ps
CPU time 496.65 seconds
Started Feb 09 06:56:53 AM UTC 25
Finished Feb 09 07:05:15 AM UTC 25
Peak memory 208412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099198382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 22.uart_perf.4099198382
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_rx_oversample.3005591614
Short name T528
Test name
Test status
Simulation time 7377755374 ps
CPU time 86.83 seconds
Started Feb 09 06:56:15 AM UTC 25
Finished Feb 09 06:57:44 AM UTC 25
Peak memory 207616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005591614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3005591614
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.337708373
Short name T522
Test name
Test status
Simulation time 74288994995 ps
CPU time 22.12 seconds
Started Feb 09 06:56:34 AM UTC 25
Finished Feb 09 06:56:57 AM UTC 25
Peak memory 208324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337708373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity
_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 22.uart_rx_parity_err.337708373
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.2129340872
Short name T517
Test name
Test status
Simulation time 1919834707 ps
CPU time 3.77 seconds
Started Feb 09 06:56:27 AM UTC 25
Finished Feb 09 06:56:32 AM UTC 25
Peak memory 204672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129340872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2129340872
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_smoke.871739525
Short name T512
Test name
Test status
Simulation time 124591805 ps
CPU time 1.67 seconds
Started Feb 09 06:56:02 AM UTC 25
Finished Feb 09 06:56:05 AM UTC 25
Peak memory 206412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871739525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 22.uart_smoke.871739525
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_stress_all.2332785715
Short name T524
Test name
Test status
Simulation time 8395248959 ps
CPU time 16.05 seconds
Started Feb 09 06:56:58 AM UTC 25
Finished Feb 09 06:57:15 AM UTC 25
Peak memory 208372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332785715 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2332785715
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.716850516
Short name T117
Test name
Test status
Simulation time 301529528870 ps
CPU time 664.1 seconds
Started Feb 09 06:56:57 AM UTC 25
Finished Feb 09 07:08:09 AM UTC 25
Peak memory 239388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=716850516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.716850516
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.4105071230
Short name T518
Test name
Test status
Simulation time 1575806141 ps
CPU time 3.4 seconds
Started Feb 09 06:56:39 AM UTC 25
Finished Feb 09 06:56:43 AM UTC 25
Peak memory 207548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105071230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.uart_tx_ovrd.4105071230
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_tx_rx.39212030
Short name T514
Test name
Test status
Simulation time 12841851306 ps
CPU time 14.86 seconds
Started Feb 09 06:56:02 AM UTC 25
Finished Feb 09 06:56:18 AM UTC 25
Peak memory 206780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39212030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 22.uart_tx_rx.39212030
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/22.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/220.uart_fifo_reset.1968068355
Short name T1090
Test name
Test status
Simulation time 151120585116 ps
CPU time 74.14 seconds
Started Feb 09 07:32:47 AM UTC 25
Finished Feb 09 07:34:02 AM UTC 25
Peak memory 208352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968068355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 220.uart_fifo_reset.1968068355
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/220.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/221.uart_fifo_reset.1173419303
Short name T1125
Test name
Test status
Simulation time 57895092623 ps
CPU time 145.92 seconds
Started Feb 09 07:32:49 AM UTC 25
Finished Feb 09 07:35:17 AM UTC 25
Peak memory 208252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173419303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 221.uart_fifo_reset.1173419303
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/221.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/222.uart_fifo_reset.3553766783
Short name T1076
Test name
Test status
Simulation time 84117011832 ps
CPU time 42.33 seconds
Started Feb 09 07:32:49 AM UTC 25
Finished Feb 09 07:33:32 AM UTC 25
Peak memory 208424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553766783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 222.uart_fifo_reset.3553766783
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/222.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/223.uart_fifo_reset.3082031888
Short name T1075
Test name
Test status
Simulation time 47276465504 ps
CPU time 29.18 seconds
Started Feb 09 07:32:54 AM UTC 25
Finished Feb 09 07:33:24 AM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082031888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 223.uart_fifo_reset.3082031888
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/223.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/224.uart_fifo_reset.323287742
Short name T1087
Test name
Test status
Simulation time 68116878272 ps
CPU time 53.17 seconds
Started Feb 09 07:32:58 AM UTC 25
Finished Feb 09 07:33:53 AM UTC 25
Peak memory 208404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323287742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 224.uart_fifo_reset.323287742
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/224.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/225.uart_fifo_reset.2648638435
Short name T1088
Test name
Test status
Simulation time 14902788631 ps
CPU time 48.39 seconds
Started Feb 09 07:33:03 AM UTC 25
Finished Feb 09 07:33:53 AM UTC 25
Peak memory 208416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648638435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 225.uart_fifo_reset.2648638435
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/225.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/226.uart_fifo_reset.1730595143
Short name T1079
Test name
Test status
Simulation time 41197638321 ps
CPU time 27.19 seconds
Started Feb 09 07:33:07 AM UTC 25
Finished Feb 09 07:33:36 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730595143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 226.uart_fifo_reset.1730595143
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/226.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/227.uart_fifo_reset.1652787282
Short name T1094
Test name
Test status
Simulation time 14548660138 ps
CPU time 58.87 seconds
Started Feb 09 07:33:09 AM UTC 25
Finished Feb 09 07:34:10 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652787282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 227.uart_fifo_reset.1652787282
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/227.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/228.uart_fifo_reset.968427787
Short name T1143
Test name
Test status
Simulation time 103050872610 ps
CPU time 153.26 seconds
Started Feb 09 07:33:12 AM UTC 25
Finished Feb 09 07:35:48 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968427787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 228.uart_fifo_reset.968427787
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/228.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/229.uart_fifo_reset.2415127226
Short name T278
Test name
Test status
Simulation time 24826866019 ps
CPU time 22.08 seconds
Started Feb 09 07:33:13 AM UTC 25
Finished Feb 09 07:33:37 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415127226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 229.uart_fifo_reset.2415127226
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/229.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_alert_test.1898108522
Short name T537
Test name
Test status
Simulation time 20465445 ps
CPU time 0.85 seconds
Started Feb 09 06:58:28 AM UTC 25
Finished Feb 09 06:58:30 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898108522 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1898108522
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_fifo_full.3073168200
Short name T196
Test name
Test status
Simulation time 40342084500 ps
CPU time 28.36 seconds
Started Feb 09 06:57:20 AM UTC 25
Finished Feb 09 06:57:50 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073168200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 23.uart_fifo_full.3073168200
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.2404488475
Short name T582
Test name
Test status
Simulation time 159293144923 ps
CPU time 250.94 seconds
Started Feb 09 06:57:37 AM UTC 25
Finished Feb 09 07:01:52 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404488475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.uart_fifo_overflow.2404488475
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_fifo_reset.3108611994
Short name T245
Test name
Test status
Simulation time 66625100526 ps
CPU time 104.48 seconds
Started Feb 09 06:57:45 AM UTC 25
Finished Feb 09 06:59:31 AM UTC 25
Peak memory 208504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108611994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 23.uart_fifo_reset.3108611994
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_intr.2812651813
Short name T536
Test name
Test status
Simulation time 42408273906 ps
CPU time 35.22 seconds
Started Feb 09 06:57:51 AM UTC 25
Finished Feb 09 06:58:27 AM UTC 25
Peak memory 207000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812651813 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.uart_intr.2812651813
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.3503137485
Short name T763
Test name
Test status
Simulation time 87168700767 ps
CPU time 825.37 seconds
Started Feb 09 06:58:15 AM UTC 25
Finished Feb 09 07:12:11 AM UTC 25
Peak memory 211884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503137485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3503137485
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_loopback.1638865159
Short name T533
Test name
Test status
Simulation time 4184894865 ps
CPU time 9.2 seconds
Started Feb 09 06:58:12 AM UTC 25
Finished Feb 09 06:58:22 AM UTC 25
Peak memory 207496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638865159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 23.uart_loopback.1638865159
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_noise_filter.3967193905
Short name T547
Test name
Test status
Simulation time 190798609861 ps
CPU time 89.74 seconds
Started Feb 09 06:57:57 AM UTC 25
Finished Feb 09 06:59:28 AM UTC 25
Peak memory 208680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967193905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 23.uart_noise_filter.3967193905
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_perf.1893094192
Short name T976
Test name
Test status
Simulation time 29814226443 ps
CPU time 1704.83 seconds
Started Feb 09 06:58:13 AM UTC 25
Finished Feb 09 07:26:55 AM UTC 25
Peak memory 212076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893094192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 23.uart_perf.1893094192
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_rx_oversample.4167051877
Short name T543
Test name
Test status
Simulation time 8012608687 ps
CPU time 77.95 seconds
Started Feb 09 06:57:45 AM UTC 25
Finished Feb 09 06:59:04 AM UTC 25
Peak memory 208208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167051877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.4167051877
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.2293450289
Short name T670
Test name
Test status
Simulation time 106746654011 ps
CPU time 552.71 seconds
Started Feb 09 06:58:03 AM UTC 25
Finished Feb 09 07:07:22 AM UTC 25
Peak memory 208424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293450289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.uart_rx_parity_err.2293450289
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.1213331829
Short name T530
Test name
Test status
Simulation time 4664297308 ps
CPU time 6.98 seconds
Started Feb 09 06:57:57 AM UTC 25
Finished Feb 09 06:58:05 AM UTC 25
Peak memory 204800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213331829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1213331829
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_smoke.4005418238
Short name T525
Test name
Test status
Simulation time 447018075 ps
CPU time 1.51 seconds
Started Feb 09 06:57:16 AM UTC 25
Finished Feb 09 06:57:19 AM UTC 25
Peak memory 207272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005418238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.uart_smoke.4005418238
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_stress_all.2414062501
Short name T572
Test name
Test status
Simulation time 159917164037 ps
CPU time 154.04 seconds
Started Feb 09 06:58:25 AM UTC 25
Finished Feb 09 07:01:02 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414062501 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2414062501
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.750675200
Short name T115
Test name
Test status
Simulation time 47178115644 ps
CPU time 440.29 seconds
Started Feb 09 06:58:23 AM UTC 25
Finished Feb 09 07:05:49 AM UTC 25
Peak memory 217492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=750675200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.750675200
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.1265747627
Short name T531
Test name
Test status
Simulation time 1750502956 ps
CPU time 5.66 seconds
Started Feb 09 06:58:06 AM UTC 25
Finished Feb 09 06:58:13 AM UTC 25
Peak memory 206864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265747627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.uart_tx_ovrd.1265747627
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_tx_rx.3414355845
Short name T540
Test name
Test status
Simulation time 63767399391 ps
CPU time 99.05 seconds
Started Feb 09 06:57:16 AM UTC 25
Finished Feb 09 06:58:58 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414355845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.uart_tx_rx.3414355845
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/23.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3100757579
Short name T1111
Test name
Test status
Simulation time 194135052636 ps
CPU time 95.21 seconds
Started Feb 09 07:33:14 AM UTC 25
Finished Feb 09 07:34:51 AM UTC 25
Peak memory 208436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100757579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 230.uart_fifo_reset.3100757579
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/230.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/232.uart_fifo_reset.2698935690
Short name T1097
Test name
Test status
Simulation time 23525493203 ps
CPU time 60.97 seconds
Started Feb 09 07:33:15 AM UTC 25
Finished Feb 09 07:34:18 AM UTC 25
Peak memory 208404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698935690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 232.uart_fifo_reset.2698935690
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/232.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2687334523
Short name T1092
Test name
Test status
Simulation time 186792001652 ps
CPU time 47.3 seconds
Started Feb 09 07:33:16 AM UTC 25
Finished Feb 09 07:34:05 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687334523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 233.uart_fifo_reset.2687334523
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/233.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/235.uart_fifo_reset.3897303068
Short name T1081
Test name
Test status
Simulation time 33069934368 ps
CPU time 17.02 seconds
Started Feb 09 07:33:19 AM UTC 25
Finished Feb 09 07:33:38 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897303068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 235.uart_fifo_reset.3897303068
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/235.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/236.uart_fifo_reset.143858372
Short name T1085
Test name
Test status
Simulation time 39528292498 ps
CPU time 28.73 seconds
Started Feb 09 07:33:21 AM UTC 25
Finished Feb 09 07:33:51 AM UTC 25
Peak memory 208420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143858372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 236.uart_fifo_reset.143858372
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/236.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/237.uart_fifo_reset.2653930021
Short name T1148
Test name
Test status
Simulation time 86668503869 ps
CPU time 160.92 seconds
Started Feb 09 07:33:25 AM UTC 25
Finished Feb 09 07:36:08 AM UTC 25
Peak memory 208444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653930021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 237.uart_fifo_reset.2653930021
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/237.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/238.uart_fifo_reset.1905785415
Short name T1095
Test name
Test status
Simulation time 24629267778 ps
CPU time 51.03 seconds
Started Feb 09 07:33:25 AM UTC 25
Finished Feb 09 07:34:17 AM UTC 25
Peak memory 208416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905785415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 238.uart_fifo_reset.1905785415
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/238.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/239.uart_fifo_reset.698459910
Short name T269
Test name
Test status
Simulation time 16733140881 ps
CPU time 31.61 seconds
Started Feb 09 07:33:32 AM UTC 25
Finished Feb 09 07:34:05 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698459910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 239.uart_fifo_reset.698459910
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/239.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_alert_test.275277498
Short name T550
Test name
Test status
Simulation time 12383474 ps
CPU time 0.86 seconds
Started Feb 09 06:59:47 AM UTC 25
Finished Feb 09 06:59:49 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275277498 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.275277498
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_fifo_full.331592763
Short name T554
Test name
Test status
Simulation time 69690786939 ps
CPU time 77.08 seconds
Started Feb 09 06:58:32 AM UTC 25
Finished Feb 09 06:59:51 AM UTC 25
Peak memory 208516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331592763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 24.uart_fifo_full.331592763
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.3902552583
Short name T552
Test name
Test status
Simulation time 12655334765 ps
CPU time 62.58 seconds
Started Feb 09 06:58:45 AM UTC 25
Finished Feb 09 06:59:50 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902552583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.uart_fifo_overflow.3902552583
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_intr.2293341302
Short name T561
Test name
Test status
Simulation time 95798653832 ps
CPU time 73.5 seconds
Started Feb 09 06:59:01 AM UTC 25
Finished Feb 09 07:00:16 AM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293341302 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.uart_intr.2293341302
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.1835635431
Short name T594
Test name
Test status
Simulation time 56493766205 ps
CPU time 184.19 seconds
Started Feb 09 06:59:29 AM UTC 25
Finished Feb 09 07:02:36 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835635431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1835635431
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_loopback.3065978692
Short name T548
Test name
Test status
Simulation time 8640591311 ps
CPU time 17.11 seconds
Started Feb 09 06:59:22 AM UTC 25
Finished Feb 09 06:59:40 AM UTC 25
Peak memory 207508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065978692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 24.uart_loopback.3065978692
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_noise_filter.1723249165
Short name T551
Test name
Test status
Simulation time 45763684065 ps
CPU time 43.35 seconds
Started Feb 09 06:59:05 AM UTC 25
Finished Feb 09 06:59:50 AM UTC 25
Peak memory 208604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723249165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 24.uart_noise_filter.1723249165
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_perf.2643680580
Short name T610
Test name
Test status
Simulation time 22215856974 ps
CPU time 234.94 seconds
Started Feb 09 06:59:23 AM UTC 25
Finished Feb 09 07:03:22 AM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643680580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 24.uart_perf.2643680580
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_rx_oversample.2898962984
Short name T558
Test name
Test status
Simulation time 6558565913 ps
CPU time 60.71 seconds
Started Feb 09 06:58:59 AM UTC 25
Finished Feb 09 07:00:01 AM UTC 25
Peak memory 208260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898962984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2898962984
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.2463683861
Short name T614
Test name
Test status
Simulation time 324562214062 ps
CPU time 258.01 seconds
Started Feb 09 06:59:15 AM UTC 25
Finished Feb 09 07:03:37 AM UTC 25
Peak memory 208596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463683861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.uart_rx_parity_err.2463683861
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.2827615193
Short name T544
Test name
Test status
Simulation time 7026947856 ps
CPU time 6.95 seconds
Started Feb 09 06:59:06 AM UTC 25
Finished Feb 09 06:59:14 AM UTC 25
Peak memory 206848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827615193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2827615193
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_smoke.2408838600
Short name T538
Test name
Test status
Simulation time 672127344 ps
CPU time 2.12 seconds
Started Feb 09 06:58:28 AM UTC 25
Finished Feb 09 06:58:32 AM UTC 25
Peak memory 207492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408838600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.uart_smoke.2408838600
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_stress_all.3026718354
Short name T596
Test name
Test status
Simulation time 44650046289 ps
CPU time 179.01 seconds
Started Feb 09 06:59:41 AM UTC 25
Finished Feb 09 07:02:43 AM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026718354 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3026718354
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.1492387268
Short name T881
Test name
Test status
Simulation time 87006594430 ps
CPU time 1098.02 seconds
Started Feb 09 06:59:32 AM UTC 25
Finished Feb 09 07:18:03 AM UTC 25
Peak memory 224540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1492387268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1492387268
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.2568470047
Short name T546
Test name
Test status
Simulation time 1291710912 ps
CPU time 3.86 seconds
Started Feb 09 06:59:17 AM UTC 25
Finished Feb 09 06:59:22 AM UTC 25
Peak memory 207128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568470047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.uart_tx_ovrd.2568470047
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_tx_rx.990647591
Short name T553
Test name
Test status
Simulation time 46335287516 ps
CPU time 76.79 seconds
Started Feb 09 06:58:31 AM UTC 25
Finished Feb 09 06:59:50 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990647591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 24.uart_tx_rx.990647591
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/24.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/240.uart_fifo_reset.837202133
Short name T1084
Test name
Test status
Simulation time 18534846551 ps
CPU time 9.59 seconds
Started Feb 09 07:33:33 AM UTC 25
Finished Feb 09 07:33:44 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837202133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 240.uart_fifo_reset.837202133
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/240.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/241.uart_fifo_reset.4036255487
Short name T1131
Test name
Test status
Simulation time 43177577854 ps
CPU time 111.25 seconds
Started Feb 09 07:33:35 AM UTC 25
Finished Feb 09 07:35:29 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036255487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 241.uart_fifo_reset.4036255487
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/241.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/242.uart_fifo_reset.2468010377
Short name T1091
Test name
Test status
Simulation time 27274995553 ps
CPU time 28.32 seconds
Started Feb 09 07:33:35 AM UTC 25
Finished Feb 09 07:34:05 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468010377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 242.uart_fifo_reset.2468010377
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/242.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/243.uart_fifo_reset.3402416612
Short name T1160
Test name
Test status
Simulation time 128952276809 ps
CPU time 217.27 seconds
Started Feb 09 07:33:36 AM UTC 25
Finished Feb 09 07:37:17 AM UTC 25
Peak memory 208648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402416612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 243.uart_fifo_reset.3402416612
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/243.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/244.uart_fifo_reset.3127010315
Short name T1118
Test name
Test status
Simulation time 29619370671 ps
CPU time 86.43 seconds
Started Feb 09 07:33:37 AM UTC 25
Finished Feb 09 07:35:06 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127010315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 244.uart_fifo_reset.3127010315
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/244.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/245.uart_fifo_reset.1424062695
Short name T1100
Test name
Test status
Simulation time 26546013577 ps
CPU time 53.27 seconds
Started Feb 09 07:33:37 AM UTC 25
Finished Feb 09 07:34:32 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424062695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 245.uart_fifo_reset.1424062695
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/245.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/246.uart_fifo_reset.606139273
Short name T1139
Test name
Test status
Simulation time 96056969835 ps
CPU time 119.97 seconds
Started Feb 09 07:33:38 AM UTC 25
Finished Feb 09 07:35:40 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606139273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 246.uart_fifo_reset.606139273
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/246.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/247.uart_fifo_reset.3521478734
Short name T1054
Test name
Test status
Simulation time 110548284068 ps
CPU time 20.65 seconds
Started Feb 09 07:33:41 AM UTC 25
Finished Feb 09 07:34:03 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521478734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 247.uart_fifo_reset.3521478734
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/247.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3476682810
Short name T1107
Test name
Test status
Simulation time 18365992707 ps
CPU time 63.22 seconds
Started Feb 09 07:33:41 AM UTC 25
Finished Feb 09 07:34:46 AM UTC 25
Peak memory 208392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476682810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 248.uart_fifo_reset.3476682810
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/248.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/249.uart_fifo_reset.440490418
Short name T1116
Test name
Test status
Simulation time 153947884299 ps
CPU time 78.06 seconds
Started Feb 09 07:33:44 AM UTC 25
Finished Feb 09 07:35:04 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440490418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 249.uart_fifo_reset.440490418
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/249.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_alert_test.4056822704
Short name T564
Test name
Test status
Simulation time 51475527 ps
CPU time 0.84 seconds
Started Feb 09 07:00:27 AM UTC 25
Finished Feb 09 07:00:28 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056822704 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.4056822704
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_fifo_full.4203286720
Short name T178
Test name
Test status
Simulation time 87374280003 ps
CPU time 73.61 seconds
Started Feb 09 06:59:51 AM UTC 25
Finished Feb 09 07:01:07 AM UTC 25
Peak memory 208396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203286720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 25.uart_fifo_full.4203286720
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.3869765877
Short name T567
Test name
Test status
Simulation time 58396777875 ps
CPU time 42.01 seconds
Started Feb 09 06:59:51 AM UTC 25
Finished Feb 09 07:00:35 AM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869765877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 25.uart_fifo_overflow.3869765877
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_fifo_reset.972505876
Short name T581
Test name
Test status
Simulation time 27762698986 ps
CPU time 106.54 seconds
Started Feb 09 06:59:51 AM UTC 25
Finished Feb 09 07:01:40 AM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972505876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 25.uart_fifo_reset.972505876
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_intr.86112971
Short name T563
Test name
Test status
Simulation time 25719619094 ps
CPU time 29.18 seconds
Started Feb 09 06:59:55 AM UTC 25
Finished Feb 09 07:00:26 AM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86112971 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.uart_intr.86112971
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.2274245867
Short name T654
Test name
Test status
Simulation time 59429673701 ps
CPU time 340.31 seconds
Started Feb 09 07:00:17 AM UTC 25
Finished Feb 09 07:06:02 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274245867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2274245867
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_loopback.1116243729
Short name T565
Test name
Test status
Simulation time 3129341629 ps
CPU time 12.81 seconds
Started Feb 09 07:00:15 AM UTC 25
Finished Feb 09 07:00:30 AM UTC 25
Peak memory 206548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116243729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 25.uart_loopback.1116243729
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_noise_filter.2154366711
Short name T411
Test name
Test status
Simulation time 20823681464 ps
CPU time 19.01 seconds
Started Feb 09 06:59:56 AM UTC 25
Finished Feb 09 07:00:16 AM UTC 25
Peak memory 204936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154366711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.uart_noise_filter.2154366711
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_perf.2583396330
Short name T802
Test name
Test status
Simulation time 29654444693 ps
CPU time 815.43 seconds
Started Feb 09 07:00:17 AM UTC 25
Finished Feb 09 07:14:02 AM UTC 25
Peak memory 212044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583396330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 25.uart_perf.2583396330
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_rx_oversample.624664010
Short name T566
Test name
Test status
Simulation time 6596835478 ps
CPU time 37.97 seconds
Started Feb 09 06:59:52 AM UTC 25
Finished Feb 09 07:00:31 AM UTC 25
Peak memory 207060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624664010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.624664010
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.176137730
Short name T576
Test name
Test status
Simulation time 96694444786 ps
CPU time 54.28 seconds
Started Feb 09 07:00:02 AM UTC 25
Finished Feb 09 07:01:10 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176137730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity
_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.uart_rx_parity_err.176137730
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.2424014018
Short name T559
Test name
Test status
Simulation time 5119100784 ps
CPU time 5.64 seconds
Started Feb 09 06:59:59 AM UTC 25
Finished Feb 09 07:00:06 AM UTC 25
Peak memory 204728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424014018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2424014018
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_smoke.2921825050
Short name T555
Test name
Test status
Simulation time 635523320 ps
CPU time 2.74 seconds
Started Feb 09 06:59:49 AM UTC 25
Finished Feb 09 06:59:53 AM UTC 25
Peak memory 206996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921825050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.uart_smoke.2921825050
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_stress_all.3751348913
Short name T668
Test name
Test status
Simulation time 216684556544 ps
CPU time 409.82 seconds
Started Feb 09 07:00:19 AM UTC 25
Finished Feb 09 07:07:14 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751348913 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3751348913
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.1343282954
Short name T118
Test name
Test status
Simulation time 54322026699 ps
CPU time 557.42 seconds
Started Feb 09 07:00:17 AM UTC 25
Finished Feb 09 07:09:42 AM UTC 25
Peak memory 225144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1343282954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1343282954
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.1451917875
Short name T569
Test name
Test status
Simulation time 12421083538 ps
CPU time 24.83 seconds
Started Feb 09 07:00:15 AM UTC 25
Finished Feb 09 07:00:42 AM UTC 25
Peak memory 208188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451917875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.uart_tx_ovrd.1451917875
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_tx_rx.3556066534
Short name T573
Test name
Test status
Simulation time 31845704593 ps
CPU time 72.1 seconds
Started Feb 09 06:59:51 AM UTC 25
Finished Feb 09 07:01:05 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556066534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.uart_tx_rx.3556066534
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/25.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/250.uart_fifo_reset.1888702378
Short name T237
Test name
Test status
Simulation time 19624196258 ps
CPU time 29.81 seconds
Started Feb 09 07:33:52 AM UTC 25
Finished Feb 09 07:34:23 AM UTC 25
Peak memory 208500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888702378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 250.uart_fifo_reset.1888702378
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/250.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/251.uart_fifo_reset.3147193294
Short name T1161
Test name
Test status
Simulation time 111555233264 ps
CPU time 206.66 seconds
Started Feb 09 07:33:52 AM UTC 25
Finished Feb 09 07:37:21 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147193294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 251.uart_fifo_reset.3147193294
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/251.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/252.uart_fifo_reset.779718605
Short name T1113
Test name
Test status
Simulation time 154668930839 ps
CPU time 61.16 seconds
Started Feb 09 07:33:54 AM UTC 25
Finished Feb 09 07:34:56 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779718605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 252.uart_fifo_reset.779718605
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/252.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/253.uart_fifo_reset.1392633141
Short name T1154
Test name
Test status
Simulation time 71983804807 ps
CPU time 152.52 seconds
Started Feb 09 07:33:54 AM UTC 25
Finished Feb 09 07:36:29 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392633141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 253.uart_fifo_reset.1392633141
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/253.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/254.uart_fifo_reset.1168590346
Short name T1102
Test name
Test status
Simulation time 114484256082 ps
CPU time 32.97 seconds
Started Feb 09 07:33:59 AM UTC 25
Finished Feb 09 07:34:33 AM UTC 25
Peak memory 207988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168590346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 254.uart_fifo_reset.1168590346
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/254.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/255.uart_fifo_reset.1000265338
Short name T1130
Test name
Test status
Simulation time 102927807841 ps
CPU time 82.44 seconds
Started Feb 09 07:34:04 AM UTC 25
Finished Feb 09 07:35:28 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000265338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 255.uart_fifo_reset.1000265338
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/255.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/256.uart_fifo_reset.3309000697
Short name T257
Test name
Test status
Simulation time 62036558132 ps
CPU time 36.69 seconds
Started Feb 09 07:34:04 AM UTC 25
Finished Feb 09 07:34:42 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309000697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 256.uart_fifo_reset.3309000697
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/256.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/257.uart_fifo_reset.1072862521
Short name T1103
Test name
Test status
Simulation time 60360048790 ps
CPU time 26.87 seconds
Started Feb 09 07:34:05 AM UTC 25
Finished Feb 09 07:34:33 AM UTC 25
Peak memory 208576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072862521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 257.uart_fifo_reset.1072862521
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/257.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/258.uart_fifo_reset.1545789775
Short name T1126
Test name
Test status
Simulation time 19842390979 ps
CPU time 71.36 seconds
Started Feb 09 07:34:05 AM UTC 25
Finished Feb 09 07:35:18 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545789775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 258.uart_fifo_reset.1545789775
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/258.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/259.uart_fifo_reset.2817702400
Short name T1101
Test name
Test status
Simulation time 30506040505 ps
CPU time 25.71 seconds
Started Feb 09 07:34:06 AM UTC 25
Finished Feb 09 07:34:33 AM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817702400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 259.uart_fifo_reset.2817702400
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/259.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_alert_test.3269890024
Short name T578
Test name
Test status
Simulation time 14220850 ps
CPU time 0.86 seconds
Started Feb 09 07:01:15 AM UTC 25
Finished Feb 09 07:01:17 AM UTC 25
Peak memory 202484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269890024 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3269890024
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_fifo_full.2986290590
Short name T175
Test name
Test status
Simulation time 84537586478 ps
CPU time 68.96 seconds
Started Feb 09 07:00:32 AM UTC 25
Finished Feb 09 07:01:43 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986290590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 26.uart_fifo_full.2986290590
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.985001342
Short name T627
Test name
Test status
Simulation time 135983865170 ps
CPU time 236.8 seconds
Started Feb 09 07:00:36 AM UTC 25
Finished Feb 09 07:04:36 AM UTC 25
Peak memory 208516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985001342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_over
flow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 26.uart_fifo_overflow.985001342
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_fifo_reset.3764853656
Short name T222
Test name
Test status
Simulation time 44663766144 ps
CPU time 72.5 seconds
Started Feb 09 07:00:41 AM UTC 25
Finished Feb 09 07:01:55 AM UTC 25
Peak memory 208624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764853656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 26.uart_fifo_reset.3764853656
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.404514948
Short name T637
Test name
Test status
Simulation time 106864124957 ps
CPU time 227.52 seconds
Started Feb 09 07:01:10 AM UTC 25
Finished Feb 09 07:05:01 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404514948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.404514948
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_loopback.967885190
Short name T575
Test name
Test status
Simulation time 1056690703 ps
CPU time 1.63 seconds
Started Feb 09 07:01:07 AM UTC 25
Finished Feb 09 07:01:10 AM UTC 25
Peak memory 206324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967885190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.uart_loopback.967885190
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_noise_filter.1322968018
Short name T589
Test name
Test status
Simulation time 151888637883 ps
CPU time 78.44 seconds
Started Feb 09 07:00:47 AM UTC 25
Finished Feb 09 07:02:07 AM UTC 25
Peak memory 217396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322968018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 26.uart_noise_filter.1322968018
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_perf.1719203330
Short name T664
Test name
Test status
Simulation time 15069090462 ps
CPU time 339.28 seconds
Started Feb 09 07:01:09 AM UTC 25
Finished Feb 09 07:06:54 AM UTC 25
Peak memory 208460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719203330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 26.uart_perf.1719203330
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_rx_oversample.2478865220
Short name T587
Test name
Test status
Simulation time 6271167772 ps
CPU time 79.89 seconds
Started Feb 09 07:00:43 AM UTC 25
Finished Feb 09 07:02:05 AM UTC 25
Peak memory 207560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478865220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2478865220
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.182782699
Short name T180
Test name
Test status
Simulation time 108865580299 ps
CPU time 381.9 seconds
Started Feb 09 07:01:02 AM UTC 25
Finished Feb 09 07:07:30 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182782699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity
_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 26.uart_rx_parity_err.182782699
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.148894554
Short name T607
Test name
Test status
Simulation time 50070221812 ps
CPU time 128.93 seconds
Started Feb 09 07:00:56 AM UTC 25
Finished Feb 09 07:03:07 AM UTC 25
Peak memory 206848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148894554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_
bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 26.uart_rx_start_bit_filter.148894554
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_smoke.3958598705
Short name T571
Test name
Test status
Simulation time 5393260165 ps
CPU time 15.46 seconds
Started Feb 09 07:00:30 AM UTC 25
Finished Feb 09 07:00:46 AM UTC 25
Peak memory 207660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958598705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.uart_smoke.3958598705
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_stress_all.360545576
Short name T699
Test name
Test status
Simulation time 214316896440 ps
CPU time 440.84 seconds
Started Feb 09 07:01:14 AM UTC 25
Finished Feb 09 07:08:40 AM UTC 25
Peak memory 217300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360545576 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.360545576
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.3272521717
Short name T736
Test name
Test status
Simulation time 163819309717 ps
CPU time 566.44 seconds
Started Feb 09 07:01:12 AM UTC 25
Finished Feb 09 07:10:45 AM UTC 25
Peak memory 219408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3272521717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3272521717
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.2072841996
Short name T574
Test name
Test status
Simulation time 492643355 ps
CPU time 2.05 seconds
Started Feb 09 07:01:05 AM UTC 25
Finished Feb 09 07:01:09 AM UTC 25
Peak memory 206992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072841996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.uart_tx_ovrd.2072841996
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_tx_rx.3049832423
Short name T595
Test name
Test status
Simulation time 81343761156 ps
CPU time 126.53 seconds
Started Feb 09 07:00:31 AM UTC 25
Finished Feb 09 07:02:40 AM UTC 25
Peak memory 208676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049832423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.uart_tx_rx.3049832423
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/260.uart_fifo_reset.3485405772
Short name T1122
Test name
Test status
Simulation time 21097969719 ps
CPU time 64.52 seconds
Started Feb 09 07:34:06 AM UTC 25
Finished Feb 09 07:35:12 AM UTC 25
Peak memory 207708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485405772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 260.uart_fifo_reset.3485405772
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/260.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/261.uart_fifo_reset.1557875770
Short name T252
Test name
Test status
Simulation time 144166727434 ps
CPU time 157.84 seconds
Started Feb 09 07:34:06 AM UTC 25
Finished Feb 09 07:36:47 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557875770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 261.uart_fifo_reset.1557875770
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/261.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/262.uart_fifo_reset.2354601697
Short name T1158
Test name
Test status
Simulation time 68930358549 ps
CPU time 165.35 seconds
Started Feb 09 07:34:10 AM UTC 25
Finished Feb 09 07:36:58 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354601697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 262.uart_fifo_reset.2354601697
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/262.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/263.uart_fifo_reset.2099669848
Short name T1149
Test name
Test status
Simulation time 65503664148 ps
CPU time 120.88 seconds
Started Feb 09 07:34:10 AM UTC 25
Finished Feb 09 07:36:13 AM UTC 25
Peak memory 208576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099669848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 263.uart_fifo_reset.2099669848
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/263.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/264.uart_fifo_reset.221119339
Short name T1165
Test name
Test status
Simulation time 111505415000 ps
CPU time 221.98 seconds
Started Feb 09 07:34:18 AM UTC 25
Finished Feb 09 07:38:04 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221119339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 264.uart_fifo_reset.221119339
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/264.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/265.uart_fifo_reset.4054785165
Short name T1104
Test name
Test status
Simulation time 33126864449 ps
CPU time 22.32 seconds
Started Feb 09 07:34:18 AM UTC 25
Finished Feb 09 07:34:42 AM UTC 25
Peak memory 208280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054785165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 265.uart_fifo_reset.4054785165
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/265.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/266.uart_fifo_reset.3609180268
Short name T1108
Test name
Test status
Simulation time 48121625050 ps
CPU time 27.57 seconds
Started Feb 09 07:34:18 AM UTC 25
Finished Feb 09 07:34:47 AM UTC 25
Peak memory 208600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609180268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 266.uart_fifo_reset.3609180268
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/266.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/267.uart_fifo_reset.293081910
Short name T1146
Test name
Test status
Simulation time 155845621190 ps
CPU time 99.87 seconds
Started Feb 09 07:34:20 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293081910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 267.uart_fifo_reset.293081910
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/267.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/268.uart_fifo_reset.3410639715
Short name T1140
Test name
Test status
Simulation time 50330603857 ps
CPU time 79.08 seconds
Started Feb 09 07:34:22 AM UTC 25
Finished Feb 09 07:35:43 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410639715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 268.uart_fifo_reset.3410639715
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/268.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/269.uart_fifo_reset.752716608
Short name T1106
Test name
Test status
Simulation time 67975095329 ps
CPU time 17.99 seconds
Started Feb 09 07:34:24 AM UTC 25
Finished Feb 09 07:34:43 AM UTC 25
Peak memory 208516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752716608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 269.uart_fifo_reset.752716608
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/269.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_alert_test.2180578650
Short name T590
Test name
Test status
Simulation time 20161361 ps
CPU time 0.82 seconds
Started Feb 09 07:02:06 AM UTC 25
Finished Feb 09 07:02:08 AM UTC 25
Peak memory 202484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180578650 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2180578650
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_fifo_full.3761335064
Short name T608
Test name
Test status
Simulation time 149016955851 ps
CPU time 93.66 seconds
Started Feb 09 07:01:33 AM UTC 25
Finished Feb 09 07:03:09 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761335064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 27.uart_fifo_full.3761335064
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.2255998995
Short name T198
Test name
Test status
Simulation time 62306401632 ps
CPU time 11.11 seconds
Started Feb 09 07:01:39 AM UTC 25
Finished Feb 09 07:01:51 AM UTC 25
Peak memory 207872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255998995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.uart_fifo_overflow.2255998995
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_intr.4286248692
Short name T603
Test name
Test status
Simulation time 45306470963 ps
CPU time 69.02 seconds
Started Feb 09 07:01:43 AM UTC 25
Finished Feb 09 07:02:54 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286248692 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.uart_intr.4286248692
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.2497037774
Short name T765
Test name
Test status
Simulation time 69816512697 ps
CPU time 608.27 seconds
Started Feb 09 07:01:58 AM UTC 25
Finished Feb 09 07:12:13 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497037774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2497037774
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_loopback.3804312294
Short name T588
Test name
Test status
Simulation time 1816528677 ps
CPU time 8.21 seconds
Started Feb 09 07:01:56 AM UTC 25
Finished Feb 09 07:02:05 AM UTC 25
Peak memory 206788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804312294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 27.uart_loopback.3804312294
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_noise_filter.963404653
Short name T412
Test name
Test status
Simulation time 85476956979 ps
CPU time 48.34 seconds
Started Feb 09 07:01:52 AM UTC 25
Finished Feb 09 07:02:42 AM UTC 25
Peak memory 217408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963404653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fil
ter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.uart_noise_filter.963404653
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_perf.3227410559
Short name T63
Test name
Test status
Simulation time 10106654451 ps
CPU time 485.78 seconds
Started Feb 09 07:01:57 AM UTC 25
Finished Feb 09 07:10:08 AM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227410559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 27.uart_perf.3227410559
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_rx_oversample.3738913795
Short name T583
Test name
Test status
Simulation time 3363450464 ps
CPU time 9.02 seconds
Started Feb 09 07:01:42 AM UTC 25
Finished Feb 09 07:01:52 AM UTC 25
Peak memory 207056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738913795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3738913795
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.797789783
Short name T592
Test name
Test status
Simulation time 37205210899 ps
CPU time 25.47 seconds
Started Feb 09 07:01:53 AM UTC 25
Finished Feb 09 07:02:20 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797789783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity
_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 27.uart_rx_parity_err.797789783
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.3079602871
Short name T585
Test name
Test status
Simulation time 1241183417 ps
CPU time 2.21 seconds
Started Feb 09 07:01:53 AM UTC 25
Finished Feb 09 07:01:57 AM UTC 25
Peak memory 204684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079602871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3079602871
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_smoke.2552651693
Short name T580
Test name
Test status
Simulation time 6012536077 ps
CPU time 19.38 seconds
Started Feb 09 07:01:18 AM UTC 25
Finished Feb 09 07:01:38 AM UTC 25
Peak memory 208424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552651693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.uart_smoke.2552651693
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_stress_all.2831448975
Short name T698
Test name
Test status
Simulation time 197464275403 ps
CPU time 386.62 seconds
Started Feb 09 07:02:06 AM UTC 25
Finished Feb 09 07:08:37 AM UTC 25
Peak memory 208504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831448975 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2831448975
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.1482256737
Short name T116
Test name
Test status
Simulation time 64048724350 ps
CPU time 274.51 seconds
Started Feb 09 07:02:04 AM UTC 25
Finished Feb 09 07:06:42 AM UTC 25
Peak memory 225156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1482256737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1482256737
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.3130877545
Short name T586
Test name
Test status
Simulation time 1266398557 ps
CPU time 8.12 seconds
Started Feb 09 07:01:53 AM UTC 25
Finished Feb 09 07:02:03 AM UTC 25
Peak memory 207112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130877545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.uart_tx_ovrd.3130877545
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_tx_rx.2428889556
Short name T591
Test name
Test status
Simulation time 65351463783 ps
CPU time 40.39 seconds
Started Feb 09 07:01:27 AM UTC 25
Finished Feb 09 07:02:09 AM UTC 25
Peak memory 208640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428889556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.uart_tx_rx.2428889556
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/27.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/270.uart_fifo_reset.835863678
Short name T256
Test name
Test status
Simulation time 203869379441 ps
CPU time 31.05 seconds
Started Feb 09 07:34:33 AM UTC 25
Finished Feb 09 07:35:05 AM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835863678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 270.uart_fifo_reset.835863678
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/270.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1644954501
Short name T1142
Test name
Test status
Simulation time 88314823195 ps
CPU time 71.88 seconds
Started Feb 09 07:34:34 AM UTC 25
Finished Feb 09 07:35:48 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644954501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 271.uart_fifo_reset.1644954501
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/271.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/272.uart_fifo_reset.466422021
Short name T1109
Test name
Test status
Simulation time 21378238302 ps
CPU time 14.35 seconds
Started Feb 09 07:34:34 AM UTC 25
Finished Feb 09 07:34:50 AM UTC 25
Peak memory 207924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466422021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 272.uart_fifo_reset.466422021
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/272.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/273.uart_fifo_reset.3361737401
Short name T1127
Test name
Test status
Simulation time 50433217590 ps
CPU time 43.73 seconds
Started Feb 09 07:34:34 AM UTC 25
Finished Feb 09 07:35:20 AM UTC 25
Peak memory 208596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361737401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 273.uart_fifo_reset.3361737401
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/273.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/274.uart_fifo_reset.2273868226
Short name T1124
Test name
Test status
Simulation time 20660243041 ps
CPU time 31 seconds
Started Feb 09 07:34:43 AM UTC 25
Finished Feb 09 07:35:16 AM UTC 25
Peak memory 208240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273868226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 274.uart_fifo_reset.2273868226
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/274.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/275.uart_fifo_reset.1052759112
Short name T1136
Test name
Test status
Simulation time 27718703531 ps
CPU time 52.57 seconds
Started Feb 09 07:34:43 AM UTC 25
Finished Feb 09 07:35:37 AM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052759112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 275.uart_fifo_reset.1052759112
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/275.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/276.uart_fifo_reset.796570711
Short name T1163
Test name
Test status
Simulation time 104272197066 ps
CPU time 171.02 seconds
Started Feb 09 07:34:43 AM UTC 25
Finished Feb 09 07:37:37 AM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796570711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 276.uart_fifo_reset.796570711
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/276.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/277.uart_fifo_reset.3495540721
Short name T1151
Test name
Test status
Simulation time 433708098964 ps
CPU time 92.71 seconds
Started Feb 09 07:34:44 AM UTC 25
Finished Feb 09 07:36:19 AM UTC 25
Peak memory 208620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495540721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 277.uart_fifo_reset.3495540721
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/277.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/278.uart_fifo_reset.2586801711
Short name T1117
Test name
Test status
Simulation time 46922979900 ps
CPU time 15.91 seconds
Started Feb 09 07:34:47 AM UTC 25
Finished Feb 09 07:35:05 AM UTC 25
Peak memory 208444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586801711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 278.uart_fifo_reset.2586801711
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/278.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2105816590
Short name T1157
Test name
Test status
Simulation time 132501289640 ps
CPU time 110.55 seconds
Started Feb 09 07:34:48 AM UTC 25
Finished Feb 09 07:36:42 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105816590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 279.uart_fifo_reset.2105816590
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/279.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_alert_test.504786181
Short name T605
Test name
Test status
Simulation time 111683771 ps
CPU time 0.84 seconds
Started Feb 09 07:02:58 AM UTC 25
Finished Feb 09 07:03:00 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504786181 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.504786181
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_fifo_full.2894719280
Short name T192
Test name
Test status
Simulation time 32062883516 ps
CPU time 18.64 seconds
Started Feb 09 07:02:10 AM UTC 25
Finished Feb 09 07:02:30 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894719280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 28.uart_fifo_full.2894719280
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.2033208573
Short name T713
Test name
Test status
Simulation time 124275735685 ps
CPU time 422.3 seconds
Started Feb 09 07:02:21 AM UTC 25
Finished Feb 09 07:09:29 AM UTC 25
Peak memory 208648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033208573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 28.uart_fifo_overflow.2033208573
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_fifo_reset.2926267498
Short name T253
Test name
Test status
Simulation time 23994965477 ps
CPU time 40.85 seconds
Started Feb 09 07:02:26 AM UTC 25
Finished Feb 09 07:03:08 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926267498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 28.uart_fifo_reset.2926267498
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_intr.1788182155
Short name T598
Test name
Test status
Simulation time 7717797951 ps
CPU time 9.56 seconds
Started Feb 09 07:02:37 AM UTC 25
Finished Feb 09 07:02:48 AM UTC 25
Peak memory 208528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788182155 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.uart_intr.1788182155
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.957730362
Short name T661
Test name
Test status
Simulation time 383239147176 ps
CPU time 213.06 seconds
Started Feb 09 07:02:52 AM UTC 25
Finished Feb 09 07:06:28 AM UTC 25
Peak memory 208436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957730362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.957730362
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_loopback.1024325158
Short name T606
Test name
Test status
Simulation time 3799724137 ps
CPU time 10.28 seconds
Started Feb 09 07:02:49 AM UTC 25
Finished Feb 09 07:03:00 AM UTC 25
Peak memory 204804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024325158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 28.uart_loopback.1024325158
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_noise_filter.1468028160
Short name T633
Test name
Test status
Simulation time 77142981435 ps
CPU time 128.62 seconds
Started Feb 09 07:02:40 AM UTC 25
Finished Feb 09 07:04:51 AM UTC 25
Peak memory 208228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468028160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 28.uart_noise_filter.1468028160
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_perf.3138153810
Short name T1016
Test name
Test status
Simulation time 31143506920 ps
CPU time 1616.85 seconds
Started Feb 09 07:02:51 AM UTC 25
Finished Feb 09 07:30:05 AM UTC 25
Peak memory 211944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138153810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 28.uart_perf.3138153810
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_rx_oversample.1237534199
Short name T597
Test name
Test status
Simulation time 2801983230 ps
CPU time 14.96 seconds
Started Feb 09 07:02:30 AM UTC 25
Finished Feb 09 07:02:46 AM UTC 25
Peak memory 207056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237534199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1237534199
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.995306102
Short name T613
Test name
Test status
Simulation time 54211332347 ps
CPU time 44.28 seconds
Started Feb 09 07:02:44 AM UTC 25
Finished Feb 09 07:03:30 AM UTC 25
Peak memory 208152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995306102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity
_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 28.uart_rx_parity_err.995306102
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.3548248070
Short name T604
Test name
Test status
Simulation time 5492388984 ps
CPU time 12.28 seconds
Started Feb 09 07:02:43 AM UTC 25
Finished Feb 09 07:02:57 AM UTC 25
Peak memory 206848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548248070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3548248070
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_smoke.3281437737
Short name T593
Test name
Test status
Simulation time 11633538854 ps
CPU time 15.96 seconds
Started Feb 09 07:02:08 AM UTC 25
Finished Feb 09 07:02:25 AM UTC 25
Peak memory 208432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281437737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.uart_smoke.3281437737
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_stress_all.3270310051
Short name T643
Test name
Test status
Simulation time 69356448623 ps
CPU time 140.44 seconds
Started Feb 09 07:02:55 AM UTC 25
Finished Feb 09 07:05:18 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270310051 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3270310051
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.927400408
Short name T397
Test name
Test status
Simulation time 4973339837 ps
CPU time 83.54 seconds
Started Feb 09 07:02:54 AM UTC 25
Finished Feb 09 07:04:19 AM UTC 25
Peak memory 217296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=927400408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.927400408
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.4207854283
Short name T602
Test name
Test status
Simulation time 1118171453 ps
CPU time 3.48 seconds
Started Feb 09 07:02:48 AM UTC 25
Finished Feb 09 07:02:53 AM UTC 25
Peak memory 206912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207854283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.uart_tx_ovrd.4207854283
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_tx_rx.1985471052
Short name T599
Test name
Test status
Simulation time 45009886949 ps
CPU time 39.6 seconds
Started Feb 09 07:02:09 AM UTC 25
Finished Feb 09 07:02:50 AM UTC 25
Peak memory 208444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985471052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.uart_tx_rx.1985471052
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/28.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/280.uart_fifo_reset.268125199
Short name T1129
Test name
Test status
Simulation time 31903176262 ps
CPU time 35.05 seconds
Started Feb 09 07:34:50 AM UTC 25
Finished Feb 09 07:35:27 AM UTC 25
Peak memory 208284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268125199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 280.uart_fifo_reset.268125199
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/280.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/281.uart_fifo_reset.3992857345
Short name T1133
Test name
Test status
Simulation time 51807180612 ps
CPU time 42.01 seconds
Started Feb 09 07:34:50 AM UTC 25
Finished Feb 09 07:35:34 AM UTC 25
Peak memory 208248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992857345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 281.uart_fifo_reset.3992857345
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/281.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/282.uart_fifo_reset.1955028537
Short name T1135
Test name
Test status
Simulation time 14431528056 ps
CPU time 43.14 seconds
Started Feb 09 07:34:52 AM UTC 25
Finished Feb 09 07:35:37 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955028537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 282.uart_fifo_reset.1955028537
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/282.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/283.uart_fifo_reset.836292381
Short name T1164
Test name
Test status
Simulation time 111065772190 ps
CPU time 186.11 seconds
Started Feb 09 07:34:53 AM UTC 25
Finished Feb 09 07:38:02 AM UTC 25
Peak memory 208496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836292381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 283.uart_fifo_reset.836292381
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/283.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/284.uart_fifo_reset.3620702369
Short name T1132
Test name
Test status
Simulation time 28167094327 ps
CPU time 35.92 seconds
Started Feb 09 07:34:53 AM UTC 25
Finished Feb 09 07:35:30 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620702369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 284.uart_fifo_reset.3620702369
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/284.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/286.uart_fifo_reset.3886719907
Short name T1128
Test name
Test status
Simulation time 31461490941 ps
CPU time 25.97 seconds
Started Feb 09 07:34:59 AM UTC 25
Finished Feb 09 07:35:26 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886719907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 286.uart_fifo_reset.3886719907
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/286.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/287.uart_fifo_reset.4009084408
Short name T1141
Test name
Test status
Simulation time 78799246128 ps
CPU time 41.58 seconds
Started Feb 09 07:35:00 AM UTC 25
Finished Feb 09 07:35:43 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009084408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 287.uart_fifo_reset.4009084408
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/287.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/288.uart_fifo_reset.703946971
Short name T1152
Test name
Test status
Simulation time 108977675970 ps
CPU time 74.31 seconds
Started Feb 09 07:35:05 AM UTC 25
Finished Feb 09 07:36:21 AM UTC 25
Peak memory 208496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703946971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 288.uart_fifo_reset.703946971
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/288.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/289.uart_fifo_reset.624158662
Short name T1137
Test name
Test status
Simulation time 119349243808 ps
CPU time 31.27 seconds
Started Feb 09 07:35:05 AM UTC 25
Finished Feb 09 07:35:38 AM UTC 25
Peak memory 208560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624158662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 289.uart_fifo_reset.624158662
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/289.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_alert_test.509309989
Short name T615
Test name
Test status
Simulation time 30722897 ps
CPU time 0.82 seconds
Started Feb 09 07:03:47 AM UTC 25
Finished Feb 09 07:03:49 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509309989 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.509309989
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_fifo_full.3626412653
Short name T167
Test name
Test status
Simulation time 21060788496 ps
CPU time 41.82 seconds
Started Feb 09 07:03:03 AM UTC 25
Finished Feb 09 07:03:47 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626412653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 29.uart_fifo_full.3626412653
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.3597205222
Short name T639
Test name
Test status
Simulation time 56309785275 ps
CPU time 118.77 seconds
Started Feb 09 07:03:08 AM UTC 25
Finished Feb 09 07:05:10 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597205222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.uart_fifo_overflow.3597205222
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_fifo_reset.2789442192
Short name T669
Test name
Test status
Simulation time 92412444254 ps
CPU time 243.84 seconds
Started Feb 09 07:03:09 AM UTC 25
Finished Feb 09 07:07:17 AM UTC 25
Peak memory 208396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789442192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 29.uart_fifo_reset.2789442192
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_intr.923815382
Short name T612
Test name
Test status
Simulation time 15740528347 ps
CPU time 9.35 seconds
Started Feb 09 07:03:17 AM UTC 25
Finished Feb 09 07:03:28 AM UTC 25
Peak memory 208032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923815382 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.uart_intr.923815382
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.1734910946
Short name T720
Test name
Test status
Simulation time 112374008317 ps
CPU time 360.2 seconds
Started Feb 09 07:03:38 AM UTC 25
Finished Feb 09 07:09:43 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734910946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1734910946
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_loopback.3909885227
Short name T601
Test name
Test status
Simulation time 1772950218 ps
CPU time 11.63 seconds
Started Feb 09 07:03:29 AM UTC 25
Finished Feb 09 07:03:42 AM UTC 25
Peak memory 207000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909885227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 29.uart_loopback.3909885227
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_noise_filter.2845675671
Short name T625
Test name
Test status
Simulation time 26063818182 ps
CPU time 70.53 seconds
Started Feb 09 07:03:18 AM UTC 25
Finished Feb 09 07:04:31 AM UTC 25
Peak memory 207296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845675671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 29.uart_noise_filter.2845675671
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_perf.4130971295
Short name T60
Test name
Test status
Simulation time 11340987963 ps
CPU time 386.4 seconds
Started Feb 09 07:03:31 AM UTC 25
Finished Feb 09 07:10:02 AM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130971295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 29.uart_perf.4130971295
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_rx_oversample.3122555855
Short name T609
Test name
Test status
Simulation time 4681318623 ps
CPU time 6.93 seconds
Started Feb 09 07:03:09 AM UTC 25
Finished Feb 09 07:03:18 AM UTC 25
Peak memory 206936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122555855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3122555855
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.2455590808
Short name T617
Test name
Test status
Simulation time 60524823510 ps
CPU time 36.55 seconds
Started Feb 09 07:03:27 AM UTC 25
Finished Feb 09 07:04:05 AM UTC 25
Peak memory 208072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455590808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.uart_rx_parity_err.2455590808
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.3845771885
Short name T616
Test name
Test status
Simulation time 39744463044 ps
CPU time 32.5 seconds
Started Feb 09 07:03:23 AM UTC 25
Finished Feb 09 07:03:56 AM UTC 25
Peak memory 204800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845771885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3845771885
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_smoke.3021200318
Short name T611
Test name
Test status
Simulation time 5975862591 ps
CPU time 24.69 seconds
Started Feb 09 07:03:01 AM UTC 25
Finished Feb 09 07:03:27 AM UTC 25
Peak memory 207864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021200318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.uart_smoke.3021200318
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_stress_all.1719318580
Short name T621
Test name
Test status
Simulation time 19135522333 ps
CPU time 32 seconds
Started Feb 09 07:03:43 AM UTC 25
Finished Feb 09 07:04:17 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719318580 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1719318580
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.2279647164
Short name T399
Test name
Test status
Simulation time 53513738071 ps
CPU time 264 seconds
Started Feb 09 07:03:43 AM UTC 25
Finished Feb 09 07:08:11 AM UTC 25
Peak memory 225124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2279647164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2279647164
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.3901318187
Short name T618
Test name
Test status
Simulation time 6029486767 ps
CPU time 41.16 seconds
Started Feb 09 07:03:28 AM UTC 25
Finished Feb 09 07:04:11 AM UTC 25
Peak memory 208440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901318187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.uart_tx_ovrd.3901318187
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_tx_rx.4234477603
Short name T622
Test name
Test status
Simulation time 55334551314 ps
CPU time 76.68 seconds
Started Feb 09 07:03:01 AM UTC 25
Finished Feb 09 07:04:20 AM UTC 25
Peak memory 208572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234477603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.uart_tx_rx.4234477603
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/29.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2039293091
Short name T251
Test name
Test status
Simulation time 159500917339 ps
CPU time 71.29 seconds
Started Feb 09 07:35:06 AM UTC 25
Finished Feb 09 07:36:19 AM UTC 25
Peak memory 208620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039293091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 290.uart_fifo_reset.2039293091
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/290.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/291.uart_fifo_reset.520863828
Short name T1167
Test name
Test status
Simulation time 157171147082 ps
CPU time 194.47 seconds
Started Feb 09 07:35:07 AM UTC 25
Finished Feb 09 07:38:24 AM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520863828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 291.uart_fifo_reset.520863828
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/291.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/292.uart_fifo_reset.2230984921
Short name T1159
Test name
Test status
Simulation time 164119267680 ps
CPU time 118.95 seconds
Started Feb 09 07:35:10 AM UTC 25
Finished Feb 09 07:37:11 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230984921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 292.uart_fifo_reset.2230984921
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/292.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/293.uart_fifo_reset.396132828
Short name T1138
Test name
Test status
Simulation time 36642807591 ps
CPU time 26.76 seconds
Started Feb 09 07:35:10 AM UTC 25
Finished Feb 09 07:35:38 AM UTC 25
Peak memory 208356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396132828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 293.uart_fifo_reset.396132828
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/293.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/294.uart_fifo_reset.1327921798
Short name T226
Test name
Test status
Simulation time 27652300595 ps
CPU time 49.17 seconds
Started Feb 09 07:35:11 AM UTC 25
Finished Feb 09 07:36:02 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327921798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 294.uart_fifo_reset.1327921798
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/294.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/295.uart_fifo_reset.2127077298
Short name T1147
Test name
Test status
Simulation time 27513944708 ps
CPU time 52.47 seconds
Started Feb 09 07:35:13 AM UTC 25
Finished Feb 09 07:36:08 AM UTC 25
Peak memory 208444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127077298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 295.uart_fifo_reset.2127077298
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/295.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/296.uart_fifo_reset.871045278
Short name T1144
Test name
Test status
Simulation time 374057164025 ps
CPU time 40.18 seconds
Started Feb 09 07:35:13 AM UTC 25
Finished Feb 09 07:35:55 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871045278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 296.uart_fifo_reset.871045278
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/296.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/297.uart_fifo_reset.1579993415
Short name T1145
Test name
Test status
Simulation time 107476761526 ps
CPU time 40.37 seconds
Started Feb 09 07:35:17 AM UTC 25
Finished Feb 09 07:35:58 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579993415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 297.uart_fifo_reset.1579993415
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/297.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/298.uart_fifo_reset.778968992
Short name T1134
Test name
Test status
Simulation time 29788216938 ps
CPU time 16.24 seconds
Started Feb 09 07:35:18 AM UTC 25
Finished Feb 09 07:35:35 AM UTC 25
Peak memory 208424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778968992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 298.uart_fifo_reset.778968992
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/298.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/299.uart_fifo_reset.1042699172
Short name T1156
Test name
Test status
Simulation time 48219535320 ps
CPU time 78.45 seconds
Started Feb 09 07:35:19 AM UTC 25
Finished Feb 09 07:36:39 AM UTC 25
Peak memory 208508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042699172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 299.uart_fifo_reset.1042699172
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/299.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_alert_test.2371329062
Short name T429
Test name
Test status
Simulation time 22407938 ps
CPU time 0.84 seconds
Started Feb 09 06:37:50 AM UTC 25
Finished Feb 09 06:37:52 AM UTC 25
Peak memory 204404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371329062 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2371329062
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.1572578753
Short name T184
Test name
Test status
Simulation time 137850856302 ps
CPU time 255.4 seconds
Started Feb 09 06:37:06 AM UTC 25
Finished Feb 09 06:41:25 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572578753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.uart_fifo_overflow.1572578753
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_fifo_reset.858014661
Short name T57
Test name
Test status
Simulation time 75553609577 ps
CPU time 160.65 seconds
Started Feb 09 06:37:06 AM UTC 25
Finished Feb 09 06:39:49 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858014661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 3.uart_fifo_reset.858014661
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_intr.1918421031
Short name T20
Test name
Test status
Simulation time 20761789684 ps
CPU time 36.14 seconds
Started Feb 09 06:37:11 AM UTC 25
Finished Feb 09 06:37:48 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918421031 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.uart_intr.1918421031
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.4279768275
Short name T292
Test name
Test status
Simulation time 98894941521 ps
CPU time 135.77 seconds
Started Feb 09 06:37:35 AM UTC 25
Finished Feb 09 06:39:53 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279768275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.4279768275
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_loopback.3782363343
Short name T23
Test name
Test status
Simulation time 5773842005 ps
CPU time 8.06 seconds
Started Feb 09 06:37:25 AM UTC 25
Finished Feb 09 06:37:34 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782363343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 3.uart_loopback.3782363343
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_noise_filter.2881140457
Short name T293
Test name
Test status
Simulation time 102203747817 ps
CPU time 218.52 seconds
Started Feb 09 06:37:14 AM UTC 25
Finished Feb 09 06:40:55 AM UTC 25
Peak memory 208808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881140457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 3.uart_noise_filter.2881140457
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_perf.216196843
Short name T305
Test name
Test status
Simulation time 7560437877 ps
CPU time 192.36 seconds
Started Feb 09 06:37:34 AM UTC 25
Finished Feb 09 06:40:50 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216196843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 3.uart_perf.216196843
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_rx_oversample.2341153053
Short name T428
Test name
Test status
Simulation time 2783633783 ps
CPU time 4.68 seconds
Started Feb 09 06:37:09 AM UTC 25
Finished Feb 09 06:37:14 AM UTC 25
Peak memory 207060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341153053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2341153053
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.2908403900
Short name T133
Test name
Test status
Simulation time 47999361240 ps
CPU time 17.53 seconds
Started Feb 09 06:37:16 AM UTC 25
Finished Feb 09 06:37:35 AM UTC 25
Peak memory 208608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908403900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.uart_rx_parity_err.2908403900
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.1825052700
Short name T325
Test name
Test status
Simulation time 5070772169 ps
CPU time 8.24 seconds
Started Feb 09 06:37:15 AM UTC 25
Finished Feb 09 06:37:24 AM UTC 25
Peak memory 206772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825052700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1825052700
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_sec_cm.3823721807
Short name T112
Test name
Test status
Simulation time 231914408 ps
CPU time 1.29 seconds
Started Feb 09 06:37:49 AM UTC 25
Finished Feb 09 06:37:52 AM UTC 25
Peak memory 239868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823721807 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3823721807
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_smoke.1183810433
Short name T321
Test name
Test status
Simulation time 926200473 ps
CPU time 6.44 seconds
Started Feb 09 06:37:02 AM UTC 25
Finished Feb 09 06:37:10 AM UTC 25
Peak memory 207144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183810433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.uart_smoke.1183810433
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.3352324033
Short name T301
Test name
Test status
Simulation time 7102776905 ps
CPU time 44.91 seconds
Started Feb 09 06:37:23 AM UTC 25
Finished Feb 09 06:38:09 AM UTC 25
Peak memory 208232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352324033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.uart_tx_ovrd.3352324033
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_tx_rx.3145048580
Short name T144
Test name
Test status
Simulation time 52734040406 ps
CPU time 42.6 seconds
Started Feb 09 06:37:05 AM UTC 25
Finished Feb 09 06:37:50 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145048580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.uart_tx_rx.3145048580
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_alert_test.4039775369
Short name T631
Test name
Test status
Simulation time 24332949 ps
CPU time 0.85 seconds
Started Feb 09 07:04:39 AM UTC 25
Finished Feb 09 07:04:41 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039775369 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.4039775369
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_fifo_full.2580193111
Short name T179
Test name
Test status
Simulation time 49113006872 ps
CPU time 51.27 seconds
Started Feb 09 07:04:05 AM UTC 25
Finished Feb 09 07:04:58 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580193111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 30.uart_fifo_full.2580193111
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.405162474
Short name T730
Test name
Test status
Simulation time 115405122419 ps
CPU time 371.85 seconds
Started Feb 09 07:04:11 AM UTC 25
Finished Feb 09 07:10:28 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405162474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_over
flow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 30.uart_fifo_overflow.405162474
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_fifo_reset.3109612471
Short name T214
Test name
Test status
Simulation time 34677259153 ps
CPU time 46.63 seconds
Started Feb 09 07:04:11 AM UTC 25
Finished Feb 09 07:05:00 AM UTC 25
Peak memory 208424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109612471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 30.uart_fifo_reset.3109612471
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_intr.726499912
Short name T634
Test name
Test status
Simulation time 15463294855 ps
CPU time 37.21 seconds
Started Feb 09 07:04:18 AM UTC 25
Finished Feb 09 07:04:56 AM UTC 25
Peak memory 208024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726499912 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.uart_intr.726499912
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.1839969181
Short name T788
Test name
Test status
Simulation time 95230983774 ps
CPU time 515.02 seconds
Started Feb 09 07:04:34 AM UTC 25
Finished Feb 09 07:13:15 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839969181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1839969181
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_loopback.910065174
Short name T632
Test name
Test status
Simulation time 6419384884 ps
CPU time 12.84 seconds
Started Feb 09 07:04:29 AM UTC 25
Finished Feb 09 07:04:43 AM UTC 25
Peak memory 207388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910065174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.uart_loopback.910065174
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_noise_filter.2823169207
Short name T630
Test name
Test status
Simulation time 6192183962 ps
CPU time 18.19 seconds
Started Feb 09 07:04:21 AM UTC 25
Finished Feb 09 07:04:40 AM UTC 25
Peak memory 208604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823169207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 30.uart_noise_filter.2823169207
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_perf.1100590874
Short name T768
Test name
Test status
Simulation time 35938693073 ps
CPU time 462.73 seconds
Started Feb 09 07:04:32 AM UTC 25
Finished Feb 09 07:12:20 AM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100590874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 30.uart_perf.1100590874
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_rx_oversample.2031901733
Short name T628
Test name
Test status
Simulation time 7244834854 ps
CPU time 20.91 seconds
Started Feb 09 07:04:15 AM UTC 25
Finished Feb 09 07:04:37 AM UTC 25
Peak memory 206992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031901733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2031901733
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.3965700140
Short name T635
Test name
Test status
Simulation time 117853999671 ps
CPU time 35.46 seconds
Started Feb 09 07:04:23 AM UTC 25
Finished Feb 09 07:05:00 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965700140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.uart_rx_parity_err.3965700140
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.3816944556
Short name T624
Test name
Test status
Simulation time 3555967029 ps
CPU time 6.47 seconds
Started Feb 09 07:04:21 AM UTC 25
Finished Feb 09 07:04:28 AM UTC 25
Peak memory 206848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816944556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3816944556
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_smoke.4272409534
Short name T620
Test name
Test status
Simulation time 5838050749 ps
CPU time 22.54 seconds
Started Feb 09 07:03:50 AM UTC 25
Finished Feb 09 07:04:14 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272409534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.uart_smoke.4272409534
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_stress_all.2723215571
Short name T636
Test name
Test status
Simulation time 18550170444 ps
CPU time 21.46 seconds
Started Feb 09 07:04:37 AM UTC 25
Finished Feb 09 07:05:00 AM UTC 25
Peak memory 208464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723215571 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2723215571
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.3810193619
Short name T400
Test name
Test status
Simulation time 23871251704 ps
CPU time 146.92 seconds
Started Feb 09 07:04:37 AM UTC 25
Finished Feb 09 07:07:07 AM UTC 25
Peak memory 217416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3810193619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3810193619
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.3054908117
Short name T626
Test name
Test status
Simulation time 2388880508 ps
CPU time 5.22 seconds
Started Feb 09 07:04:27 AM UTC 25
Finished Feb 09 07:04:33 AM UTC 25
Peak memory 207144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054908117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.uart_tx_ovrd.3054908117
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_tx_rx.3094391713
Short name T623
Test name
Test status
Simulation time 10830780878 ps
CPU time 27.38 seconds
Started Feb 09 07:03:57 AM UTC 25
Finished Feb 09 07:04:26 AM UTC 25
Peak memory 208400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094391713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.uart_tx_rx.3094391713
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/30.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_alert_test.1909523755
Short name T644
Test name
Test status
Simulation time 42207211 ps
CPU time 0.82 seconds
Started Feb 09 07:05:23 AM UTC 25
Finished Feb 09 07:05:25 AM UTC 25
Peak memory 202484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909523755 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1909523755
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_fifo_full.552312767
Short name T663
Test name
Test status
Simulation time 119311828168 ps
CPU time 126.33 seconds
Started Feb 09 07:04:44 AM UTC 25
Finished Feb 09 07:06:53 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552312767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 31.uart_fifo_full.552312767
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.1513303180
Short name T417
Test name
Test status
Simulation time 25132122815 ps
CPU time 35.92 seconds
Started Feb 09 07:04:51 AM UTC 25
Finished Feb 09 07:05:29 AM UTC 25
Peak memory 208444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513303180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.uart_fifo_overflow.1513303180
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_fifo_reset.1862401331
Short name T219
Test name
Test status
Simulation time 32883405598 ps
CPU time 23.49 seconds
Started Feb 09 07:04:58 AM UTC 25
Finished Feb 09 07:05:22 AM UTC 25
Peak memory 208496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862401331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 31.uart_fifo_reset.1862401331
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_intr.2523034246
Short name T648
Test name
Test status
Simulation time 30967021158 ps
CPU time 32.36 seconds
Started Feb 09 07:05:01 AM UTC 25
Finished Feb 09 07:05:35 AM UTC 25
Peak memory 207256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523034246 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.uart_intr.2523034246
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.3365664356
Short name T845
Test name
Test status
Simulation time 130379367544 ps
CPU time 673.39 seconds
Started Feb 09 07:05:14 AM UTC 25
Finished Feb 09 07:16:35 AM UTC 25
Peak memory 212176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365664356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3365664356
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_loopback.2977439531
Short name T645
Test name
Test status
Simulation time 7214115254 ps
CPU time 16.17 seconds
Started Feb 09 07:05:10 AM UTC 25
Finished Feb 09 07:05:27 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977439531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 31.uart_loopback.2977439531
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_noise_filter.2918017423
Short name T647
Test name
Test status
Simulation time 12982214152 ps
CPU time 28.42 seconds
Started Feb 09 07:05:01 AM UTC 25
Finished Feb 09 07:05:31 AM UTC 25
Peak memory 206908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918017423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 31.uart_noise_filter.2918017423
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_perf.4158200999
Short name T912
Test name
Test status
Simulation time 16397529132 ps
CPU time 882.2 seconds
Started Feb 09 07:05:11 AM UTC 25
Finished Feb 09 07:20:03 AM UTC 25
Peak memory 212076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158200999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 31.uart_perf.4158200999
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_rx_oversample.1778272382
Short name T641
Test name
Test status
Simulation time 2449606048 ps
CPU time 12.76 seconds
Started Feb 09 07:05:00 AM UTC 25
Finished Feb 09 07:05:14 AM UTC 25
Peak memory 207300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778272382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1778272382
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.2402927022
Short name T679
Test name
Test status
Simulation time 150122716600 ps
CPU time 156.28 seconds
Started Feb 09 07:05:02 AM UTC 25
Finished Feb 09 07:07:41 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402927022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.uart_rx_parity_err.2402927022
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.2196505763
Short name T656
Test name
Test status
Simulation time 30183871638 ps
CPU time 73.15 seconds
Started Feb 09 07:05:01 AM UTC 25
Finished Feb 09 07:06:16 AM UTC 25
Peak memory 206848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196505763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2196505763
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_smoke.847115057
Short name T638
Test name
Test status
Simulation time 5543964639 ps
CPU time 23.28 seconds
Started Feb 09 07:04:41 AM UTC 25
Finished Feb 09 07:05:06 AM UTC 25
Peak memory 207524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847115057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 31.uart_smoke.847115057
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_stress_all.473557258
Short name T899
Test name
Test status
Simulation time 1043258071529 ps
CPU time 809.44 seconds
Started Feb 09 07:05:18 AM UTC 25
Finished Feb 09 07:18:57 AM UTC 25
Peak memory 220996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473557258 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.473557258
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.1949269798
Short name T640
Test name
Test status
Simulation time 448704536 ps
CPU time 2.56 seconds
Started Feb 09 07:05:07 AM UTC 25
Finished Feb 09 07:05:11 AM UTC 25
Peak memory 207380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949269798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.uart_tx_ovrd.1949269798
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_tx_rx.1614354918
Short name T657
Test name
Test status
Simulation time 129316476975 ps
CPU time 94.11 seconds
Started Feb 09 07:04:42 AM UTC 25
Finished Feb 09 07:06:19 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614354918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.uart_tx_rx.1614354918
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/31.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_alert_test.4051737330
Short name T658
Test name
Test status
Simulation time 36891924 ps
CPU time 0.83 seconds
Started Feb 09 07:06:20 AM UTC 25
Finished Feb 09 07:06:22 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051737330 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.4051737330
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_fifo_full.4045684834
Short name T702
Test name
Test status
Simulation time 128814659767 ps
CPU time 197.83 seconds
Started Feb 09 07:05:29 AM UTC 25
Finished Feb 09 07:08:50 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045684834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 32.uart_fifo_full.4045684834
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.2072684472
Short name T667
Test name
Test status
Simulation time 60903893800 ps
CPU time 98.21 seconds
Started Feb 09 07:05:30 AM UTC 25
Finished Feb 09 07:07:10 AM UTC 25
Peak memory 208456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072684472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.uart_fifo_overflow.2072684472
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_fifo_reset.631990995
Short name T203
Test name
Test status
Simulation time 52475153368 ps
CPU time 151.97 seconds
Started Feb 09 07:05:30 AM UTC 25
Finished Feb 09 07:08:04 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631990995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 32.uart_fifo_reset.631990995
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_intr.784005766
Short name T650
Test name
Test status
Simulation time 4709268054 ps
CPU time 8.09 seconds
Started Feb 09 07:05:35 AM UTC 25
Finished Feb 09 07:05:44 AM UTC 25
Peak memory 206840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784005766 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.uart_intr.784005766
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.385334780
Short name T701
Test name
Test status
Simulation time 81301872190 ps
CPU time 162.86 seconds
Started Feb 09 07:06:03 AM UTC 25
Finished Feb 09 07:08:49 AM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385334780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.385334780
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_loopback.3813835287
Short name T655
Test name
Test status
Simulation time 11783911989 ps
CPU time 13.77 seconds
Started Feb 09 07:05:55 AM UTC 25
Finished Feb 09 07:06:10 AM UTC 25
Peak memory 208348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813835287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 32.uart_loopback.3813835287
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_noise_filter.1866843499
Short name T662
Test name
Test status
Simulation time 62243436634 ps
CPU time 52.85 seconds
Started Feb 09 07:05:37 AM UTC 25
Finished Feb 09 07:06:31 AM UTC 25
Peak memory 207120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866843499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 32.uart_noise_filter.1866843499
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_perf.768715666
Short name T887
Test name
Test status
Simulation time 15166987601 ps
CPU time 732.36 seconds
Started Feb 09 07:05:57 AM UTC 25
Finished Feb 09 07:18:19 AM UTC 25
Peak memory 212168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768715666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 32.uart_perf.768715666
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_rx_oversample.3977330022
Short name T649
Test name
Test status
Simulation time 2267716965 ps
CPU time 2.72 seconds
Started Feb 09 07:05:32 AM UTC 25
Finished Feb 09 07:05:36 AM UTC 25
Peak memory 206984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977330022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3977330022
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.3149642052
Short name T188
Test name
Test status
Simulation time 82110499926 ps
CPU time 71.88 seconds
Started Feb 09 07:05:48 AM UTC 25
Finished Feb 09 07:07:02 AM UTC 25
Peak memory 208448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149642052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.uart_rx_parity_err.3149642052
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.4193768469
Short name T652
Test name
Test status
Simulation time 2173189032 ps
CPU time 8.46 seconds
Started Feb 09 07:05:45 AM UTC 25
Finished Feb 09 07:05:55 AM UTC 25
Peak memory 204864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193768469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 32.uart_rx_start_bit_filter.4193768469
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_smoke.3337353645
Short name T646
Test name
Test status
Simulation time 459987496 ps
CPU time 2.38 seconds
Started Feb 09 07:05:26 AM UTC 25
Finished Feb 09 07:05:29 AM UTC 25
Peak memory 207432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337353645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.uart_smoke.3337353645
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_stress_all.812899364
Short name T757
Test name
Test status
Simulation time 308294355732 ps
CPU time 327.02 seconds
Started Feb 09 07:06:17 AM UTC 25
Finished Feb 09 07:11:48 AM UTC 25
Peak memory 208580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812899364 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.812899364
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.685003933
Short name T790
Test name
Test status
Simulation time 59964936446 ps
CPU time 422.86 seconds
Started Feb 09 07:06:11 AM UTC 25
Finished Feb 09 07:13:20 AM UTC 25
Peak memory 225204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=685003933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.685003933
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.729273482
Short name T653
Test name
Test status
Simulation time 1776710872 ps
CPU time 4.66 seconds
Started Feb 09 07:05:50 AM UTC 25
Finished Feb 09 07:05:56 AM UTC 25
Peak memory 207564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729273482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.uart_tx_ovrd.729273482
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_tx_rx.1796404560
Short name T651
Test name
Test status
Simulation time 13885814969 ps
CPU time 19.81 seconds
Started Feb 09 07:05:27 AM UTC 25
Finished Feb 09 07:05:48 AM UTC 25
Peak memory 206780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796404560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.uart_tx_rx.1796404560
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/32.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_alert_test.3409175147
Short name T672
Test name
Test status
Simulation time 19385883 ps
CPU time 0.85 seconds
Started Feb 09 07:07:23 AM UTC 25
Finished Feb 09 07:07:25 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409175147 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3409175147
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_fifo_full.2970198510
Short name T421
Test name
Test status
Simulation time 23449645610 ps
CPU time 61.47 seconds
Started Feb 09 07:06:28 AM UTC 25
Finished Feb 09 07:07:31 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970198510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 33.uart_fifo_full.2970198510
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.2113987292
Short name T168
Test name
Test status
Simulation time 101971931429 ps
CPU time 76.23 seconds
Started Feb 09 07:06:29 AM UTC 25
Finished Feb 09 07:07:47 AM UTC 25
Peak memory 207824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113987292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 33.uart_fifo_overflow.2113987292
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_intr.3353587109
Short name T689
Test name
Test status
Simulation time 31436149248 ps
CPU time 71.2 seconds
Started Feb 09 07:06:54 AM UTC 25
Finished Feb 09 07:08:07 AM UTC 25
Peak memory 208460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353587109 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.uart_intr.3353587109
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.2210390508
Short name T871
Test name
Test status
Simulation time 83644152406 ps
CPU time 620.17 seconds
Started Feb 09 07:07:11 AM UTC 25
Finished Feb 09 07:17:38 AM UTC 25
Peak memory 208564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210390508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2210390508
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_loopback.1310557095
Short name T676
Test name
Test status
Simulation time 7390166900 ps
CPU time 16.98 seconds
Started Feb 09 07:07:09 AM UTC 25
Finished Feb 09 07:07:28 AM UTC 25
Peak memory 207316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310557095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 33.uart_loopback.1310557095
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_noise_filter.3287843826
Short name T683
Test name
Test status
Simulation time 275100744325 ps
CPU time 57.9 seconds
Started Feb 09 07:06:54 AM UTC 25
Finished Feb 09 07:07:54 AM UTC 25
Peak memory 207916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287843826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 33.uart_noise_filter.3287843826
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_perf.1906403337
Short name T801
Test name
Test status
Simulation time 30156701670 ps
CPU time 405.14 seconds
Started Feb 09 07:07:10 AM UTC 25
Finished Feb 09 07:14:01 AM UTC 25
Peak memory 208332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906403337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 33.uart_perf.1906403337
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_rx_oversample.2518997678
Short name T665
Test name
Test status
Simulation time 6872152741 ps
CPU time 10.52 seconds
Started Feb 09 07:06:43 AM UTC 25
Finished Feb 09 07:06:55 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518997678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2518997678
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.434807392
Short name T674
Test name
Test status
Simulation time 10472352575 ps
CPU time 21.13 seconds
Started Feb 09 07:07:03 AM UTC 25
Finished Feb 09 07:07:26 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434807392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity
_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 33.uart_rx_parity_err.434807392
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.2615502667
Short name T686
Test name
Test status
Simulation time 35584188819 ps
CPU time 57.03 seconds
Started Feb 09 07:06:56 AM UTC 25
Finished Feb 09 07:07:55 AM UTC 25
Peak memory 204800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615502667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2615502667
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_smoke.51621500
Short name T659
Test name
Test status
Simulation time 504005529 ps
CPU time 1.85 seconds
Started Feb 09 07:06:23 AM UTC 25
Finished Feb 09 07:06:26 AM UTC 25
Peak memory 207736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51621500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 33.uart_smoke.51621500
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_stress_all.394911925
Short name T703
Test name
Test status
Simulation time 108918966376 ps
CPU time 92.17 seconds
Started Feb 09 07:07:18 AM UTC 25
Finished Feb 09 07:08:52 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394911925 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.394911925
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.223703181
Short name T716
Test name
Test status
Simulation time 25027726559 ps
CPU time 138.28 seconds
Started Feb 09 07:07:16 AM UTC 25
Finished Feb 09 07:09:37 AM UTC 25
Peak memory 217356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=223703181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.223703181
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.2667174494
Short name T671
Test name
Test status
Simulation time 7383820175 ps
CPU time 14.39 seconds
Started Feb 09 07:07:07 AM UTC 25
Finished Feb 09 07:07:23 AM UTC 25
Peak memory 208256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667174494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.uart_tx_ovrd.2667174494
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_tx_rx.1907852882
Short name T673
Test name
Test status
Simulation time 139891796523 ps
CPU time 56.52 seconds
Started Feb 09 07:06:27 AM UTC 25
Finished Feb 09 07:07:25 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907852882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.uart_tx_rx.1907852882
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/33.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_alert_test.3066794140
Short name T685
Test name
Test status
Simulation time 12907171 ps
CPU time 0.85 seconds
Started Feb 09 07:07:53 AM UTC 25
Finished Feb 09 07:07:55 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066794140 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3066794140
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_fifo_full.4106109832
Short name T678
Test name
Test status
Simulation time 10728900646 ps
CPU time 9.65 seconds
Started Feb 09 07:07:26 AM UTC 25
Finished Feb 09 07:07:37 AM UTC 25
Peak memory 208440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106109832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 34.uart_fifo_full.4106109832
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.2544646306
Short name T705
Test name
Test status
Simulation time 149847484949 ps
CPU time 89.6 seconds
Started Feb 09 07:07:27 AM UTC 25
Finished Feb 09 07:08:59 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544646306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 34.uart_fifo_overflow.2544646306
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_fifo_reset.2428671586
Short name T230
Test name
Test status
Simulation time 16965285203 ps
CPU time 21.74 seconds
Started Feb 09 07:07:28 AM UTC 25
Finished Feb 09 07:07:51 AM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428671586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 34.uart_fifo_reset.2428671586
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_intr.864882240
Short name T688
Test name
Test status
Simulation time 14618978371 ps
CPU time 32.06 seconds
Started Feb 09 07:07:30 AM UTC 25
Finished Feb 09 07:08:04 AM UTC 25
Peak memory 208604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864882240 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.uart_intr.864882240
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.1805108308
Short name T760
Test name
Test status
Simulation time 49693027747 ps
CPU time 252.45 seconds
Started Feb 09 07:07:48 AM UTC 25
Finished Feb 09 07:12:04 AM UTC 25
Peak memory 208440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805108308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1805108308
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_loopback.3756666367
Short name T684
Test name
Test status
Simulation time 8018830568 ps
CPU time 8.98 seconds
Started Feb 09 07:07:44 AM UTC 25
Finished Feb 09 07:07:54 AM UTC 25
Peak memory 208272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756666367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 34.uart_loopback.3756666367
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_noise_filter.3623576238
Short name T733
Test name
Test status
Simulation time 91665664351 ps
CPU time 180.32 seconds
Started Feb 09 07:07:30 AM UTC 25
Finished Feb 09 07:10:34 AM UTC 25
Peak memory 208572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623576238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.uart_noise_filter.3623576238
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_perf.2709572792
Short name T924
Test name
Test status
Simulation time 16529232580 ps
CPU time 784.43 seconds
Started Feb 09 07:07:47 AM UTC 25
Finished Feb 09 07:21:00 AM UTC 25
Peak memory 212204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709572792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 34.uart_perf.2709572792
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_rx_oversample.2674227514
Short name T682
Test name
Test status
Simulation time 4157620519 ps
CPU time 22.76 seconds
Started Feb 09 07:07:28 AM UTC 25
Finished Feb 09 07:07:52 AM UTC 25
Peak memory 207056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674227514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2674227514
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.1046896813
Short name T189
Test name
Test status
Simulation time 166829414070 ps
CPU time 329.6 seconds
Started Feb 09 07:07:37 AM UTC 25
Finished Feb 09 07:13:11 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046896813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 34.uart_rx_parity_err.1046896813
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.4186996717
Short name T680
Test name
Test status
Simulation time 29804798972 ps
CPU time 9.35 seconds
Started Feb 09 07:07:32 AM UTC 25
Finished Feb 09 07:07:43 AM UTC 25
Peak memory 204864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186996717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 34.uart_rx_start_bit_filter.4186996717
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_smoke.239328801
Short name T675
Test name
Test status
Simulation time 525635576 ps
CPU time 2.5 seconds
Started Feb 09 07:07:24 AM UTC 25
Finished Feb 09 07:07:28 AM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239328801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 34.uart_smoke.239328801
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_stress_all.138085228
Short name T953
Test name
Test status
Simulation time 311665443419 ps
CPU time 964.98 seconds
Started Feb 09 07:07:52 AM UTC 25
Finished Feb 09 07:24:07 AM UTC 25
Peak memory 212084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138085228 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.138085228
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.578294739
Short name T119
Test name
Test status
Simulation time 29940296505 ps
CPU time 260.08 seconds
Started Feb 09 07:07:49 AM UTC 25
Finished Feb 09 07:12:13 AM UTC 25
Peak memory 223652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=578294739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.578294739
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.1514543389
Short name T681
Test name
Test status
Simulation time 1381160742 ps
CPU time 3.89 seconds
Started Feb 09 07:07:41 AM UTC 25
Finished Feb 09 07:07:47 AM UTC 25
Peak memory 207572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514543389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.uart_tx_ovrd.1514543389
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_tx_rx.2417406917
Short name T691
Test name
Test status
Simulation time 106051142253 ps
CPU time 43.2 seconds
Started Feb 09 07:07:26 AM UTC 25
Finished Feb 09 07:08:11 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417406917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.uart_tx_rx.2417406917
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/34.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_alert_test.975120953
Short name T696
Test name
Test status
Simulation time 18011009 ps
CPU time 0.84 seconds
Started Feb 09 07:08:30 AM UTC 25
Finished Feb 09 07:08:32 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975120953 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.975120953
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_fifo_full.772778192
Short name T61
Test name
Test status
Simulation time 215896858383 ps
CPU time 123.8 seconds
Started Feb 09 07:07:56 AM UTC 25
Finished Feb 09 07:10:02 AM UTC 25
Peak memory 208508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772778192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 35.uart_fifo_full.772778192
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.68124527
Short name T712
Test name
Test status
Simulation time 85547137385 ps
CPU time 75.2 seconds
Started Feb 09 07:07:56 AM UTC 25
Finished Feb 09 07:09:13 AM UTC 25
Peak memory 208432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68124527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overf
low_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.uart_fifo_overflow.68124527
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_fifo_reset.1318338785
Short name T212
Test name
Test status
Simulation time 14538147941 ps
CPU time 48.97 seconds
Started Feb 09 07:07:59 AM UTC 25
Finished Feb 09 07:08:50 AM UTC 25
Peak memory 208496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318338785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 35.uart_fifo_reset.1318338785
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_intr.1877777377
Short name T692
Test name
Test status
Simulation time 4471956206 ps
CPU time 12.32 seconds
Started Feb 09 07:08:05 AM UTC 25
Finished Feb 09 07:08:19 AM UTC 25
Peak memory 204864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877777377 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.uart_intr.1877777377
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.3260567695
Short name T767
Test name
Test status
Simulation time 94224978829 ps
CPU time 238.74 seconds
Started Feb 09 07:08:17 AM UTC 25
Finished Feb 09 07:12:20 AM UTC 25
Peak memory 208500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260567695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3260567695
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_loopback.2037439045
Short name T694
Test name
Test status
Simulation time 3793154440 ps
CPU time 15.45 seconds
Started Feb 09 07:08:12 AM UTC 25
Finished Feb 09 07:08:28 AM UTC 25
Peak memory 206900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037439045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 35.uart_loopback.2037439045
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_noise_filter.2274197070
Short name T719
Test name
Test status
Simulation time 170734315130 ps
CPU time 91.02 seconds
Started Feb 09 07:08:08 AM UTC 25
Finished Feb 09 07:09:41 AM UTC 25
Peak memory 208680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274197070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 35.uart_noise_filter.2274197070
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_perf.3067850016
Short name T715
Test name
Test status
Simulation time 5407189791 ps
CPU time 76.7 seconds
Started Feb 09 07:08:14 AM UTC 25
Finished Feb 09 07:09:32 AM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067850016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 35.uart_perf.3067850016
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_rx_oversample.3563283936
Short name T690
Test name
Test status
Simulation time 1823791121 ps
CPU time 2.92 seconds
Started Feb 09 07:08:04 AM UTC 25
Finished Feb 09 07:08:08 AM UTC 25
Peak memory 208132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563283936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3563283936
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.272349554
Short name T772
Test name
Test status
Simulation time 110724975708 ps
CPU time 264.81 seconds
Started Feb 09 07:08:09 AM UTC 25
Finished Feb 09 07:12:38 AM UTC 25
Peak memory 208440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272349554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity
_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 35.uart_rx_parity_err.272349554
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.1916843119
Short name T697
Test name
Test status
Simulation time 38869208350 ps
CPU time 22.56 seconds
Started Feb 09 07:08:09 AM UTC 25
Finished Feb 09 07:08:33 AM UTC 25
Peak memory 206848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916843119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1916843119
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_smoke.782123453
Short name T687
Test name
Test status
Simulation time 246917359 ps
CPU time 2.33 seconds
Started Feb 09 07:07:55 AM UTC 25
Finished Feb 09 07:07:58 AM UTC 25
Peak memory 207000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782123453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 35.uart_smoke.782123453
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_stress_all.3834941561
Short name T193
Test name
Test status
Simulation time 37710039992 ps
CPU time 32.36 seconds
Started Feb 09 07:08:22 AM UTC 25
Finished Feb 09 07:08:56 AM UTC 25
Peak memory 208412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834941561 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3834941561
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.1633262536
Short name T853
Test name
Test status
Simulation time 268260789417 ps
CPU time 516.82 seconds
Started Feb 09 07:08:19 AM UTC 25
Finished Feb 09 07:17:02 AM UTC 25
Peak memory 235516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1633262536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1633262536
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.1421875936
Short name T693
Test name
Test status
Simulation time 10989157932 ps
CPU time 9.29 seconds
Started Feb 09 07:08:12 AM UTC 25
Finished Feb 09 07:08:22 AM UTC 25
Peak memory 208092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421875936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.uart_tx_ovrd.1421875936
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_tx_rx.4173450582
Short name T695
Test name
Test status
Simulation time 19109885095 ps
CPU time 31.98 seconds
Started Feb 09 07:07:55 AM UTC 25
Finished Feb 09 07:08:28 AM UTC 25
Peak memory 208240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173450582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.uart_tx_rx.4173450582
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/35.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_alert_test.2440965656
Short name T711
Test name
Test status
Simulation time 13050150 ps
CPU time 0.87 seconds
Started Feb 09 07:09:11 AM UTC 25
Finished Feb 09 07:09:13 AM UTC 25
Peak memory 204432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440965656 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2440965656
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_fifo_full.4175249547
Short name T724
Test name
Test status
Simulation time 66187870842 ps
CPU time 74.17 seconds
Started Feb 09 07:08:34 AM UTC 25
Finished Feb 09 07:09:50 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175249547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 36.uart_fifo_full.4175249547
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.2468988912
Short name T717
Test name
Test status
Simulation time 32779248404 ps
CPU time 57.77 seconds
Started Feb 09 07:08:38 AM UTC 25
Finished Feb 09 07:09:37 AM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468988912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.uart_fifo_overflow.2468988912
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_fifo_reset.3319801462
Short name T420
Test name
Test status
Simulation time 88648146026 ps
CPU time 28.44 seconds
Started Feb 09 07:08:41 AM UTC 25
Finished Feb 09 07:09:11 AM UTC 25
Peak memory 208396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319801462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 36.uart_fifo_reset.3319801462
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_intr.1081016268
Short name T721
Test name
Test status
Simulation time 51080510952 ps
CPU time 53.64 seconds
Started Feb 09 07:08:50 AM UTC 25
Finished Feb 09 07:09:45 AM UTC 25
Peak memory 208388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081016268 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.uart_intr.1081016268
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.3185157718
Short name T837
Test name
Test status
Simulation time 81462277680 ps
CPU time 407.55 seconds
Started Feb 09 07:09:03 AM UTC 25
Finished Feb 09 07:15:56 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185157718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3185157718
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_loopback.1599098380
Short name T708
Test name
Test status
Simulation time 3118637398 ps
CPU time 10 seconds
Started Feb 09 07:08:57 AM UTC 25
Finished Feb 09 07:09:09 AM UTC 25
Peak memory 208440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599098380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 36.uart_loopback.1599098380
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_noise_filter.3179019417
Short name T718
Test name
Test status
Simulation time 13053117200 ps
CPU time 48.4 seconds
Started Feb 09 07:08:50 AM UTC 25
Finished Feb 09 07:09:40 AM UTC 25
Peak memory 208596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179019417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 36.uart_noise_filter.3179019417
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_perf.3589994860
Short name T782
Test name
Test status
Simulation time 8022061231 ps
CPU time 236.45 seconds
Started Feb 09 07:08:59 AM UTC 25
Finished Feb 09 07:12:59 AM UTC 25
Peak memory 208412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589994860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 36.uart_perf.3589994860
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_rx_oversample.958033948
Short name T707
Test name
Test status
Simulation time 5457002706 ps
CPU time 16.98 seconds
Started Feb 09 07:08:49 AM UTC 25
Finished Feb 09 07:09:07 AM UTC 25
Peak memory 207124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958033948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.958033948
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.1732158413
Short name T750
Test name
Test status
Simulation time 154249632187 ps
CPU time 150.1 seconds
Started Feb 09 07:08:52 AM UTC 25
Finished Feb 09 07:11:25 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732158413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.uart_rx_parity_err.1732158413
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.1475175337
Short name T704
Test name
Test status
Simulation time 3048779018 ps
CPU time 3.55 seconds
Started Feb 09 07:08:51 AM UTC 25
Finished Feb 09 07:08:56 AM UTC 25
Peak memory 204732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475175337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1475175337
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_smoke.2086670633
Short name T700
Test name
Test status
Simulation time 5889028259 ps
CPU time 17.41 seconds
Started Feb 09 07:08:30 AM UTC 25
Finished Feb 09 07:08:48 AM UTC 25
Peak memory 207996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086670633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.uart_smoke.2086670633
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_stress_all.4144519251
Short name T816
Test name
Test status
Simulation time 152161640449 ps
CPU time 322.48 seconds
Started Feb 09 07:09:10 AM UTC 25
Finished Feb 09 07:14:37 AM UTC 25
Peak memory 208748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144519251 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4144519251
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.630816097
Short name T221
Test name
Test status
Simulation time 215987976812 ps
CPU time 846.58 seconds
Started Feb 09 07:09:09 AM UTC 25
Finished Feb 09 07:23:25 AM UTC 25
Peak memory 238904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=630816097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.630816097
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.992148935
Short name T706
Test name
Test status
Simulation time 660707727 ps
CPU time 5 seconds
Started Feb 09 07:08:56 AM UTC 25
Finished Feb 09 07:09:02 AM UTC 25
Peak memory 207928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992148935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.uart_tx_ovrd.992148935
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_tx_rx.2225703632
Short name T709
Test name
Test status
Simulation time 50906829867 ps
CPU time 35.63 seconds
Started Feb 09 07:08:33 AM UTC 25
Finished Feb 09 07:09:10 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225703632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.uart_tx_rx.2225703632
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/36.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_alert_test.3730993946
Short name T726
Test name
Test status
Simulation time 43178611 ps
CPU time 0.82 seconds
Started Feb 09 07:09:51 AM UTC 25
Finished Feb 09 07:09:53 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730993946 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3730993946
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_fifo_full.2331432658
Short name T762
Test name
Test status
Simulation time 63225404713 ps
CPU time 173.68 seconds
Started Feb 09 07:09:14 AM UTC 25
Finished Feb 09 07:12:10 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331432658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 37.uart_fifo_full.2331432658
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.1378227615
Short name T728
Test name
Test status
Simulation time 23661229135 ps
CPU time 62.86 seconds
Started Feb 09 07:09:14 AM UTC 25
Finished Feb 09 07:10:18 AM UTC 25
Peak memory 208372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378227615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 37.uart_fifo_overflow.1378227615
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_fifo_reset.4132374042
Short name T64
Test name
Test status
Simulation time 89464277917 ps
CPU time 38.34 seconds
Started Feb 09 07:09:30 AM UTC 25
Finished Feb 09 07:10:10 AM UTC 25
Peak memory 208496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132374042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 37.uart_fifo_reset.4132374042
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_intr.661020510
Short name T753
Test name
Test status
Simulation time 307368760790 ps
CPU time 119.81 seconds
Started Feb 09 07:09:33 AM UTC 25
Finished Feb 09 07:11:35 AM UTC 25
Peak memory 207600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661020510 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.uart_intr.661020510
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.1783425135
Short name T896
Test name
Test status
Simulation time 123081344341 ps
CPU time 534.02 seconds
Started Feb 09 07:09:47 AM UTC 25
Finished Feb 09 07:18:47 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783425135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1783425135
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_loopback.3461653112
Short name T722
Test name
Test status
Simulation time 1097809128 ps
CPU time 2.46 seconds
Started Feb 09 07:09:43 AM UTC 25
Finished Feb 09 07:09:46 AM UTC 25
Peak memory 206892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461653112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 37.uart_loopback.3461653112
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_noise_filter.77770298
Short name T741
Test name
Test status
Simulation time 97862149154 ps
CPU time 88.59 seconds
Started Feb 09 07:09:37 AM UTC 25
Finished Feb 09 07:11:08 AM UTC 25
Peak memory 208660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77770298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filt
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 37.uart_noise_filter.77770298
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_perf.3034236503
Short name T1115
Test name
Test status
Simulation time 28385718564 ps
CPU time 1499.08 seconds
Started Feb 09 07:09:44 AM UTC 25
Finished Feb 09 07:34:59 AM UTC 25
Peak memory 212016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034236503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 37.uart_perf.3034236503
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_rx_oversample.623536558
Short name T731
Test name
Test status
Simulation time 5727364910 ps
CPU time 56.75 seconds
Started Feb 09 07:09:31 AM UTC 25
Finished Feb 09 07:10:29 AM UTC 25
Peak memory 207236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623536558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.623536558
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.3453564645
Short name T740
Test name
Test status
Simulation time 208417289421 ps
CPU time 82.73 seconds
Started Feb 09 07:09:41 AM UTC 25
Finished Feb 09 07:11:06 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453564645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 37.uart_rx_parity_err.3453564645
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.3961992193
Short name T723
Test name
Test status
Simulation time 2823619795 ps
CPU time 9.46 seconds
Started Feb 09 07:09:38 AM UTC 25
Finished Feb 09 07:09:49 AM UTC 25
Peak memory 204800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961992193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3961992193
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_smoke.531710715
Short name T714
Test name
Test status
Simulation time 6159878280 ps
CPU time 17.91 seconds
Started Feb 09 07:09:11 AM UTC 25
Finished Feb 09 07:09:30 AM UTC 25
Peak memory 208180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531710715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 37.uart_smoke.531710715
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_stress_all.4226272074
Short name T169
Test name
Test status
Simulation time 151689271308 ps
CPU time 58.25 seconds
Started Feb 09 07:09:50 AM UTC 25
Finished Feb 09 07:10:50 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226272074 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.4226272074
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.3937624209
Short name T946
Test name
Test status
Simulation time 152819744664 ps
CPU time 796.81 seconds
Started Feb 09 07:09:47 AM UTC 25
Finished Feb 09 07:23:13 AM UTC 25
Peak memory 245132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3937624209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3937624209
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.2957820042
Short name T725
Test name
Test status
Simulation time 887795428 ps
CPU time 6.08 seconds
Started Feb 09 07:09:42 AM UTC 25
Finished Feb 09 07:09:50 AM UTC 25
Peak memory 206932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957820042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.uart_tx_ovrd.2957820042
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_tx_rx.1919852830
Short name T745
Test name
Test status
Simulation time 54064639976 ps
CPU time 118.1 seconds
Started Feb 09 07:09:12 AM UTC 25
Finished Feb 09 07:11:12 AM UTC 25
Peak memory 208412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919852830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.uart_tx_rx.1919852830
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/37.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_alert_test.3979137108
Short name T732
Test name
Test status
Simulation time 11475713 ps
CPU time 0.83 seconds
Started Feb 09 07:10:30 AM UTC 25
Finished Feb 09 07:10:32 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979137108 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3979137108
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_fifo_full.3266649849
Short name T194
Test name
Test status
Simulation time 34452910616 ps
CPU time 26.18 seconds
Started Feb 09 07:09:54 AM UTC 25
Finished Feb 09 07:10:22 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266649849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 38.uart_fifo_full.3266649849
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.2501653781
Short name T747
Test name
Test status
Simulation time 36301914263 ps
CPU time 74.97 seconds
Started Feb 09 07:09:56 AM UTC 25
Finished Feb 09 07:11:13 AM UTC 25
Peak memory 208580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501653781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 38.uart_fifo_overflow.2501653781
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_fifo_reset.2562676597
Short name T756
Test name
Test status
Simulation time 168430858124 ps
CPU time 101.95 seconds
Started Feb 09 07:10:03 AM UTC 25
Finished Feb 09 07:11:47 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562676597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 38.uart_fifo_reset.2562676597
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_intr.309968800
Short name T738
Test name
Test status
Simulation time 78521078271 ps
CPU time 46.28 seconds
Started Feb 09 07:10:06 AM UTC 25
Finished Feb 09 07:10:54 AM UTC 25
Peak memory 206840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309968800 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.uart_intr.309968800
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.251074888
Short name T820
Test name
Test status
Simulation time 183466934190 ps
CPU time 259.2 seconds
Started Feb 09 07:10:20 AM UTC 25
Finished Feb 09 07:14:44 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251074888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.251074888
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_loopback.3560973185
Short name T729
Test name
Test status
Simulation time 1328514901 ps
CPU time 3.49 seconds
Started Feb 09 07:10:20 AM UTC 25
Finished Feb 09 07:10:26 AM UTC 25
Peak memory 204740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560973185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 38.uart_loopback.3560973185
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_noise_filter.4024730189
Short name T737
Test name
Test status
Simulation time 69182598653 ps
CPU time 37.84 seconds
Started Feb 09 07:10:09 AM UTC 25
Finished Feb 09 07:10:49 AM UTC 25
Peak memory 208680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024730189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 38.uart_noise_filter.4024730189
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_perf.3604843186
Short name T792
Test name
Test status
Simulation time 14084767319 ps
CPU time 197.78 seconds
Started Feb 09 07:10:20 AM UTC 25
Finished Feb 09 07:13:41 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604843186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 38.uart_perf.3604843186
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_rx_oversample.4211365220
Short name T66
Test name
Test status
Simulation time 4479096554 ps
CPU time 9.47 seconds
Started Feb 09 07:10:03 AM UTC 25
Finished Feb 09 07:10:14 AM UTC 25
Peak memory 207280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211365220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.4211365220
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.2897497858
Short name T426
Test name
Test status
Simulation time 104950814933 ps
CPU time 135.59 seconds
Started Feb 09 07:10:15 AM UTC 25
Finished Feb 09 07:12:33 AM UTC 25
Peak memory 208504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897497858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 38.uart_rx_parity_err.2897497858
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.214946894
Short name T65
Test name
Test status
Simulation time 4554480947 ps
CPU time 1.95 seconds
Started Feb 09 07:10:10 AM UTC 25
Finished Feb 09 07:10:14 AM UTC 25
Peak memory 204404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214946894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_
bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 38.uart_rx_start_bit_filter.214946894
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_smoke.3659948149
Short name T62
Test name
Test status
Simulation time 6044698920 ps
CPU time 13.21 seconds
Started Feb 09 07:09:51 AM UTC 25
Finished Feb 09 07:10:06 AM UTC 25
Peak memory 208424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659948149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.uart_smoke.3659948149
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_stress_all.1969368414
Short name T813
Test name
Test status
Simulation time 409887365633 ps
CPU time 233.77 seconds
Started Feb 09 07:10:28 AM UTC 25
Finished Feb 09 07:14:25 AM UTC 25
Peak memory 217320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969368414 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1969368414
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.1423784435
Short name T849
Test name
Test status
Simulation time 79924143925 ps
CPU time 383.63 seconds
Started Feb 09 07:10:24 AM UTC 25
Finished Feb 09 07:16:52 AM UTC 25
Peak memory 223952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1423784435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1423784435
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.2211017357
Short name T727
Test name
Test status
Simulation time 973245965 ps
CPU time 2.67 seconds
Started Feb 09 07:10:15 AM UTC 25
Finished Feb 09 07:10:18 AM UTC 25
Peak memory 207012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211017357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.uart_tx_ovrd.2211017357
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_tx_rx.3786553621
Short name T735
Test name
Test status
Simulation time 17294689034 ps
CPU time 41.18 seconds
Started Feb 09 07:09:54 AM UTC 25
Finished Feb 09 07:10:37 AM UTC 25
Peak memory 208508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786553621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.uart_tx_rx.3786553621
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/38.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_alert_test.272928055
Short name T748
Test name
Test status
Simulation time 50246738 ps
CPU time 0.78 seconds
Started Feb 09 07:11:12 AM UTC 25
Finished Feb 09 07:11:14 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272928055 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.272928055
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_fifo_full.2049250283
Short name T773
Test name
Test status
Simulation time 49145462616 ps
CPU time 120.78 seconds
Started Feb 09 07:10:36 AM UTC 25
Finished Feb 09 07:12:39 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049250283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 39.uart_fifo_full.2049250283
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.2152560150
Short name T176
Test name
Test status
Simulation time 47469956256 ps
CPU time 41.05 seconds
Started Feb 09 07:10:36 AM UTC 25
Finished Feb 09 07:11:18 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152560150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 39.uart_fifo_overflow.2152560150
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_fifo_reset.2019638963
Short name T413
Test name
Test status
Simulation time 105039990491 ps
CPU time 132.14 seconds
Started Feb 09 07:10:38 AM UTC 25
Finished Feb 09 07:12:53 AM UTC 25
Peak memory 208524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019638963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 39.uart_fifo_reset.2019638963
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_intr.2861571249
Short name T739
Test name
Test status
Simulation time 15661329804 ps
CPU time 18.54 seconds
Started Feb 09 07:10:46 AM UTC 25
Finished Feb 09 07:11:06 AM UTC 25
Peak memory 208608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861571249 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.uart_intr.2861571249
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.1831214114
Short name T827
Test name
Test status
Simulation time 47774573155 ps
CPU time 249.03 seconds
Started Feb 09 07:11:11 AM UTC 25
Finished Feb 09 07:15:24 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831214114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1831214114
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_loopback.4090447854
Short name T743
Test name
Test status
Simulation time 316427804 ps
CPU time 2 seconds
Started Feb 09 07:11:08 AM UTC 25
Finished Feb 09 07:11:11 AM UTC 25
Peak memory 206744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090447854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 39.uart_loopback.4090447854
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_noise_filter.3833379352
Short name T824
Test name
Test status
Simulation time 122020206160 ps
CPU time 268.67 seconds
Started Feb 09 07:10:50 AM UTC 25
Finished Feb 09 07:15:23 AM UTC 25
Peak memory 217324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833379352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.uart_noise_filter.3833379352
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_perf.1283969459
Short name T800
Test name
Test status
Simulation time 9266142811 ps
CPU time 167.02 seconds
Started Feb 09 07:11:10 AM UTC 25
Finished Feb 09 07:14:00 AM UTC 25
Peak memory 208572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283969459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 39.uart_perf.1283969459
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_rx_oversample.1163967680
Short name T744
Test name
Test status
Simulation time 4993592967 ps
CPU time 31.95 seconds
Started Feb 09 07:10:38 AM UTC 25
Finished Feb 09 07:11:12 AM UTC 25
Peak memory 207120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163967680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1163967680
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.3943735526
Short name T777
Test name
Test status
Simulation time 197295203898 ps
CPU time 109.85 seconds
Started Feb 09 07:10:56 AM UTC 25
Finished Feb 09 07:12:48 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943735526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 39.uart_rx_parity_err.3943735526
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.3858601935
Short name T742
Test name
Test status
Simulation time 31328895575 ps
CPU time 19.16 seconds
Started Feb 09 07:10:50 AM UTC 25
Finished Feb 09 07:11:11 AM UTC 25
Peak memory 206848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858601935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3858601935
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_smoke.314349181
Short name T734
Test name
Test status
Simulation time 851577085 ps
CPU time 2.85 seconds
Started Feb 09 07:10:32 AM UTC 25
Finished Feb 09 07:10:36 AM UTC 25
Peak memory 207028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314349181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 39.uart_smoke.314349181
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_stress_all.2984606754
Short name T797
Test name
Test status
Simulation time 281377231761 ps
CPU time 159.6 seconds
Started Feb 09 07:11:12 AM UTC 25
Finished Feb 09 07:13:54 AM UTC 25
Peak memory 217428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984606754 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2984606754
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.560921035
Short name T746
Test name
Test status
Simulation time 1353800812 ps
CPU time 3.2 seconds
Started Feb 09 07:11:08 AM UTC 25
Finished Feb 09 07:11:12 AM UTC 25
Peak memory 207652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560921035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.uart_tx_ovrd.560921035
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_tx_rx.2823418246
Short name T766
Test name
Test status
Simulation time 38674807616 ps
CPU time 98.85 seconds
Started Feb 09 07:10:34 AM UTC 25
Finished Feb 09 07:12:15 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823418246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.uart_tx_rx.2823418246
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/39.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_alert_test.4230351731
Short name T430
Test name
Test status
Simulation time 45703190 ps
CPU time 0.84 seconds
Started Feb 09 06:38:42 AM UTC 25
Finished Feb 09 06:38:44 AM UTC 25
Peak memory 204404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230351731 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.4230351731
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_fifo_full.3682631918
Short name T132
Test name
Test status
Simulation time 56454325190 ps
CPU time 49.61 seconds
Started Feb 09 06:37:54 AM UTC 25
Finished Feb 09 06:38:45 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682631918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 4.uart_fifo_full.3682631918
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.3969892667
Short name T157
Test name
Test status
Simulation time 183096509530 ps
CPU time 73.21 seconds
Started Feb 09 06:37:56 AM UTC 25
Finished Feb 09 06:39:11 AM UTC 25
Peak memory 208452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969892667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.uart_fifo_overflow.3969892667
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_fifo_reset.1001517092
Short name T146
Test name
Test status
Simulation time 206875569958 ps
CPU time 50.1 seconds
Started Feb 09 06:37:58 AM UTC 25
Finished Feb 09 06:38:49 AM UTC 25
Peak memory 208448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001517092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 4.uart_fifo_reset.1001517092
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_intr.1698378105
Short name T137
Test name
Test status
Simulation time 46297062548 ps
CPU time 44.28 seconds
Started Feb 09 06:38:10 AM UTC 25
Finished Feb 09 06:38:56 AM UTC 25
Peak memory 208164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698378105 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.uart_intr.1698378105
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.1021175829
Short name T318
Test name
Test status
Simulation time 47240959532 ps
CPU time 116.16 seconds
Started Feb 09 06:38:33 AM UTC 25
Finished Feb 09 06:40:31 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021175829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1021175829
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_loopback.2341823654
Short name T431
Test name
Test status
Simulation time 5084368842 ps
CPU time 19.74 seconds
Started Feb 09 06:38:25 AM UTC 25
Finished Feb 09 06:38:46 AM UTC 25
Peak memory 206848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341823654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 4.uart_loopback.2341823654
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_noise_filter.2000247336
Short name T55
Test name
Test status
Simulation time 19177727401 ps
CPU time 58.71 seconds
Started Feb 09 06:38:15 AM UTC 25
Finished Feb 09 06:39:16 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000247336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 4.uart_noise_filter.2000247336
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_perf.1350291583
Short name T447
Test name
Test status
Simulation time 6173622489 ps
CPU time 494.88 seconds
Started Feb 09 06:38:30 AM UTC 25
Finished Feb 09 06:46:51 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350291583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 4.uart_perf.1350291583
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_rx_oversample.1833031401
Short name T402
Test name
Test status
Simulation time 4239736507 ps
CPU time 14.48 seconds
Started Feb 09 06:38:05 AM UTC 25
Finished Feb 09 06:38:21 AM UTC 25
Peak memory 207060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833031401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1833031401
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.497903275
Short name T54
Test name
Test status
Simulation time 28518489238 ps
CPU time 41.93 seconds
Started Feb 09 06:38:23 AM UTC 25
Finished Feb 09 06:39:07 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497903275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity
_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 4.uart_rx_parity_err.497903275
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.3831367567
Short name T344
Test name
Test status
Simulation time 75787591424 ps
CPU time 126.72 seconds
Started Feb 09 06:38:21 AM UTC 25
Finished Feb 09 06:40:30 AM UTC 25
Peak memory 206776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831367567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3831367567
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_sec_cm.2994436439
Short name T113
Test name
Test status
Simulation time 131274065 ps
CPU time 1.22 seconds
Started Feb 09 06:38:39 AM UTC 25
Finished Feb 09 06:38:41 AM UTC 25
Peak memory 239932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994436439 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2994436439
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_smoke.3349140208
Short name T347
Test name
Test status
Simulation time 695778455 ps
CPU time 2.27 seconds
Started Feb 09 06:37:51 AM UTC 25
Finished Feb 09 06:37:55 AM UTC 25
Peak memory 208140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349140208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.uart_smoke.3349140208
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_stress_all.1400755887
Short name T342
Test name
Test status
Simulation time 12541333816 ps
CPU time 103.54 seconds
Started Feb 09 06:38:38 AM UTC 25
Finished Feb 09 06:40:24 AM UTC 25
Peak memory 208580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400755887 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1400755887
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.1554437380
Short name T201
Test name
Test status
Simulation time 230854349596 ps
CPU time 2427.78 seconds
Started Feb 09 06:38:38 AM UTC 25
Finished Feb 09 07:19:32 AM UTC 25
Peak memory 249148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1554437380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1554437380
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.4187923917
Short name T356
Test name
Test status
Simulation time 869853749 ps
CPU time 6.54 seconds
Started Feb 09 06:38:25 AM UTC 25
Finished Feb 09 06:38:32 AM UTC 25
Peak memory 207224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187923917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.uart_tx_ovrd.4187923917
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_tx_rx.2574701484
Short name T145
Test name
Test status
Simulation time 8567272612 ps
CPU time 29.75 seconds
Started Feb 09 06:37:52 AM UTC 25
Finished Feb 09 06:38:24 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574701484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.uart_tx_rx.2574701484
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/4.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_alert_test.4027983775
Short name T761
Test name
Test status
Simulation time 12634416 ps
CPU time 0.83 seconds
Started Feb 09 07:12:05 AM UTC 25
Finished Feb 09 07:12:07 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027983775 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.4027983775
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_fifo_full.2251486711
Short name T769
Test name
Test status
Simulation time 36496946531 ps
CPU time 67.96 seconds
Started Feb 09 07:11:14 AM UTC 25
Finished Feb 09 07:12:24 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251486711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 40.uart_fifo_full.2251486711
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.2879571502
Short name T187
Test name
Test status
Simulation time 72558748529 ps
CPU time 65.55 seconds
Started Feb 09 07:11:15 AM UTC 25
Finished Feb 09 07:12:23 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879571502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 40.uart_fifo_overflow.2879571502
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_fifo_reset.785689672
Short name T810
Test name
Test status
Simulation time 271770606981 ps
CPU time 178.15 seconds
Started Feb 09 07:11:17 AM UTC 25
Finished Feb 09 07:14:18 AM UTC 25
Peak memory 208504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785689672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 40.uart_fifo_reset.785689672
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_intr.1720923263
Short name T752
Test name
Test status
Simulation time 7770912195 ps
CPU time 7.11 seconds
Started Feb 09 07:11:26 AM UTC 25
Finished Feb 09 07:11:34 AM UTC 25
Peak memory 206848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720923263 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.uart_intr.1720923263
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.53380155
Short name T811
Test name
Test status
Simulation time 122520135493 ps
CPU time 149.81 seconds
Started Feb 09 07:11:49 AM UTC 25
Finished Feb 09 07:14:21 AM UTC 25
Peak memory 208416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53380155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=
uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.53380155
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_loopback.673632357
Short name T759
Test name
Test status
Simulation time 9622202018 ps
CPU time 15.4 seconds
Started Feb 09 07:11:47 AM UTC 25
Finished Feb 09 07:12:04 AM UTC 25
Peak memory 208516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673632357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.uart_loopback.673632357
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_noise_filter.87088170
Short name T775
Test name
Test status
Simulation time 99406405399 ps
CPU time 70.22 seconds
Started Feb 09 07:11:31 AM UTC 25
Finished Feb 09 07:12:43 AM UTC 25
Peak memory 216944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87088170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filt
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 40.uart_noise_filter.87088170
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_perf.3923164170
Short name T958
Test name
Test status
Simulation time 15721954686 ps
CPU time 782.57 seconds
Started Feb 09 07:11:48 AM UTC 25
Finished Feb 09 07:24:59 AM UTC 25
Peak memory 212012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923164170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 40.uart_perf.3923164170
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_rx_oversample.936446610
Short name T751
Test name
Test status
Simulation time 1697426103 ps
CPU time 9.6 seconds
Started Feb 09 07:11:20 AM UTC 25
Finished Feb 09 07:11:30 AM UTC 25
Peak memory 206996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936446610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.936446610
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.1571077719
Short name T796
Test name
Test status
Simulation time 232790803763 ps
CPU time 134.13 seconds
Started Feb 09 07:11:36 AM UTC 25
Finished Feb 09 07:13:52 AM UTC 25
Peak memory 208452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571077719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 40.uart_rx_parity_err.1571077719
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.1560824094
Short name T754
Test name
Test status
Simulation time 4239054688 ps
CPU time 3.16 seconds
Started Feb 09 07:11:35 AM UTC 25
Finished Feb 09 07:11:39 AM UTC 25
Peak memory 204800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560824094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1560824094
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_smoke.1183673835
Short name T749
Test name
Test status
Simulation time 464312393 ps
CPU time 2.39 seconds
Started Feb 09 07:11:13 AM UTC 25
Finished Feb 09 07:11:17 AM UTC 25
Peak memory 207652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183673835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.uart_smoke.1183673835
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_stress_all.3386090434
Short name T272
Test name
Test status
Simulation time 279400119842 ps
CPU time 164.79 seconds
Started Feb 09 07:12:04 AM UTC 25
Finished Feb 09 07:14:52 AM UTC 25
Peak memory 208388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386090434 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3386090434
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.1810316902
Short name T808
Test name
Test status
Simulation time 27555998504 ps
CPU time 129.87 seconds
Started Feb 09 07:11:58 AM UTC 25
Finished Feb 09 07:14:10 AM UTC 25
Peak memory 221616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1810316902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1810316902
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.1678299896
Short name T755
Test name
Test status
Simulation time 1353639819 ps
CPU time 4.68 seconds
Started Feb 09 07:11:40 AM UTC 25
Finished Feb 09 07:11:46 AM UTC 25
Peak memory 207824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678299896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.uart_tx_ovrd.1678299896
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_tx_rx.1302426759
Short name T410
Test name
Test status
Simulation time 24285654540 ps
CPU time 52.52 seconds
Started Feb 09 07:11:13 AM UTC 25
Finished Feb 09 07:12:07 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302426759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.uart_tx_rx.1302426759
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/40.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_alert_test.985014437
Short name T774
Test name
Test status
Simulation time 30685460 ps
CPU time 0.85 seconds
Started Feb 09 07:12:39 AM UTC 25
Finished Feb 09 07:12:41 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985014437 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.985014437
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_fifo_full.331661127
Short name T778
Test name
Test status
Simulation time 44037203165 ps
CPU time 38.69 seconds
Started Feb 09 07:12:11 AM UTC 25
Finished Feb 09 07:12:52 AM UTC 25
Peak memory 208384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331661127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 41.uart_fifo_full.331661127
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.3237494321
Short name T822
Test name
Test status
Simulation time 71912903504 ps
CPU time 159.22 seconds
Started Feb 09 07:12:11 AM UTC 25
Finished Feb 09 07:14:54 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237494321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 41.uart_fifo_overflow.3237494321
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_fifo_reset.840373263
Short name T209
Test name
Test status
Simulation time 146443479444 ps
CPU time 59.41 seconds
Started Feb 09 07:12:14 AM UTC 25
Finished Feb 09 07:13:15 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840373263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 41.uart_fifo_reset.840373263
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_intr.163761534
Short name T823
Test name
Test status
Simulation time 168180371683 ps
CPU time 169.04 seconds
Started Feb 09 07:12:14 AM UTC 25
Finished Feb 09 07:15:06 AM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163761534 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.uart_intr.163761534
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.2223350456
Short name T942
Test name
Test status
Simulation time 68735744748 ps
CPU time 602.07 seconds
Started Feb 09 07:12:26 AM UTC 25
Finished Feb 09 07:22:36 AM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223350456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2223350456
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_loopback.1165558568
Short name T776
Test name
Test status
Simulation time 10915842110 ps
CPU time 20.44 seconds
Started Feb 09 07:12:24 AM UTC 25
Finished Feb 09 07:12:46 AM UTC 25
Peak memory 208580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165558568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 41.uart_loopback.1165558568
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_noise_filter.964586380
Short name T779
Test name
Test status
Simulation time 18602276832 ps
CPU time 35.71 seconds
Started Feb 09 07:12:15 AM UTC 25
Finished Feb 09 07:12:52 AM UTC 25
Peak memory 207268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964586380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fil
ter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.uart_noise_filter.964586380
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_perf.1388513838
Short name T944
Test name
Test status
Simulation time 14792410596 ps
CPU time 634.86 seconds
Started Feb 09 07:12:25 AM UTC 25
Finished Feb 09 07:23:07 AM UTC 25
Peak memory 209972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388513838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 41.uart_perf.1388513838
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_rx_oversample.1876246342
Short name T771
Test name
Test status
Simulation time 6611813451 ps
CPU time 23.13 seconds
Started Feb 09 07:12:14 AM UTC 25
Finished Feb 09 07:12:38 AM UTC 25
Peak memory 207056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876246342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1876246342
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.3195995792
Short name T874
Test name
Test status
Simulation time 191354004338 ps
CPU time 320.27 seconds
Started Feb 09 07:12:20 AM UTC 25
Finished Feb 09 07:17:44 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195995792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 41.uart_rx_parity_err.3195995792
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.4147342378
Short name T785
Test name
Test status
Simulation time 28362059593 ps
CPU time 49.35 seconds
Started Feb 09 07:12:16 AM UTC 25
Finished Feb 09 07:13:07 AM UTC 25
Peak memory 204864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147342378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 41.uart_rx_start_bit_filter.4147342378
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_smoke.398741140
Short name T764
Test name
Test status
Simulation time 745585191 ps
CPU time 3.25 seconds
Started Feb 09 07:12:08 AM UTC 25
Finished Feb 09 07:12:13 AM UTC 25
Peak memory 208268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398741140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 41.uart_smoke.398741140
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_stress_all.378608247
Short name T210
Test name
Test status
Simulation time 117810285328 ps
CPU time 394.71 seconds
Started Feb 09 07:12:39 AM UTC 25
Finished Feb 09 07:19:19 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378608247 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.378608247
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.2441443807
Short name T1078
Test name
Test status
Simulation time 68144104290 ps
CPU time 1247.93 seconds
Started Feb 09 07:12:33 AM UTC 25
Finished Feb 09 07:33:35 AM UTC 25
Peak memory 238916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2441443807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2441443807
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.2417798438
Short name T770
Test name
Test status
Simulation time 867931335 ps
CPU time 3.54 seconds
Started Feb 09 07:12:21 AM UTC 25
Finished Feb 09 07:12:26 AM UTC 25
Peak memory 206964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417798438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.uart_tx_ovrd.2417798438
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_tx_rx.1180133162
Short name T794
Test name
Test status
Simulation time 105210537159 ps
CPU time 99.64 seconds
Started Feb 09 07:12:08 AM UTC 25
Finished Feb 09 07:13:50 AM UTC 25
Peak memory 208516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180133162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.uart_tx_rx.1180133162
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/41.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_alert_test.1939125703
Short name T787
Test name
Test status
Simulation time 34168527 ps
CPU time 0.85 seconds
Started Feb 09 07:13:11 AM UTC 25
Finished Feb 09 07:13:14 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939125703 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1939125703
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_fifo_full.2822405877
Short name T863
Test name
Test status
Simulation time 124690525576 ps
CPU time 275.39 seconds
Started Feb 09 07:12:44 AM UTC 25
Finished Feb 09 07:17:23 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822405877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 42.uart_fifo_full.2822405877
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.3066597169
Short name T799
Test name
Test status
Simulation time 122311245784 ps
CPU time 70.28 seconds
Started Feb 09 07:12:47 AM UTC 25
Finished Feb 09 07:13:59 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066597169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 42.uart_fifo_overflow.3066597169
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_fifo_reset.976068264
Short name T185
Test name
Test status
Simulation time 201453549876 ps
CPU time 101.2 seconds
Started Feb 09 07:12:47 AM UTC 25
Finished Feb 09 07:14:30 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976068264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 42.uart_fifo_reset.976068264
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.4204991049
Short name T906
Test name
Test status
Simulation time 116550322150 ps
CPU time 385.8 seconds
Started Feb 09 07:13:03 AM UTC 25
Finished Feb 09 07:19:34 AM UTC 25
Peak memory 208416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204991049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4204991049
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_loopback.2716197313
Short name T784
Test name
Test status
Simulation time 927837939 ps
CPU time 1.19 seconds
Started Feb 09 07:13:00 AM UTC 25
Finished Feb 09 07:13:03 AM UTC 25
Peak memory 204408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716197313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 42.uart_loopback.2716197313
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_noise_filter.832484138
Short name T858
Test name
Test status
Simulation time 94738827013 ps
CPU time 254.94 seconds
Started Feb 09 07:12:53 AM UTC 25
Finished Feb 09 07:17:12 AM UTC 25
Peak memory 207852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832484138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fil
ter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.uart_noise_filter.832484138
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_perf.1760017656
Short name T903
Test name
Test status
Simulation time 9031790952 ps
CPU time 374.82 seconds
Started Feb 09 07:13:00 AM UTC 25
Finished Feb 09 07:19:20 AM UTC 25
Peak memory 208420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760017656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 42.uart_perf.1760017656
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_rx_oversample.3047425964
Short name T783
Test name
Test status
Simulation time 5469555117 ps
CPU time 9.55 seconds
Started Feb 09 07:12:49 AM UTC 25
Finished Feb 09 07:13:00 AM UTC 25
Peak memory 207056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047425964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3047425964
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.951505671
Short name T806
Test name
Test status
Simulation time 113784258778 ps
CPU time 68.88 seconds
Started Feb 09 07:12:58 AM UTC 25
Finished Feb 09 07:14:09 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951505671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity
_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.uart_rx_parity_err.951505671
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.3647481917
Short name T795
Test name
Test status
Simulation time 45921637926 ps
CPU time 56.27 seconds
Started Feb 09 07:12:54 AM UTC 25
Finished Feb 09 07:13:52 AM UTC 25
Peak memory 204800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647481917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3647481917
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_smoke.3185672630
Short name T781
Test name
Test status
Simulation time 5981765548 ps
CPU time 15.75 seconds
Started Feb 09 07:12:40 AM UTC 25
Finished Feb 09 07:12:58 AM UTC 25
Peak memory 208328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185672630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.uart_smoke.3185672630
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_stress_all.2007487649
Short name T255
Test name
Test status
Simulation time 82239618564 ps
CPU time 350.57 seconds
Started Feb 09 07:13:08 AM UTC 25
Finished Feb 09 07:19:03 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007487649 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2007487649
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.2627202958
Short name T952
Test name
Test status
Simulation time 224010086154 ps
CPU time 649.7 seconds
Started Feb 09 07:13:07 AM UTC 25
Finished Feb 09 07:24:05 AM UTC 25
Peak memory 237548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2627202958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2627202958
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.2847608070
Short name T786
Test name
Test status
Simulation time 7624234382 ps
CPU time 8.32 seconds
Started Feb 09 07:12:58 AM UTC 25
Finished Feb 09 07:13:08 AM UTC 25
Peak memory 208188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847608070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.uart_tx_ovrd.2847608070
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_tx_rx.3520827473
Short name T780
Test name
Test status
Simulation time 27191964309 ps
CPU time 13.1 seconds
Started Feb 09 07:12:43 AM UTC 25
Finished Feb 09 07:12:57 AM UTC 25
Peak memory 206848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520827473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.uart_tx_rx.3520827473
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_alert_test.2119198383
Short name T804
Test name
Test status
Simulation time 14489812 ps
CPU time 0.86 seconds
Started Feb 09 07:14:01 AM UTC 25
Finished Feb 09 07:14:03 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119198383 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2119198383
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_fifo_full.3672879403
Short name T911
Test name
Test status
Simulation time 318830918496 ps
CPU time 385.16 seconds
Started Feb 09 07:13:17 AM UTC 25
Finished Feb 09 07:19:47 AM UTC 25
Peak memory 208580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672879403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 43.uart_fifo_full.3672879403
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.598531374
Short name T809
Test name
Test status
Simulation time 48728123701 ps
CPU time 52 seconds
Started Feb 09 07:13:19 AM UTC 25
Finished Feb 09 07:14:13 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598531374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_over
flow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 43.uart_fifo_overflow.598531374
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_fifo_reset.4250052423
Short name T793
Test name
Test status
Simulation time 8844783566 ps
CPU time 22.16 seconds
Started Feb 09 07:13:21 AM UTC 25
Finished Feb 09 07:13:44 AM UTC 25
Peak memory 208420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250052423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 43.uart_fifo_reset.4250052423
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_intr.3852415990
Short name T872
Test name
Test status
Simulation time 147381586054 ps
CPU time 233.63 seconds
Started Feb 09 07:13:42 AM UTC 25
Finished Feb 09 07:17:39 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852415990 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.uart_intr.3852415990
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.3907732318
Short name T884
Test name
Test status
Simulation time 99720689608 ps
CPU time 244.7 seconds
Started Feb 09 07:13:59 AM UTC 25
Finished Feb 09 07:18:07 AM UTC 25
Peak memory 208608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907732318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3907732318
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_loopback.2465795122
Short name T803
Test name
Test status
Simulation time 6948344789 ps
CPU time 8.39 seconds
Started Feb 09 07:13:53 AM UTC 25
Finished Feb 09 07:14:02 AM UTC 25
Peak memory 206956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465795122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 43.uart_loopback.2465795122
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_noise_filter.428366159
Short name T414
Test name
Test status
Simulation time 106951950137 ps
CPU time 67.87 seconds
Started Feb 09 07:13:45 AM UTC 25
Finished Feb 09 07:14:55 AM UTC 25
Peak memory 207640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428366159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fil
ter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.uart_noise_filter.428366159
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_perf.2045260958
Short name T856
Test name
Test status
Simulation time 10348378377 ps
CPU time 192.01 seconds
Started Feb 09 07:13:55 AM UTC 25
Finished Feb 09 07:17:10 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045260958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 43.uart_perf.2045260958
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_rx_oversample.3880426561
Short name T821
Test name
Test status
Simulation time 6773651666 ps
CPU time 61.48 seconds
Started Feb 09 07:13:41 AM UTC 25
Finished Feb 09 07:14:44 AM UTC 25
Peak memory 207056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880426561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3880426561
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.1304410930
Short name T846
Test name
Test status
Simulation time 291393364935 ps
CPU time 168.59 seconds
Started Feb 09 07:13:52 AM UTC 25
Finished Feb 09 07:16:43 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304410930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.uart_rx_parity_err.1304410930
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.2480401476
Short name T805
Test name
Test status
Simulation time 2597153482 ps
CPU time 10.47 seconds
Started Feb 09 07:13:52 AM UTC 25
Finished Feb 09 07:14:04 AM UTC 25
Peak memory 206784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480401476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2480401476
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_smoke.2427675994
Short name T789
Test name
Test status
Simulation time 445933795 ps
CPU time 2.09 seconds
Started Feb 09 07:13:15 AM UTC 25
Finished Feb 09 07:13:18 AM UTC 25
Peak memory 207408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427675994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.uart_smoke.2427675994
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_stress_all.2101874605
Short name T227
Test name
Test status
Simulation time 134780251546 ps
CPU time 597.3 seconds
Started Feb 09 07:14:00 AM UTC 25
Finished Feb 09 07:24:05 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101874605 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2101874605
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.2084331620
Short name T905
Test name
Test status
Simulation time 31041263918 ps
CPU time 324.04 seconds
Started Feb 09 07:14:00 AM UTC 25
Finished Feb 09 07:19:29 AM UTC 25
Peak memory 223800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2084331620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2084331620
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.1033616377
Short name T798
Test name
Test status
Simulation time 2109521028 ps
CPU time 4.36 seconds
Started Feb 09 07:13:53 AM UTC 25
Finished Feb 09 07:13:58 AM UTC 25
Peak memory 207648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033616377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.uart_tx_ovrd.1033616377
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_tx_rx.1162441269
Short name T791
Test name
Test status
Simulation time 21598487330 ps
CPU time 22.71 seconds
Started Feb 09 07:13:16 AM UTC 25
Finished Feb 09 07:13:40 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162441269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.uart_tx_rx.1162441269
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/43.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_alert_test.2257833920
Short name T819
Test name
Test status
Simulation time 12933998 ps
CPU time 0.85 seconds
Started Feb 09 07:14:37 AM UTC 25
Finished Feb 09 07:14:39 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257833920 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2257833920
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_fifo_full.3126824811
Short name T864
Test name
Test status
Simulation time 273759785725 ps
CPU time 195.64 seconds
Started Feb 09 07:14:04 AM UTC 25
Finished Feb 09 07:17:23 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126824811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 44.uart_fifo_full.3126824811
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.2698666133
Short name T825
Test name
Test status
Simulation time 38967042299 ps
CPU time 77.3 seconds
Started Feb 09 07:14:04 AM UTC 25
Finished Feb 09 07:15:24 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698666133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 44.uart_fifo_overflow.2698666133
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_fifo_reset.14175209
Short name T207
Test name
Test status
Simulation time 19797562799 ps
CPU time 21.43 seconds
Started Feb 09 07:14:11 AM UTC 25
Finished Feb 09 07:14:33 AM UTC 25
Peak memory 208340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14175209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 44.uart_fifo_reset.14175209
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_intr.4159018340
Short name T839
Test name
Test status
Simulation time 55438935798 ps
CPU time 118.86 seconds
Started Feb 09 07:14:12 AM UTC 25
Finished Feb 09 07:16:13 AM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159018340 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.uart_intr.4159018340
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.281336067
Short name T992
Test name
Test status
Simulation time 107689767846 ps
CPU time 832.27 seconds
Started Feb 09 07:14:29 AM UTC 25
Finished Feb 09 07:28:31 AM UTC 25
Peak memory 212020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281336067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.281336067
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_loopback.3393329973
Short name T817
Test name
Test status
Simulation time 4902284664 ps
CPU time 10.41 seconds
Started Feb 09 07:14:26 AM UTC 25
Finished Feb 09 07:14:38 AM UTC 25
Peak memory 207248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393329973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 44.uart_loopback.3393329973
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_noise_filter.1559149101
Short name T850
Test name
Test status
Simulation time 160412312298 ps
CPU time 157.15 seconds
Started Feb 09 07:14:14 AM UTC 25
Finished Feb 09 07:16:54 AM UTC 25
Peak memory 217488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559149101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.uart_noise_filter.1559149101
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_perf.1868904777
Short name T922
Test name
Test status
Simulation time 23614212871 ps
CPU time 379.27 seconds
Started Feb 09 07:14:27 AM UTC 25
Finished Feb 09 07:20:51 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868904777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 44.uart_perf.1868904777
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_rx_oversample.886565964
Short name T814
Test name
Test status
Simulation time 2011547664 ps
CPU time 14.26 seconds
Started Feb 09 07:14:11 AM UTC 25
Finished Feb 09 07:14:26 AM UTC 25
Peak memory 206924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886565964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.886565964
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.1328917797
Short name T838
Test name
Test status
Simulation time 213988630143 ps
CPU time 101.04 seconds
Started Feb 09 07:14:22 AM UTC 25
Finished Feb 09 07:16:05 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328917797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 44.uart_rx_parity_err.1328917797
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.322175253
Short name T812
Test name
Test status
Simulation time 1797932017 ps
CPU time 2.45 seconds
Started Feb 09 07:14:20 AM UTC 25
Finished Feb 09 07:14:23 AM UTC 25
Peak memory 204736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322175253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_
bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 44.uart_rx_start_bit_filter.322175253
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_smoke.2709328526
Short name T807
Test name
Test status
Simulation time 890657127 ps
CPU time 5.34 seconds
Started Feb 09 07:14:03 AM UTC 25
Finished Feb 09 07:14:10 AM UTC 25
Peak memory 207972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709328526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.uart_smoke.2709328526
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_stress_all.3769255741
Short name T913
Test name
Test status
Simulation time 427517348365 ps
CPU time 326.74 seconds
Started Feb 09 07:14:34 AM UTC 25
Finished Feb 09 07:20:05 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769255741 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3769255741
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.572149490
Short name T948
Test name
Test status
Simulation time 140607808679 ps
CPU time 525.22 seconds
Started Feb 09 07:14:31 AM UTC 25
Finished Feb 09 07:23:23 AM UTC 25
Peak memory 231896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=572149490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.572149490
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.1241232638
Short name T815
Test name
Test status
Simulation time 1403485695 ps
CPU time 3.08 seconds
Started Feb 09 07:14:24 AM UTC 25
Finished Feb 09 07:14:28 AM UTC 25
Peak memory 207620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241232638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.uart_tx_ovrd.1241232638
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_tx_rx.1959089458
Short name T831
Test name
Test status
Simulation time 115600756999 ps
CPU time 94.81 seconds
Started Feb 09 07:14:03 AM UTC 25
Finished Feb 09 07:15:40 AM UTC 25
Peak memory 208440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959089458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.uart_tx_rx.1959089458
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/44.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_alert_test.4062329142
Short name T832
Test name
Test status
Simulation time 27460487 ps
CPU time 0.88 seconds
Started Feb 09 07:15:38 AM UTC 25
Finished Feb 09 07:15:41 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062329142 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.4062329142
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_fifo_full.3144426139
Short name T830
Test name
Test status
Simulation time 39279795532 ps
CPU time 55.34 seconds
Started Feb 09 07:14:40 AM UTC 25
Finished Feb 09 07:15:37 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144426139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 45.uart_fifo_full.3144426139
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.1850385877
Short name T900
Test name
Test status
Simulation time 108643583566 ps
CPU time 248.81 seconds
Started Feb 09 07:14:45 AM UTC 25
Finished Feb 09 07:18:57 AM UTC 25
Peak memory 208408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850385877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 45.uart_fifo_overflow.1850385877
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_fifo_reset.1925986933
Short name T855
Test name
Test status
Simulation time 140032938835 ps
CPU time 139.87 seconds
Started Feb 09 07:14:45 AM UTC 25
Finished Feb 09 07:17:07 AM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925986933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 45.uart_fifo_reset.1925986933
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_intr.1978546659
Short name T940
Test name
Test status
Simulation time 184434269985 ps
CPU time 434.28 seconds
Started Feb 09 07:14:55 AM UTC 25
Finished Feb 09 07:22:15 AM UTC 25
Peak memory 207060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978546659 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.uart_intr.1978546659
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.1571612225
Short name T951
Test name
Test status
Simulation time 208549665172 ps
CPU time 512.18 seconds
Started Feb 09 07:15:25 AM UTC 25
Finished Feb 09 07:24:04 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571612225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1571612225
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_loopback.2351829193
Short name T829
Test name
Test status
Simulation time 7016656862 ps
CPU time 5.84 seconds
Started Feb 09 07:15:24 AM UTC 25
Finished Feb 09 07:15:32 AM UTC 25
Peak memory 208032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351829193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 45.uart_loopback.2351829193
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_noise_filter.3259341970
Short name T892
Test name
Test status
Simulation time 86866449197 ps
CPU time 216.91 seconds
Started Feb 09 07:14:56 AM UTC 25
Finished Feb 09 07:18:36 AM UTC 25
Peak memory 208684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259341970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.uart_noise_filter.3259341970
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_perf.3886397662
Short name T875
Test name
Test status
Simulation time 11532230641 ps
CPU time 140.61 seconds
Started Feb 09 07:15:24 AM UTC 25
Finished Feb 09 07:17:48 AM UTC 25
Peak memory 208460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886397662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 45.uart_perf.3886397662
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_rx_oversample.156058329
Short name T833
Test name
Test status
Simulation time 5921422114 ps
CPU time 49.21 seconds
Started Feb 09 07:14:53 AM UTC 25
Finished Feb 09 07:15:44 AM UTC 25
Peak memory 207124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156058329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.156058329
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.1318663669
Short name T424
Test name
Test status
Simulation time 137687890937 ps
CPU time 133.8 seconds
Started Feb 09 07:15:06 AM UTC 25
Finished Feb 09 07:17:22 AM UTC 25
Peak memory 208412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318663669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 45.uart_rx_parity_err.1318663669
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.3062274561
Short name T826
Test name
Test status
Simulation time 4070916518 ps
CPU time 17.55 seconds
Started Feb 09 07:15:05 AM UTC 25
Finished Feb 09 07:15:24 AM UTC 25
Peak memory 204800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062274561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3062274561
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_smoke.2903170720
Short name T818
Test name
Test status
Simulation time 5915172531 ps
CPU time 23.64 seconds
Started Feb 09 07:14:38 AM UTC 25
Finished Feb 09 07:15:03 AM UTC 25
Peak memory 207964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903170720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.uart_smoke.2903170720
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_stress_all.2883709775
Short name T841
Test name
Test status
Simulation time 106339831008 ps
CPU time 51.81 seconds
Started Feb 09 07:15:32 AM UTC 25
Finished Feb 09 07:16:26 AM UTC 25
Peak memory 208412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883709775 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2883709775
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.1086879862
Short name T859
Test name
Test status
Simulation time 5520266076 ps
CPU time 98.33 seconds
Started Feb 09 07:15:32 AM UTC 25
Finished Feb 09 07:17:13 AM UTC 25
Peak memory 217356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1086879862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1086879862
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.1140222028
Short name T836
Test name
Test status
Simulation time 7094640597 ps
CPU time 22.96 seconds
Started Feb 09 07:15:23 AM UTC 25
Finished Feb 09 07:15:47 AM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140222028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.uart_tx_ovrd.1140222028
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_tx_rx.1285861455
Short name T835
Test name
Test status
Simulation time 244931691390 ps
CPU time 65 seconds
Started Feb 09 07:14:39 AM UTC 25
Finished Feb 09 07:15:46 AM UTC 25
Peak memory 208456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285861455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.uart_tx_rx.1285861455
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/45.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_alert_test.4000372288
Short name T848
Test name
Test status
Simulation time 40392099 ps
CPU time 0.84 seconds
Started Feb 09 07:16:45 AM UTC 25
Finished Feb 09 07:16:47 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000372288 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.4000372288
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_fifo_full.3013848352
Short name T840
Test name
Test status
Simulation time 41668509984 ps
CPU time 38.03 seconds
Started Feb 09 07:15:45 AM UTC 25
Finished Feb 09 07:16:24 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013848352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 46.uart_fifo_full.3013848352
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.3517709881
Short name T847
Test name
Test status
Simulation time 11557725225 ps
CPU time 56.73 seconds
Started Feb 09 07:15:46 AM UTC 25
Finished Feb 09 07:16:44 AM UTC 25
Peak memory 208244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517709881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 46.uart_fifo_overflow.3517709881
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_intr.2207473385
Short name T898
Test name
Test status
Simulation time 229015719093 ps
CPU time 169.9 seconds
Started Feb 09 07:15:57 AM UTC 25
Finished Feb 09 07:18:50 AM UTC 25
Peak memory 206848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207473385 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.uart_intr.2207473385
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.742233353
Short name T935
Test name
Test status
Simulation time 81895471023 ps
CPU time 305.8 seconds
Started Feb 09 07:16:34 AM UTC 25
Finished Feb 09 07:21:45 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742233353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.742233353
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_loopback.2185788559
Short name T844
Test name
Test status
Simulation time 4189976437 ps
CPU time 2.85 seconds
Started Feb 09 07:16:29 AM UTC 25
Finished Feb 09 07:16:33 AM UTC 25
Peak memory 206776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185788559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 46.uart_loopback.2185788559
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_noise_filter.4191822553
Short name T854
Test name
Test status
Simulation time 67535850184 ps
CPU time 56.74 seconds
Started Feb 09 07:16:06 AM UTC 25
Finished Feb 09 07:17:05 AM UTC 25
Peak memory 208712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191822553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.uart_noise_filter.4191822553
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_perf.3478615192
Short name T1024
Test name
Test status
Simulation time 17298837154 ps
CPU time 834.81 seconds
Started Feb 09 07:16:33 AM UTC 25
Finished Feb 09 07:30:38 AM UTC 25
Peak memory 212076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478615192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 46.uart_perf.3478615192
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_rx_oversample.2317480985
Short name T843
Test name
Test status
Simulation time 3679694652 ps
CPU time 43.45 seconds
Started Feb 09 07:15:48 AM UTC 25
Finished Feb 09 07:16:33 AM UTC 25
Peak memory 208072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317480985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2317480985
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.310769830
Short name T425
Test name
Test status
Simulation time 57703851538 ps
CPU time 78.97 seconds
Started Feb 09 07:16:25 AM UTC 25
Finished Feb 09 07:17:46 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310769830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity
_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.uart_rx_parity_err.310769830
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.1245074567
Short name T842
Test name
Test status
Simulation time 4756261114 ps
CPU time 13.9 seconds
Started Feb 09 07:16:13 AM UTC 25
Finished Feb 09 07:16:28 AM UTC 25
Peak memory 204800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245074567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1245074567
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_smoke.4159260109
Short name T834
Test name
Test status
Simulation time 953989556 ps
CPU time 2.25 seconds
Started Feb 09 07:15:42 AM UTC 25
Finished Feb 09 07:15:45 AM UTC 25
Peak memory 207148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159260109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.uart_smoke.4159260109
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_stress_all.4158379933
Short name T1179
Test name
Test status
Simulation time 874938258622 ps
CPU time 3464.43 seconds
Started Feb 09 07:16:45 AM UTC 25
Finished Feb 09 08:15:02 AM UTC 25
Peak memory 212084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158379933 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.4158379933
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.3437865807
Short name T960
Test name
Test status
Simulation time 63519349196 ps
CPU time 497.64 seconds
Started Feb 09 07:16:37 AM UTC 25
Finished Feb 09 07:25:00 AM UTC 25
Peak memory 225288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3437865807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3437865807
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.1019010655
Short name T852
Test name
Test status
Simulation time 6866399752 ps
CPU time 32.45 seconds
Started Feb 09 07:16:26 AM UTC 25
Finished Feb 09 07:17:00 AM UTC 25
Peak memory 208120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019010655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.uart_tx_ovrd.1019010655
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_tx_rx.3737585441
Short name T879
Test name
Test status
Simulation time 289460604749 ps
CPU time 136.1 seconds
Started Feb 09 07:15:42 AM UTC 25
Finished Feb 09 07:18:00 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737585441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.uart_tx_rx.3737585441
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/46.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_alert_test.1129258053
Short name T867
Test name
Test status
Simulation time 62928459 ps
CPU time 0.85 seconds
Started Feb 09 07:17:23 AM UTC 25
Finished Feb 09 07:17:25 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129258053 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1129258053
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_fifo_full.2750157800
Short name T857
Test name
Test status
Simulation time 12006087953 ps
CPU time 14.88 seconds
Started Feb 09 07:16:54 AM UTC 25
Finished Feb 09 07:17:10 AM UTC 25
Peak memory 208392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750157800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 47.uart_fifo_full.2750157800
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.1150362650
Short name T930
Test name
Test status
Simulation time 145136813982 ps
CPU time 277.65 seconds
Started Feb 09 07:16:55 AM UTC 25
Finished Feb 09 07:21:36 AM UTC 25
Peak memory 208368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150362650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 47.uart_fifo_overflow.1150362650
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_fifo_reset.1530694503
Short name T208
Test name
Test status
Simulation time 26191152439 ps
CPU time 25.07 seconds
Started Feb 09 07:16:56 AM UTC 25
Finished Feb 09 07:17:22 AM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530694503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 47.uart_fifo_reset.1530694503
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_intr.170760719
Short name T878
Test name
Test status
Simulation time 29071122653 ps
CPU time 54.61 seconds
Started Feb 09 07:17:03 AM UTC 25
Finished Feb 09 07:18:00 AM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170760719 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.uart_intr.170760719
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.603313898
Short name T1176
Test name
Test status
Simulation time 189876930926 ps
CPU time 1619.36 seconds
Started Feb 09 07:17:16 AM UTC 25
Finished Feb 09 07:44:32 AM UTC 25
Peak memory 212080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603313898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.603313898
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_loopback.787181933
Short name T865
Test name
Test status
Simulation time 9654674665 ps
CPU time 10.32 seconds
Started Feb 09 07:17:13 AM UTC 25
Finished Feb 09 07:17:24 AM UTC 25
Peak memory 208316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787181933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.uart_loopback.787181933
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_noise_filter.1754178074
Short name T888
Test name
Test status
Simulation time 54298585870 ps
CPU time 75.51 seconds
Started Feb 09 07:17:05 AM UTC 25
Finished Feb 09 07:18:23 AM UTC 25
Peak memory 207984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754178074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.uart_noise_filter.1754178074
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_perf.1074284119
Short name T919
Test name
Test status
Simulation time 14592818239 ps
CPU time 206.76 seconds
Started Feb 09 07:17:14 AM UTC 25
Finished Feb 09 07:20:44 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074284119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 47.uart_perf.1074284119
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_rx_oversample.1973387339
Short name T862
Test name
Test status
Simulation time 1898421506 ps
CPU time 14.18 seconds
Started Feb 09 07:17:01 AM UTC 25
Finished Feb 09 07:17:17 AM UTC 25
Peak memory 207056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973387339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1973387339
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.3213920533
Short name T869
Test name
Test status
Simulation time 32063019585 ps
CPU time 20.83 seconds
Started Feb 09 07:17:10 AM UTC 25
Finished Feb 09 07:17:33 AM UTC 25
Peak memory 208372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213920533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 47.uart_rx_parity_err.3213920533
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.2829533564
Short name T866
Test name
Test status
Simulation time 19196900293 ps
CPU time 14.71 seconds
Started Feb 09 07:17:08 AM UTC 25
Finished Feb 09 07:17:24 AM UTC 25
Peak memory 204928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829533564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2829533564
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_smoke.4204397796
Short name T851
Test name
Test status
Simulation time 650557268 ps
CPU time 4.83 seconds
Started Feb 09 07:16:48 AM UTC 25
Finished Feb 09 07:16:54 AM UTC 25
Peak memory 206860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204397796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.uart_smoke.4204397796
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_stress_all.2839114978
Short name T961
Test name
Test status
Simulation time 321418400790 ps
CPU time 467.08 seconds
Started Feb 09 07:17:18 AM UTC 25
Finished Feb 09 07:25:10 AM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839114978 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2839114978
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.3483514007
Short name T69
Test name
Test status
Simulation time 87669170888 ps
CPU time 506.52 seconds
Started Feb 09 07:17:17 AM UTC 25
Finished Feb 09 07:25:50 AM UTC 25
Peak memory 237532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3483514007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3483514007
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.2361406896
Short name T860
Test name
Test status
Simulation time 901399166 ps
CPU time 3.29 seconds
Started Feb 09 07:17:10 AM UTC 25
Finished Feb 09 07:17:15 AM UTC 25
Peak memory 207384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361406896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.uart_tx_ovrd.2361406896
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_tx_rx.4008249810
Short name T861
Test name
Test status
Simulation time 41916895435 ps
CPU time 22.08 seconds
Started Feb 09 07:16:53 AM UTC 25
Finished Feb 09 07:17:16 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008249810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.uart_tx_rx.4008249810
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/47.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_alert_test.202632568
Short name T880
Test name
Test status
Simulation time 12717138 ps
CPU time 0.85 seconds
Started Feb 09 07:17:59 AM UTC 25
Finished Feb 09 07:18:01 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202632568 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.202632568
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_fifo_full.2918497414
Short name T893
Test name
Test status
Simulation time 84765410524 ps
CPU time 73.37 seconds
Started Feb 09 07:17:24 AM UTC 25
Finished Feb 09 07:18:39 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918497414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 48.uart_fifo_full.2918497414
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.4251068733
Short name T897
Test name
Test status
Simulation time 85474819061 ps
CPU time 82.06 seconds
Started Feb 09 07:17:25 AM UTC 25
Finished Feb 09 07:18:49 AM UTC 25
Peak memory 208376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251068733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 48.uart_fifo_overflow.4251068733
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_fifo_reset.2097424246
Short name T216
Test name
Test status
Simulation time 109579512575 ps
CPU time 125.49 seconds
Started Feb 09 07:17:25 AM UTC 25
Finished Feb 09 07:19:33 AM UTC 25
Peak memory 208448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097424246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 48.uart_fifo_reset.2097424246
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_intr.2930573404
Short name T885
Test name
Test status
Simulation time 50621852830 ps
CPU time 41.21 seconds
Started Feb 09 07:17:27 AM UTC 25
Finished Feb 09 07:18:10 AM UTC 25
Peak memory 208464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930573404 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.uart_intr.2930573404
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.3969964083
Short name T916
Test name
Test status
Simulation time 152115254725 ps
CPU time 158.71 seconds
Started Feb 09 07:17:47 AM UTC 25
Finished Feb 09 07:20:28 AM UTC 25
Peak memory 208612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969964083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3969964083
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_loopback.850231718
Short name T876
Test name
Test status
Simulation time 10165643878 ps
CPU time 14.21 seconds
Started Feb 09 07:17:42 AM UTC 25
Finished Feb 09 07:17:57 AM UTC 25
Peak memory 208360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850231718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.uart_loopback.850231718
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_noise_filter.3970262710
Short name T915
Test name
Test status
Simulation time 90731733666 ps
CPU time 151.74 seconds
Started Feb 09 07:17:33 AM UTC 25
Finished Feb 09 07:20:08 AM UTC 25
Peak memory 208620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970262710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.uart_noise_filter.3970262710
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_perf.2511986878
Short name T993
Test name
Test status
Simulation time 11320484836 ps
CPU time 644.18 seconds
Started Feb 09 07:17:45 AM UTC 25
Finished Feb 09 07:28:36 AM UTC 25
Peak memory 212144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511986878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 48.uart_perf.2511986878
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_rx_oversample.1768072980
Short name T870
Test name
Test status
Simulation time 4614868958 ps
CPU time 9.7 seconds
Started Feb 09 07:17:26 AM UTC 25
Finished Feb 09 07:17:37 AM UTC 25
Peak memory 207120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768072980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1768072980
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.340352764
Short name T190
Test name
Test status
Simulation time 126203208920 ps
CPU time 67.98 seconds
Started Feb 09 07:17:38 AM UTC 25
Finished Feb 09 07:18:48 AM UTC 25
Peak memory 208424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340352764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity
_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.uart_rx_parity_err.340352764
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.114359312
Short name T873
Test name
Test status
Simulation time 2861762084 ps
CPU time 1.86 seconds
Started Feb 09 07:17:37 AM UTC 25
Finished Feb 09 07:17:40 AM UTC 25
Peak memory 206388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114359312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_
bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 48.uart_rx_start_bit_filter.114359312
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_smoke.3844139116
Short name T868
Test name
Test status
Simulation time 292508401 ps
CPU time 1.96 seconds
Started Feb 09 07:17:23 AM UTC 25
Finished Feb 09 07:17:26 AM UTC 25
Peak memory 207376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844139116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.uart_smoke.3844139116
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_stress_all.499885060
Short name T971
Test name
Test status
Simulation time 49300858957 ps
CPU time 486.79 seconds
Started Feb 09 07:17:58 AM UTC 25
Finished Feb 09 07:26:11 AM UTC 25
Peak memory 208412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499885060 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.499885060
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.2012934031
Short name T941
Test name
Test status
Simulation time 30266095086 ps
CPU time 279.1 seconds
Started Feb 09 07:17:49 AM UTC 25
Finished Feb 09 07:22:32 AM UTC 25
Peak memory 217332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2012934031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2012934031
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.1781707866
Short name T877
Test name
Test status
Simulation time 7137073012 ps
CPU time 15.93 seconds
Started Feb 09 07:17:41 AM UTC 25
Finished Feb 09 07:17:58 AM UTC 25
Peak memory 208504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781707866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.uart_tx_ovrd.1781707866
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_tx_rx.1349573830
Short name T883
Test name
Test status
Simulation time 21142484320 ps
CPU time 41.02 seconds
Started Feb 09 07:17:23 AM UTC 25
Finished Feb 09 07:18:05 AM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349573830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.uart_tx_rx.1349573830
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/48.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_alert_test.2991918806
Short name T895
Test name
Test status
Simulation time 25186304 ps
CPU time 0.84 seconds
Started Feb 09 07:18:41 AM UTC 25
Finished Feb 09 07:18:43 AM UTC 25
Peak memory 204468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991918806 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2991918806
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_fifo_full.3117369923
Short name T909
Test name
Test status
Simulation time 31639465003 ps
CPU time 91.27 seconds
Started Feb 09 07:18:02 AM UTC 25
Finished Feb 09 07:19:36 AM UTC 25
Peak memory 207912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117369923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 49.uart_fifo_full.3117369923
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.2382279029
Short name T904
Test name
Test status
Simulation time 63965565656 ps
CPU time 77.45 seconds
Started Feb 09 07:18:03 AM UTC 25
Finished Feb 09 07:19:23 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382279029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 49.uart_fifo_overflow.2382279029
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_fifo_reset.40952571
Short name T917
Test name
Test status
Simulation time 91822473860 ps
CPU time 143.13 seconds
Started Feb 09 07:18:04 AM UTC 25
Finished Feb 09 07:20:30 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40952571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 49.uart_fifo_reset.40952571
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_intr.3622858205
Short name T910
Test name
Test status
Simulation time 40065534482 ps
CPU time 95.48 seconds
Started Feb 09 07:18:09 AM UTC 25
Finished Feb 09 07:19:46 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622858205 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.uart_intr.3622858205
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.3726093046
Short name T921
Test name
Test status
Simulation time 154269833224 ps
CPU time 133.55 seconds
Started Feb 09 07:18:32 AM UTC 25
Finished Feb 09 07:20:48 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726093046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3726093046
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_loopback.1499358620
Short name T891
Test name
Test status
Simulation time 2315216461 ps
CPU time 2.79 seconds
Started Feb 09 07:18:27 AM UTC 25
Finished Feb 09 07:18:31 AM UTC 25
Peak memory 206924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499358620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 49.uart_loopback.1499358620
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_noise_filter.2784780697
Short name T925
Test name
Test status
Simulation time 94357506984 ps
CPU time 175.05 seconds
Started Feb 09 07:18:11 AM UTC 25
Finished Feb 09 07:21:09 AM UTC 25
Peak memory 217364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784780697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 49.uart_noise_filter.2784780697
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_perf.952079627
Short name T932
Test name
Test status
Simulation time 6805385502 ps
CPU time 188.09 seconds
Started Feb 09 07:18:29 AM UTC 25
Finished Feb 09 07:21:41 AM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952079627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 49.uart_perf.952079627
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_rx_oversample.262671632
Short name T886
Test name
Test status
Simulation time 5175423959 ps
CPU time 5.08 seconds
Started Feb 09 07:18:06 AM UTC 25
Finished Feb 09 07:18:13 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262671632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.262671632
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.1911200522
Short name T908
Test name
Test status
Simulation time 80522105519 ps
CPU time 73.67 seconds
Started Feb 09 07:18:20 AM UTC 25
Finished Feb 09 07:19:35 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911200522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 49.uart_rx_parity_err.1911200522
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.486404813
Short name T889
Test name
Test status
Simulation time 6073328038 ps
CPU time 10.59 seconds
Started Feb 09 07:18:14 AM UTC 25
Finished Feb 09 07:18:26 AM UTC 25
Peak memory 204864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486404813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_
bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 49.uart_rx_start_bit_filter.486404813
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_smoke.3688502676
Short name T882
Test name
Test status
Simulation time 967981486 ps
CPU time 2.46 seconds
Started Feb 09 07:18:00 AM UTC 25
Finished Feb 09 07:18:04 AM UTC 25
Peak memory 208204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688502676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.uart_smoke.3688502676
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_stress_all.3821919938
Short name T901
Test name
Test status
Simulation time 60933217859 ps
CPU time 28.39 seconds
Started Feb 09 07:18:40 AM UTC 25
Finished Feb 09 07:19:10 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821919938 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3821919938
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.1510673529
Short name T981
Test name
Test status
Simulation time 49740879719 ps
CPU time 511.04 seconds
Started Feb 09 07:18:37 AM UTC 25
Finished Feb 09 07:27:14 AM UTC 25
Peak memory 229856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1510673529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1510673529
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.2274307005
Short name T890
Test name
Test status
Simulation time 650426897 ps
CPU time 2.76 seconds
Started Feb 09 07:18:24 AM UTC 25
Finished Feb 09 07:18:28 AM UTC 25
Peak memory 208160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274307005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.uart_tx_ovrd.2274307005
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_tx_rx.1069000096
Short name T894
Test name
Test status
Simulation time 61058563263 ps
CPU time 38.17 seconds
Started Feb 09 07:18:01 AM UTC 25
Finished Feb 09 07:18:41 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069000096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.uart_tx_rx.1069000096
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/49.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_alert_test.1969394130
Short name T433
Test name
Test status
Simulation time 41390296 ps
CPU time 0.85 seconds
Started Feb 09 06:39:45 AM UTC 25
Finished Feb 09 06:39:47 AM UTC 25
Peak memory 204404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969394130 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1969394130
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_fifo_reset.4172901631
Short name T300
Test name
Test status
Simulation time 196106506957 ps
CPU time 234.49 seconds
Started Feb 09 06:38:53 AM UTC 25
Finished Feb 09 06:42:51 AM UTC 25
Peak memory 208516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172901631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 5.uart_fifo_reset.4172901631
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_intr.2263793472
Short name T101
Test name
Test status
Simulation time 54895135899 ps
CPU time 59.44 seconds
Started Feb 09 06:39:03 AM UTC 25
Finished Feb 09 06:40:05 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263793472 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.uart_intr.2263793472
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.2652658771
Short name T498
Test name
Test status
Simulation time 124261069957 ps
CPU time 934.73 seconds
Started Feb 09 06:39:25 AM UTC 25
Finished Feb 09 06:55:10 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652658771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2652658771
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_loopback.2965389342
Short name T432
Test name
Test status
Simulation time 5716300468 ps
CPU time 26.06 seconds
Started Feb 09 06:39:17 AM UTC 25
Finished Feb 09 06:39:45 AM UTC 25
Peak memory 207444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965389342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 5.uart_loopback.2965389342
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_noise_filter.3420863481
Short name T315
Test name
Test status
Simulation time 126991409424 ps
CPU time 101.74 seconds
Started Feb 09 06:39:08 AM UTC 25
Finished Feb 09 06:40:51 AM UTC 25
Peak memory 208684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420863481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.uart_noise_filter.3420863481
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_perf.957772470
Short name T297
Test name
Test status
Simulation time 14673765207 ps
CPU time 308.66 seconds
Started Feb 09 06:39:17 AM UTC 25
Finished Feb 09 06:44:30 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957772470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 5.uart_perf.957772470
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_rx_oversample.2506234514
Short name T401
Test name
Test status
Simulation time 3239961873 ps
CPU time 17.73 seconds
Started Feb 09 06:38:56 AM UTC 25
Finished Feb 09 06:39:16 AM UTC 25
Peak memory 206984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506234514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2506234514
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.3862805197
Short name T302
Test name
Test status
Simulation time 139013800811 ps
CPU time 291.2 seconds
Started Feb 09 06:39:17 AM UTC 25
Finished Feb 09 06:44:12 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862805197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.uart_rx_parity_err.3862805197
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.3841375452
Short name T349
Test name
Test status
Simulation time 3140598991 ps
CPU time 3.63 seconds
Started Feb 09 06:39:12 AM UTC 25
Finished Feb 09 06:39:16 AM UTC 25
Peak memory 206772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841375452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3841375452
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_smoke.1380955686
Short name T329
Test name
Test status
Simulation time 5667930510 ps
CPU time 16.34 seconds
Started Feb 09 06:38:45 AM UTC 25
Finished Feb 09 06:39:02 AM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380955686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.uart_smoke.1380955686
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.972879234
Short name T828
Test name
Test status
Simulation time 80858131428 ps
CPU time 2130.35 seconds
Started Feb 09 06:39:38 AM UTC 25
Finished Feb 09 07:15:31 AM UTC 25
Peak memory 228672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=972879234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.972879234
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.3039824680
Short name T56
Test name
Test status
Simulation time 675140340 ps
CPU time 6.04 seconds
Started Feb 09 06:39:17 AM UTC 25
Finished Feb 09 06:39:24 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039824680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.uart_tx_ovrd.3039824680
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_tx_rx.3094451544
Short name T311
Test name
Test status
Simulation time 52804481787 ps
CPU time 258.99 seconds
Started Feb 09 06:38:46 AM UTC 25
Finished Feb 09 06:43:09 AM UTC 25
Peak memory 208676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094451544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.uart_tx_rx.3094451544
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/5.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/50.uart_fifo_reset.4113311600
Short name T902
Test name
Test status
Simulation time 15550814989 ps
CPU time 25.63 seconds
Started Feb 09 07:18:44 AM UTC 25
Finished Feb 09 07:19:12 AM UTC 25
Peak memory 208304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113311600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 50.uart_fifo_reset.4113311600
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/50.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.1889460404
Short name T73
Test name
Test status
Simulation time 472646495384 ps
CPU time 1318.98 seconds
Started Feb 09 07:18:48 AM UTC 25
Finished Feb 09 07:41:02 AM UTC 25
Peak memory 242948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1889460404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1889460404
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/51.uart_fifo_reset.3661945937
Short name T246
Test name
Test status
Simulation time 46505888904 ps
CPU time 66.74 seconds
Started Feb 09 07:18:49 AM UTC 25
Finished Feb 09 07:19:58 AM UTC 25
Peak memory 208524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661945937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 51.uart_fifo_reset.3661945937
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/51.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.939200040
Short name T999
Test name
Test status
Simulation time 414679004289 ps
CPU time 605 seconds
Started Feb 09 07:18:50 AM UTC 25
Finished Feb 09 07:29:03 AM UTC 25
Peak memory 235352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=939200040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.939200040
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/52.uart_fifo_reset.3041708461
Short name T923
Test name
Test status
Simulation time 127372294479 ps
CPU time 125.9 seconds
Started Feb 09 07:18:51 AM UTC 25
Finished Feb 09 07:20:59 AM UTC 25
Peak memory 208644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041708461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 52.uart_fifo_reset.3041708461
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/52.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.1275775901
Short name T1099
Test name
Test status
Simulation time 66015314245 ps
CPU time 913.02 seconds
Started Feb 09 07:18:58 AM UTC 25
Finished Feb 09 07:34:21 AM UTC 25
Peak memory 228568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1275775901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1275775901
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/53.uart_fifo_reset.2140208329
Short name T907
Test name
Test status
Simulation time 57346611267 ps
CPU time 35.63 seconds
Started Feb 09 07:18:58 AM UTC 25
Finished Feb 09 07:19:35 AM UTC 25
Peak memory 208432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140208329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 53.uart_fifo_reset.2140208329
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/53.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.2952348876
Short name T939
Test name
Test status
Simulation time 69822946184 ps
CPU time 186.76 seconds
Started Feb 09 07:19:05 AM UTC 25
Finished Feb 09 07:22:15 AM UTC 25
Peak memory 219636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2952348876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2952348876
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/54.uart_fifo_reset.1798869054
Short name T920
Test name
Test status
Simulation time 22079006200 ps
CPU time 92.78 seconds
Started Feb 09 07:19:11 AM UTC 25
Finished Feb 09 07:20:46 AM UTC 25
Peak memory 208496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798869054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 54.uart_fifo_reset.1798869054
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/54.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/55.uart_fifo_reset.75493112
Short name T934
Test name
Test status
Simulation time 69946151051 ps
CPU time 141.86 seconds
Started Feb 09 07:19:20 AM UTC 25
Finished Feb 09 07:21:44 AM UTC 25
Peak memory 208428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75493112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 55.uart_fifo_reset.75493112
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/55.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.3966515098
Short name T937
Test name
Test status
Simulation time 16113105698 ps
CPU time 159.07 seconds
Started Feb 09 07:19:21 AM UTC 25
Finished Feb 09 07:22:03 AM UTC 25
Peak memory 223644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3966515098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3966515098
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/56.uart_fifo_reset.3414133984
Short name T199
Test name
Test status
Simulation time 228827506947 ps
CPU time 38.2 seconds
Started Feb 09 07:19:24 AM UTC 25
Finished Feb 09 07:20:04 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414133984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 56.uart_fifo_reset.3414133984
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/56.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.3307661663
Short name T258
Test name
Test status
Simulation time 227483536096 ps
CPU time 609.54 seconds
Started Feb 09 07:19:29 AM UTC 25
Finished Feb 09 07:29:46 AM UTC 25
Peak memory 223576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3307661663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3307661663
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.2523124836
Short name T974
Test name
Test status
Simulation time 164074339022 ps
CPU time 418.31 seconds
Started Feb 09 07:19:33 AM UTC 25
Finished Feb 09 07:26:37 AM UTC 25
Peak memory 221620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2523124836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2523124836
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/58.uart_fifo_reset.1672427692
Short name T204
Test name
Test status
Simulation time 14513832562 ps
CPU time 53.06 seconds
Started Feb 09 07:19:35 AM UTC 25
Finished Feb 09 07:20:30 AM UTC 25
Peak memory 208508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672427692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 58.uart_fifo_reset.1672427692
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/58.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.2704123627
Short name T72
Test name
Test status
Simulation time 76012666005 ps
CPU time 767.73 seconds
Started Feb 09 07:19:35 AM UTC 25
Finished Feb 09 07:32:32 AM UTC 25
Peak memory 238988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2704123627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2704123627
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/59.uart_fifo_reset.1775068893
Short name T914
Test name
Test status
Simulation time 31201104345 ps
CPU time 27.63 seconds
Started Feb 09 07:19:37 AM UTC 25
Finished Feb 09 07:20:06 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775068893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 59.uart_fifo_reset.1775068893
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/59.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.3201670795
Short name T1123
Test name
Test status
Simulation time 331008492568 ps
CPU time 925.52 seconds
Started Feb 09 07:19:37 AM UTC 25
Finished Feb 09 07:35:12 AM UTC 25
Peak memory 238936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3201670795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3201670795
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_alert_test.2729297017
Short name T434
Test name
Test status
Simulation time 36279624 ps
CPU time 0.83 seconds
Started Feb 09 06:40:45 AM UTC 25
Finished Feb 09 06:40:47 AM UTC 25
Peak memory 204404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729297017 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2729297017
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_fifo_full.1146444473
Short name T171
Test name
Test status
Simulation time 263289849800 ps
CPU time 67.65 seconds
Started Feb 09 06:39:54 AM UTC 25
Finished Feb 09 06:41:04 AM UTC 25
Peak memory 208672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146444473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 6.uart_fifo_full.1146444473
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.3299960023
Short name T163
Test name
Test status
Simulation time 52825666756 ps
CPU time 35.07 seconds
Started Feb 09 06:40:00 AM UTC 25
Finished Feb 09 06:40:36 AM UTC 25
Peak memory 208120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299960023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.uart_fifo_overflow.3299960023
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_fifo_reset.1707739221
Short name T172
Test name
Test status
Simulation time 102637517132 ps
CPU time 137.31 seconds
Started Feb 09 06:40:02 AM UTC 25
Finished Feb 09 06:42:22 AM UTC 25
Peak memory 208620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707739221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 6.uart_fifo_reset.1707739221
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_intr.1064017107
Short name T283
Test name
Test status
Simulation time 6850603358 ps
CPU time 9.98 seconds
Started Feb 09 06:40:21 AM UTC 25
Finished Feb 09 06:40:33 AM UTC 25
Peak memory 208224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064017107 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.uart_intr.1064017107
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.509470087
Short name T535
Test name
Test status
Simulation time 191171893248 ps
CPU time 1057.71 seconds
Started Feb 09 06:40:37 AM UTC 25
Finished Feb 09 06:58:27 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509470087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.509470087
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_perf.3519773985
Short name T288
Test name
Test status
Simulation time 11446467909 ps
CPU time 589.22 seconds
Started Feb 09 06:40:34 AM UTC 25
Finished Feb 09 06:50:30 AM UTC 25
Peak memory 208412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519773985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 6.uart_perf.3519773985
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_rx_oversample.934132183
Short name T435
Test name
Test status
Simulation time 6430498392 ps
CPU time 50.08 seconds
Started Feb 09 06:40:05 AM UTC 25
Finished Feb 09 06:40:57 AM UTC 25
Peak memory 208356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934132183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.934132183
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.1428558423
Short name T147
Test name
Test status
Simulation time 19526539765 ps
CPU time 28.95 seconds
Started Feb 09 06:40:31 AM UTC 25
Finished Feb 09 06:41:01 AM UTC 25
Peak memory 208296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428558423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.uart_rx_parity_err.1428558423
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.1239538715
Short name T303
Test name
Test status
Simulation time 2317678988 ps
CPU time 4.91 seconds
Started Feb 09 06:40:27 AM UTC 25
Finished Feb 09 06:40:33 AM UTC 25
Peak memory 204860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239538715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1239538715
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_smoke.3926564215
Short name T330
Test name
Test status
Simulation time 5869171335 ps
CPU time 8.97 seconds
Started Feb 09 06:39:48 AM UTC 25
Finished Feb 09 06:39:59 AM UTC 25
Peak memory 208092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926564215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.uart_smoke.3926564215
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_stress_all.1228375474
Short name T149
Test name
Test status
Simulation time 109793320080 ps
CPU time 66.03 seconds
Started Feb 09 06:40:39 AM UTC 25
Finished Feb 09 06:41:47 AM UTC 25
Peak memory 208620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228375474 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1228375474
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.1697813552
Short name T26
Test name
Test status
Simulation time 36695449916 ps
CPU time 673.81 seconds
Started Feb 09 06:40:39 AM UTC 25
Finished Feb 09 06:52:01 AM UTC 25
Peak memory 217436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1697813552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1697813552
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.6689168
Short name T290
Test name
Test status
Simulation time 613984899 ps
CPU time 4.78 seconds
Started Feb 09 06:40:32 AM UTC 25
Finished Feb 09 06:40:38 AM UTC 25
Peak memory 207360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6689168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 6.uart_tx_ovrd.6689168
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/6.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/60.uart_fifo_reset.3879680288
Short name T918
Test name
Test status
Simulation time 19672245800 ps
CPU time 54.86 seconds
Started Feb 09 07:19:44 AM UTC 25
Finished Feb 09 07:20:40 AM UTC 25
Peak memory 208536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879680288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 60.uart_fifo_reset.3879680288
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/60.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.1624113659
Short name T955
Test name
Test status
Simulation time 18267587794 ps
CPU time 285.09 seconds
Started Feb 09 07:19:47 AM UTC 25
Finished Feb 09 07:24:36 AM UTC 25
Peak memory 225128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1624113659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1624113659
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/61.uart_fifo_reset.2553417934
Short name T931
Test name
Test status
Simulation time 88948382138 ps
CPU time 110 seconds
Started Feb 09 07:19:48 AM UTC 25
Finished Feb 09 07:21:40 AM UTC 25
Peak memory 208616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553417934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 61.uart_fifo_reset.2553417934
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/61.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.1384600391
Short name T1006
Test name
Test status
Simulation time 37023497488 ps
CPU time 562.29 seconds
Started Feb 09 07:19:59 AM UTC 25
Finished Feb 09 07:29:29 AM UTC 25
Peak memory 217300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1384600391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1384600391
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/62.uart_fifo_reset.4265088003
Short name T929
Test name
Test status
Simulation time 41267904128 ps
CPU time 83.88 seconds
Started Feb 09 07:20:04 AM UTC 25
Finished Feb 09 07:21:30 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265088003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 62.uart_fifo_reset.4265088003
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/62.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.1530796245
Short name T75
Test name
Test status
Simulation time 88749456602 ps
CPU time 1347.31 seconds
Started Feb 09 07:20:05 AM UTC 25
Finished Feb 09 07:42:48 AM UTC 25
Peak memory 238912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1530796245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1530796245
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/63.uart_fifo_reset.1574276776
Short name T268
Test name
Test status
Simulation time 45101248312 ps
CPU time 15.59 seconds
Started Feb 09 07:20:06 AM UTC 25
Finished Feb 09 07:20:23 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574276776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 63.uart_fifo_reset.1574276776
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/63.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.3223618790
Short name T70
Test name
Test status
Simulation time 43316881835 ps
CPU time 542.98 seconds
Started Feb 09 07:20:06 AM UTC 25
Finished Feb 09 07:29:16 AM UTC 25
Peak memory 235408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3223618790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3223618790
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/64.uart_fifo_reset.1390563790
Short name T213
Test name
Test status
Simulation time 17081288889 ps
CPU time 57.67 seconds
Started Feb 09 07:20:08 AM UTC 25
Finished Feb 09 07:21:08 AM UTC 25
Peak memory 208456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390563790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 64.uart_fifo_reset.1390563790
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/64.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.677559511
Short name T1162
Test name
Test status
Simulation time 576975472472 ps
CPU time 1013.4 seconds
Started Feb 09 07:20:16 AM UTC 25
Finished Feb 09 07:37:22 AM UTC 25
Peak memory 238844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=677559511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.677559511
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.3811238504
Short name T71
Test name
Test status
Simulation time 64070409364 ps
CPU time 607.48 seconds
Started Feb 09 07:20:30 AM UTC 25
Finished Feb 09 07:30:44 AM UTC 25
Peak memory 235468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3811238504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3811238504
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/66.uart_fifo_reset.1932212035
Short name T926
Test name
Test status
Simulation time 60856876018 ps
CPU time 50.33 seconds
Started Feb 09 07:20:31 AM UTC 25
Finished Feb 09 07:21:22 AM UTC 25
Peak memory 208300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932212035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 66.uart_fifo_reset.1932212035
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/66.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.2144323580
Short name T1007
Test name
Test status
Simulation time 116547702088 ps
CPU time 531.89 seconds
Started Feb 09 07:20:31 AM UTC 25
Finished Feb 09 07:29:29 AM UTC 25
Peak memory 235440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2144323580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2144323580
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/67.uart_fifo_reset.839604097
Short name T250
Test name
Test status
Simulation time 34406408228 ps
CPU time 25.06 seconds
Started Feb 09 07:20:41 AM UTC 25
Finished Feb 09 07:21:07 AM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839604097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 67.uart_fifo_reset.839604097
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/67.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.258346344
Short name T1121
Test name
Test status
Simulation time 48465674900 ps
CPU time 856.15 seconds
Started Feb 09 07:20:45 AM UTC 25
Finished Feb 09 07:35:11 AM UTC 25
Peak memory 228676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=258346344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.258346344
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/68.uart_fifo_reset.979296495
Short name T950
Test name
Test status
Simulation time 263900542494 ps
CPU time 189.13 seconds
Started Feb 09 07:20:47 AM UTC 25
Finished Feb 09 07:23:59 AM UTC 25
Peak memory 208416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979296495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 68.uart_fifo_reset.979296495
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/68.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.3526341212
Short name T973
Test name
Test status
Simulation time 47191587795 ps
CPU time 333.89 seconds
Started Feb 09 07:20:49 AM UTC 25
Finished Feb 09 07:26:27 AM UTC 25
Peak memory 223576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3526341212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3526341212
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/69.uart_fifo_reset.1725694386
Short name T927
Test name
Test status
Simulation time 10167509250 ps
CPU time 34.67 seconds
Started Feb 09 07:20:52 AM UTC 25
Finished Feb 09 07:21:28 AM UTC 25
Peak memory 208340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725694386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 69.uart_fifo_reset.1725694386
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/69.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.1686789914
Short name T1015
Test name
Test status
Simulation time 700851823547 ps
CPU time 530.65 seconds
Started Feb 09 07:21:00 AM UTC 25
Finished Feb 09 07:29:57 AM UTC 25
Peak memory 234972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1686789914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1686789914
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_alert_test.4021766311
Short name T436
Test name
Test status
Simulation time 20584114 ps
CPU time 0.84 seconds
Started Feb 09 06:41:30 AM UTC 25
Finished Feb 09 06:41:32 AM UTC 25
Peak memory 204404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021766311 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.4021766311
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_fifo_full.2888488378
Short name T333
Test name
Test status
Simulation time 206845167899 ps
CPU time 408.67 seconds
Started Feb 09 06:40:51 AM UTC 25
Finished Feb 09 06:47:45 AM UTC 25
Peak memory 208576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888488378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 7.uart_fifo_full.2888488378
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.736173084
Short name T164
Test name
Test status
Simulation time 18208392783 ps
CPU time 34.95 seconds
Started Feb 09 06:40:53 AM UTC 25
Finished Feb 09 06:41:29 AM UTC 25
Peak memory 208440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736173084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_over
flow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.uart_fifo_overflow.736173084
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2263758116
Short name T153
Test name
Test status
Simulation time 54370802208 ps
CPU time 42.07 seconds
Started Feb 09 06:40:57 AM UTC 25
Finished Feb 09 06:41:40 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263758116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 7.uart_fifo_reset.2263758116
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_intr.871958163
Short name T299
Test name
Test status
Simulation time 15196496294 ps
CPU time 12.63 seconds
Started Feb 09 06:41:02 AM UTC 25
Finished Feb 09 06:41:16 AM UTC 25
Peak memory 208516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871958163 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.uart_intr.871958163
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.3586144137
Short name T361
Test name
Test status
Simulation time 100857763610 ps
CPU time 227.9 seconds
Started Feb 09 06:41:16 AM UTC 25
Finished Feb 09 06:45:07 AM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586144137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3586144137
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_loopback.1773546027
Short name T405
Test name
Test status
Simulation time 11473056607 ps
CPU time 14.5 seconds
Started Feb 09 06:41:13 AM UTC 25
Finished Feb 09 06:41:29 AM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773546027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 7.uart_loopback.1773546027
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_noise_filter.3543221639
Short name T286
Test name
Test status
Simulation time 92258789788 ps
CPU time 319 seconds
Started Feb 09 06:41:05 AM UTC 25
Finished Feb 09 06:46:28 AM UTC 25
Peak memory 208592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543221639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.uart_noise_filter.3543221639
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_perf.280687832
Short name T427
Test name
Test status
Simulation time 21786301084 ps
CPU time 1128.73 seconds
Started Feb 09 06:41:16 AM UTC 25
Finished Feb 09 07:00:17 AM UTC 25
Peak memory 211948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280687832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ
=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 7.uart_perf.280687832
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_rx_oversample.2846183651
Short name T403
Test name
Test status
Simulation time 1863963561 ps
CPU time 8.49 seconds
Started Feb 09 06:40:58 AM UTC 25
Finished Feb 09 06:41:07 AM UTC 25
Peak memory 207224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846183651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2846183651
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.3509313132
Short name T309
Test name
Test status
Simulation time 44446913839 ps
CPU time 71.46 seconds
Started Feb 09 06:41:08 AM UTC 25
Finished Feb 09 06:42:22 AM UTC 25
Peak memory 208000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509313132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.uart_rx_parity_err.3509313132
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.184089787
Short name T371
Test name
Test status
Simulation time 4917211972 ps
CPU time 2.19 seconds
Started Feb 09 06:41:05 AM UTC 25
Finished Feb 09 06:41:09 AM UTC 25
Peak memory 206912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184089787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_
bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 7.uart_rx_start_bit_filter.184089787
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_smoke.4228760672
Short name T362
Test name
Test status
Simulation time 5808013727 ps
CPU time 14.91 seconds
Started Feb 09 06:40:47 AM UTC 25
Finished Feb 09 06:41:04 AM UTC 25
Peak memory 207436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228760672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.uart_smoke.4228760672
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_stress_all.805095891
Short name T186
Test name
Test status
Simulation time 470022323094 ps
CPU time 1560.83 seconds
Started Feb 09 06:41:29 AM UTC 25
Finished Feb 09 07:07:46 AM UTC 25
Peak memory 222456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805095891 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.805095891
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.1082751323
Short name T34
Test name
Test status
Simulation time 60545640141 ps
CPU time 789.61 seconds
Started Feb 09 06:41:25 AM UTC 25
Finished Feb 09 06:54:44 AM UTC 25
Peak memory 223636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1082751323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1082751323
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.3029890762
Short name T359
Test name
Test status
Simulation time 1730082778 ps
CPU time 1.89 seconds
Started Feb 09 06:41:09 AM UTC 25
Finished Feb 09 06:41:12 AM UTC 25
Peak memory 206408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029890762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.uart_tx_ovrd.3029890762
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_tx_rx.3934313740
Short name T331
Test name
Test status
Simulation time 20984787259 ps
CPU time 46.28 seconds
Started Feb 09 06:40:48 AM UTC 25
Finished Feb 09 06:41:37 AM UTC 25
Peak memory 208604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934313740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.uart_tx_rx.3934313740
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/7.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/70.uart_fifo_reset.3274288007
Short name T936
Test name
Test status
Simulation time 62751943240 ps
CPU time 49.54 seconds
Started Feb 09 07:21:01 AM UTC 25
Finished Feb 09 07:21:52 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274288007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 70.uart_fifo_reset.3274288007
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/70.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.4004521064
Short name T995
Test name
Test status
Simulation time 32509857719 ps
CPU time 444.85 seconds
Started Feb 09 07:21:08 AM UTC 25
Finished Feb 09 07:28:39 AM UTC 25
Peak memory 217520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4004521064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.4004521064
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/71.uart_fifo_reset.2773898477
Short name T945
Test name
Test status
Simulation time 66739501175 ps
CPU time 119.55 seconds
Started Feb 09 07:21:08 AM UTC 25
Finished Feb 09 07:23:10 AM UTC 25
Peak memory 208396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773898477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 71.uart_fifo_reset.2773898477
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/71.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.1002688192
Short name T1169
Test name
Test status
Simulation time 271867200072 ps
CPU time 1061.57 seconds
Started Feb 09 07:21:09 AM UTC 25
Finished Feb 09 07:39:03 AM UTC 25
Peak memory 238936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1002688192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1002688192
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/72.uart_fifo_reset.3939435349
Short name T928
Test name
Test status
Simulation time 19511344683 ps
CPU time 17.75 seconds
Started Feb 09 07:21:09 AM UTC 25
Finished Feb 09 07:21:29 AM UTC 25
Peak memory 208288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939435349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 72.uart_fifo_reset.3939435349
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/72.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.964858975
Short name T76
Test name
Test status
Simulation time 2496901405595 ps
CPU time 1431.71 seconds
Started Feb 09 07:21:24 AM UTC 25
Finished Feb 09 07:45:31 AM UTC 25
Peak memory 243144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=964858975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.964858975
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.3737743631
Short name T1174
Test name
Test status
Simulation time 320047383749 ps
CPU time 1309.56 seconds
Started Feb 09 07:21:29 AM UTC 25
Finished Feb 09 07:43:33 AM UTC 25
Peak memory 238792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3737743631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3737743631
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/74.uart_fifo_reset.1031902724
Short name T274
Test name
Test status
Simulation time 27231264535 ps
CPU time 30.03 seconds
Started Feb 09 07:21:30 AM UTC 25
Finished Feb 09 07:22:01 AM UTC 25
Peak memory 208396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031902724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 74.uart_fifo_reset.1031902724
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/74.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.1399985790
Short name T949
Test name
Test status
Simulation time 11760058444 ps
CPU time 139.51 seconds
Started Feb 09 07:21:31 AM UTC 25
Finished Feb 09 07:23:53 AM UTC 25
Peak memory 217300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1399985790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1399985790
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/75.uart_fifo_reset.1441815365
Short name T968
Test name
Test status
Simulation time 112365467254 ps
CPU time 245.09 seconds
Started Feb 09 07:21:37 AM UTC 25
Finished Feb 09 07:25:46 AM UTC 25
Peak memory 208496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441815365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 75.uart_fifo_reset.1441815365
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/75.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.2785903085
Short name T1046
Test name
Test status
Simulation time 122155885588 ps
CPU time 613.06 seconds
Started Feb 09 07:21:41 AM UTC 25
Finished Feb 09 07:32:01 AM UTC 25
Peak memory 224680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2785903085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2785903085
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/76.uart_fifo_reset.3374737116
Short name T206
Test name
Test status
Simulation time 67777217329 ps
CPU time 78.01 seconds
Started Feb 09 07:21:42 AM UTC 25
Finished Feb 09 07:23:02 AM UTC 25
Peak memory 208524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374737116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 76.uart_fifo_reset.3374737116
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/76.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.2646712721
Short name T1044
Test name
Test status
Simulation time 40806861219 ps
CPU time 607.38 seconds
Started Feb 09 07:21:42 AM UTC 25
Finished Feb 09 07:31:57 AM UTC 25
Peak memory 225148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2646712721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2646712721
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/77.uart_fifo_reset.2334263031
Short name T938
Test name
Test status
Simulation time 79244955786 ps
CPU time 24.79 seconds
Started Feb 09 07:21:45 AM UTC 25
Finished Feb 09 07:22:11 AM UTC 25
Peak memory 207828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334263031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 77.uart_fifo_reset.2334263031
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/77.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.1288467266
Short name T1001
Test name
Test status
Simulation time 197744105144 ps
CPU time 437.56 seconds
Started Feb 09 07:21:45 AM UTC 25
Finished Feb 09 07:29:08 AM UTC 25
Peak memory 217432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1288467266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1288467266
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/78.uart_fifo_reset.2904613093
Short name T947
Test name
Test status
Simulation time 133462310671 ps
CPU time 79.66 seconds
Started Feb 09 07:21:53 AM UTC 25
Finished Feb 09 07:23:15 AM UTC 25
Peak memory 208496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904613093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 78.uart_fifo_reset.2904613093
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/78.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.1105796544
Short name T990
Test name
Test status
Simulation time 36281589962 ps
CPU time 390.11 seconds
Started Feb 09 07:21:54 AM UTC 25
Finished Feb 09 07:28:30 AM UTC 25
Peak memory 225272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1105796544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1105796544
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/79.uart_fifo_reset.423435825
Short name T422
Test name
Test status
Simulation time 112848165098 ps
CPU time 237.86 seconds
Started Feb 09 07:22:02 AM UTC 25
Finished Feb 09 07:26:03 AM UTC 25
Peak memory 208620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423435825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 79.uart_fifo_reset.423435825
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/79.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.820177910
Short name T1003
Test name
Test status
Simulation time 71577034711 ps
CPU time 424.02 seconds
Started Feb 09 07:22:03 AM UTC 25
Finished Feb 09 07:29:13 AM UTC 25
Peak memory 223632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=820177910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.820177910
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_alert_test.2997409410
Short name T439
Test name
Test status
Simulation time 14138226 ps
CPU time 0.84 seconds
Started Feb 09 06:42:30 AM UTC 25
Finished Feb 09 06:42:32 AM UTC 25
Peak memory 204404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997409410 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2997409410
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_fifo_full.170312984
Short name T154
Test name
Test status
Simulation time 28977733276 ps
CPU time 48.7 seconds
Started Feb 09 06:41:39 AM UTC 25
Finished Feb 09 06:42:29 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170312984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 8.uart_fifo_full.170312984
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_fifo_reset.1039569066
Short name T314
Test name
Test status
Simulation time 8866641913 ps
CPU time 14.94 seconds
Started Feb 09 06:41:45 AM UTC 25
Finished Feb 09 06:42:01 AM UTC 25
Peak memory 208620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039569066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 8.uart_fifo_reset.1039569066
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_intr.2042343180
Short name T370
Test name
Test status
Simulation time 234989256425 ps
CPU time 371.82 seconds
Started Feb 09 06:42:02 AM UTC 25
Finished Feb 09 06:48:19 AM UTC 25
Peak memory 208424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042343180 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.uart_intr.2042343180
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_loopback.446986549
Short name T438
Test name
Test status
Simulation time 998989833 ps
CPU time 2.26 seconds
Started Feb 09 06:42:22 AM UTC 25
Finished Feb 09 06:42:26 AM UTC 25
Peak memory 204736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446986549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.uart_loopback.446986549
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_perf.1728328269
Short name T365
Test name
Test status
Simulation time 9830149311 ps
CPU time 533.47 seconds
Started Feb 09 06:42:23 AM UTC 25
Finished Feb 09 06:51:22 AM UTC 25
Peak memory 208608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728328269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 8.uart_perf.1728328269
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_rx_oversample.1144265588
Short name T437
Test name
Test status
Simulation time 5589227629 ps
CPU time 32.65 seconds
Started Feb 09 06:41:48 AM UTC 25
Finished Feb 09 06:42:22 AM UTC 25
Peak memory 207072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144265588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1144265588
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.4037924570
Short name T158
Test name
Test status
Simulation time 60867512610 ps
CPU time 125.39 seconds
Started Feb 09 06:42:18 AM UTC 25
Finished Feb 09 06:44:26 AM UTC 25
Peak memory 208488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037924570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.uart_rx_parity_err.4037924570
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.2905943513
Short name T380
Test name
Test status
Simulation time 501270003 ps
CPU time 2.79 seconds
Started Feb 09 06:42:13 AM UTC 25
Finished Feb 09 06:42:17 AM UTC 25
Peak memory 204796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905943513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2905943513
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_smoke.3949998001
Short name T364
Test name
Test status
Simulation time 649394000 ps
CPU time 2.8 seconds
Started Feb 09 06:41:33 AM UTC 25
Finished Feb 09 06:41:37 AM UTC 25
Peak memory 208600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949998001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.uart_smoke.3949998001
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.585623898
Short name T27
Test name
Test status
Simulation time 61888279399 ps
CPU time 664.75 seconds
Started Feb 09 06:42:24 AM UTC 25
Finished Feb 09 06:53:37 AM UTC 25
Peak memory 223708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=585623898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.585623898
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.1357494190
Short name T353
Test name
Test status
Simulation time 1300615383 ps
CPU time 2.75 seconds
Started Feb 09 06:42:18 AM UTC 25
Finished Feb 09 06:42:22 AM UTC 25
Peak memory 208264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357494190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.uart_tx_ovrd.1357494190
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_tx_rx.810013416
Short name T316
Test name
Test status
Simulation time 90181888171 ps
CPU time 33.02 seconds
Started Feb 09 06:41:38 AM UTC 25
Finished Feb 09 06:42:12 AM UTC 25
Peak memory 208420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810013416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 8.uart_tx_rx.810013416
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/8.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/80.uart_fifo_reset.2473509163
Short name T943
Test name
Test status
Simulation time 40306458416 ps
CPU time 42.44 seconds
Started Feb 09 07:22:13 AM UTC 25
Finished Feb 09 07:22:57 AM UTC 25
Peak memory 208620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473509163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 80.uart_fifo_reset.2473509163
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/80.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.2554335831
Short name T957
Test name
Test status
Simulation time 19670974706 ps
CPU time 149.64 seconds
Started Feb 09 07:22:16 AM UTC 25
Finished Feb 09 07:24:48 AM UTC 25
Peak memory 224632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2554335831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2554335831
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/81.uart_fifo_reset.1280447184
Short name T215
Test name
Test status
Simulation time 83760992364 ps
CPU time 65.75 seconds
Started Feb 09 07:22:16 AM UTC 25
Finished Feb 09 07:23:23 AM UTC 25
Peak memory 208588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280447184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 81.uart_fifo_reset.1280447184
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/81.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.3476444469
Short name T1172
Test name
Test status
Simulation time 199014886677 ps
CPU time 1095.11 seconds
Started Feb 09 07:22:33 AM UTC 25
Finished Feb 09 07:41:00 AM UTC 25
Peak memory 228836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3476444469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3476444469
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/82.uart_fifo_reset.211524112
Short name T956
Test name
Test status
Simulation time 189545202556 ps
CPU time 124.15 seconds
Started Feb 09 07:22:37 AM UTC 25
Finished Feb 09 07:24:43 AM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211524112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 82.uart_fifo_reset.211524112
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/82.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.3937091542
Short name T1173
Test name
Test status
Simulation time 434938055745 ps
CPU time 1184.49 seconds
Started Feb 09 07:22:57 AM UTC 25
Finished Feb 09 07:42:55 AM UTC 25
Peak memory 228532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3937091542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3937091542
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/83.uart_fifo_reset.1311470905
Short name T972
Test name
Test status
Simulation time 61490254890 ps
CPU time 189.95 seconds
Started Feb 09 07:23:03 AM UTC 25
Finished Feb 09 07:26:16 AM UTC 25
Peak memory 208424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311470905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 83.uart_fifo_reset.1311470905
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/83.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.1655247912
Short name T1004
Test name
Test status
Simulation time 31481796984 ps
CPU time 365.46 seconds
Started Feb 09 07:23:08 AM UTC 25
Finished Feb 09 07:29:18 AM UTC 25
Peak memory 224372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1655247912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1655247912
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/84.uart_fifo_reset.1276913436
Short name T965
Test name
Test status
Simulation time 122369063058 ps
CPU time 140.6 seconds
Started Feb 09 07:23:11 AM UTC 25
Finished Feb 09 07:25:34 AM UTC 25
Peak memory 208456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276913436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 84.uart_fifo_reset.1276913436
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/84.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.2969979724
Short name T1166
Test name
Test status
Simulation time 49331526220 ps
CPU time 899.42 seconds
Started Feb 09 07:23:13 AM UTC 25
Finished Feb 09 07:38:22 AM UTC 25
Peak memory 224776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2969979724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2969979724
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/85.uart_fifo_reset.84657225
Short name T966
Test name
Test status
Simulation time 122384399061 ps
CPU time 142.25 seconds
Started Feb 09 07:23:15 AM UTC 25
Finished Feb 09 07:25:40 AM UTC 25
Peak memory 208648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84657225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 85.uart_fifo_reset.84657225
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/85.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.889591593
Short name T74
Test name
Test status
Simulation time 78033732124 ps
CPU time 1090.04 seconds
Started Feb 09 07:23:23 AM UTC 25
Finished Feb 09 07:41:46 AM UTC 25
Peak memory 238932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=889591593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.889591593
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/86.uart_fifo_reset.3428114391
Short name T228
Test name
Test status
Simulation time 15530882465 ps
CPU time 56.4 seconds
Started Feb 09 07:23:24 AM UTC 25
Finished Feb 09 07:24:23 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428114391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 86.uart_fifo_reset.3428114391
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/86.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.3969267670
Short name T988
Test name
Test status
Simulation time 32802657809 ps
CPU time 295.19 seconds
Started Feb 09 07:23:26 AM UTC 25
Finished Feb 09 07:28:25 AM UTC 25
Peak memory 217560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3969267670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3969267670
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/87.uart_fifo_reset.42478842
Short name T959
Test name
Test status
Simulation time 177816451803 ps
CPU time 64.6 seconds
Started Feb 09 07:23:54 AM UTC 25
Finished Feb 09 07:25:00 AM UTC 25
Peak memory 208420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42478842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 87.uart_fifo_reset.42478842
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/87.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.3239164708
Short name T1096
Test name
Test status
Simulation time 145951503913 ps
CPU time 610.54 seconds
Started Feb 09 07:24:00 AM UTC 25
Finished Feb 09 07:34:17 AM UTC 25
Peak memory 223824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3239164708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3239164708
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/88.uart_fifo_reset.933326500
Short name T982
Test name
Test status
Simulation time 227550561428 ps
CPU time 188.83 seconds
Started Feb 09 07:24:05 AM UTC 25
Finished Feb 09 07:27:17 AM UTC 25
Peak memory 208460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933326500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 88.uart_fifo_reset.933326500
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/88.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.3887966879
Short name T986
Test name
Test status
Simulation time 13500787014 ps
CPU time 216.35 seconds
Started Feb 09 07:24:05 AM UTC 25
Finished Feb 09 07:27:45 AM UTC 25
Peak memory 217432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3887966879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3887966879
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/89.uart_fifo_reset.2633445123
Short name T962
Test name
Test status
Simulation time 40959045237 ps
CPU time 62.8 seconds
Started Feb 09 07:24:06 AM UTC 25
Finished Feb 09 07:25:11 AM UTC 25
Peak memory 208648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633445123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 89.uart_fifo_reset.2633445123
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/89.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.193686724
Short name T1000
Test name
Test status
Simulation time 91222775707 ps
CPU time 293.51 seconds
Started Feb 09 07:24:08 AM UTC 25
Finished Feb 09 07:29:06 AM UTC 25
Peak memory 223708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=193686724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.193686724
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_alert_test.3067119458
Short name T47
Test name
Test status
Simulation time 61648639 ps
CPU time 0.85 seconds
Started Feb 09 06:44:00 AM UTC 25
Finished Feb 09 06:44:02 AM UTC 25
Peak memory 204404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067119458 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3067119458
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_fifo_full.1541212013
Short name T41
Test name
Test status
Simulation time 45560191316 ps
CPU time 34.15 seconds
Started Feb 09 06:42:48 AM UTC 25
Finished Feb 09 06:43:24 AM UTC 25
Peak memory 208404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541212013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 9.uart_fifo_full.1541212013
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.364469988
Short name T313
Test name
Test status
Simulation time 92690559826 ps
CPU time 324.86 seconds
Started Feb 09 06:42:52 AM UTC 25
Finished Feb 09 06:48:21 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364469988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_over
flow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 9.uart_fifo_overflow.364469988
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_intr.2089699553
Short name T45
Test name
Test status
Simulation time 123305011071 ps
CPU time 49.01 seconds
Started Feb 09 06:43:02 AM UTC 25
Finished Feb 09 06:43:54 AM UTC 25
Peak memory 206916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089699553 -assert nopostproc +UVM_TESTNAME=uart_base_test
+UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.uart_intr.2089699553
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.3381489014
Short name T294
Test name
Test status
Simulation time 66543913990 ps
CPU time 238.32 seconds
Started Feb 09 06:43:47 AM UTC 25
Finished Feb 09 06:47:48 AM UTC 25
Peak memory 208496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381489014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3381489014
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_loopback.426188956
Short name T46
Test name
Test status
Simulation time 14081307635 ps
CPU time 25.9 seconds
Started Feb 09 06:43:32 AM UTC 25
Finished Feb 09 06:43:59 AM UTC 25
Peak memory 207776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426188956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.uart_loopback.426188956
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_noise_filter.4174494105
Short name T307
Test name
Test status
Simulation time 37769190626 ps
CPU time 96.08 seconds
Started Feb 09 06:43:10 AM UTC 25
Finished Feb 09 06:44:48 AM UTC 25
Peak memory 208432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174494105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_fi
lter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 9.uart_noise_filter.4174494105
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_perf.4208628930
Short name T467
Test name
Test status
Simulation time 7747031852 ps
CPU time 437.96 seconds
Started Feb 09 06:43:35 AM UTC 25
Finished Feb 09 06:50:58 AM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208628930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 9.uart_perf.4208628930
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_rx_oversample.4294194864
Short name T440
Test name
Test status
Simulation time 6310321001 ps
CPU time 69.29 seconds
Started Feb 09 06:43:00 AM UTC 25
Finished Feb 09 06:44:11 AM UTC 25
Peak memory 207480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294194864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SE
Q=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4294194864
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.3517156075
Short name T42
Test name
Test status
Simulation time 13252055843 ps
CPU time 8.87 seconds
Started Feb 09 06:43:21 AM UTC 25
Finished Feb 09 06:43:31 AM UTC 25
Peak memory 208524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517156075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parit
y_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.uart_rx_parity_err.3517156075
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.4025965032
Short name T312
Test name
Test status
Simulation time 79943645150 ps
CPU time 75.93 seconds
Started Feb 09 06:43:11 AM UTC 25
Finished Feb 09 06:44:28 AM UTC 25
Peak memory 204724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025965032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start
_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 9.uart_rx_start_bit_filter.4025965032
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_smoke.3362881554
Short name T295
Test name
Test status
Simulation time 5385150175 ps
CPU time 12.43 seconds
Started Feb 09 06:42:33 AM UTC 25
Finished Feb 09 06:42:47 AM UTC 25
Peak memory 208064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362881554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.uart_smoke.3362881554
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_stress_all.1421996156
Short name T326
Test name
Test status
Simulation time 636427811399 ps
CPU time 395.62 seconds
Started Feb 09 06:43:55 AM UTC 25
Finished Feb 09 06:50:35 AM UTC 25
Peak memory 217372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421996156 -assert nopostproc +UVM_TESTNAME=uart_base_tes
t +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1421996156
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.3064535620
Short name T40
Test name
Test status
Simulation time 85803536837 ps
CPU time 1057.31 seconds
Started Feb 09 06:43:52 AM UTC 25
Finished Feb 09 07:01:41 AM UTC 25
Peak memory 226424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3064535620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3064535620
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.1256374639
Short name T43
Test name
Test status
Simulation time 7637443461 ps
CPU time 18.96 seconds
Started Feb 09 06:43:25 AM UTC 25
Finished Feb 09 06:43:45 AM UTC 25
Peak memory 208184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256374639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.uart_tx_ovrd.1256374639
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_tx_rx.3079015509
Short name T44
Test name
Test status
Simulation time 101983599371 ps
CPU time 61.82 seconds
Started Feb 09 06:42:47 AM UTC 25
Finished Feb 09 06:43:50 AM UTC 25
Peak memory 208548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079015509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.uart_tx_rx.3079015509
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/9.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/90.uart_fifo_reset.20397237
Short name T967
Test name
Test status
Simulation time 86673856564 ps
CPU time 89.35 seconds
Started Feb 09 07:24:09 AM UTC 25
Finished Feb 09 07:25:41 AM UTC 25
Peak memory 208584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20397237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 90.uart_fifo_reset.20397237
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/90.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.4168564732
Short name T1031
Test name
Test status
Simulation time 184610000220 ps
CPU time 403.35 seconds
Started Feb 09 07:24:23 AM UTC 25
Finished Feb 09 07:31:12 AM UTC 25
Peak memory 219572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4168564732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.4168564732
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/91.uart_fifo_reset.2710684747
Short name T969
Test name
Test status
Simulation time 24872574720 ps
CPU time 86.82 seconds
Started Feb 09 07:24:36 AM UTC 25
Finished Feb 09 07:26:05 AM UTC 25
Peak memory 208496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710684747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 91.uart_fifo_reset.2710684747
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/91.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.2890624049
Short name T984
Test name
Test status
Simulation time 22204328366 ps
CPU time 152.22 seconds
Started Feb 09 07:24:44 AM UTC 25
Finished Feb 09 07:27:20 AM UTC 25
Peak memory 217500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2890624049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2890624049
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/92.uart_fifo_reset.3162261412
Short name T963
Test name
Test status
Simulation time 154295448930 ps
CPU time 27.78 seconds
Started Feb 09 07:24:49 AM UTC 25
Finished Feb 09 07:25:18 AM UTC 25
Peak memory 208168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162261412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 92.uart_fifo_reset.3162261412
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/92.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.1695317190
Short name T1177
Test name
Test status
Simulation time 62025056102 ps
CPU time 1164.11 seconds
Started Feb 09 07:25:00 AM UTC 25
Finished Feb 09 07:44:37 AM UTC 25
Peak memory 228696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1695317190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1695317190
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/93.uart_fifo_reset.2015952233
Short name T964
Test name
Test status
Simulation time 63240031122 ps
CPU time 19.24 seconds
Started Feb 09 07:25:01 AM UTC 25
Finished Feb 09 07:25:21 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015952233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 93.uart_fifo_reset.2015952233
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/93.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/94.uart_fifo_reset.2725770449
Short name T989
Test name
Test status
Simulation time 74816791720 ps
CPU time 195.37 seconds
Started Feb 09 07:25:11 AM UTC 25
Finished Feb 09 07:28:29 AM UTC 25
Peak memory 208584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725770449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 94.uart_fifo_reset.2725770449
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/94.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.4144478019
Short name T1178
Test name
Test status
Simulation time 83799793545 ps
CPU time 1189.27 seconds
Started Feb 09 07:25:12 AM UTC 25
Finished Feb 09 07:45:14 AM UTC 25
Peak memory 228700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4144478019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.4144478019
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/95.uart_fifo_reset.427833764
Short name T240
Test name
Test status
Simulation time 66067247705 ps
CPU time 59.7 seconds
Started Feb 09 07:25:18 AM UTC 25
Finished Feb 09 07:26:19 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427833764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 95.uart_fifo_reset.427833764
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/95.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.3252714274
Short name T1171
Test name
Test status
Simulation time 185144647040 ps
CPU time 922.6 seconds
Started Feb 09 07:25:22 AM UTC 25
Finished Feb 09 07:40:55 AM UTC 25
Peak memory 235468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3252714274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3252714274
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.2557878561
Short name T1168
Test name
Test status
Simulation time 90918673285 ps
CPU time 789.03 seconds
Started Feb 09 07:25:41 AM UTC 25
Finished Feb 09 07:39:00 AM UTC 25
Peak memory 225036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2557878561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2557878561
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/97.uart_fifo_reset.2551010837
Short name T970
Test name
Test status
Simulation time 30194038592 ps
CPU time 24.2 seconds
Started Feb 09 07:25:41 AM UTC 25
Finished Feb 09 07:26:07 AM UTC 25
Peak memory 208556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551010837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 97.uart_fifo_reset.2551010837
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/97.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.2269185647
Short name T1175
Test name
Test status
Simulation time 55920871923 ps
CPU time 1072.31 seconds
Started Feb 09 07:25:46 AM UTC 25
Finished Feb 09 07:43:51 AM UTC 25
Peak memory 224440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2269185647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2269185647
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/98.uart_fifo_reset.2044922072
Short name T1083
Test name
Test status
Simulation time 171398705575 ps
CPU time 464.73 seconds
Started Feb 09 07:25:50 AM UTC 25
Finished Feb 09 07:33:41 AM UTC 25
Peak memory 208420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044922072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 98.uart_fifo_reset.2044922072
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/98.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.3643642100
Short name T1155
Test name
Test status
Simulation time 44242304766 ps
CPU time 624.65 seconds
Started Feb 09 07:26:05 AM UTC 25
Finished Feb 09 07:36:37 AM UTC 25
Peak memory 224464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3643642100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3643642100
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/99.uart_fifo_reset.972922376
Short name T977
Test name
Test status
Simulation time 25949025869 ps
CPU time 49.27 seconds
Started Feb 09 07:26:06 AM UTC 25
Finished Feb 09 07:26:57 AM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972922376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 99.uart_fifo_reset.972922376
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/99.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.3149223789
Short name T1045
Test name
Test status
Simulation time 108559981795 ps
CPU time 346.07 seconds
Started Feb 09 07:26:08 AM UTC 25
Finished Feb 09 07:31:58 AM UTC 25
Peak memory 237524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_
all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3149223789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3149223789
Directory /workspaces/repo/scratch/os_regression/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest
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