| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.12 | 99.08 | 97.65 | 100.00 | 98.35 | 100.00 | 99.64 |
| T1253 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.2587958619 | Oct 15 11:29:33 AM UTC 24 | Oct 15 11:29:45 AM UTC 24 | 25222567 ps | ||
| T1254 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.204640177 | Oct 15 11:29:29 AM UTC 24 | Oct 15 11:29:45 AM UTC 24 | 173203688 ps | ||
| T1255 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.4202021205 | Oct 15 11:29:32 AM UTC 24 | Oct 15 11:29:45 AM UTC 24 | 140087485 ps | ||
| T1256 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.911138400 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 40348364 ps | ||
| T1257 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.703333069 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 141601359 ps | ||
| T1258 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4111802729 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 168137214 ps | ||
| T1259 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.3480140488 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 60851951 ps | ||
| T1260 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.3821533872 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 35153467 ps | ||
| T1261 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.1857150317 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 23039075 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.2292676449 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 41513684 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.2291224100 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 175353741 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.2890100449 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 107870138 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.2001234288 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 18282073 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.103158671 | Oct 15 11:29:29 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 463553199 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.1922491479 | Oct 15 11:29:45 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 67426680 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.2465043726 | Oct 15 11:29:45 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 70499746 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.807132247 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 60576455 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.3291039961 | Oct 15 11:29:45 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 10720900 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.2489999809 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 44837715 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3859394410 | Oct 15 11:29:45 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 32637493 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.3239827313 | Oct 15 11:29:45 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 31578662 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.1208529637 | Oct 15 11:29:45 AM UTC 24 | Oct 15 11:29:46 AM UTC 24 | 94380618 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.2152981582 | Oct 15 11:29:45 AM UTC 24 | Oct 15 11:29:47 AM UTC 24 | 30340363 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.831898910 | Oct 15 11:29:45 AM UTC 24 | Oct 15 11:29:47 AM UTC 24 | 17825174 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.435105603 | Oct 15 11:29:45 AM UTC 24 | Oct 15 11:29:47 AM UTC 24 | 47420100 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.3628346898 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:47 AM UTC 24 | 65567956 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2768702799 | Oct 15 11:29:45 AM UTC 24 | Oct 15 11:29:47 AM UTC 24 | 14780336 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3431635200 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:47 AM UTC 24 | 69446888 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.702889638 | Oct 15 11:29:45 AM UTC 24 | Oct 15 11:29:47 AM UTC 24 | 178078218 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.389870470 | Oct 15 11:29:44 AM UTC 24 | Oct 15 11:29:47 AM UTC 24 | 102589474 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.319952675 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:50 AM UTC 24 | 17872576 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.391373937 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:50 AM UTC 24 | 21703360 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.1874749220 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:50 AM UTC 24 | 46511049 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2787272925 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:50 AM UTC 24 | 22701138 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.3649606213 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:51 AM UTC 24 | 30146100 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.1033563117 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:51 AM UTC 24 | 169330110 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.3294002911 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:51 AM UTC 24 | 41562177 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1136148063 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:51 AM UTC 24 | 28068575 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.811863186 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:51 AM UTC 24 | 28369740 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.2149592531 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:51 AM UTC 24 | 45385333 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.2076105585 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:51 AM UTC 24 | 17056968 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3749939550 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:52 AM UTC 24 | 20374988 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.1833244431 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:52 AM UTC 24 | 40119991 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.643757482 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:52 AM UTC 24 | 18775962 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.811769491 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:52 AM UTC 24 | 35101748 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.779579413 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:52 AM UTC 24 | 27370051 ps | ||
| T1297 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.365222280 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:52 AM UTC 24 | 14530843 ps | ||
| T1298 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.727110863 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:52 AM UTC 24 | 13281883 ps | ||
| T1299 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2478101476 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:52 AM UTC 24 | 10840816 ps | ||
| T1300 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3321747515 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:52 AM UTC 24 | 37541326 ps | ||
| T1301 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.673537 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:52 AM UTC 24 | 23384116 ps | ||
| T1302 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.1611960808 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:52 AM UTC 24 | 14630849 ps | ||
| T1303 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.1984005447 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:52 AM UTC 24 | 26805401 ps | ||
| T1304 | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2953707706 | Oct 15 11:29:49 AM UTC 24 | Oct 15 11:29:52 AM UTC 24 | 40842752 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.525890871 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 24545350388 ps |
| CPU time | 32.21 seconds |
| Started | Oct 15 10:27:39 AM UTC 24 |
| Finished | Oct 15 10:28:12 AM UTC 24 |
| Peak memory | 208916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525890871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.525890871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.1519638270 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4912583471 ps |
| CPU time | 14.48 seconds |
| Started | Oct 15 10:29:00 AM UTC 24 |
| Finished | Oct 15 10:29:16 AM UTC 24 |
| Peak memory | 208912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1519638270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_ with_rand_reset.1519638270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_stress_all.3504086483 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 436547082271 ps |
| CPU time | 718.05 seconds |
| Started | Oct 15 10:27:45 AM UTC 24 |
| Finished | Oct 15 10:39:54 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504086483 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3504086483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_fifo_full.1665961918 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 37277271325 ps |
| CPU time | 100.52 seconds |
| Started | Oct 15 10:27:38 AM UTC 24 |
| Finished | Oct 15 10:29:21 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665961918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1665961918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_stress_all.543945872 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 347706874451 ps |
| CPU time | 318.03 seconds |
| Started | Oct 15 10:39:09 AM UTC 24 |
| Finished | Oct 15 10:44:32 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543945872 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.543945872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.2115183292 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 134257372591 ps |
| CPU time | 377.86 seconds |
| Started | Oct 15 10:28:49 AM UTC 24 |
| Finished | Oct 15 10:35:14 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115183292 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2115183292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_stress_all.1999878766 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 134122918520 ps |
| CPU time | 144.35 seconds |
| Started | Oct 15 10:37:51 AM UTC 24 |
| Finished | Oct 15 10:40:19 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999878766 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1999878766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_stress_all.3916565207 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 89554748689 ps |
| CPU time | 424.65 seconds |
| Started | Oct 15 10:30:07 AM UTC 24 |
| Finished | Oct 15 10:37:18 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916565207 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3916565207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.3980403478 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13326245386 ps |
| CPU time | 39.08 seconds |
| Started | Oct 15 10:37:43 AM UTC 24 |
| Finished | Oct 15 10:38:24 AM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3980403478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_ with_rand_reset.3980403478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_stress_all.1610781945 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 399037689519 ps |
| CPU time | 225.03 seconds |
| Started | Oct 15 10:54:24 AM UTC 24 |
| Finished | Oct 15 10:58:13 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610781945 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1610781945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_sec_cm.939088217 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 208596129 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 10:27:56 AM UTC 24 |
| Finished | Oct 15 10:27:59 AM UTC 24 |
| Peak memory | 239764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939088217 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.939088217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_stress_all.1367058855 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 240230511849 ps |
| CPU time | 257.85 seconds |
| Started | Oct 15 10:44:59 AM UTC 24 |
| Finished | Oct 15 10:49:21 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367058855 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1367058855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_stress_all.3872029595 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 392490636279 ps |
| CPU time | 1335.43 seconds |
| Started | Oct 15 10:31:34 AM UTC 24 |
| Finished | Oct 15 10:54:09 AM UTC 24 |
| Peak memory | 212064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872029595 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3872029595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_stress_all.2365230733 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 110481328400 ps |
| CPU time | 520.2 seconds |
| Started | Oct 15 10:33:38 AM UTC 24 |
| Finished | Oct 15 10:42:26 AM UTC 24 |
| Peak memory | 217732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365230733 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2365230733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_fifo_reset.643420849 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 53352083722 ps |
| CPU time | 144.69 seconds |
| Started | Oct 15 10:27:40 AM UTC 24 |
| Finished | Oct 15 10:30:07 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643420849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.643420849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.2176563352 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 12058343 ps |
| CPU time | 0.55 seconds |
| Started | Oct 15 11:29:09 AM UTC 24 |
| Finished | Oct 15 11:29:12 AM UTC 24 |
| Peak memory | 206572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176563352 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2176563352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_fifo_full.3647341131 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 207329532900 ps |
| CPU time | 410.91 seconds |
| Started | Oct 15 10:31:42 AM UTC 24 |
| Finished | Oct 15 10:38:39 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647341131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3647341131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_stress_all.1840312573 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 324570698193 ps |
| CPU time | 160.29 seconds |
| Started | Oct 15 10:40:21 AM UTC 24 |
| Finished | Oct 15 10:43:04 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840312573 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1840312573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.2274653554 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 213835187280 ps |
| CPU time | 126.93 seconds |
| Started | Oct 15 10:46:58 AM UTC 24 |
| Finished | Oct 15 10:49:08 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274653554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2274653554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_tx_rx.728415959 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 141898459182 ps |
| CPU time | 106.46 seconds |
| Started | Oct 15 10:27:38 AM UTC 24 |
| Finished | Oct 15 10:29:27 AM UTC 24 |
| Peak memory | 208964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728415959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.728415959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_fifo_reset.3797124675 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 38491628661 ps |
| CPU time | 24.01 seconds |
| Started | Oct 15 10:31:49 AM UTC 24 |
| Finished | Oct 15 10:32:14 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797124675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3797124675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.1497272958 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 160184523 ps |
| CPU time | 1.38 seconds |
| Started | Oct 15 11:29:27 AM UTC 24 |
| Finished | Oct 15 11:29:33 AM UTC 24 |
| Peak memory | 208048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497272958 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1497272958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.2065257380 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 98365862952 ps |
| CPU time | 1038.68 seconds |
| Started | Oct 15 10:35:21 AM UTC 24 |
| Finished | Oct 15 10:52:54 AM UTC 24 |
| Peak memory | 211904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065257380 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2065257380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_fifo_full.1622054645 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 177922093491 ps |
| CPU time | 383.18 seconds |
| Started | Oct 15 10:49:32 AM UTC 24 |
| Finished | Oct 15 10:56:01 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622054645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1622054645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_intr.1356164294 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 146486080864 ps |
| CPU time | 424.44 seconds |
| Started | Oct 15 10:30:46 AM UTC 24 |
| Finished | Oct 15 10:37:57 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356164294 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1356164294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_alert_test.70249406 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 12294434 ps |
| CPU time | 0.74 seconds |
| Started | Oct 15 10:27:59 AM UTC 24 |
| Finished | Oct 15 10:28:01 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70249406 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.70249406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.3493436640 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 48349321290 ps |
| CPU time | 99.5 seconds |
| Started | Oct 15 10:30:06 AM UTC 24 |
| Finished | Oct 15 10:31:47 AM UTC 24 |
| Peak memory | 217708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3493436640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_ with_rand_reset.3493436640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.1764974199 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 57995867072 ps |
| CPU time | 63.84 seconds |
| Started | Oct 15 10:53:17 AM UTC 24 |
| Finished | Oct 15 10:54:23 AM UTC 24 |
| Peak memory | 224068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1764974199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all _with_rand_reset.1764974199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_stress_all.1148454048 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 319624774066 ps |
| CPU time | 376.06 seconds |
| Started | Oct 15 10:43:05 AM UTC 24 |
| Finished | Oct 15 10:49:27 AM UTC 24 |
| Peak memory | 221140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148454048 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1148454048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_fifo_reset.2895942026 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 50909687117 ps |
| CPU time | 34.56 seconds |
| Started | Oct 15 10:28:13 AM UTC 24 |
| Finished | Oct 15 10:28:49 AM UTC 24 |
| Peak memory | 208296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895942026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2895942026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_fifo_full.2753745856 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 339302710865 ps |
| CPU time | 176.1 seconds |
| Started | Oct 15 10:56:02 AM UTC 24 |
| Finished | Oct 15 10:59:01 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753745856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2753745856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.2391175086 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 18921396 ps |
| CPU time | 0.51 seconds |
| Started | Oct 15 11:29:34 AM UTC 24 |
| Finished | Oct 15 11:29:36 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391175086 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2391175086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_fifo_reset.1056684584 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 26250157623 ps |
| CPU time | 68.03 seconds |
| Started | Oct 15 10:30:24 AM UTC 24 |
| Finished | Oct 15 10:31:34 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056684584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1056684584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_fifo_reset.4090537563 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 142765171269 ps |
| CPU time | 127.39 seconds |
| Started | Oct 15 10:44:11 AM UTC 24 |
| Finished | Oct 15 10:46:21 AM UTC 24 |
| Peak memory | 208540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090537563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.4090537563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_stress_all.2363487389 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 277626314968 ps |
| CPU time | 691.32 seconds |
| Started | Oct 15 10:49:22 AM UTC 24 |
| Finished | Oct 15 11:01:04 AM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363487389 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2363487389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_fifo_reset.3705583702 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 27852386551 ps |
| CPU time | 35.26 seconds |
| Started | Oct 15 10:42:11 AM UTC 24 |
| Finished | Oct 15 10:42:47 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705583702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3705583702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_fifo_reset.3607957500 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 23507652698 ps |
| CPU time | 90.51 seconds |
| Started | Oct 15 11:06:28 AM UTC 24 |
| Finished | Oct 15 11:08:00 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607957500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3607957500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_fifo_reset.4046505385 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 26123277511 ps |
| CPU time | 51.08 seconds |
| Started | Oct 15 10:38:25 AM UTC 24 |
| Finished | Oct 15 10:39:18 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046505385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4046505385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.510032938 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 65650638 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 11:29:15 AM UTC 24 |
| Finished | Oct 15 11:29:17 AM UTC 24 |
| Peak memory | 207632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510032938 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.510032938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_stress_all.807250819 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 187830376122 ps |
| CPU time | 423.31 seconds |
| Started | Oct 15 10:58:55 AM UTC 24 |
| Finished | Oct 15 11:06:05 AM UTC 24 |
| Peak memory | 212028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807250819 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.807250819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.156764440 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 29736295246 ps |
| CPU time | 120.13 seconds |
| Started | Oct 15 10:29:17 AM UTC 24 |
| Finished | Oct 15 10:31:20 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156764440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.156764440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_stress_all.278980404 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 36488252496 ps |
| CPU time | 203.57 seconds |
| Started | Oct 15 10:41:45 AM UTC 24 |
| Finished | Oct 15 10:45:13 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278980404 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.278980404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/131.uart_fifo_reset.2219421830 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 102035253995 ps |
| CPU time | 89.93 seconds |
| Started | Oct 15 11:19:40 AM UTC 24 |
| Finished | Oct 15 11:21:12 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219421830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2219421830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/131.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/163.uart_fifo_reset.3202297613 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 29258085483 ps |
| CPU time | 26.13 seconds |
| Started | Oct 15 11:20:36 AM UTC 24 |
| Finished | Oct 15 11:21:03 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202297613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3202297613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/163.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_stress_all.3924677864 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 68819482869 ps |
| CPU time | 155.51 seconds |
| Started | Oct 15 10:55:42 AM UTC 24 |
| Finished | Oct 15 10:58:20 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924677864 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3924677864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.3352868493 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 27189617168 ps |
| CPU time | 66.97 seconds |
| Started | Oct 15 11:02:34 AM UTC 24 |
| Finished | Oct 15 11:03:43 AM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3352868493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all _with_rand_reset.3352868493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_fifo_full.2582169894 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 53264812059 ps |
| CPU time | 66.56 seconds |
| Started | Oct 15 10:40:27 AM UTC 24 |
| Finished | Oct 15 10:41:36 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582169894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2582169894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/127.uart_fifo_reset.1828709317 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 122654710301 ps |
| CPU time | 124.87 seconds |
| Started | Oct 15 11:19:34 AM UTC 24 |
| Finished | Oct 15 11:21:41 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828709317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1828709317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/127.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/159.uart_fifo_reset.3549974473 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 254106834679 ps |
| CPU time | 94.58 seconds |
| Started | Oct 15 11:20:30 AM UTC 24 |
| Finished | Oct 15 11:22:07 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549974473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3549974473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/159.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_fifo_full.1884984340 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 58263444599 ps |
| CPU time | 34.38 seconds |
| Started | Oct 15 10:51:50 AM UTC 24 |
| Finished | Oct 15 10:52:26 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884984340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1884984340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_perf.242467205 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 13088949070 ps |
| CPU time | 124.33 seconds |
| Started | Oct 15 10:49:17 AM UTC 24 |
| Finished | Oct 15 10:51:24 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242467205 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.242467205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/223.uart_fifo_reset.2033098988 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 82606385085 ps |
| CPU time | 70.27 seconds |
| Started | Oct 15 11:22:23 AM UTC 24 |
| Finished | Oct 15 11:23:36 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033098988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2033098988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/223.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_fifo_reset.537405859 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 52110835632 ps |
| CPU time | 37.28 seconds |
| Started | Oct 15 11:01:57 AM UTC 24 |
| Finished | Oct 15 11:02:36 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537405859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.537405859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_tx_rx.694752747 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 269170309852 ps |
| CPU time | 184.58 seconds |
| Started | Oct 15 11:01:36 AM UTC 24 |
| Finished | Oct 15 11:04:44 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694752747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.694752747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/298.uart_fifo_reset.3806641501 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 87403519393 ps |
| CPU time | 184.1 seconds |
| Started | Oct 15 11:24:36 AM UTC 24 |
| Finished | Oct 15 11:27:43 AM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806641501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3806641501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/298.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.2778063815 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 52278006123 ps |
| CPU time | 33.76 seconds |
| Started | Oct 15 10:34:34 AM UTC 24 |
| Finished | Oct 15 10:35:10 AM UTC 24 |
| Peak memory | 208456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778063815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2778063815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_fifo_reset.547547093 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 119033934094 ps |
| CPU time | 74.06 seconds |
| Started | Oct 15 10:36:14 AM UTC 24 |
| Finished | Oct 15 10:37:30 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547547093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.547547093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.3185735924 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 65362966887 ps |
| CPU time | 140.06 seconds |
| Started | Oct 15 10:43:52 AM UTC 24 |
| Finished | Oct 15 10:46:15 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185735924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3185735924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_noise_filter.1185954621 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 69796745089 ps |
| CPU time | 192.73 seconds |
| Started | Oct 15 10:44:28 AM UTC 24 |
| Finished | Oct 15 10:47:44 AM UTC 24 |
| Peak memory | 219792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185954621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1185954621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_tx_rx.3263008683 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 53631986710 ps |
| CPU time | 54.03 seconds |
| Started | Oct 15 10:43:32 AM UTC 24 |
| Finished | Oct 15 10:44:27 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263008683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3263008683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/119.uart_fifo_reset.2978548083 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 224695964676 ps |
| CPU time | 132.64 seconds |
| Started | Oct 15 11:19:27 AM UTC 24 |
| Finished | Oct 15 11:21:42 AM UTC 24 |
| Peak memory | 208632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978548083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2978548083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/119.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_intr.2585541273 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 26845536338 ps |
| CPU time | 12.09 seconds |
| Started | Oct 15 10:45:26 AM UTC 24 |
| Finished | Oct 15 10:45:40 AM UTC 24 |
| Peak memory | 208732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585541273 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2585541273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/138.uart_fifo_reset.1288377863 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 29793259274 ps |
| CPU time | 36.72 seconds |
| Started | Oct 15 11:19:50 AM UTC 24 |
| Finished | Oct 15 11:20:28 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288377863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1288377863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/138.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.2322064666 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2649115734 ps |
| CPU time | 40.76 seconds |
| Started | Oct 15 10:51:23 AM UTC 24 |
| Finished | Oct 15 10:52:05 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2322064666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all _with_rand_reset.2322064666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/185.uart_fifo_reset.159705035 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 60879094528 ps |
| CPU time | 55.19 seconds |
| Started | Oct 15 11:21:19 AM UTC 24 |
| Finished | Oct 15 11:22:16 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159705035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.159705035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/185.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_stress_all.2234969328 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 305782616311 ps |
| CPU time | 717.84 seconds |
| Started | Oct 15 10:57:16 AM UTC 24 |
| Finished | Oct 15 11:09:23 AM UTC 24 |
| Peak memory | 222420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234969328 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2234969328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/233.uart_fifo_reset.3802121252 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 72467218917 ps |
| CPU time | 53.59 seconds |
| Started | Oct 15 11:22:40 AM UTC 24 |
| Finished | Oct 15 11:23:35 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802121252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3802121252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/233.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_fifo_reset.1411219055 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 87588197156 ps |
| CPU time | 46.88 seconds |
| Started | Oct 15 11:07:08 AM UTC 24 |
| Finished | Oct 15 11:07:57 AM UTC 24 |
| Peak memory | 208952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411219055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1411219055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_fifo_reset.3438805670 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 91989529553 ps |
| CPU time | 138.65 seconds |
| Started | Oct 15 11:14:56 AM UTC 24 |
| Finished | Oct 15 11:17:18 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438805670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3438805670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/99.uart_fifo_reset.940338775 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 64250300431 ps |
| CPU time | 28.57 seconds |
| Started | Oct 15 11:18:57 AM UTC 24 |
| Finished | Oct 15 11:19:26 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940338775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.940338775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/99.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.2858622821 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 428825800 ps |
| CPU time | 1.25 seconds |
| Started | Oct 15 11:29:29 AM UTC 24 |
| Finished | Oct 15 11:29:32 AM UTC 24 |
| Peak memory | 207688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858622821 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2858622821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.1362903597 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 209021093444 ps |
| CPU time | 465.06 seconds |
| Started | Oct 15 10:27:45 AM UTC 24 |
| Finished | Oct 15 10:35:37 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362903597 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1362903597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/100.uart_fifo_reset.3269798112 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 66249697540 ps |
| CPU time | 36.83 seconds |
| Started | Oct 15 11:19:00 AM UTC 24 |
| Finished | Oct 15 11:19:38 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269798112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3269798112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/100.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/103.uart_fifo_reset.2431256914 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 68165548397 ps |
| CPU time | 22.83 seconds |
| Started | Oct 15 11:19:06 AM UTC 24 |
| Finished | Oct 15 11:19:31 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431256914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2431256914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/103.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/132.uart_fifo_reset.2655391977 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 18075915246 ps |
| CPU time | 14.88 seconds |
| Started | Oct 15 11:19:41 AM UTC 24 |
| Finished | Oct 15 11:19:57 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655391977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2655391977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/132.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/133.uart_fifo_reset.2687328690 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 207439561976 ps |
| CPU time | 168.4 seconds |
| Started | Oct 15 11:19:43 AM UTC 24 |
| Finished | Oct 15 11:22:34 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687328690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2687328690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/133.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/149.uart_fifo_reset.626831144 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 23263952121 ps |
| CPU time | 22.77 seconds |
| Started | Oct 15 11:20:11 AM UTC 24 |
| Finished | Oct 15 11:20:35 AM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626831144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.626831144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/149.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/161.uart_fifo_reset.3418983317 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 36087978053 ps |
| CPU time | 11.74 seconds |
| Started | Oct 15 11:20:34 AM UTC 24 |
| Finished | Oct 15 11:20:46 AM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418983317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3418983317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/161.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/215.uart_fifo_reset.2758611605 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 135617030152 ps |
| CPU time | 70.8 seconds |
| Started | Oct 15 11:22:08 AM UTC 24 |
| Finished | Oct 15 11:23:20 AM UTC 24 |
| Peak memory | 208620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758611605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2758611605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/215.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/218.uart_fifo_reset.3904120837 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 158953315872 ps |
| CPU time | 297.78 seconds |
| Started | Oct 15 11:22:16 AM UTC 24 |
| Finished | Oct 15 11:27:18 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904120837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3904120837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/218.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/229.uart_fifo_reset.3867030506 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 8271562492 ps |
| CPU time | 22.26 seconds |
| Started | Oct 15 11:22:32 AM UTC 24 |
| Finished | Oct 15 11:22:55 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867030506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3867030506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/229.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/232.uart_fifo_reset.21556542 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 15167079167 ps |
| CPU time | 33.68 seconds |
| Started | Oct 15 11:22:39 AM UTC 24 |
| Finished | Oct 15 11:23:14 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21556542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.21556542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/232.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/239.uart_fifo_reset.3615724806 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 265587937399 ps |
| CPU time | 130.2 seconds |
| Started | Oct 15 11:22:53 AM UTC 24 |
| Finished | Oct 15 11:25:05 AM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615724806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3615724806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/239.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/243.uart_fifo_reset.3365047269 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 98274931155 ps |
| CPU time | 55.45 seconds |
| Started | Oct 15 11:23:04 AM UTC 24 |
| Finished | Oct 15 11:24:01 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365047269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3365047269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/243.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3107061188 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 102415993561 ps |
| CPU time | 36.61 seconds |
| Started | Oct 15 11:23:12 AM UTC 24 |
| Finished | Oct 15 11:23:50 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107061188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3107061188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/245.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/250.uart_fifo_reset.4127677769 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 25195717263 ps |
| CPU time | 71.57 seconds |
| Started | Oct 15 11:23:21 AM UTC 24 |
| Finished | Oct 15 11:24:35 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127677769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.4127677769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/250.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/264.uart_fifo_reset.3499821666 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 55447299962 ps |
| CPU time | 73 seconds |
| Started | Oct 15 11:23:49 AM UTC 24 |
| Finished | Oct 15 11:25:03 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499821666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3499821666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/264.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/290.uart_fifo_reset.1735830244 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 96450558396 ps |
| CPU time | 43.61 seconds |
| Started | Oct 15 11:24:25 AM UTC 24 |
| Finished | Oct 15 11:25:10 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735830244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1735830244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/290.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_fifo_reset.2662484985 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 10171486206 ps |
| CPU time | 35.77 seconds |
| Started | Oct 15 11:15:24 AM UTC 24 |
| Finished | Oct 15 11:16:01 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662484985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2662484985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/75.uart_fifo_reset.3019653579 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 5016452563 ps |
| CPU time | 19.18 seconds |
| Started | Oct 15 11:17:46 AM UTC 24 |
| Finished | Oct 15 11:18:06 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019653579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3019653579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/75.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/77.uart_fifo_reset.3367833793 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 213174156149 ps |
| CPU time | 345.6 seconds |
| Started | Oct 15 11:17:51 AM UTC 24 |
| Finished | Oct 15 11:23:41 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367833793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3367833793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/77.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.2976117294 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 16262671 ps |
| CPU time | 0.66 seconds |
| Started | Oct 15 11:29:10 AM UTC 24 |
| Finished | Oct 15 11:29:12 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976117294 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2976117294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.1832218601 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 74407126 ps |
| CPU time | 2.08 seconds |
| Started | Oct 15 11:29:09 AM UTC 24 |
| Finished | Oct 15 11:29:13 AM UTC 24 |
| Peak memory | 207748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832218601 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1832218601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.4284944526 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 1034958207 ps |
| CPU time | 1.54 seconds |
| Started | Oct 15 11:29:09 AM UTC 24 |
| Finished | Oct 15 11:29:13 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284944526 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4284944526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3835873178 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 59711703 ps |
| CPU time | 0.69 seconds |
| Started | Oct 15 11:29:12 AM UTC 24 |
| Finished | Oct 15 11:29:14 AM UTC 24 |
| Peak memory | 206432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3835873178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_r eset.3835873178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.2099932248 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 39498783 ps |
| CPU time | 0.67 seconds |
| Started | Oct 15 11:29:09 AM UTC 24 |
| Finished | Oct 15 11:29:12 AM UTC 24 |
| Peak memory | 204448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099932248 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2099932248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3875536031 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 22169962 ps |
| CPU time | 0.83 seconds |
| Started | Oct 15 11:29:12 AM UTC 24 |
| Finished | Oct 15 11:29:14 AM UTC 24 |
| Peak memory | 206372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875536031 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.3875536031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2096886822 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 243406736 ps |
| CPU time | 1.35 seconds |
| Started | Oct 15 11:29:09 AM UTC 24 |
| Finished | Oct 15 11:29:12 AM UTC 24 |
| Peak memory | 209108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096886822 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2096886822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.3526870765 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 84407244 ps |
| CPU time | 1.27 seconds |
| Started | Oct 15 11:29:09 AM UTC 24 |
| Finished | Oct 15 11:29:12 AM UTC 24 |
| Peak memory | 208052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526870765 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3526870765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.2518459542 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 92998073 ps |
| CPU time | 1.37 seconds |
| Started | Oct 15 11:29:13 AM UTC 24 |
| Finished | Oct 15 11:29:33 AM UTC 24 |
| Peak memory | 206440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518459542 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2518459542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.1600699524 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 56065193 ps |
| CPU time | 0.59 seconds |
| Started | Oct 15 11:29:13 AM UTC 24 |
| Finished | Oct 15 11:29:32 AM UTC 24 |
| Peak memory | 204292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600699524 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1600699524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.3885957119 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 13881014 ps |
| CPU time | 0.74 seconds |
| Started | Oct 15 11:29:13 AM UTC 24 |
| Finished | Oct 15 11:29:32 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885957119 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3885957119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.507363166 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 75578953 ps |
| CPU time | 0.55 seconds |
| Started | Oct 15 11:29:13 AM UTC 24 |
| Finished | Oct 15 11:29:22 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507363166 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.507363166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.942958752 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 70001914 ps |
| CPU time | 1.58 seconds |
| Started | Oct 15 11:29:12 AM UTC 24 |
| Finished | Oct 15 11:29:15 AM UTC 24 |
| Peak memory | 209180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942958752 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.942958752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.1863742472 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 710057978 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 11:29:12 AM UTC 24 |
| Finished | Oct 15 11:29:15 AM UTC 24 |
| Peak memory | 208060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863742472 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1863742472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1685781497 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 53149842 ps |
| CPU time | 0.77 seconds |
| Started | Oct 15 11:29:29 AM UTC 24 |
| Finished | Oct 15 11:29:32 AM UTC 24 |
| Peak memory | 207748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1685781497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_ reset.1685781497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.944953173 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 42821336 ps |
| CPU time | 0.51 seconds |
| Started | Oct 15 11:29:29 AM UTC 24 |
| Finished | Oct 15 11:29:32 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944953173 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.944953173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.2002457297 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 17716359 ps |
| CPU time | 0.54 seconds |
| Started | Oct 15 11:29:29 AM UTC 24 |
| Finished | Oct 15 11:29:31 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002457297 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2002457297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.3372779350 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 33071600 ps |
| CPU time | 0.75 seconds |
| Started | Oct 15 11:29:29 AM UTC 24 |
| Finished | Oct 15 11:29:32 AM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372779350 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.3372779350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.4261731240 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 192613694 ps |
| CPU time | 1.88 seconds |
| Started | Oct 15 11:29:29 AM UTC 24 |
| Finished | Oct 15 11:29:33 AM UTC 24 |
| Peak memory | 209120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261731240 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.4261731240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1759105052 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 111149495 ps |
| CPU time | 0.86 seconds |
| Started | Oct 15 11:29:32 AM UTC 24 |
| Finished | Oct 15 11:29:44 AM UTC 24 |
| Peak memory | 207748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1759105052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_ reset.1759105052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.969037324 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 15912970 ps |
| CPU time | 0.61 seconds |
| Started | Oct 15 11:29:32 AM UTC 24 |
| Finished | Oct 15 11:29:44 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969037324 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.969037324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.1573526901 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 36513737 ps |
| CPU time | 0.5 seconds |
| Started | Oct 15 11:29:32 AM UTC 24 |
| Finished | Oct 15 11:29:44 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573526901 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1573526901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1761200291 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 12558002 ps |
| CPU time | 0.61 seconds |
| Started | Oct 15 11:29:32 AM UTC 24 |
| Finished | Oct 15 11:29:44 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761200291 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.1761200291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3794467935 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 75699614 ps |
| CPU time | 1.74 seconds |
| Started | Oct 15 11:29:29 AM UTC 24 |
| Finished | Oct 15 11:29:33 AM UTC 24 |
| Peak memory | 209132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794467935 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3794467935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.1613455818 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 156017508 ps |
| CPU time | 0.78 seconds |
| Started | Oct 15 11:29:30 AM UTC 24 |
| Finished | Oct 15 11:29:32 AM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613455818 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1613455818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2000501410 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 66013991 ps |
| CPU time | 0.64 seconds |
| Started | Oct 15 11:29:33 AM UTC 24 |
| Finished | Oct 15 11:29:45 AM UTC 24 |
| Peak memory | 206372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2000501410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_ reset.2000501410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.3048776945 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 11652047 ps |
| CPU time | 0.51 seconds |
| Started | Oct 15 11:29:33 AM UTC 24 |
| Finished | Oct 15 11:29:44 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048776945 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3048776945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.2617232656 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 17225730 ps |
| CPU time | 0.54 seconds |
| Started | Oct 15 11:29:32 AM UTC 24 |
| Finished | Oct 15 11:29:44 AM UTC 24 |
| Peak memory | 204272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617232656 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2617232656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.2587958619 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 25222567 ps |
| CPU time | 0.78 seconds |
| Started | Oct 15 11:29:33 AM UTC 24 |
| Finished | Oct 15 11:29:45 AM UTC 24 |
| Peak memory | 206288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587958619 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.2587958619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.4202021205 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 140087485 ps |
| CPU time | 1.42 seconds |
| Started | Oct 15 11:29:32 AM UTC 24 |
| Finished | Oct 15 11:29:45 AM UTC 24 |
| Peak memory | 209136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202021205 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.4202021205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.3010068732 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 158893163 ps |
| CPU time | 0.92 seconds |
| Started | Oct 15 11:29:32 AM UTC 24 |
| Finished | Oct 15 11:29:45 AM UTC 24 |
| Peak memory | 206892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010068732 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3010068732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2375558635 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 70027202 ps |
| CPU time | 0.64 seconds |
| Started | Oct 15 11:29:34 AM UTC 24 |
| Finished | Oct 15 11:29:37 AM UTC 24 |
| Peak memory | 206336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2375558635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_ reset.2375558635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.2973299121 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 16693431 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:34 AM UTC 24 |
| Finished | Oct 15 11:29:36 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973299121 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2973299121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2530411868 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 50155191 ps |
| CPU time | 0.58 seconds |
| Started | Oct 15 11:29:34 AM UTC 24 |
| Finished | Oct 15 11:29:37 AM UTC 24 |
| Peak memory | 202344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530411868 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.2530411868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1745614381 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 22906958 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 11:29:34 AM UTC 24 |
| Finished | Oct 15 11:29:37 AM UTC 24 |
| Peak memory | 209124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745614381 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1745614381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.1547016602 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 173228957 ps |
| CPU time | 1.19 seconds |
| Started | Oct 15 11:29:34 AM UTC 24 |
| Finished | Oct 15 11:29:37 AM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547016602 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1547016602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4224577955 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 20303134 ps |
| CPU time | 0.81 seconds |
| Started | Oct 15 11:29:37 AM UTC 24 |
| Finished | Oct 15 11:29:42 AM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4224577955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_ reset.4224577955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.2368207956 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 13838896 ps |
| CPU time | 0.53 seconds |
| Started | Oct 15 11:29:34 AM UTC 24 |
| Finished | Oct 15 11:29:37 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368207956 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2368207956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.3121168446 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 23448366 ps |
| CPU time | 0.5 seconds |
| Started | Oct 15 11:29:34 AM UTC 24 |
| Finished | Oct 15 11:29:37 AM UTC 24 |
| Peak memory | 204368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121168446 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3121168446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.2546371760 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 48519287 ps |
| CPU time | 0.67 seconds |
| Started | Oct 15 11:29:34 AM UTC 24 |
| Finished | Oct 15 11:29:37 AM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546371760 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.2546371760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.987735281 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 117934044 ps |
| CPU time | 1.81 seconds |
| Started | Oct 15 11:29:34 AM UTC 24 |
| Finished | Oct 15 11:29:38 AM UTC 24 |
| Peak memory | 209136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987735281 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.987735281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3442325043 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 103227755 ps |
| CPU time | 0.88 seconds |
| Started | Oct 15 11:29:34 AM UTC 24 |
| Finished | Oct 15 11:29:37 AM UTC 24 |
| Peak memory | 207220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442325043 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3442325043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3830724876 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 123055972 ps |
| CPU time | 0.76 seconds |
| Started | Oct 15 11:29:37 AM UTC 24 |
| Finished | Oct 15 11:29:42 AM UTC 24 |
| Peak memory | 207748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3830724876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_ reset.3830724876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.91329251 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 45599065 ps |
| CPU time | 0.51 seconds |
| Started | Oct 15 11:29:37 AM UTC 24 |
| Finished | Oct 15 11:29:42 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91329251 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.91329251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.2064878394 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 11189651 ps |
| CPU time | 0.48 seconds |
| Started | Oct 15 11:29:37 AM UTC 24 |
| Finished | Oct 15 11:29:42 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064878394 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2064878394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2349068451 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 80728645 ps |
| CPU time | 0.56 seconds |
| Started | Oct 15 11:29:37 AM UTC 24 |
| Finished | Oct 15 11:29:42 AM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349068451 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.2349068451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.1702245442 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 49910074 ps |
| CPU time | 1 seconds |
| Started | Oct 15 11:29:37 AM UTC 24 |
| Finished | Oct 15 11:29:42 AM UTC 24 |
| Peak memory | 207484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702245442 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1702245442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.1150708967 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 175183131 ps |
| CPU time | 0.77 seconds |
| Started | Oct 15 11:29:37 AM UTC 24 |
| Finished | Oct 15 11:29:42 AM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150708967 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1150708967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4111802729 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 168137214 ps |
| CPU time | 0.69 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 206372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4111802729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_ reset.4111802729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.3137847085 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 24767594 ps |
| CPU time | 0.51 seconds |
| Started | Oct 15 11:29:39 AM UTC 24 |
| Finished | Oct 15 11:29:43 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137847085 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3137847085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.3779362087 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 35268349 ps |
| CPU time | 0.47 seconds |
| Started | Oct 15 11:29:39 AM UTC 24 |
| Finished | Oct 15 11:29:43 AM UTC 24 |
| Peak memory | 204320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779362087 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3779362087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.703333069 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 141601359 ps |
| CPU time | 0.67 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703333069 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.703333069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.175738722 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 143251073 ps |
| CPU time | 1.45 seconds |
| Started | Oct 15 11:29:39 AM UTC 24 |
| Finished | Oct 15 11:29:44 AM UTC 24 |
| Peak memory | 209124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175738722 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.175738722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.3119743670 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 40467343 ps |
| CPU time | 0.8 seconds |
| Started | Oct 15 11:29:39 AM UTC 24 |
| Finished | Oct 15 11:29:43 AM UTC 24 |
| Peak memory | 207668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119743670 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3119743670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.807132247 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 60576455 ps |
| CPU time | 0.93 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 207748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=807132247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_r eset.807132247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.3821533872 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 35153467 ps |
| CPU time | 0.7 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 204252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821533872 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3821533872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.911138400 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 40348364 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911138400 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.911138400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.3480140488 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 60851951 ps |
| CPU time | 0.69 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480140488 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.3480140488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.1857150317 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 23039075 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857150317 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1857150317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.2291224100 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 175353741 ps |
| CPU time | 0.94 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 207688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291224100 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2291224100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3431635200 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 69446888 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:47 AM UTC 24 |
| Peak memory | 207748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3431635200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_ reset.3431635200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.2001234288 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 18282073 ps |
| CPU time | 0.67 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001234288 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2001234288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.2292676449 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 41513684 ps |
| CPU time | 0.57 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 204320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292676449 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2292676449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.2890100449 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 107870138 ps |
| CPU time | 0.79 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 202344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890100449 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.2890100449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.389870470 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 102589474 ps |
| CPU time | 1.4 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:47 AM UTC 24 |
| Peak memory | 209120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389870470 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.389870470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.2489999809 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 44837715 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 207068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489999809 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2489999809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2768702799 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 14780336 ps |
| CPU time | 0.8 seconds |
| Started | Oct 15 11:29:45 AM UTC 24 |
| Finished | Oct 15 11:29:47 AM UTC 24 |
| Peak memory | 207732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2768702799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_ reset.2768702799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.2465043726 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 70499746 ps |
| CPU time | 0.61 seconds |
| Started | Oct 15 11:29:45 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465043726 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2465043726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.1922491479 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 67426680 ps |
| CPU time | 0.61 seconds |
| Started | Oct 15 11:29:45 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 203428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922491479 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1922491479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.1208529637 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 94380618 ps |
| CPU time | 0.75 seconds |
| Started | Oct 15 11:29:45 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208529637 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.1208529637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.3628346898 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 65567956 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 11:29:44 AM UTC 24 |
| Finished | Oct 15 11:29:47 AM UTC 24 |
| Peak memory | 207748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628346898 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3628346898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.702889638 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 178078218 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 11:29:45 AM UTC 24 |
| Finished | Oct 15 11:29:47 AM UTC 24 |
| Peak memory | 206972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702889638 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.702889638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.1103341510 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 13709739 ps |
| CPU time | 0.64 seconds |
| Started | Oct 15 11:29:15 AM UTC 24 |
| Finished | Oct 15 11:29:27 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103341510 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1103341510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.1527213407 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 1262686991 ps |
| CPU time | 1.36 seconds |
| Started | Oct 15 11:29:15 AM UTC 24 |
| Finished | Oct 15 11:29:28 AM UTC 24 |
| Peak memory | 206552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527213407 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1527213407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2988811572 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 17632824 ps |
| CPU time | 0.58 seconds |
| Started | Oct 15 11:29:15 AM UTC 24 |
| Finished | Oct 15 11:29:27 AM UTC 24 |
| Peak memory | 206372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2988811572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_r eset.2988811572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.1682444036 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 57495119 ps |
| CPU time | 0.66 seconds |
| Started | Oct 15 11:29:15 AM UTC 24 |
| Finished | Oct 15 11:29:27 AM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682444036 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.1682444036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.3291039961 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 10720900 ps |
| CPU time | 0.55 seconds |
| Started | Oct 15 11:29:45 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 204356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291039961 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3291039961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.3239827313 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 31578662 ps |
| CPU time | 0.56 seconds |
| Started | Oct 15 11:29:45 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239827313 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3239827313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.435105603 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 47420100 ps |
| CPU time | 0.54 seconds |
| Started | Oct 15 11:29:45 AM UTC 24 |
| Finished | Oct 15 11:29:47 AM UTC 24 |
| Peak memory | 204108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435105603 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.435105603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.831898910 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 17825174 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:45 AM UTC 24 |
| Finished | Oct 15 11:29:47 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831898910 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.831898910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3859394410 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 32637493 ps |
| CPU time | 0.54 seconds |
| Started | Oct 15 11:29:45 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859394410 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3859394410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.2152981582 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 30340363 ps |
| CPU time | 0.53 seconds |
| Started | Oct 15 11:29:45 AM UTC 24 |
| Finished | Oct 15 11:29:47 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152981582 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2152981582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.319952675 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 17872576 ps |
| CPU time | 0.51 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:50 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319952675 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.319952675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.1874749220 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 46511049 ps |
| CPU time | 0.62 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:50 AM UTC 24 |
| Peak memory | 204156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874749220 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1874749220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.391373937 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 21703360 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:50 AM UTC 24 |
| Peak memory | 204116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391373937 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.391373937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2787272925 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 22701138 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:50 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787272925 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2787272925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2968571670 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 54383838 ps |
| CPU time | 0.69 seconds |
| Started | Oct 15 11:29:15 AM UTC 24 |
| Finished | Oct 15 11:29:28 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968571670 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2968571670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2162434721 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 63865435 ps |
| CPU time | 1.28 seconds |
| Started | Oct 15 11:29:15 AM UTC 24 |
| Finished | Oct 15 11:29:17 AM UTC 24 |
| Peak memory | 208104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162434721 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2162434721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.2204354055 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 47752939 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:15 AM UTC 24 |
| Finished | Oct 15 11:29:17 AM UTC 24 |
| Peak memory | 204172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204354055 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2204354055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3222011924 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 57869252 ps |
| CPU time | 0.63 seconds |
| Started | Oct 15 11:29:16 AM UTC 24 |
| Finished | Oct 15 11:29:21 AM UTC 24 |
| Peak memory | 206432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3222011924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_r eset.3222011924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2767683477 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 44328104 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:15 AM UTC 24 |
| Finished | Oct 15 11:29:17 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767683477 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2767683477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.702660410 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 13154015 ps |
| CPU time | 0.53 seconds |
| Started | Oct 15 11:29:15 AM UTC 24 |
| Finished | Oct 15 11:29:17 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702660410 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.702660410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.3941243570 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 233905026 ps |
| CPU time | 0.7 seconds |
| Started | Oct 15 11:29:16 AM UTC 24 |
| Finished | Oct 15 11:29:21 AM UTC 24 |
| Peak memory | 206372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941243570 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.3941243570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.3284475668 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 167520232 ps |
| CPU time | 1.46 seconds |
| Started | Oct 15 11:29:15 AM UTC 24 |
| Finished | Oct 15 11:29:17 AM UTC 24 |
| Peak memory | 209124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284475668 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3284475668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1136148063 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 28068575 ps |
| CPU time | 0.53 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:51 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136148063 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1136148063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.779579413 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 27370051 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:52 AM UTC 24 |
| Peak memory | 203980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779579413 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.779579413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.811863186 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 28369740 ps |
| CPU time | 0.5 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:51 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811863186 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.811863186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.2076105585 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 17056968 ps |
| CPU time | 0.54 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:51 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076105585 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2076105585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.2149592531 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 45385333 ps |
| CPU time | 0.48 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:51 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149592531 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2149592531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.643757482 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 18775962 ps |
| CPU time | 0.54 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:52 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643757482 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.643757482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.1833244431 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 40119991 ps |
| CPU time | 0.59 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:52 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833244431 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1833244431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2478101476 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 10840816 ps |
| CPU time | 0.63 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:52 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478101476 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2478101476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3321747515 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 37541326 ps |
| CPU time | 0.64 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:52 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321747515 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3321747515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.727110863 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 13281883 ps |
| CPU time | 0.54 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:52 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727110863 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.727110863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.503148928 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 247714307 ps |
| CPU time | 0.6 seconds |
| Started | Oct 15 11:29:17 AM UTC 24 |
| Finished | Oct 15 11:29:22 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503148928 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.503148928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.329643385 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 35553686 ps |
| CPU time | 1.2 seconds |
| Started | Oct 15 11:29:17 AM UTC 24 |
| Finished | Oct 15 11:29:23 AM UTC 24 |
| Peak memory | 206500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329643385 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.329643385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.1126236374 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 69313485 ps |
| CPU time | 0.5 seconds |
| Started | Oct 15 11:29:16 AM UTC 24 |
| Finished | Oct 15 11:29:21 AM UTC 24 |
| Peak memory | 204184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126236374 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1126236374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2770740965 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 19076828 ps |
| CPU time | 0.8 seconds |
| Started | Oct 15 11:29:17 AM UTC 24 |
| Finished | Oct 15 11:29:32 AM UTC 24 |
| Peak memory | 207696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2770740965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_r eset.2770740965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.850201092 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 163862870 ps |
| CPU time | 0.48 seconds |
| Started | Oct 15 11:29:16 AM UTC 24 |
| Finished | Oct 15 11:29:21 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850201092 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.850201092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.4080201892 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 45744908 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:16 AM UTC 24 |
| Finished | Oct 15 11:29:21 AM UTC 24 |
| Peak memory | 204240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080201892 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4080201892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.3696157238 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 129150346 ps |
| CPU time | 0.69 seconds |
| Started | Oct 15 11:29:17 AM UTC 24 |
| Finished | Oct 15 11:29:22 AM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696157238 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.3696157238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.3525744332 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 39042116 ps |
| CPU time | 0.92 seconds |
| Started | Oct 15 11:29:16 AM UTC 24 |
| Finished | Oct 15 11:29:21 AM UTC 24 |
| Peak memory | 207752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525744332 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3525744332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.3533847994 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 334896568 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 11:29:16 AM UTC 24 |
| Finished | Oct 15 11:29:21 AM UTC 24 |
| Peak memory | 207392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533847994 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3533847994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.365222280 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 14530843 ps |
| CPU time | 0.61 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:52 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365222280 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.365222280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3749939550 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 20374988 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:52 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749939550 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3749939550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.811769491 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 35101748 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:52 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811769491 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.811769491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.1033563117 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 169330110 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:51 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033563117 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1033563117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.3294002911 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 41562177 ps |
| CPU time | 0.55 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:51 AM UTC 24 |
| Peak memory | 201772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294002911 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3294002911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.3649606213 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 30146100 ps |
| CPU time | 0.53 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:51 AM UTC 24 |
| Peak memory | 203768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649606213 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3649606213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.1984005447 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 26805401 ps |
| CPU time | 0.58 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:52 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984005447 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1984005447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.673537 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 23384116 ps |
| CPU time | 0.53 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:52 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.673537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2953707706 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 40842752 ps |
| CPU time | 0.62 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:52 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953707706 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2953707706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.1611960808 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 14630849 ps |
| CPU time | 0.58 seconds |
| Started | Oct 15 11:29:49 AM UTC 24 |
| Finished | Oct 15 11:29:52 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611960808 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1611960808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2193730238 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 24492652 ps |
| CPU time | 0.69 seconds |
| Started | Oct 15 11:29:19 AM UTC 24 |
| Finished | Oct 15 11:29:27 AM UTC 24 |
| Peak memory | 207344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2193730238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_r eset.2193730238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1786659547 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 77784028 ps |
| CPU time | 0.64 seconds |
| Started | Oct 15 11:29:22 AM UTC 24 |
| Finished | Oct 15 11:29:27 AM UTC 24 |
| Peak memory | 206432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1786659547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_r eset.1786659547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.1938635446 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 116113554 ps |
| CPU time | 0.57 seconds |
| Started | Oct 15 11:29:22 AM UTC 24 |
| Finished | Oct 15 11:29:26 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938635446 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1938635446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.22113840 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 38869359 ps |
| CPU time | 0.51 seconds |
| Started | Oct 15 11:29:22 AM UTC 24 |
| Finished | Oct 15 11:29:26 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22113840 -assert nopostproc +UVM_TESTNAME=uart_base_te st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.22113840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.1982331861 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 55381135 ps |
| CPU time | 0.62 seconds |
| Started | Oct 15 11:29:22 AM UTC 24 |
| Finished | Oct 15 11:29:27 AM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982331861 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.1982331861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.1212236138 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 29607994 ps |
| CPU time | 1.38 seconds |
| Started | Oct 15 11:29:19 AM UTC 24 |
| Finished | Oct 15 11:29:28 AM UTC 24 |
| Peak memory | 209136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212236138 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1212236138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.3481506935 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 237155297 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 11:29:19 AM UTC 24 |
| Finished | Oct 15 11:29:28 AM UTC 24 |
| Peak memory | 208100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481506935 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3481506935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2178556058 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 50283795 ps |
| CPU time | 0.69 seconds |
| Started | Oct 15 11:29:23 AM UTC 24 |
| Finished | Oct 15 11:29:28 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2178556058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_r eset.2178556058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.3527367641 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 17213967 ps |
| CPU time | 0.5 seconds |
| Started | Oct 15 11:29:23 AM UTC 24 |
| Finished | Oct 15 11:29:28 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527367641 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3527367641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.3599174566 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 15841770 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:22 AM UTC 24 |
| Finished | Oct 15 11:29:26 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599174566 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3599174566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.2871198839 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 51432052 ps |
| CPU time | 0.65 seconds |
| Started | Oct 15 11:29:23 AM UTC 24 |
| Finished | Oct 15 11:29:28 AM UTC 24 |
| Peak memory | 206372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871198839 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.2871198839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.4201497636 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 610705154 ps |
| CPU time | 2.38 seconds |
| Started | Oct 15 11:29:22 AM UTC 24 |
| Finished | Oct 15 11:29:28 AM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201497636 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.4201497636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.3227666421 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 467596482 ps |
| CPU time | 1.14 seconds |
| Started | Oct 15 11:29:22 AM UTC 24 |
| Finished | Oct 15 11:29:27 AM UTC 24 |
| Peak memory | 207628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227666421 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3227666421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2692558248 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 46311384 ps |
| CPU time | 0.59 seconds |
| Started | Oct 15 11:29:27 AM UTC 24 |
| Finished | Oct 15 11:29:42 AM UTC 24 |
| Peak memory | 206372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2692558248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_r eset.2692558248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.2469388768 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 42343257 ps |
| CPU time | 0.62 seconds |
| Started | Oct 15 11:29:27 AM UTC 24 |
| Finished | Oct 15 11:29:32 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469388768 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2469388768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.34016334 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 14183669 ps |
| CPU time | 0.56 seconds |
| Started | Oct 15 11:29:27 AM UTC 24 |
| Finished | Oct 15 11:29:32 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34016334 -assert nopostproc +UVM_TESTNAME=uart_base_te st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.34016334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.4059573968 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 29463576 ps |
| CPU time | 0.72 seconds |
| Started | Oct 15 11:29:27 AM UTC 24 |
| Finished | Oct 15 11:29:32 AM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059573968 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.4059573968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.536751903 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 233506496 ps |
| CPU time | 1.38 seconds |
| Started | Oct 15 11:29:23 AM UTC 24 |
| Finished | Oct 15 11:29:32 AM UTC 24 |
| Peak memory | 209132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536751903 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.536751903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3921652633 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 28772609 ps |
| CPU time | 0.9 seconds |
| Started | Oct 15 11:29:29 AM UTC 24 |
| Finished | Oct 15 11:29:32 AM UTC 24 |
| Peak memory | 207984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3921652633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_r eset.3921652633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.2073870089 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 14646511 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 11:29:29 AM UTC 24 |
| Finished | Oct 15 11:29:31 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073870089 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2073870089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.2704777965 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 44371257 ps |
| CPU time | 0.5 seconds |
| Started | Oct 15 11:29:29 AM UTC 24 |
| Finished | Oct 15 11:29:31 AM UTC 24 |
| Peak memory | 204388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704777965 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2704777965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.2724008770 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 54252793 ps |
| CPU time | 0.62 seconds |
| Started | Oct 15 11:29:29 AM UTC 24 |
| Finished | Oct 15 11:29:31 AM UTC 24 |
| Peak memory | 206376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724008770 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.2724008770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.103158671 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 463553199 ps |
| CPU time | 2.35 seconds |
| Started | Oct 15 11:29:29 AM UTC 24 |
| Finished | Oct 15 11:29:46 AM UTC 24 |
| Peak memory | 208940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103158671 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.103158671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.204640177 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 173203688 ps |
| CPU time | 0.9 seconds |
| Started | Oct 15 11:29:29 AM UTC 24 |
| Finished | Oct 15 11:29:45 AM UTC 24 |
| Peak memory | 208396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204640177 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.204640177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_intr.2092978890 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 120753616863 ps |
| CPU time | 229.05 seconds |
| Started | Oct 15 10:27:41 AM UTC 24 |
| Finished | Oct 15 10:31:34 AM UTC 24 |
| Peak memory | 208484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092978890 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2092978890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_loopback.2068508184 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 7977314991 ps |
| CPU time | 11.31 seconds |
| Started | Oct 15 10:27:43 AM UTC 24 |
| Finished | Oct 15 10:27:55 AM UTC 24 |
| Peak memory | 208868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068508184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2068508184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_noise_filter.3238166472 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 73184335472 ps |
| CPU time | 174.69 seconds |
| Started | Oct 15 10:27:41 AM UTC 24 |
| Finished | Oct 15 10:30:39 AM UTC 24 |
| Peak memory | 208088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238166472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3238166472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_perf.1959907832 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 10521812636 ps |
| CPU time | 673.53 seconds |
| Started | Oct 15 10:27:44 AM UTC 24 |
| Finished | Oct 15 10:39:08 AM UTC 24 |
| Peak memory | 208684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959907832 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1959907832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_rx_oversample.3681086271 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3896834080 ps |
| CPU time | 38.65 seconds |
| Started | Oct 15 10:27:40 AM UTC 24 |
| Finished | Oct 15 10:28:20 AM UTC 24 |
| Peak memory | 207408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681086271 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3681086271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.513308082 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 52911230371 ps |
| CPU time | 121.97 seconds |
| Started | Oct 15 10:27:42 AM UTC 24 |
| Finished | Oct 15 10:29:46 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513308082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.513308082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.2364915068 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 40061328891 ps |
| CPU time | 45.05 seconds |
| Started | Oct 15 10:27:41 AM UTC 24 |
| Finished | Oct 15 10:28:28 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364915068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2364915068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_smoke.1271392412 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6104838210 ps |
| CPU time | 6.3 seconds |
| Started | Oct 15 10:27:36 AM UTC 24 |
| Finished | Oct 15 10:27:44 AM UTC 24 |
| Peak memory | 208236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271392412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1271392412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.3628179079 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2990906466 ps |
| CPU time | 79.1 seconds |
| Started | Oct 15 10:27:45 AM UTC 24 |
| Finished | Oct 15 10:29:06 AM UTC 24 |
| Peak memory | 217728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3628179079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_ with_rand_reset.3628179079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.4045083530 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 7507493485 ps |
| CPU time | 16.06 seconds |
| Started | Oct 15 10:27:42 AM UTC 24 |
| Finished | Oct 15 10:27:59 AM UTC 24 |
| Peak memory | 208496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045083530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.4045083530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/0.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_alert_test.279652936 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 33456795 ps |
| CPU time | 0.74 seconds |
| Started | Oct 15 10:29:13 AM UTC 24 |
| Finished | Oct 15 10:29:15 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279652936 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.279652936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_fifo_full.3616332001 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 46280077192 ps |
| CPU time | 109.79 seconds |
| Started | Oct 15 10:28:04 AM UTC 24 |
| Finished | Oct 15 10:29:56 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616332001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3616332001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.3980465309 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 111649498221 ps |
| CPU time | 270.49 seconds |
| Started | Oct 15 10:28:10 AM UTC 24 |
| Finished | Oct 15 10:32:45 AM UTC 24 |
| Peak memory | 208660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980465309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3980465309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_intr.2986080195 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 18331923640 ps |
| CPU time | 46.44 seconds |
| Started | Oct 15 10:28:21 AM UTC 24 |
| Finished | Oct 15 10:29:09 AM UTC 24 |
| Peak memory | 208364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986080195 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2986080195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_loopback.3456838101 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10730266136 ps |
| CPU time | 27.22 seconds |
| Started | Oct 15 10:28:45 AM UTC 24 |
| Finished | Oct 15 10:29:14 AM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456838101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3456838101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_noise_filter.2758775431 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 35188087601 ps |
| CPU time | 41.84 seconds |
| Started | Oct 15 10:28:28 AM UTC 24 |
| Finished | Oct 15 10:29:11 AM UTC 24 |
| Peak memory | 207500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758775431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2758775431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_perf.959987828 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 15181317880 ps |
| CPU time | 39.17 seconds |
| Started | Oct 15 10:28:49 AM UTC 24 |
| Finished | Oct 15 10:29:30 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959987828 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.959987828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_rx_oversample.2505773176 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1914446371 ps |
| CPU time | 18.72 seconds |
| Started | Oct 15 10:28:20 AM UTC 24 |
| Finished | Oct 15 10:28:40 AM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505773176 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2505773176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.2185969403 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 41220538232 ps |
| CPU time | 100.81 seconds |
| Started | Oct 15 10:28:40 AM UTC 24 |
| Finished | Oct 15 10:30:23 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185969403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2185969403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.810366785 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5643779372 ps |
| CPU time | 4.38 seconds |
| Started | Oct 15 10:28:39 AM UTC 24 |
| Finished | Oct 15 10:28:44 AM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810366785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.810366785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_sec_cm.1188984159 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 229000650 ps |
| CPU time | 1.26 seconds |
| Started | Oct 15 10:29:10 AM UTC 24 |
| Finished | Oct 15 10:29:12 AM UTC 24 |
| Peak memory | 237596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188984159 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1188984159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_smoke.2474505136 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 272270599 ps |
| CPU time | 1.7 seconds |
| Started | Oct 15 10:28:00 AM UTC 24 |
| Finished | Oct 15 10:28:03 AM UTC 24 |
| Peak memory | 208348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474505136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2474505136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_stress_all.2628880089 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 197704615245 ps |
| CPU time | 1965.01 seconds |
| Started | Oct 15 10:29:08 AM UTC 24 |
| Finished | Oct 15 11:02:20 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628880089 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2628880089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.93757540 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2072471473 ps |
| CPU time | 2.39 seconds |
| Started | Oct 15 10:28:45 AM UTC 24 |
| Finished | Oct 15 10:28:49 AM UTC 24 |
| Peak memory | 207496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93757540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.93757540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/1.uart_tx_rx.305848212 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 46704795635 ps |
| CPU time | 16.66 seconds |
| Started | Oct 15 10:28:02 AM UTC 24 |
| Finished | Oct 15 10:28:19 AM UTC 24 |
| Peak memory | 207232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305848212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.305848212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_alert_test.1346555698 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 15947510 ps |
| CPU time | 0.76 seconds |
| Started | Oct 15 10:43:25 AM UTC 24 |
| Finished | Oct 15 10:43:27 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346555698 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1346555698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_fifo_full.2203986595 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 30539984526 ps |
| CPU time | 22.04 seconds |
| Started | Oct 15 10:41:49 AM UTC 24 |
| Finished | Oct 15 10:42:13 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203986595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2203986595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.46044172 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 44087251704 ps |
| CPU time | 100.05 seconds |
| Started | Oct 15 10:42:06 AM UTC 24 |
| Finished | Oct 15 10:43:48 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46044172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.46044172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_intr.2504785723 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 8932709116 ps |
| CPU time | 5.95 seconds |
| Started | Oct 15 10:42:26 AM UTC 24 |
| Finished | Oct 15 10:42:33 AM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504785723 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2504785723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.2127819711 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 99378205725 ps |
| CPU time | 365.98 seconds |
| Started | Oct 15 10:42:55 AM UTC 24 |
| Finished | Oct 15 10:49:07 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127819711 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2127819711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_loopback.157861554 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 3437448147 ps |
| CPU time | 1.47 seconds |
| Started | Oct 15 10:42:52 AM UTC 24 |
| Finished | Oct 15 10:42:55 AM UTC 24 |
| Peak memory | 206308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157861554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 10.uart_loopback.157861554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_noise_filter.777005530 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 126509592621 ps |
| CPU time | 101.39 seconds |
| Started | Oct 15 10:42:27 AM UTC 24 |
| Finished | Oct 15 10:44:10 AM UTC 24 |
| Peak memory | 208920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777005530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.777005530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_perf.658555382 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 9447362126 ps |
| CPU time | 101.25 seconds |
| Started | Oct 15 10:42:55 AM UTC 24 |
| Finished | Oct 15 10:44:39 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658555382 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.658555382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_rx_oversample.4094027307 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 3066523384 ps |
| CPU time | 10.14 seconds |
| Started | Oct 15 10:42:14 AM UTC 24 |
| Finished | Oct 15 10:42:25 AM UTC 24 |
| Peak memory | 207532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094027307 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.4094027307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.3218359895 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 45526604641 ps |
| CPU time | 24.93 seconds |
| Started | Oct 15 10:42:34 AM UTC 24 |
| Finished | Oct 15 10:43:00 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218359895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3218359895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.2824025687 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 45141817838 ps |
| CPU time | 111.92 seconds |
| Started | Oct 15 10:42:33 AM UTC 24 |
| Finished | Oct 15 10:44:27 AM UTC 24 |
| Peak memory | 205304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824025687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2824025687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_smoke.1563171004 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 5544688844 ps |
| CPU time | 22.35 seconds |
| Started | Oct 15 10:41:46 AM UTC 24 |
| Finished | Oct 15 10:42:10 AM UTC 24 |
| Peak memory | 208204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563171004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1563171004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.2007559641 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 70283335562 ps |
| CPU time | 140.01 seconds |
| Started | Oct 15 10:43:01 AM UTC 24 |
| Finished | Oct 15 10:45:25 AM UTC 24 |
| Peak memory | 217904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2007559641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all _with_rand_reset.2007559641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.4223223993 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 722527171 ps |
| CPU time | 2.25 seconds |
| Started | Oct 15 10:42:48 AM UTC 24 |
| Finished | Oct 15 10:42:51 AM UTC 24 |
| Peak memory | 207436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223223993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4223223993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/10.uart_tx_rx.2804935184 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 30785182780 ps |
| CPU time | 42.99 seconds |
| Started | Oct 15 10:41:47 AM UTC 24 |
| Finished | Oct 15 10:42:32 AM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804935184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2804935184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/10.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/101.uart_fifo_reset.3523403530 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 185970609975 ps |
| CPU time | 198.08 seconds |
| Started | Oct 15 11:19:02 AM UTC 24 |
| Finished | Oct 15 11:22:23 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523403530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3523403530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/101.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/102.uart_fifo_reset.1202599670 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 141698670961 ps |
| CPU time | 155.64 seconds |
| Started | Oct 15 11:19:04 AM UTC 24 |
| Finished | Oct 15 11:21:43 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202599670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1202599670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/102.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/104.uart_fifo_reset.1292819772 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 58647339840 ps |
| CPU time | 59.25 seconds |
| Started | Oct 15 11:19:06 AM UTC 24 |
| Finished | Oct 15 11:20:07 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292819772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1292819772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/104.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/105.uart_fifo_reset.131903994 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 7369028846 ps |
| CPU time | 19.28 seconds |
| Started | Oct 15 11:19:09 AM UTC 24 |
| Finished | Oct 15 11:19:30 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131903994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.131903994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/105.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/106.uart_fifo_reset.510768933 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 11071274176 ps |
| CPU time | 21.35 seconds |
| Started | Oct 15 11:19:09 AM UTC 24 |
| Finished | Oct 15 11:19:32 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510768933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.510768933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/106.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/107.uart_fifo_reset.155285633 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 12773445482 ps |
| CPU time | 12.97 seconds |
| Started | Oct 15 11:19:10 AM UTC 24 |
| Finished | Oct 15 11:19:24 AM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155285633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.155285633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/107.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/108.uart_fifo_reset.1117762966 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 90500038881 ps |
| CPU time | 77.13 seconds |
| Started | Oct 15 11:19:16 AM UTC 24 |
| Finished | Oct 15 11:20:35 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117762966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1117762966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/108.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/109.uart_fifo_reset.559299754 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 117741031538 ps |
| CPU time | 57.36 seconds |
| Started | Oct 15 11:19:18 AM UTC 24 |
| Finished | Oct 15 11:20:18 AM UTC 24 |
| Peak memory | 208812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559299754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.559299754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/109.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_alert_test.1731004641 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 14798556 ps |
| CPU time | 0.79 seconds |
| Started | Oct 15 10:45:01 AM UTC 24 |
| Finished | Oct 15 10:45:03 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731004641 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1731004641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_fifo_full.3198465719 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 56039095675 ps |
| CPU time | 72.91 seconds |
| Started | Oct 15 10:43:49 AM UTC 24 |
| Finished | Oct 15 10:45:04 AM UTC 24 |
| Peak memory | 208912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198465719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3198465719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_intr.409576774 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 70332748274 ps |
| CPU time | 58.02 seconds |
| Started | Oct 15 10:44:25 AM UTC 24 |
| Finished | Oct 15 10:45:25 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409576774 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.409576774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.3729075819 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 95672016478 ps |
| CPU time | 744.39 seconds |
| Started | Oct 15 10:44:40 AM UTC 24 |
| Finished | Oct 15 10:57:15 AM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729075819 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3729075819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_loopback.3272553033 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3818933908 ps |
| CPU time | 2.41 seconds |
| Started | Oct 15 10:44:37 AM UTC 24 |
| Finished | Oct 15 10:44:41 AM UTC 24 |
| Peak memory | 207428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272553033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3272553033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_perf.3593645787 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 9618232777 ps |
| CPU time | 532.87 seconds |
| Started | Oct 15 10:44:40 AM UTC 24 |
| Finished | Oct 15 10:53:40 AM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593645787 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3593645787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_rx_oversample.1405440641 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 3921472100 ps |
| CPU time | 15.33 seconds |
| Started | Oct 15 10:44:22 AM UTC 24 |
| Finished | Oct 15 10:44:39 AM UTC 24 |
| Peak memory | 207584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405440641 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1405440641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.2623184476 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 36501588023 ps |
| CPU time | 25.99 seconds |
| Started | Oct 15 10:44:32 AM UTC 24 |
| Finished | Oct 15 10:45:00 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623184476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2623184476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.2100389100 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 837276166 ps |
| CPU time | 2.88 seconds |
| Started | Oct 15 10:44:28 AM UTC 24 |
| Finished | Oct 15 10:44:32 AM UTC 24 |
| Peak memory | 205112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100389100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2100389100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_smoke.2641803634 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 562471569 ps |
| CPU time | 1.79 seconds |
| Started | Oct 15 10:43:28 AM UTC 24 |
| Finished | Oct 15 10:43:31 AM UTC 24 |
| Peak memory | 207736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641803634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2641803634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.2068428743 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 6456350685 ps |
| CPU time | 45.23 seconds |
| Started | Oct 15 10:44:42 AM UTC 24 |
| Finished | Oct 15 10:45:28 AM UTC 24 |
| Peak memory | 217900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2068428743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all _with_rand_reset.2068428743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.675403622 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 2720931448 ps |
| CPU time | 2.37 seconds |
| Started | Oct 15 10:44:33 AM UTC 24 |
| Finished | Oct 15 10:44:37 AM UTC 24 |
| Peak memory | 208412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675403622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.675403622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/11.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/110.uart_fifo_reset.804646266 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 137026958085 ps |
| CPU time | 87.78 seconds |
| Started | Oct 15 11:19:21 AM UTC 24 |
| Finished | Oct 15 11:20:51 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804646266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.804646266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/110.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/111.uart_fifo_reset.791867907 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 74405287924 ps |
| CPU time | 38.56 seconds |
| Started | Oct 15 11:19:22 AM UTC 24 |
| Finished | Oct 15 11:20:02 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791867907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.791867907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/111.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/112.uart_fifo_reset.146492834 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 32879531798 ps |
| CPU time | 46.6 seconds |
| Started | Oct 15 11:19:22 AM UTC 24 |
| Finished | Oct 15 11:20:10 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146492834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.146492834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/112.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/113.uart_fifo_reset.2838617884 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 77515909327 ps |
| CPU time | 41.19 seconds |
| Started | Oct 15 11:19:23 AM UTC 24 |
| Finished | Oct 15 11:20:06 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838617884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2838617884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/113.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/114.uart_fifo_reset.2135496175 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 9442894090 ps |
| CPU time | 13.8 seconds |
| Started | Oct 15 11:19:25 AM UTC 24 |
| Finished | Oct 15 11:19:40 AM UTC 24 |
| Peak memory | 207144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135496175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2135496175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/114.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/115.uart_fifo_reset.1565212223 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 17098698118 ps |
| CPU time | 64.89 seconds |
| Started | Oct 15 11:19:25 AM UTC 24 |
| Finished | Oct 15 11:20:32 AM UTC 24 |
| Peak memory | 208664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565212223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1565212223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/115.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/116.uart_fifo_reset.1795733217 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 57443725795 ps |
| CPU time | 15.85 seconds |
| Started | Oct 15 11:19:26 AM UTC 24 |
| Finished | Oct 15 11:19:43 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795733217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1795733217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/116.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/117.uart_fifo_reset.1397888672 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 144132401511 ps |
| CPU time | 73.78 seconds |
| Started | Oct 15 11:19:26 AM UTC 24 |
| Finished | Oct 15 11:20:42 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397888672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1397888672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/117.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/118.uart_fifo_reset.3479675829 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 160263786549 ps |
| CPU time | 378.45 seconds |
| Started | Oct 15 11:19:26 AM UTC 24 |
| Finished | Oct 15 11:25:49 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479675829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3479675829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/118.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_alert_test.176362910 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 23028226 ps |
| CPU time | 0.72 seconds |
| Started | Oct 15 10:45:56 AM UTC 24 |
| Finished | Oct 15 10:45:58 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176362910 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.176362910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_fifo_full.88865753 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 27697562979 ps |
| CPU time | 62.52 seconds |
| Started | Oct 15 10:45:05 AM UTC 24 |
| Finished | Oct 15 10:46:09 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88865753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.88865753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.3475050890 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 35451988934 ps |
| CPU time | 49.09 seconds |
| Started | Oct 15 10:45:07 AM UTC 24 |
| Finished | Oct 15 10:45:58 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475050890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3475050890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_fifo_reset.1111776122 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 54353456608 ps |
| CPU time | 30.1 seconds |
| Started | Oct 15 10:45:13 AM UTC 24 |
| Finished | Oct 15 10:45:45 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111776122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1111776122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.1452786234 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 135542643849 ps |
| CPU time | 424.7 seconds |
| Started | Oct 15 10:45:42 AM UTC 24 |
| Finished | Oct 15 10:52:53 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452786234 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1452786234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_loopback.3133549260 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 3604040502 ps |
| CPU time | 3.02 seconds |
| Started | Oct 15 10:45:39 AM UTC 24 |
| Finished | Oct 15 10:45:43 AM UTC 24 |
| Peak memory | 205112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133549260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3133549260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_noise_filter.1415820447 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 109214091307 ps |
| CPU time | 129.69 seconds |
| Started | Oct 15 10:45:27 AM UTC 24 |
| Finished | Oct 15 10:47:40 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415820447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1415820447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_perf.2853114253 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 22141832962 ps |
| CPU time | 409.47 seconds |
| Started | Oct 15 10:45:41 AM UTC 24 |
| Finished | Oct 15 10:52:37 AM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853114253 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2853114253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_rx_oversample.2942546595 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 3923633752 ps |
| CPU time | 11.81 seconds |
| Started | Oct 15 10:45:25 AM UTC 24 |
| Finished | Oct 15 10:45:38 AM UTC 24 |
| Peak memory | 207284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942546595 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2942546595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.3795194810 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 34070639615 ps |
| CPU time | 20.15 seconds |
| Started | Oct 15 10:45:34 AM UTC 24 |
| Finished | Oct 15 10:45:55 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795194810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3795194810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.2682326235 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1684888342 ps |
| CPU time | 2.49 seconds |
| Started | Oct 15 10:45:29 AM UTC 24 |
| Finished | Oct 15 10:45:33 AM UTC 24 |
| Peak memory | 205112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682326235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2682326235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_smoke.2992881177 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 107210758 ps |
| CPU time | 1.16 seconds |
| Started | Oct 15 10:45:04 AM UTC 24 |
| Finished | Oct 15 10:45:06 AM UTC 24 |
| Peak memory | 206308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992881177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2992881177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_stress_all.973609253 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 206408464007 ps |
| CPU time | 455.55 seconds |
| Started | Oct 15 10:45:46 AM UTC 24 |
| Finished | Oct 15 10:53:28 AM UTC 24 |
| Peak memory | 212044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973609253 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.973609253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.3375200255 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 4205507681 ps |
| CPU time | 109.75 seconds |
| Started | Oct 15 10:45:44 AM UTC 24 |
| Finished | Oct 15 10:47:36 AM UTC 24 |
| Peak memory | 224580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3375200255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all _with_rand_reset.3375200255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.735036784 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 1089335123 ps |
| CPU time | 2.02 seconds |
| Started | Oct 15 10:45:38 AM UTC 24 |
| Finished | Oct 15 10:45:41 AM UTC 24 |
| Peak memory | 207392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735036784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.735036784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/12.uart_tx_rx.1822592425 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 14990467319 ps |
| CPU time | 31.34 seconds |
| Started | Oct 15 10:45:04 AM UTC 24 |
| Finished | Oct 15 10:45:37 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822592425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1822592425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/12.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/120.uart_fifo_reset.1153939305 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 58081771196 ps |
| CPU time | 21.7 seconds |
| Started | Oct 15 11:19:30 AM UTC 24 |
| Finished | Oct 15 11:19:53 AM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153939305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1153939305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/120.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/121.uart_fifo_reset.2891120406 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 113585093970 ps |
| CPU time | 125.1 seconds |
| Started | Oct 15 11:19:31 AM UTC 24 |
| Finished | Oct 15 11:21:39 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891120406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2891120406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/121.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/122.uart_fifo_reset.147646515 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 206759959086 ps |
| CPU time | 63.27 seconds |
| Started | Oct 15 11:19:31 AM UTC 24 |
| Finished | Oct 15 11:20:36 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147646515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.147646515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/122.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/123.uart_fifo_reset.1185768295 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 16383890838 ps |
| CPU time | 60.6 seconds |
| Started | Oct 15 11:19:31 AM UTC 24 |
| Finished | Oct 15 11:20:34 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185768295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1185768295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/123.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/124.uart_fifo_reset.793614009 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 239970374739 ps |
| CPU time | 373.83 seconds |
| Started | Oct 15 11:19:33 AM UTC 24 |
| Finished | Oct 15 11:25:51 AM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793614009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.793614009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/124.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/125.uart_fifo_reset.3590731790 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 25788992599 ps |
| CPU time | 17.62 seconds |
| Started | Oct 15 11:19:33 AM UTC 24 |
| Finished | Oct 15 11:19:51 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590731790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3590731790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/125.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/126.uart_fifo_reset.1712683552 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 50371884553 ps |
| CPU time | 70.68 seconds |
| Started | Oct 15 11:19:33 AM UTC 24 |
| Finished | Oct 15 11:20:45 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712683552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1712683552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/126.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/128.uart_fifo_reset.1310520319 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 70235010990 ps |
| CPU time | 50.8 seconds |
| Started | Oct 15 11:19:35 AM UTC 24 |
| Finished | Oct 15 11:20:27 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310520319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1310520319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/128.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/129.uart_fifo_reset.3917226393 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 96457010881 ps |
| CPU time | 132.13 seconds |
| Started | Oct 15 11:19:35 AM UTC 24 |
| Finished | Oct 15 11:21:49 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917226393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3917226393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/129.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_alert_test.1682218813 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 10831632 ps |
| CPU time | 0.75 seconds |
| Started | Oct 15 10:47:45 AM UTC 24 |
| Finished | Oct 15 10:47:47 AM UTC 24 |
| Peak memory | 204388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682218813 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1682218813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_fifo_full.3211031102 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 34677236770 ps |
| CPU time | 21.29 seconds |
| Started | Oct 15 10:46:07 AM UTC 24 |
| Finished | Oct 15 10:46:30 AM UTC 24 |
| Peak memory | 208568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211031102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3211031102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.1881831469 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 43758828970 ps |
| CPU time | 44.71 seconds |
| Started | Oct 15 10:46:10 AM UTC 24 |
| Finished | Oct 15 10:46:57 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881831469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1881831469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_fifo_reset.973664113 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 235665052677 ps |
| CPU time | 35.97 seconds |
| Started | Oct 15 10:46:15 AM UTC 24 |
| Finished | Oct 15 10:46:53 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973664113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.973664113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_intr.1564658032 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 89457800361 ps |
| CPU time | 234.99 seconds |
| Started | Oct 15 10:46:31 AM UTC 24 |
| Finished | Oct 15 10:50:29 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564658032 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1564658032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.3838550168 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 282574490747 ps |
| CPU time | 107.97 seconds |
| Started | Oct 15 10:47:19 AM UTC 24 |
| Finished | Oct 15 10:49:09 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838550168 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3838550168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_loopback.1581836631 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 8688001150 ps |
| CPU time | 9.45 seconds |
| Started | Oct 15 10:46:59 AM UTC 24 |
| Finished | Oct 15 10:47:10 AM UTC 24 |
| Peak memory | 207540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581836631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1581836631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_noise_filter.3166260815 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 208488596127 ps |
| CPU time | 112.6 seconds |
| Started | Oct 15 10:46:39 AM UTC 24 |
| Finished | Oct 15 10:48:34 AM UTC 24 |
| Peak memory | 217800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166260815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3166260815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_perf.1374676657 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 6203072217 ps |
| CPU time | 126.33 seconds |
| Started | Oct 15 10:47:10 AM UTC 24 |
| Finished | Oct 15 10:49:19 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374676657 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1374676657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_rx_oversample.303281816 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 6821797171 ps |
| CPU time | 33.95 seconds |
| Started | Oct 15 10:46:21 AM UTC 24 |
| Finished | Oct 15 10:46:57 AM UTC 24 |
| Peak memory | 207372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303281816 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.303281816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.3489063580 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 4001785853 ps |
| CPU time | 3.04 seconds |
| Started | Oct 15 10:46:54 AM UTC 24 |
| Finished | Oct 15 10:46:58 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489063580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3489063580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_smoke.2942550794 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 5566643908 ps |
| CPU time | 6.63 seconds |
| Started | Oct 15 10:45:58 AM UTC 24 |
| Finished | Oct 15 10:46:06 AM UTC 24 |
| Peak memory | 207536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942550794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2942550794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_stress_all.589237955 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 82492543217 ps |
| CPU time | 129.9 seconds |
| Started | Oct 15 10:47:40 AM UTC 24 |
| Finished | Oct 15 10:49:53 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589237955 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.589237955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.1866689264 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2773564142 ps |
| CPU time | 31.94 seconds |
| Started | Oct 15 10:47:37 AM UTC 24 |
| Finished | Oct 15 10:48:11 AM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1866689264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all _with_rand_reset.1866689264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.3390475981 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 6622986422 ps |
| CPU time | 18.59 seconds |
| Started | Oct 15 10:46:58 AM UTC 24 |
| Finished | Oct 15 10:47:18 AM UTC 24 |
| Peak memory | 207844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390475981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3390475981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/13.uart_tx_rx.3771203405 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 66040068402 ps |
| CPU time | 37.06 seconds |
| Started | Oct 15 10:45:59 AM UTC 24 |
| Finished | Oct 15 10:46:38 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771203405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3771203405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/13.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/130.uart_fifo_reset.190308015 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 63917815703 ps |
| CPU time | 66.51 seconds |
| Started | Oct 15 11:19:39 AM UTC 24 |
| Finished | Oct 15 11:20:47 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190308015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.190308015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/130.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/134.uart_fifo_reset.528460803 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 18257529268 ps |
| CPU time | 16.48 seconds |
| Started | Oct 15 11:19:44 AM UTC 24 |
| Finished | Oct 15 11:20:02 AM UTC 24 |
| Peak memory | 208588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528460803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.528460803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/134.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/135.uart_fifo_reset.342493632 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 146798456683 ps |
| CPU time | 74.64 seconds |
| Started | Oct 15 11:19:47 AM UTC 24 |
| Finished | Oct 15 11:21:03 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342493632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.342493632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/135.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/136.uart_fifo_reset.48082445 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 106016299530 ps |
| CPU time | 136 seconds |
| Started | Oct 15 11:19:48 AM UTC 24 |
| Finished | Oct 15 11:22:06 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48082445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.48082445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/136.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/137.uart_fifo_reset.583203437 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 148331262767 ps |
| CPU time | 71.86 seconds |
| Started | Oct 15 11:19:49 AM UTC 24 |
| Finished | Oct 15 11:21:02 AM UTC 24 |
| Peak memory | 208732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583203437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.583203437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/137.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/139.uart_fifo_reset.1366864351 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 60201412454 ps |
| CPU time | 36.34 seconds |
| Started | Oct 15 11:19:50 AM UTC 24 |
| Finished | Oct 15 11:20:28 AM UTC 24 |
| Peak memory | 208460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366864351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1366864351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/139.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_alert_test.1314441115 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 64565343 ps |
| CPU time | 0.72 seconds |
| Started | Oct 15 10:49:26 AM UTC 24 |
| Finished | Oct 15 10:49:27 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314441115 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1314441115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_fifo_full.3766367845 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 109582340029 ps |
| CPU time | 372.91 seconds |
| Started | Oct 15 10:48:04 AM UTC 24 |
| Finished | Oct 15 10:54:23 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766367845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3766367845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.1612592589 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 62384876315 ps |
| CPU time | 39.9 seconds |
| Started | Oct 15 10:48:12 AM UTC 24 |
| Finished | Oct 15 10:48:53 AM UTC 24 |
| Peak memory | 208596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612592589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1612592589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_fifo_reset.390409856 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 130469914449 ps |
| CPU time | 313.52 seconds |
| Started | Oct 15 10:48:13 AM UTC 24 |
| Finished | Oct 15 10:53:31 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390409856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.390409856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_intr.1151989561 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 29563820019 ps |
| CPU time | 70.62 seconds |
| Started | Oct 15 10:48:54 AM UTC 24 |
| Finished | Oct 15 10:50:06 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151989561 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1151989561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.455021499 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 67207946820 ps |
| CPU time | 132.7 seconds |
| Started | Oct 15 10:49:17 AM UTC 24 |
| Finished | Oct 15 10:51:33 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455021499 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.455021499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_loopback.1024083807 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 3372000642 ps |
| CPU time | 8.11 seconds |
| Started | Oct 15 10:49:15 AM UTC 24 |
| Finished | Oct 15 10:49:24 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024083807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1024083807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_noise_filter.3564484650 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 47364841399 ps |
| CPU time | 101.8 seconds |
| Started | Oct 15 10:49:05 AM UTC 24 |
| Finished | Oct 15 10:50:49 AM UTC 24 |
| Peak memory | 208280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564484650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3564484650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_rx_oversample.212425381 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 3059634085 ps |
| CPU time | 27.66 seconds |
| Started | Oct 15 10:48:35 AM UTC 24 |
| Finished | Oct 15 10:49:04 AM UTC 24 |
| Peak memory | 207448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212425381 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.212425381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.1449279324 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 138222169847 ps |
| CPU time | 337.32 seconds |
| Started | Oct 15 10:49:09 AM UTC 24 |
| Finished | Oct 15 10:54:52 AM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449279324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1449279324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.203029493 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 2150430749 ps |
| CPU time | 5.31 seconds |
| Started | Oct 15 10:49:08 AM UTC 24 |
| Finished | Oct 15 10:49:14 AM UTC 24 |
| Peak memory | 205244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203029493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.203029493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_smoke.1400335710 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 5969065616 ps |
| CPU time | 14.48 seconds |
| Started | Oct 15 10:47:48 AM UTC 24 |
| Finished | Oct 15 10:48:04 AM UTC 24 |
| Peak memory | 208140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400335710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1400335710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.3730629910 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 3853166244 ps |
| CPU time | 89.08 seconds |
| Started | Oct 15 10:49:19 AM UTC 24 |
| Finished | Oct 15 10:50:51 AM UTC 24 |
| Peak memory | 225020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3730629910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all _with_rand_reset.3730629910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.3058614628 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1315795707 ps |
| CPU time | 5.04 seconds |
| Started | Oct 15 10:49:10 AM UTC 24 |
| Finished | Oct 15 10:49:16 AM UTC 24 |
| Peak memory | 207440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058614628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3058614628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/14.uart_tx_rx.1102600923 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 39552959954 ps |
| CPU time | 21.58 seconds |
| Started | Oct 15 10:47:49 AM UTC 24 |
| Finished | Oct 15 10:48:12 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102600923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1102600923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/14.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/140.uart_fifo_reset.1334521649 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 35640920587 ps |
| CPU time | 18.53 seconds |
| Started | Oct 15 11:19:52 AM UTC 24 |
| Finished | Oct 15 11:20:12 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334521649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1334521649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/140.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/141.uart_fifo_reset.1288910410 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 92267200339 ps |
| CPU time | 89.52 seconds |
| Started | Oct 15 11:19:52 AM UTC 24 |
| Finished | Oct 15 11:21:23 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288910410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1288910410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/141.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/142.uart_fifo_reset.339474973 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 132811422241 ps |
| CPU time | 261.17 seconds |
| Started | Oct 15 11:19:54 AM UTC 24 |
| Finished | Oct 15 11:24:19 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339474973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.339474973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/142.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/143.uart_fifo_reset.10604169 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 41550275957 ps |
| CPU time | 127.25 seconds |
| Started | Oct 15 11:19:58 AM UTC 24 |
| Finished | Oct 15 11:22:08 AM UTC 24 |
| Peak memory | 208620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10604169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.10604169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/143.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/144.uart_fifo_reset.608806768 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 30205267824 ps |
| CPU time | 45.32 seconds |
| Started | Oct 15 11:20:03 AM UTC 24 |
| Finished | Oct 15 11:20:50 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608806768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.608806768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/144.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/145.uart_fifo_reset.1873828842 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 155530467125 ps |
| CPU time | 48.22 seconds |
| Started | Oct 15 11:20:03 AM UTC 24 |
| Finished | Oct 15 11:20:53 AM UTC 24 |
| Peak memory | 208508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873828842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1873828842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/145.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/146.uart_fifo_reset.1573674103 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 76957261011 ps |
| CPU time | 162.8 seconds |
| Started | Oct 15 11:20:06 AM UTC 24 |
| Finished | Oct 15 11:22:52 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573674103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1573674103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/146.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/147.uart_fifo_reset.2771187205 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 39782115818 ps |
| CPU time | 60.84 seconds |
| Started | Oct 15 11:20:08 AM UTC 24 |
| Finished | Oct 15 11:21:11 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771187205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2771187205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/147.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/148.uart_fifo_reset.1763782732 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 30081977432 ps |
| CPU time | 25.97 seconds |
| Started | Oct 15 11:20:09 AM UTC 24 |
| Finished | Oct 15 11:20:36 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763782732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1763782732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/148.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_alert_test.4080125585 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 31633103 ps |
| CPU time | 0.7 seconds |
| Started | Oct 15 10:51:34 AM UTC 24 |
| Finished | Oct 15 10:51:36 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080125585 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4080125585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.522388783 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 54185171585 ps |
| CPU time | 112.72 seconds |
| Started | Oct 15 10:49:54 AM UTC 24 |
| Finished | Oct 15 10:51:49 AM UTC 24 |
| Peak memory | 208740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522388783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.522388783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_fifo_reset.2959127975 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 111128002253 ps |
| CPU time | 338.76 seconds |
| Started | Oct 15 10:50:07 AM UTC 24 |
| Finished | Oct 15 10:55:51 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959127975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2959127975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_intr.832217778 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 54200235245 ps |
| CPU time | 32.99 seconds |
| Started | Oct 15 10:50:30 AM UTC 24 |
| Finished | Oct 15 10:51:05 AM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832217778 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.832217778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.1935538862 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 112572538637 ps |
| CPU time | 743.97 seconds |
| Started | Oct 15 10:51:21 AM UTC 24 |
| Finished | Oct 15 11:03:55 AM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935538862 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1935538862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_loopback.1813430171 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1825700846 ps |
| CPU time | 2.27 seconds |
| Started | Oct 15 10:51:05 AM UTC 24 |
| Finished | Oct 15 10:51:09 AM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813430171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1813430171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_noise_filter.1194365624 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4580138265 ps |
| CPU time | 10.01 seconds |
| Started | Oct 15 10:50:50 AM UTC 24 |
| Finished | Oct 15 10:51:01 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194365624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1194365624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_perf.3797217609 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 11075420410 ps |
| CPU time | 199.03 seconds |
| Started | Oct 15 10:51:10 AM UTC 24 |
| Finished | Oct 15 10:54:32 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797217609 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3797217609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_rx_oversample.3948723480 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 5682220378 ps |
| CPU time | 57.5 seconds |
| Started | Oct 15 10:50:21 AM UTC 24 |
| Finished | Oct 15 10:51:20 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948723480 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3948723480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.4283549925 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 58505196786 ps |
| CPU time | 132.85 seconds |
| Started | Oct 15 10:50:54 AM UTC 24 |
| Finished | Oct 15 10:53:10 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283549925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.4283549925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.620525195 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2448581488 ps |
| CPU time | 1.78 seconds |
| Started | Oct 15 10:50:51 AM UTC 24 |
| Finished | Oct 15 10:50:54 AM UTC 24 |
| Peak memory | 206248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620525195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.620525195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_smoke.3047875542 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 155579864 ps |
| CPU time | 1.08 seconds |
| Started | Oct 15 10:49:29 AM UTC 24 |
| Finished | Oct 15 10:49:31 AM UTC 24 |
| Peak memory | 206184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047875542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3047875542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_stress_all.2411073684 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 244229626557 ps |
| CPU time | 226.93 seconds |
| Started | Oct 15 10:51:25 AM UTC 24 |
| Finished | Oct 15 10:55:16 AM UTC 24 |
| Peak memory | 219892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411073684 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2411073684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.2783706878 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 7896871245 ps |
| CPU time | 18.51 seconds |
| Started | Oct 15 10:51:02 AM UTC 24 |
| Finished | Oct 15 10:51:22 AM UTC 24 |
| Peak memory | 208588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783706878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2783706878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/15.uart_tx_rx.2028900051 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 20120848789 ps |
| CPU time | 49.74 seconds |
| Started | Oct 15 10:49:29 AM UTC 24 |
| Finished | Oct 15 10:50:20 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028900051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2028900051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/15.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/150.uart_fifo_reset.276562399 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 25155162350 ps |
| CPU time | 31.98 seconds |
| Started | Oct 15 11:20:13 AM UTC 24 |
| Finished | Oct 15 11:20:46 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276562399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.276562399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/150.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/151.uart_fifo_reset.1984773401 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 136480270393 ps |
| CPU time | 38.73 seconds |
| Started | Oct 15 11:20:19 AM UTC 24 |
| Finished | Oct 15 11:20:59 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984773401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1984773401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/151.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/152.uart_fifo_reset.4276313001 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 212159370585 ps |
| CPU time | 103.17 seconds |
| Started | Oct 15 11:20:20 AM UTC 24 |
| Finished | Oct 15 11:22:05 AM UTC 24 |
| Peak memory | 208672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276313001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.4276313001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/152.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/153.uart_fifo_reset.2054045756 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 84547747807 ps |
| CPU time | 88.52 seconds |
| Started | Oct 15 11:20:20 AM UTC 24 |
| Finished | Oct 15 11:21:50 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054045756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2054045756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/153.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/154.uart_fifo_reset.2905472707 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 32050463340 ps |
| CPU time | 36.73 seconds |
| Started | Oct 15 11:20:21 AM UTC 24 |
| Finished | Oct 15 11:20:59 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905472707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2905472707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/154.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/155.uart_fifo_reset.4232285290 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 62405935707 ps |
| CPU time | 48.45 seconds |
| Started | Oct 15 11:20:28 AM UTC 24 |
| Finished | Oct 15 11:21:18 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232285290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.4232285290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/155.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/156.uart_fifo_reset.3472163510 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 20676951363 ps |
| CPU time | 11.48 seconds |
| Started | Oct 15 11:20:28 AM UTC 24 |
| Finished | Oct 15 11:20:41 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472163510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3472163510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/156.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/157.uart_fifo_reset.2645326374 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 37907846190 ps |
| CPU time | 33.58 seconds |
| Started | Oct 15 11:20:29 AM UTC 24 |
| Finished | Oct 15 11:21:04 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645326374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2645326374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/157.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/158.uart_fifo_reset.3877306131 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 100590316610 ps |
| CPU time | 229.24 seconds |
| Started | Oct 15 11:20:29 AM UTC 24 |
| Finished | Oct 15 11:24:22 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877306131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3877306131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/158.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_alert_test.3542259872 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 13290584 ps |
| CPU time | 0.69 seconds |
| Started | Oct 15 10:53:29 AM UTC 24 |
| Finished | Oct 15 10:53:31 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542259872 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3542259872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.2422681652 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 63107572221 ps |
| CPU time | 35.89 seconds |
| Started | Oct 15 10:51:55 AM UTC 24 |
| Finished | Oct 15 10:52:33 AM UTC 24 |
| Peak memory | 207380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422681652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2422681652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_fifo_reset.1838860704 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 12409897709 ps |
| CPU time | 68.17 seconds |
| Started | Oct 15 10:52:06 AM UTC 24 |
| Finished | Oct 15 10:53:16 AM UTC 24 |
| Peak memory | 208480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838860704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1838860704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_intr.2470993857 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 570355560 ps |
| CPU time | 1.39 seconds |
| Started | Oct 15 10:52:33 AM UTC 24 |
| Finished | Oct 15 10:52:36 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470993857 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2470993857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.3365248605 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 215125029413 ps |
| CPU time | 467.21 seconds |
| Started | Oct 15 10:53:11 AM UTC 24 |
| Finished | Oct 15 11:01:05 AM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365248605 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3365248605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_loopback.374973403 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1803447388 ps |
| CPU time | 2.99 seconds |
| Started | Oct 15 10:52:55 AM UTC 24 |
| Finished | Oct 15 10:52:59 AM UTC 24 |
| Peak memory | 207088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374973403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 16.uart_loopback.374973403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_noise_filter.1578400232 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 159227404485 ps |
| CPU time | 78.47 seconds |
| Started | Oct 15 10:52:36 AM UTC 24 |
| Finished | Oct 15 10:53:57 AM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578400232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1578400232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_perf.1120886944 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 12517587923 ps |
| CPU time | 436.08 seconds |
| Started | Oct 15 10:53:00 AM UTC 24 |
| Finished | Oct 15 11:00:23 AM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120886944 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1120886944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_rx_oversample.3673573293 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 6695354606 ps |
| CPU time | 71.53 seconds |
| Started | Oct 15 10:52:26 AM UTC 24 |
| Finished | Oct 15 10:53:40 AM UTC 24 |
| Peak memory | 208060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673573293 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3673573293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.1151475340 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 70268092937 ps |
| CPU time | 48.93 seconds |
| Started | Oct 15 10:52:49 AM UTC 24 |
| Finished | Oct 15 10:53:39 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151475340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1151475340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.3746003179 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3226282952 ps |
| CPU time | 9.21 seconds |
| Started | Oct 15 10:52:38 AM UTC 24 |
| Finished | Oct 15 10:52:48 AM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746003179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3746003179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_smoke.4095762980 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 472849296 ps |
| CPU time | 3.03 seconds |
| Started | Oct 15 10:51:37 AM UTC 24 |
| Finished | Oct 15 10:51:41 AM UTC 24 |
| Peak memory | 207468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095762980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.uart_smoke.4095762980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_stress_all.929578496 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 510048233671 ps |
| CPU time | 84.06 seconds |
| Started | Oct 15 10:53:24 AM UTC 24 |
| Finished | Oct 15 10:54:50 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929578496 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.929578496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.1272998628 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 11832518565 ps |
| CPU time | 47.28 seconds |
| Started | Oct 15 10:52:54 AM UTC 24 |
| Finished | Oct 15 10:53:43 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272998628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1272998628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/16.uart_tx_rx.184375214 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 8934751462 ps |
| CPU time | 11.21 seconds |
| Started | Oct 15 10:51:42 AM UTC 24 |
| Finished | Oct 15 10:51:55 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184375214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.184375214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/16.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/160.uart_fifo_reset.2449656529 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 23389785871 ps |
| CPU time | 45.52 seconds |
| Started | Oct 15 11:20:32 AM UTC 24 |
| Finished | Oct 15 11:21:19 AM UTC 24 |
| Peak memory | 208612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449656529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2449656529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/160.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/162.uart_fifo_reset.2595209700 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 115645538094 ps |
| CPU time | 67.96 seconds |
| Started | Oct 15 11:20:35 AM UTC 24 |
| Finished | Oct 15 11:21:44 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595209700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2595209700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/162.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/164.uart_fifo_reset.2143444472 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 49706312455 ps |
| CPU time | 41.49 seconds |
| Started | Oct 15 11:20:37 AM UTC 24 |
| Finished | Oct 15 11:21:20 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143444472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2143444472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/164.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/165.uart_fifo_reset.635845936 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 274109467501 ps |
| CPU time | 58.57 seconds |
| Started | Oct 15 11:20:37 AM UTC 24 |
| Finished | Oct 15 11:21:37 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635845936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.635845936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/165.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/166.uart_fifo_reset.1609903681 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 23088498364 ps |
| CPU time | 71.89 seconds |
| Started | Oct 15 11:20:37 AM UTC 24 |
| Finished | Oct 15 11:21:51 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609903681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1609903681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/166.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/167.uart_fifo_reset.3104377611 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 160198560984 ps |
| CPU time | 60.47 seconds |
| Started | Oct 15 11:20:41 AM UTC 24 |
| Finished | Oct 15 11:21:43 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104377611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3104377611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/167.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/168.uart_fifo_reset.1415064681 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 178866120325 ps |
| CPU time | 380.4 seconds |
| Started | Oct 15 11:20:42 AM UTC 24 |
| Finished | Oct 15 11:27:07 AM UTC 24 |
| Peak memory | 212080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415064681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1415064681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/168.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/169.uart_fifo_reset.3980135573 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 103319178057 ps |
| CPU time | 76.64 seconds |
| Started | Oct 15 11:20:46 AM UTC 24 |
| Finished | Oct 15 11:22:05 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980135573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3980135573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/169.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_alert_test.4083464761 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 138310701 ps |
| CPU time | 0.7 seconds |
| Started | Oct 15 10:54:25 AM UTC 24 |
| Finished | Oct 15 10:54:27 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083464761 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.4083464761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_fifo_full.2361036723 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 47929980213 ps |
| CPU time | 85.54 seconds |
| Started | Oct 15 10:53:36 AM UTC 24 |
| Finished | Oct 15 10:55:04 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361036723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2361036723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.807329519 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 106953344146 ps |
| CPU time | 562.05 seconds |
| Started | Oct 15 10:53:40 AM UTC 24 |
| Finished | Oct 15 11:03:10 AM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807329519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.807329519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_fifo_reset.2447362686 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 215799810339 ps |
| CPU time | 110.36 seconds |
| Started | Oct 15 10:53:40 AM UTC 24 |
| Finished | Oct 15 10:55:33 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447362686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2447362686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_intr.586733394 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 263158123979 ps |
| CPU time | 276.81 seconds |
| Started | Oct 15 10:53:44 AM UTC 24 |
| Finished | Oct 15 10:58:25 AM UTC 24 |
| Peak memory | 208504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586733394 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.586733394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.762381561 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 117112678195 ps |
| CPU time | 677.85 seconds |
| Started | Oct 15 10:54:22 AM UTC 24 |
| Finished | Oct 15 11:05:50 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762381561 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.762381561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_loopback.3789812513 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 3012701192 ps |
| CPU time | 9.3 seconds |
| Started | Oct 15 10:54:14 AM UTC 24 |
| Finished | Oct 15 10:54:24 AM UTC 24 |
| Peak memory | 208152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789812513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3789812513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_noise_filter.1460623856 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 3108054934 ps |
| CPU time | 7.88 seconds |
| Started | Oct 15 10:53:51 AM UTC 24 |
| Finished | Oct 15 10:54:00 AM UTC 24 |
| Peak memory | 205324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460623856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1460623856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_perf.1603436749 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 6656754016 ps |
| CPU time | 233.84 seconds |
| Started | Oct 15 10:54:18 AM UTC 24 |
| Finished | Oct 15 10:58:16 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603436749 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1603436749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_rx_oversample.1945258757 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1479427829 ps |
| CPU time | 7.06 seconds |
| Started | Oct 15 10:53:42 AM UTC 24 |
| Finished | Oct 15 10:53:50 AM UTC 24 |
| Peak memory | 207296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945258757 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1945258757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.2564764220 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 154734780505 ps |
| CPU time | 282.35 seconds |
| Started | Oct 15 10:54:01 AM UTC 24 |
| Finished | Oct 15 10:58:48 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564764220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2564764220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.2304884383 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 43467601383 ps |
| CPU time | 22.39 seconds |
| Started | Oct 15 10:53:58 AM UTC 24 |
| Finished | Oct 15 10:54:22 AM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304884383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2304884383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_smoke.1868668496 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 508845999 ps |
| CPU time | 2.79 seconds |
| Started | Oct 15 10:53:31 AM UTC 24 |
| Finished | Oct 15 10:53:35 AM UTC 24 |
| Peak memory | 207800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868668496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1868668496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.368530256 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 11196412827 ps |
| CPU time | 44.11 seconds |
| Started | Oct 15 10:54:24 AM UTC 24 |
| Finished | Oct 15 10:55:10 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=368530256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all_ with_rand_reset.368530256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.1870136049 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1771778513 ps |
| CPU time | 2.41 seconds |
| Started | Oct 15 10:54:10 AM UTC 24 |
| Finished | Oct 15 10:54:13 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870136049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1870136049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/17.uart_tx_rx.3328997058 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 194503696055 ps |
| CPU time | 43.04 seconds |
| Started | Oct 15 10:53:32 AM UTC 24 |
| Finished | Oct 15 10:54:17 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328997058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3328997058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/17.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/170.uart_fifo_reset.2731258513 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 215457200771 ps |
| CPU time | 199.03 seconds |
| Started | Oct 15 11:20:47 AM UTC 24 |
| Finished | Oct 15 11:24:09 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731258513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2731258513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/170.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/171.uart_fifo_reset.4243099502 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 64496390742 ps |
| CPU time | 151.37 seconds |
| Started | Oct 15 11:20:47 AM UTC 24 |
| Finished | Oct 15 11:23:21 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243099502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.4243099502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/171.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/172.uart_fifo_reset.2623327821 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 99597182614 ps |
| CPU time | 162.36 seconds |
| Started | Oct 15 11:20:49 AM UTC 24 |
| Finished | Oct 15 11:23:33 AM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623327821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2623327821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/172.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/173.uart_fifo_reset.785311366 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 13482965225 ps |
| CPU time | 40.43 seconds |
| Started | Oct 15 11:20:51 AM UTC 24 |
| Finished | Oct 15 11:21:32 AM UTC 24 |
| Peak memory | 208316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785311366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.785311366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/173.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/174.uart_fifo_reset.764588564 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 188797502663 ps |
| CPU time | 166.2 seconds |
| Started | Oct 15 11:20:52 AM UTC 24 |
| Finished | Oct 15 11:23:40 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764588564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.764588564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/174.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/175.uart_fifo_reset.1029166373 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 151429969339 ps |
| CPU time | 94.9 seconds |
| Started | Oct 15 11:20:54 AM UTC 24 |
| Finished | Oct 15 11:22:31 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029166373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1029166373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/175.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/176.uart_fifo_reset.1347949682 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 38917426166 ps |
| CPU time | 111.58 seconds |
| Started | Oct 15 11:21:00 AM UTC 24 |
| Finished | Oct 15 11:22:54 AM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347949682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1347949682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/176.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/177.uart_fifo_reset.1678262897 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 51119237078 ps |
| CPU time | 44.78 seconds |
| Started | Oct 15 11:21:00 AM UTC 24 |
| Finished | Oct 15 11:21:46 AM UTC 24 |
| Peak memory | 208576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678262897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1678262897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/177.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/178.uart_fifo_reset.2277446842 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 26595439589 ps |
| CPU time | 36.88 seconds |
| Started | Oct 15 11:21:03 AM UTC 24 |
| Finished | Oct 15 11:21:41 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277446842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2277446842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/178.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/179.uart_fifo_reset.3687142193 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 212194739355 ps |
| CPU time | 174.73 seconds |
| Started | Oct 15 11:21:04 AM UTC 24 |
| Finished | Oct 15 11:24:02 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687142193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3687142193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/179.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_alert_test.1977047636 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 34592977 ps |
| CPU time | 0.78 seconds |
| Started | Oct 15 10:55:51 AM UTC 24 |
| Finished | Oct 15 10:55:52 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977047636 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1977047636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_fifo_full.2488282409 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 28678765859 ps |
| CPU time | 75.02 seconds |
| Started | Oct 15 10:54:33 AM UTC 24 |
| Finished | Oct 15 10:55:50 AM UTC 24 |
| Peak memory | 208956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488282409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2488282409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.804634448 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 37375915771 ps |
| CPU time | 21.29 seconds |
| Started | Oct 15 10:54:51 AM UTC 24 |
| Finished | Oct 15 10:55:13 AM UTC 24 |
| Peak memory | 207228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804634448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.804634448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_fifo_reset.1979584719 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 181973986123 ps |
| CPU time | 193.06 seconds |
| Started | Oct 15 10:54:53 AM UTC 24 |
| Finished | Oct 15 10:58:09 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979584719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1979584719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_intr.3762809753 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 45027147553 ps |
| CPU time | 28.26 seconds |
| Started | Oct 15 10:55:11 AM UTC 24 |
| Finished | Oct 15 10:55:41 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762809753 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3762809753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.1840217260 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 52341534314 ps |
| CPU time | 331.19 seconds |
| Started | Oct 15 10:55:29 AM UTC 24 |
| Finished | Oct 15 11:01:06 AM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840217260 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1840217260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_loopback.1532969336 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 3892683097 ps |
| CPU time | 3.71 seconds |
| Started | Oct 15 10:55:24 AM UTC 24 |
| Finished | Oct 15 10:55:29 AM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532969336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1532969336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_noise_filter.720635510 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 66927155119 ps |
| CPU time | 178.89 seconds |
| Started | Oct 15 10:55:14 AM UTC 24 |
| Finished | Oct 15 10:58:16 AM UTC 24 |
| Peak memory | 208920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720635510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.720635510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_perf.1565390134 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 10749049674 ps |
| CPU time | 272.93 seconds |
| Started | Oct 15 10:55:27 AM UTC 24 |
| Finished | Oct 15 11:00:05 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565390134 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1565390134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_rx_oversample.1063961433 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2537573332 ps |
| CPU time | 19.89 seconds |
| Started | Oct 15 10:55:05 AM UTC 24 |
| Finished | Oct 15 10:55:26 AM UTC 24 |
| Peak memory | 207604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063961433 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1063961433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.2983011863 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 28395113635 ps |
| CPU time | 62.83 seconds |
| Started | Oct 15 10:55:20 AM UTC 24 |
| Finished | Oct 15 10:56:25 AM UTC 24 |
| Peak memory | 208408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983011863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2983011863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.1389398208 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 4093330803 ps |
| CPU time | 2.11 seconds |
| Started | Oct 15 10:55:16 AM UTC 24 |
| Finished | Oct 15 10:55:19 AM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389398208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1389398208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_smoke.69794327 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 674532753 ps |
| CPU time | 3.69 seconds |
| Started | Oct 15 10:54:27 AM UTC 24 |
| Finished | Oct 15 10:54:32 AM UTC 24 |
| Peak memory | 207420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69794327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 18.uart_smoke.69794327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.1749142803 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 11407083746 ps |
| CPU time | 67.88 seconds |
| Started | Oct 15 10:55:34 AM UTC 24 |
| Finished | Oct 15 10:56:44 AM UTC 24 |
| Peak memory | 219940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1749142803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all _with_rand_reset.1749142803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.1521467028 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 498637280 ps |
| CPU time | 2.18 seconds |
| Started | Oct 15 10:55:20 AM UTC 24 |
| Finished | Oct 15 10:55:23 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521467028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1521467028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/18.uart_tx_rx.615096691 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 115217580674 ps |
| CPU time | 89.59 seconds |
| Started | Oct 15 10:54:33 AM UTC 24 |
| Finished | Oct 15 10:56:05 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615096691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.615096691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/18.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/180.uart_fifo_reset.4005561712 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 72706493066 ps |
| CPU time | 175.9 seconds |
| Started | Oct 15 11:21:04 AM UTC 24 |
| Finished | Oct 15 11:24:03 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005561712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.4005561712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/180.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/181.uart_fifo_reset.1399941897 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 209916486193 ps |
| CPU time | 150.59 seconds |
| Started | Oct 15 11:21:05 AM UTC 24 |
| Finished | Oct 15 11:23:39 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399941897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1399941897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/181.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/182.uart_fifo_reset.3221399321 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 20147016177 ps |
| CPU time | 21.05 seconds |
| Started | Oct 15 11:21:05 AM UTC 24 |
| Finished | Oct 15 11:21:28 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221399321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3221399321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/182.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/183.uart_fifo_reset.2975727047 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 115397235967 ps |
| CPU time | 29.77 seconds |
| Started | Oct 15 11:21:11 AM UTC 24 |
| Finished | Oct 15 11:21:43 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975727047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2975727047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/183.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/184.uart_fifo_reset.1062163350 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 9177311448 ps |
| CPU time | 30.02 seconds |
| Started | Oct 15 11:21:12 AM UTC 24 |
| Finished | Oct 15 11:21:44 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062163350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1062163350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/184.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/186.uart_fifo_reset.154804903 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 94531112324 ps |
| CPU time | 68.17 seconds |
| Started | Oct 15 11:21:21 AM UTC 24 |
| Finished | Oct 15 11:22:31 AM UTC 24 |
| Peak memory | 208552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154804903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.154804903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/186.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/187.uart_fifo_reset.2439217617 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 78949354606 ps |
| CPU time | 146.16 seconds |
| Started | Oct 15 11:21:21 AM UTC 24 |
| Finished | Oct 15 11:23:50 AM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439217617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2439217617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/187.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/188.uart_fifo_reset.1499418751 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 63411291695 ps |
| CPU time | 168.64 seconds |
| Started | Oct 15 11:21:24 AM UTC 24 |
| Finished | Oct 15 11:24:15 AM UTC 24 |
| Peak memory | 208672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499418751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1499418751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/188.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/189.uart_fifo_reset.1325571210 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 177753960158 ps |
| CPU time | 362.02 seconds |
| Started | Oct 15 11:21:29 AM UTC 24 |
| Finished | Oct 15 11:27:36 AM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325571210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1325571210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/189.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_alert_test.522525573 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 25542106 ps |
| CPU time | 0.73 seconds |
| Started | Oct 15 10:57:44 AM UTC 24 |
| Finished | Oct 15 10:57:46 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522525573 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.522525573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.1443096782 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 48844604195 ps |
| CPU time | 27.33 seconds |
| Started | Oct 15 10:56:05 AM UTC 24 |
| Finished | Oct 15 10:56:34 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443096782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1443096782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_fifo_reset.2348679602 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 15411532586 ps |
| CPU time | 15.24 seconds |
| Started | Oct 15 10:56:19 AM UTC 24 |
| Finished | Oct 15 10:56:36 AM UTC 24 |
| Peak memory | 208324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348679602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2348679602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_intr.286935957 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 19509245774 ps |
| CPU time | 25.55 seconds |
| Started | Oct 15 10:56:34 AM UTC 24 |
| Finished | Oct 15 10:57:01 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286935957 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.286935957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.2948027201 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 133872542457 ps |
| CPU time | 359.84 seconds |
| Started | Oct 15 10:56:58 AM UTC 24 |
| Finished | Oct 15 11:03:03 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948027201 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2948027201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_loopback.2393549959 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 3384912799 ps |
| CPU time | 6.68 seconds |
| Started | Oct 15 10:56:50 AM UTC 24 |
| Finished | Oct 15 10:56:57 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393549959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2393549959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_noise_filter.1905020160 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 152913808685 ps |
| CPU time | 283.26 seconds |
| Started | Oct 15 10:56:36 AM UTC 24 |
| Finished | Oct 15 11:01:24 AM UTC 24 |
| Peak memory | 210456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905020160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1905020160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_perf.211232944 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 16164307398 ps |
| CPU time | 583.8 seconds |
| Started | Oct 15 10:56:51 AM UTC 24 |
| Finished | Oct 15 11:06:43 AM UTC 24 |
| Peak memory | 212244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211232944 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.211232944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_rx_oversample.669676613 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 4325521221 ps |
| CPU time | 10.22 seconds |
| Started | Oct 15 10:56:26 AM UTC 24 |
| Finished | Oct 15 10:56:38 AM UTC 24 |
| Peak memory | 207408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669676613 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.669676613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.4000546747 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 131698257973 ps |
| CPU time | 181.4 seconds |
| Started | Oct 15 10:56:38 AM UTC 24 |
| Finished | Oct 15 10:59:43 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000546747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.4000546747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.3240052943 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 3947908279 ps |
| CPU time | 10.97 seconds |
| Started | Oct 15 10:56:37 AM UTC 24 |
| Finished | Oct 15 10:56:50 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240052943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3240052943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_smoke.4211883841 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 5885039652 ps |
| CPU time | 25.5 seconds |
| Started | Oct 15 10:55:52 AM UTC 24 |
| Finished | Oct 15 10:56:19 AM UTC 24 |
| Peak memory | 208240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211883841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.uart_smoke.4211883841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.2842606522 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 19660437982 ps |
| CPU time | 100.93 seconds |
| Started | Oct 15 10:57:02 AM UTC 24 |
| Finished | Oct 15 10:58:45 AM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2842606522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all _with_rand_reset.2842606522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.2212039828 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 2628587239 ps |
| CPU time | 3.28 seconds |
| Started | Oct 15 10:56:44 AM UTC 24 |
| Finished | Oct 15 10:56:49 AM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212039828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2212039828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_tx_rx.1920287471 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 38287243596 ps |
| CPU time | 42.32 seconds |
| Started | Oct 15 10:55:53 AM UTC 24 |
| Finished | Oct 15 10:56:37 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920287471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1920287471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/19.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/190.uart_fifo_reset.788680145 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 231992007674 ps |
| CPU time | 48.4 seconds |
| Started | Oct 15 11:21:29 AM UTC 24 |
| Finished | Oct 15 11:22:19 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788680145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.788680145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/190.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/191.uart_fifo_reset.2906775050 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 97091656396 ps |
| CPU time | 96.12 seconds |
| Started | Oct 15 11:21:33 AM UTC 24 |
| Finished | Oct 15 11:23:11 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906775050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2906775050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/191.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/192.uart_fifo_reset.408580368 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 24788661597 ps |
| CPU time | 28.43 seconds |
| Started | Oct 15 11:21:35 AM UTC 24 |
| Finished | Oct 15 11:22:05 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408580368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.408580368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/192.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/193.uart_fifo_reset.848085893 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 105663290787 ps |
| CPU time | 44.38 seconds |
| Started | Oct 15 11:21:38 AM UTC 24 |
| Finished | Oct 15 11:22:24 AM UTC 24 |
| Peak memory | 208608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848085893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.848085893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/193.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/194.uart_fifo_reset.2239624632 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 34652972304 ps |
| CPU time | 17.43 seconds |
| Started | Oct 15 11:21:39 AM UTC 24 |
| Finished | Oct 15 11:21:58 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239624632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2239624632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/194.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/195.uart_fifo_reset.2106190720 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 69155435003 ps |
| CPU time | 56.89 seconds |
| Started | Oct 15 11:21:40 AM UTC 24 |
| Finished | Oct 15 11:22:39 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106190720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2106190720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/195.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/196.uart_fifo_reset.3826955204 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 89429762799 ps |
| CPU time | 170.14 seconds |
| Started | Oct 15 11:21:41 AM UTC 24 |
| Finished | Oct 15 11:24:34 AM UTC 24 |
| Peak memory | 208628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826955204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3826955204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/196.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/197.uart_fifo_reset.1381064816 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 71149514337 ps |
| CPU time | 40.24 seconds |
| Started | Oct 15 11:21:42 AM UTC 24 |
| Finished | Oct 15 11:22:24 AM UTC 24 |
| Peak memory | 208740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381064816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1381064816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/197.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/198.uart_fifo_reset.952977332 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 16203720184 ps |
| CPU time | 53.8 seconds |
| Started | Oct 15 11:21:44 AM UTC 24 |
| Finished | Oct 15 11:22:39 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952977332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.952977332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/198.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/199.uart_fifo_reset.253760653 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 114685340430 ps |
| CPU time | 268.82 seconds |
| Started | Oct 15 11:21:44 AM UTC 24 |
| Finished | Oct 15 11:26:16 AM UTC 24 |
| Peak memory | 208492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253760653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.253760653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/199.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_alert_test.3683576567 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 17465715 ps |
| CPU time | 0.71 seconds |
| Started | Oct 15 10:30:08 AM UTC 24 |
| Finished | Oct 15 10:30:09 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683576567 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3683576567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_fifo_full.3772560090 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 35277310638 ps |
| CPU time | 105.63 seconds |
| Started | Oct 15 10:29:16 AM UTC 24 |
| Finished | Oct 15 10:31:04 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772560090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3772560090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_fifo_reset.603059625 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30958471946 ps |
| CPU time | 15.86 seconds |
| Started | Oct 15 10:29:18 AM UTC 24 |
| Finished | Oct 15 10:29:35 AM UTC 24 |
| Peak memory | 208880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603059625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.603059625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_intr.2693683941 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 56415706870 ps |
| CPU time | 38.64 seconds |
| Started | Oct 15 10:29:27 AM UTC 24 |
| Finished | Oct 15 10:30:07 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693683941 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2693683941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.486759687 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 237833049831 ps |
| CPU time | 485.52 seconds |
| Started | Oct 15 10:29:57 AM UTC 24 |
| Finished | Oct 15 10:38:09 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486759687 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.486759687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_loopback.1655166230 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3212363684 ps |
| CPU time | 8.12 seconds |
| Started | Oct 15 10:29:56 AM UTC 24 |
| Finished | Oct 15 10:30:06 AM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655166230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1655166230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_noise_filter.3032787241 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 78067688496 ps |
| CPU time | 43.34 seconds |
| Started | Oct 15 10:29:31 AM UTC 24 |
| Finished | Oct 15 10:30:16 AM UTC 24 |
| Peak memory | 207592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032787241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3032787241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_perf.3672046015 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 9340827108 ps |
| CPU time | 366.03 seconds |
| Started | Oct 15 10:29:56 AM UTC 24 |
| Finished | Oct 15 10:36:08 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672046015 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3672046015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_rx_oversample.2873120103 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6800269596 ps |
| CPU time | 33.17 seconds |
| Started | Oct 15 10:29:21 AM UTC 24 |
| Finished | Oct 15 10:29:56 AM UTC 24 |
| Peak memory | 207312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873120103 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2873120103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.1107148172 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 28037584518 ps |
| CPU time | 55.29 seconds |
| Started | Oct 15 10:29:47 AM UTC 24 |
| Finished | Oct 15 10:30:44 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107148172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1107148172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.3025819600 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 5463462120 ps |
| CPU time | 11.71 seconds |
| Started | Oct 15 10:29:36 AM UTC 24 |
| Finished | Oct 15 10:29:49 AM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025819600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3025819600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_sec_cm.3053888382 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 71144548 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 10:30:08 AM UTC 24 |
| Finished | Oct 15 10:30:10 AM UTC 24 |
| Peak memory | 240120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053888382 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3053888382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_smoke.760914527 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 721379750 ps |
| CPU time | 2.4 seconds |
| Started | Oct 15 10:29:13 AM UTC 24 |
| Finished | Oct 15 10:29:17 AM UTC 24 |
| Peak memory | 208504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760914527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.uart_smoke.760914527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.473116848 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1397026370 ps |
| CPU time | 3.93 seconds |
| Started | Oct 15 10:29:50 AM UTC 24 |
| Finished | Oct 15 10:29:55 AM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473116848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.473116848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/2.uart_tx_rx.12904005 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 85925389357 ps |
| CPU time | 48.18 seconds |
| Started | Oct 15 10:29:15 AM UTC 24 |
| Finished | Oct 15 10:30:05 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12904005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.12904005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_alert_test.3731014967 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 16244280 ps |
| CPU time | 0.74 seconds |
| Started | Oct 15 10:58:58 AM UTC 24 |
| Finished | Oct 15 10:59:00 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731014967 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3731014967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_fifo_full.2411314130 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 62507474789 ps |
| CPU time | 156.3 seconds |
| Started | Oct 15 10:58:10 AM UTC 24 |
| Finished | Oct 15 11:00:50 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411314130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2411314130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.1383998797 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 17385631649 ps |
| CPU time | 34.02 seconds |
| Started | Oct 15 10:58:14 AM UTC 24 |
| Finished | Oct 15 10:58:50 AM UTC 24 |
| Peak memory | 208392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383998797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1383998797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_fifo_reset.1417728093 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 70998203347 ps |
| CPU time | 39.95 seconds |
| Started | Oct 15 10:58:16 AM UTC 24 |
| Finished | Oct 15 10:58:58 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417728093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1417728093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_intr.3229614687 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 11890810451 ps |
| CPU time | 3.9 seconds |
| Started | Oct 15 10:58:21 AM UTC 24 |
| Finished | Oct 15 10:58:26 AM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229614687 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3229614687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.1448617786 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 90331267584 ps |
| CPU time | 789.18 seconds |
| Started | Oct 15 10:58:49 AM UTC 24 |
| Finished | Oct 15 11:12:09 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448617786 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1448617786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_loopback.2807341239 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 6126313535 ps |
| CPU time | 13.82 seconds |
| Started | Oct 15 10:58:43 AM UTC 24 |
| Finished | Oct 15 10:58:58 AM UTC 24 |
| Peak memory | 207228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807341239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2807341239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_noise_filter.3884219857 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 44699301039 ps |
| CPU time | 61.39 seconds |
| Started | Oct 15 10:58:26 AM UTC 24 |
| Finished | Oct 15 10:59:29 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884219857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3884219857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_perf.3264920778 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 6669640181 ps |
| CPU time | 71.2 seconds |
| Started | Oct 15 10:58:46 AM UTC 24 |
| Finished | Oct 15 10:59:59 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264920778 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3264920778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_rx_oversample.1825458751 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 4719890203 ps |
| CPU time | 22.98 seconds |
| Started | Oct 15 10:58:17 AM UTC 24 |
| Finished | Oct 15 10:58:42 AM UTC 24 |
| Peak memory | 207368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825458751 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1825458751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.684078213 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 199406106708 ps |
| CPU time | 206.07 seconds |
| Started | Oct 15 10:58:32 AM UTC 24 |
| Finished | Oct 15 11:02:02 AM UTC 24 |
| Peak memory | 208660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684078213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.684078213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.727971430 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1619992878 ps |
| CPU time | 4.91 seconds |
| Started | Oct 15 10:58:27 AM UTC 24 |
| Finished | Oct 15 10:58:33 AM UTC 24 |
| Peak memory | 205056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727971430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.727971430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_smoke.1498968815 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 514447892 ps |
| CPU time | 1.72 seconds |
| Started | Oct 15 10:57:47 AM UTC 24 |
| Finished | Oct 15 10:57:50 AM UTC 24 |
| Peak memory | 206680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498968815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1498968815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.2155489191 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 46885968049 ps |
| CPU time | 64.36 seconds |
| Started | Oct 15 10:58:51 AM UTC 24 |
| Finished | Oct 15 10:59:57 AM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2155489191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all _with_rand_reset.2155489191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.2508991561 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 7972537859 ps |
| CPU time | 19.59 seconds |
| Started | Oct 15 10:58:34 AM UTC 24 |
| Finished | Oct 15 10:58:55 AM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508991561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2508991561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_tx_rx.2291114928 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 30587340524 ps |
| CPU time | 39.31 seconds |
| Started | Oct 15 10:57:50 AM UTC 24 |
| Finished | Oct 15 10:58:31 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291114928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2291114928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/20.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/200.uart_fifo_reset.3344117487 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 149547190338 ps |
| CPU time | 16.54 seconds |
| Started | Oct 15 11:21:44 AM UTC 24 |
| Finished | Oct 15 11:22:01 AM UTC 24 |
| Peak memory | 208216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344117487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3344117487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/200.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/201.uart_fifo_reset.2116352972 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 81941649348 ps |
| CPU time | 177.47 seconds |
| Started | Oct 15 11:21:44 AM UTC 24 |
| Finished | Oct 15 11:24:44 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116352972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2116352972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/201.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3688666920 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 107076110779 ps |
| CPU time | 64.18 seconds |
| Started | Oct 15 11:21:45 AM UTC 24 |
| Finished | Oct 15 11:22:51 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688666920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3688666920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/202.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/203.uart_fifo_reset.993918189 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 17422114220 ps |
| CPU time | 21.09 seconds |
| Started | Oct 15 11:21:45 AM UTC 24 |
| Finished | Oct 15 11:22:07 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993918189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.993918189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/203.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2791111068 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 17984105102 ps |
| CPU time | 30.66 seconds |
| Started | Oct 15 11:21:47 AM UTC 24 |
| Finished | Oct 15 11:22:19 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791111068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2791111068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/204.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/205.uart_fifo_reset.2237194891 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 38745326151 ps |
| CPU time | 20.39 seconds |
| Started | Oct 15 11:21:50 AM UTC 24 |
| Finished | Oct 15 11:22:12 AM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237194891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2237194891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/205.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2481379867 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 12990167427 ps |
| CPU time | 30.41 seconds |
| Started | Oct 15 11:21:51 AM UTC 24 |
| Finished | Oct 15 11:22:23 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481379867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2481379867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/206.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2329276726 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 26340628118 ps |
| CPU time | 51.35 seconds |
| Started | Oct 15 11:21:51 AM UTC 24 |
| Finished | Oct 15 11:22:44 AM UTC 24 |
| Peak memory | 208632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329276726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2329276726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/207.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/208.uart_fifo_reset.1552559449 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 215778471063 ps |
| CPU time | 157.76 seconds |
| Started | Oct 15 11:21:59 AM UTC 24 |
| Finished | Oct 15 11:24:39 AM UTC 24 |
| Peak memory | 208676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552559449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1552559449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/208.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/209.uart_fifo_reset.3439371379 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 76893639022 ps |
| CPU time | 59.57 seconds |
| Started | Oct 15 11:22:02 AM UTC 24 |
| Finished | Oct 15 11:23:03 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439371379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3439371379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/209.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_alert_test.593235340 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 14378693 ps |
| CPU time | 0.7 seconds |
| Started | Oct 15 11:00:45 AM UTC 24 |
| Finished | Oct 15 11:00:47 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593235340 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.593235340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_fifo_full.406990483 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 142660839207 ps |
| CPU time | 293.81 seconds |
| Started | Oct 15 10:59:02 AM UTC 24 |
| Finished | Oct 15 11:04:01 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406990483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.406990483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.2940242382 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 43957657756 ps |
| CPU time | 100.72 seconds |
| Started | Oct 15 10:59:03 AM UTC 24 |
| Finished | Oct 15 11:00:46 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940242382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2940242382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_fifo_reset.868886045 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 79207140469 ps |
| CPU time | 229.57 seconds |
| Started | Oct 15 10:59:06 AM UTC 24 |
| Finished | Oct 15 11:02:59 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868886045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.868886045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_intr.4005740443 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 145605974253 ps |
| CPU time | 192.4 seconds |
| Started | Oct 15 10:59:44 AM UTC 24 |
| Finished | Oct 15 11:03:00 AM UTC 24 |
| Peak memory | 208520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005740443 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.4005740443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.1361190319 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 280711846511 ps |
| CPU time | 308.91 seconds |
| Started | Oct 15 11:00:15 AM UTC 24 |
| Finished | Oct 15 11:05:29 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361190319 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1361190319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_loopback.2010086971 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 3652340763 ps |
| CPU time | 7.24 seconds |
| Started | Oct 15 11:00:06 AM UTC 24 |
| Finished | Oct 15 11:00:14 AM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010086971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2010086971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_noise_filter.1152890616 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 249468914384 ps |
| CPU time | 80.05 seconds |
| Started | Oct 15 10:59:45 AM UTC 24 |
| Finished | Oct 15 11:01:07 AM UTC 24 |
| Peak memory | 208864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152890616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1152890616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_perf.2553398657 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 11769005948 ps |
| CPU time | 444.97 seconds |
| Started | Oct 15 11:00:08 AM UTC 24 |
| Finished | Oct 15 11:07:39 AM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553398657 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2553398657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_rx_oversample.2786287629 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 4888827631 ps |
| CPU time | 13.1 seconds |
| Started | Oct 15 10:59:30 AM UTC 24 |
| Finished | Oct 15 10:59:44 AM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786287629 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2786287629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.704610575 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 61854079469 ps |
| CPU time | 36.19 seconds |
| Started | Oct 15 11:00:00 AM UTC 24 |
| Finished | Oct 15 11:00:38 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704610575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.704610575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.528559327 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 2295830682 ps |
| CPU time | 2.03 seconds |
| Started | Oct 15 10:59:58 AM UTC 24 |
| Finished | Oct 15 11:00:01 AM UTC 24 |
| Peak memory | 205104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528559327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.528559327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_smoke.2162354263 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 627088973 ps |
| CPU time | 2.02 seconds |
| Started | Oct 15 10:58:59 AM UTC 24 |
| Finished | Oct 15 10:59:02 AM UTC 24 |
| Peak memory | 208880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162354263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2162354263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_stress_all.1101542857 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 19330513971 ps |
| CPU time | 5.61 seconds |
| Started | Oct 15 11:00:38 AM UTC 24 |
| Finished | Oct 15 11:00:45 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101542857 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1101542857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.3241560697 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 11088528591 ps |
| CPU time | 61.37 seconds |
| Started | Oct 15 11:00:23 AM UTC 24 |
| Finished | Oct 15 11:01:27 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3241560697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all _with_rand_reset.3241560697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.3052536026 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 986041074 ps |
| CPU time | 1.83 seconds |
| Started | Oct 15 11:00:02 AM UTC 24 |
| Finished | Oct 15 11:00:08 AM UTC 24 |
| Peak memory | 206936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052536026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3052536026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_tx_rx.475183908 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1987765148 ps |
| CPU time | 2.03 seconds |
| Started | Oct 15 10:59:01 AM UTC 24 |
| Finished | Oct 15 10:59:04 AM UTC 24 |
| Peak memory | 207220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475183908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.475183908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/21.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/210.uart_fifo_reset.3685260327 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 87646976998 ps |
| CPU time | 26.07 seconds |
| Started | Oct 15 11:22:05 AM UTC 24 |
| Finished | Oct 15 11:22:33 AM UTC 24 |
| Peak memory | 207356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685260327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3685260327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/210.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/211.uart_fifo_reset.3343396357 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 71521452791 ps |
| CPU time | 66.24 seconds |
| Started | Oct 15 11:22:05 AM UTC 24 |
| Finished | Oct 15 11:23:13 AM UTC 24 |
| Peak memory | 208912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343396357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3343396357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/211.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/212.uart_fifo_reset.1539634296 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 98963516200 ps |
| CPU time | 130.64 seconds |
| Started | Oct 15 11:22:07 AM UTC 24 |
| Finished | Oct 15 11:24:19 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539634296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1539634296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/212.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/213.uart_fifo_reset.413417113 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 19474679861 ps |
| CPU time | 42.97 seconds |
| Started | Oct 15 11:22:07 AM UTC 24 |
| Finished | Oct 15 11:22:51 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413417113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.413417113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/213.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/214.uart_fifo_reset.2713166225 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 102963644141 ps |
| CPU time | 53.1 seconds |
| Started | Oct 15 11:22:08 AM UTC 24 |
| Finished | Oct 15 11:23:02 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713166225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2713166225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/214.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/216.uart_fifo_reset.2359368129 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 60600022087 ps |
| CPU time | 135.17 seconds |
| Started | Oct 15 11:22:09 AM UTC 24 |
| Finished | Oct 15 11:24:26 AM UTC 24 |
| Peak memory | 208496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359368129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2359368129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/216.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/217.uart_fifo_reset.2255098002 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 25050222924 ps |
| CPU time | 38.31 seconds |
| Started | Oct 15 11:22:12 AM UTC 24 |
| Finished | Oct 15 11:22:52 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255098002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2255098002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/217.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/219.uart_fifo_reset.1554503850 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 122465764498 ps |
| CPU time | 113.95 seconds |
| Started | Oct 15 11:22:18 AM UTC 24 |
| Finished | Oct 15 11:24:14 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554503850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1554503850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/219.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_alert_test.1173823404 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 16934507 ps |
| CPU time | 0.68 seconds |
| Started | Oct 15 11:01:34 AM UTC 24 |
| Finished | Oct 15 11:01:35 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173823404 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1173823404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_fifo_full.2601691772 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 58587364227 ps |
| CPU time | 38.99 seconds |
| Started | Oct 15 11:00:51 AM UTC 24 |
| Finished | Oct 15 11:01:31 AM UTC 24 |
| Peak memory | 208940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601691772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2601691772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.2566507547 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 196605368073 ps |
| CPU time | 148.07 seconds |
| Started | Oct 15 11:01:00 AM UTC 24 |
| Finished | Oct 15 11:03:31 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566507547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2566507547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_fifo_reset.535849114 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 34076835945 ps |
| CPU time | 23.47 seconds |
| Started | Oct 15 11:01:01 AM UTC 24 |
| Finished | Oct 15 11:01:26 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535849114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.535849114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_intr.1878263551 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 36542793200 ps |
| CPU time | 25.68 seconds |
| Started | Oct 15 11:01:06 AM UTC 24 |
| Finished | Oct 15 11:01:33 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878263551 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1878263551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.1345928412 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 113973328933 ps |
| CPU time | 840.21 seconds |
| Started | Oct 15 11:01:30 AM UTC 24 |
| Finished | Oct 15 11:15:42 AM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345928412 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1345928412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_loopback.663888502 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1851647537 ps |
| CPU time | 4.81 seconds |
| Started | Oct 15 11:01:26 AM UTC 24 |
| Finished | Oct 15 11:01:33 AM UTC 24 |
| Peak memory | 207088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663888502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 22.uart_loopback.663888502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_noise_filter.2628002779 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 61165198101 ps |
| CPU time | 57.78 seconds |
| Started | Oct 15 11:01:07 AM UTC 24 |
| Finished | Oct 15 11:02:07 AM UTC 24 |
| Peak memory | 208920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628002779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2628002779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_perf.78303422 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 9105915229 ps |
| CPU time | 164.46 seconds |
| Started | Oct 15 11:01:27 AM UTC 24 |
| Finished | Oct 15 11:04:16 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78303422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.78303422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_rx_oversample.4278357503 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 5263974470 ps |
| CPU time | 26.74 seconds |
| Started | Oct 15 11:01:05 AM UTC 24 |
| Finished | Oct 15 11:01:33 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278357503 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.4278357503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.3031683377 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 96514511325 ps |
| CPU time | 51.11 seconds |
| Started | Oct 15 11:01:23 AM UTC 24 |
| Finished | Oct 15 11:02:16 AM UTC 24 |
| Peak memory | 208684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031683377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3031683377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.532332255 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 5431855019 ps |
| CPU time | 12.91 seconds |
| Started | Oct 15 11:01:08 AM UTC 24 |
| Finished | Oct 15 11:01:22 AM UTC 24 |
| Peak memory | 207212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532332255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.532332255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_smoke.3672190429 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 5874611527 ps |
| CPU time | 11.12 seconds |
| Started | Oct 15 11:00:48 AM UTC 24 |
| Finished | Oct 15 11:01:00 AM UTC 24 |
| Peak memory | 208172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672190429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3672190429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_stress_all.2263684899 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 199139794632 ps |
| CPU time | 434.49 seconds |
| Started | Oct 15 11:01:34 AM UTC 24 |
| Finished | Oct 15 11:08:55 AM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263684899 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2263684899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.782134575 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 6883998722 ps |
| CPU time | 22.95 seconds |
| Started | Oct 15 11:01:31 AM UTC 24 |
| Finished | Oct 15 11:01:56 AM UTC 24 |
| Peak memory | 224112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=782134575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all_ with_rand_reset.782134575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.1148416575 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 829290583 ps |
| CPU time | 2.7 seconds |
| Started | Oct 15 11:01:25 AM UTC 24 |
| Finished | Oct 15 11:01:30 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148416575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1148416575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_tx_rx.692248885 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 75448563930 ps |
| CPU time | 215.22 seconds |
| Started | Oct 15 11:00:48 AM UTC 24 |
| Finished | Oct 15 11:04:26 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692248885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.692248885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/22.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/220.uart_fifo_reset.1500828076 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 27590906843 ps |
| CPU time | 25.57 seconds |
| Started | Oct 15 11:22:19 AM UTC 24 |
| Finished | Oct 15 11:22:46 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500828076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1500828076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/220.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/221.uart_fifo_reset.3468992393 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 68066726286 ps |
| CPU time | 144.4 seconds |
| Started | Oct 15 11:22:19 AM UTC 24 |
| Finished | Oct 15 11:24:46 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468992393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3468992393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/221.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/222.uart_fifo_reset.3298019224 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 219152417170 ps |
| CPU time | 166.02 seconds |
| Started | Oct 15 11:22:23 AM UTC 24 |
| Finished | Oct 15 11:25:12 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298019224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3298019224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/222.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/224.uart_fifo_reset.2973741276 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 123249040061 ps |
| CPU time | 114.85 seconds |
| Started | Oct 15 11:22:25 AM UTC 24 |
| Finished | Oct 15 11:24:22 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973741276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2973741276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/224.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/225.uart_fifo_reset.1996521414 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 56682124073 ps |
| CPU time | 117.68 seconds |
| Started | Oct 15 11:22:25 AM UTC 24 |
| Finished | Oct 15 11:24:24 AM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996521414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1996521414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/225.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/226.uart_fifo_reset.2720857247 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 237592903280 ps |
| CPU time | 40.07 seconds |
| Started | Oct 15 11:22:25 AM UTC 24 |
| Finished | Oct 15 11:23:06 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720857247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2720857247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/226.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/227.uart_fifo_reset.2694337312 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 124739401290 ps |
| CPU time | 75.55 seconds |
| Started | Oct 15 11:22:25 AM UTC 24 |
| Finished | Oct 15 11:23:42 AM UTC 24 |
| Peak memory | 208728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694337312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2694337312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/227.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/228.uart_fifo_reset.1147941108 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 33504008953 ps |
| CPU time | 65.32 seconds |
| Started | Oct 15 11:22:31 AM UTC 24 |
| Finished | Oct 15 11:23:38 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147941108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1147941108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/228.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_alert_test.4089125874 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 23648750 ps |
| CPU time | 0.69 seconds |
| Started | Oct 15 11:02:53 AM UTC 24 |
| Finished | Oct 15 11:02:55 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089125874 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.4089125874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_fifo_full.2350126040 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 86036043612 ps |
| CPU time | 17.87 seconds |
| Started | Oct 15 11:01:37 AM UTC 24 |
| Finished | Oct 15 11:01:56 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350126040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2350126040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.911106163 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 86125935043 ps |
| CPU time | 19.57 seconds |
| Started | Oct 15 11:01:57 AM UTC 24 |
| Finished | Oct 15 11:02:18 AM UTC 24 |
| Peak memory | 208232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911106163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.911106163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_intr.2812412791 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 32422833436 ps |
| CPU time | 73.22 seconds |
| Started | Oct 15 11:02:07 AM UTC 24 |
| Finished | Oct 15 11:03:22 AM UTC 24 |
| Peak memory | 208572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812412791 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2812412791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.3206937651 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 113358921606 ps |
| CPU time | 580.05 seconds |
| Started | Oct 15 11:02:31 AM UTC 24 |
| Finished | Oct 15 11:12:18 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206937651 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3206937651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_loopback.4092753990 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 8750270765 ps |
| CPU time | 6.49 seconds |
| Started | Oct 15 11:02:22 AM UTC 24 |
| Finished | Oct 15 11:02:30 AM UTC 24 |
| Peak memory | 208004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092753990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 23.uart_loopback.4092753990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_noise_filter.2501665869 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 17073051032 ps |
| CPU time | 33.55 seconds |
| Started | Oct 15 11:02:17 AM UTC 24 |
| Finished | Oct 15 11:02:52 AM UTC 24 |
| Peak memory | 207372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501665869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2501665869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_perf.3835688760 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 19651972545 ps |
| CPU time | 635.93 seconds |
| Started | Oct 15 11:02:25 AM UTC 24 |
| Finished | Oct 15 11:13:09 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835688760 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3835688760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_rx_oversample.2370620329 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 3603665953 ps |
| CPU time | 14.73 seconds |
| Started | Oct 15 11:02:02 AM UTC 24 |
| Finished | Oct 15 11:02:18 AM UTC 24 |
| Peak memory | 207368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370620329 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2370620329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.2846630021 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 18837441132 ps |
| CPU time | 12.13 seconds |
| Started | Oct 15 11:02:19 AM UTC 24 |
| Finished | Oct 15 11:02:33 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846630021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2846630021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.644168006 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 4513729697 ps |
| CPU time | 2 seconds |
| Started | Oct 15 11:02:18 AM UTC 24 |
| Finished | Oct 15 11:02:21 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644168006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.644168006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_smoke.4134618315 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 486267454 ps |
| CPU time | 1.54 seconds |
| Started | Oct 15 11:01:34 AM UTC 24 |
| Finished | Oct 15 11:01:36 AM UTC 24 |
| Peak memory | 206256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134618315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4134618315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_stress_all.1925936432 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 209777794771 ps |
| CPU time | 687.08 seconds |
| Started | Oct 15 11:02:37 AM UTC 24 |
| Finished | Oct 15 11:14:13 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925936432 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1925936432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.2255101451 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 506129653 ps |
| CPU time | 2.28 seconds |
| Started | Oct 15 11:02:20 AM UTC 24 |
| Finished | Oct 15 11:02:24 AM UTC 24 |
| Peak memory | 207404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255101451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2255101451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/23.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3744511235 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 150476144361 ps |
| CPU time | 71.97 seconds |
| Started | Oct 15 11:22:34 AM UTC 24 |
| Finished | Oct 15 11:23:48 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744511235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3744511235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/230.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/231.uart_fifo_reset.87046779 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 112656320801 ps |
| CPU time | 266.55 seconds |
| Started | Oct 15 11:22:35 AM UTC 24 |
| Finished | Oct 15 11:27:05 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87046779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.87046779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/231.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/234.uart_fifo_reset.31772048 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 102068689208 ps |
| CPU time | 70.93 seconds |
| Started | Oct 15 11:22:45 AM UTC 24 |
| Finished | Oct 15 11:23:58 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31772048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.31772048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/234.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/235.uart_fifo_reset.983098435 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 14667947911 ps |
| CPU time | 24.83 seconds |
| Started | Oct 15 11:22:47 AM UTC 24 |
| Finished | Oct 15 11:23:14 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983098435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.983098435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/235.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/236.uart_fifo_reset.2871590462 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 49960736086 ps |
| CPU time | 34.2 seconds |
| Started | Oct 15 11:22:51 AM UTC 24 |
| Finished | Oct 15 11:23:27 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871590462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2871590462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/236.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/237.uart_fifo_reset.3111225667 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 120649453164 ps |
| CPU time | 213.19 seconds |
| Started | Oct 15 11:22:52 AM UTC 24 |
| Finished | Oct 15 11:26:28 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111225667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3111225667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/237.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/238.uart_fifo_reset.728348325 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 90833298120 ps |
| CPU time | 107.71 seconds |
| Started | Oct 15 11:22:53 AM UTC 24 |
| Finished | Oct 15 11:24:42 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728348325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.728348325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/238.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_alert_test.961238204 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 13697629 ps |
| CPU time | 0.68 seconds |
| Started | Oct 15 11:04:05 AM UTC 24 |
| Finished | Oct 15 11:04:07 AM UTC 24 |
| Peak memory | 204388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961238204 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.961238204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_fifo_full.2428726461 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 162888451826 ps |
| CPU time | 103.42 seconds |
| Started | Oct 15 11:03:00 AM UTC 24 |
| Finished | Oct 15 11:04:46 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428726461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2428726461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.301121854 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 25566766376 ps |
| CPU time | 42.04 seconds |
| Started | Oct 15 11:03:04 AM UTC 24 |
| Finished | Oct 15 11:03:48 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301121854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.301121854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_fifo_reset.286272371 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 219238813892 ps |
| CPU time | 69.23 seconds |
| Started | Oct 15 11:03:11 AM UTC 24 |
| Finished | Oct 15 11:04:23 AM UTC 24 |
| Peak memory | 208656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286272371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.286272371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_intr.1281311253 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 21152052644 ps |
| CPU time | 13.48 seconds |
| Started | Oct 15 11:03:23 AM UTC 24 |
| Finished | Oct 15 11:03:38 AM UTC 24 |
| Peak memory | 208464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281311253 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1281311253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.750723515 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 79704237514 ps |
| CPU time | 680.03 seconds |
| Started | Oct 15 11:03:49 AM UTC 24 |
| Finished | Oct 15 11:15:17 AM UTC 24 |
| Peak memory | 211992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750723515 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.750723515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_loopback.630642016 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1116225358 ps |
| CPU time | 2.49 seconds |
| Started | Oct 15 11:03:44 AM UTC 24 |
| Finished | Oct 15 11:03:47 AM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630642016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 24.uart_loopback.630642016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_noise_filter.2218800976 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 52499834044 ps |
| CPU time | 119.41 seconds |
| Started | Oct 15 11:03:30 AM UTC 24 |
| Finished | Oct 15 11:05:32 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218800976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2218800976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_perf.2689664219 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 11649878517 ps |
| CPU time | 191.35 seconds |
| Started | Oct 15 11:03:48 AM UTC 24 |
| Finished | Oct 15 11:07:02 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689664219 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2689664219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_rx_oversample.2733674855 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 4252998183 ps |
| CPU time | 11.02 seconds |
| Started | Oct 15 11:03:17 AM UTC 24 |
| Finished | Oct 15 11:03:30 AM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733674855 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2733674855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.1401409644 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 32932840496 ps |
| CPU time | 74.44 seconds |
| Started | Oct 15 11:03:39 AM UTC 24 |
| Finished | Oct 15 11:04:55 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401409644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1401409644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.2534171784 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 4012527803 ps |
| CPU time | 4.84 seconds |
| Started | Oct 15 11:03:31 AM UTC 24 |
| Finished | Oct 15 11:03:37 AM UTC 24 |
| Peak memory | 205240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534171784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2534171784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_smoke.2032774291 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 5568710468 ps |
| CPU time | 20.23 seconds |
| Started | Oct 15 11:02:55 AM UTC 24 |
| Finished | Oct 15 11:03:16 AM UTC 24 |
| Peak memory | 207676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032774291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2032774291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_stress_all.762312123 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 182704488537 ps |
| CPU time | 376.02 seconds |
| Started | Oct 15 11:04:02 AM UTC 24 |
| Finished | Oct 15 11:10:23 AM UTC 24 |
| Peak memory | 208672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762312123 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.762312123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.2598565305 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 2705553297 ps |
| CPU time | 71.39 seconds |
| Started | Oct 15 11:03:56 AM UTC 24 |
| Finished | Oct 15 11:05:09 AM UTC 24 |
| Peak memory | 217848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2598565305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all _with_rand_reset.2598565305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.2073312640 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 6987947391 ps |
| CPU time | 23.75 seconds |
| Started | Oct 15 11:03:40 AM UTC 24 |
| Finished | Oct 15 11:04:05 AM UTC 24 |
| Peak memory | 208336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073312640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2073312640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_tx_rx.3339750894 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 44687817327 ps |
| CPU time | 80.53 seconds |
| Started | Oct 15 11:03:00 AM UTC 24 |
| Finished | Oct 15 11:04:23 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339750894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3339750894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/24.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/240.uart_fifo_reset.2221480193 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 20736802486 ps |
| CPU time | 69.53 seconds |
| Started | Oct 15 11:22:55 AM UTC 24 |
| Finished | Oct 15 11:24:06 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221480193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2221480193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/240.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/241.uart_fifo_reset.940687850 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 296987159944 ps |
| CPU time | 135.25 seconds |
| Started | Oct 15 11:22:56 AM UTC 24 |
| Finished | Oct 15 11:25:13 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940687850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.940687850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/241.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/242.uart_fifo_reset.1997045213 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 420126763409 ps |
| CPU time | 49.03 seconds |
| Started | Oct 15 11:23:03 AM UTC 24 |
| Finished | Oct 15 11:23:54 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997045213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1997045213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/242.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/244.uart_fifo_reset.2533116868 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 63412492649 ps |
| CPU time | 28.09 seconds |
| Started | Oct 15 11:23:07 AM UTC 24 |
| Finished | Oct 15 11:23:36 AM UTC 24 |
| Peak memory | 208880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533116868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2533116868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/244.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/246.uart_fifo_reset.2692226339 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 55878435343 ps |
| CPU time | 35.24 seconds |
| Started | Oct 15 11:23:14 AM UTC 24 |
| Finished | Oct 15 11:23:51 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692226339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2692226339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/246.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/247.uart_fifo_reset.1377549621 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 23104313571 ps |
| CPU time | 43.36 seconds |
| Started | Oct 15 11:23:14 AM UTC 24 |
| Finished | Oct 15 11:23:59 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377549621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1377549621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/247.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/248.uart_fifo_reset.2252376506 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 105200901652 ps |
| CPU time | 29.07 seconds |
| Started | Oct 15 11:23:15 AM UTC 24 |
| Finished | Oct 15 11:23:46 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252376506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2252376506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/248.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/249.uart_fifo_reset.447457046 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 33180982653 ps |
| CPU time | 28.6 seconds |
| Started | Oct 15 11:23:19 AM UTC 24 |
| Finished | Oct 15 11:23:49 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447457046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.447457046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/249.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_alert_test.2773193018 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 34693384 ps |
| CPU time | 0.68 seconds |
| Started | Oct 15 11:04:54 AM UTC 24 |
| Finished | Oct 15 11:04:56 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773193018 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2773193018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_fifo_full.2280117040 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 47591918168 ps |
| CPU time | 23.64 seconds |
| Started | Oct 15 11:04:23 AM UTC 24 |
| Finished | Oct 15 11:04:48 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280117040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2280117040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.2473945769 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 100008883710 ps |
| CPU time | 33 seconds |
| Started | Oct 15 11:04:23 AM UTC 24 |
| Finished | Oct 15 11:04:58 AM UTC 24 |
| Peak memory | 208456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473945769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2473945769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_fifo_reset.1714722147 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 57683016950 ps |
| CPU time | 111.73 seconds |
| Started | Oct 15 11:04:27 AM UTC 24 |
| Finished | Oct 15 11:06:22 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714722147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1714722147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_intr.547738213 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 26185259311 ps |
| CPU time | 17.97 seconds |
| Started | Oct 15 11:04:44 AM UTC 24 |
| Finished | Oct 15 11:05:04 AM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547738213 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.547738213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.154524563 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 134985481858 ps |
| CPU time | 989.35 seconds |
| Started | Oct 15 11:04:53 AM UTC 24 |
| Finished | Oct 15 11:21:34 AM UTC 24 |
| Peak memory | 212244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154524563 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.154524563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_loopback.1170762311 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 7795867551 ps |
| CPU time | 7.09 seconds |
| Started | Oct 15 11:04:51 AM UTC 24 |
| Finished | Oct 15 11:04:59 AM UTC 24 |
| Peak memory | 208452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170762311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1170762311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_noise_filter.3633165531 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 97370539694 ps |
| CPU time | 235.77 seconds |
| Started | Oct 15 11:04:47 AM UTC 24 |
| Finished | Oct 15 11:08:46 AM UTC 24 |
| Peak memory | 208864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633165531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3633165531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_perf.2572804406 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 9706793053 ps |
| CPU time | 193.9 seconds |
| Started | Oct 15 11:04:51 AM UTC 24 |
| Finished | Oct 15 11:08:08 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572804406 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2572804406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_rx_oversample.1976728045 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 4725695066 ps |
| CPU time | 32.97 seconds |
| Started | Oct 15 11:04:42 AM UTC 24 |
| Finished | Oct 15 11:05:17 AM UTC 24 |
| Peak memory | 207472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976728045 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1976728045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.401542324 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 31143621659 ps |
| CPU time | 37.11 seconds |
| Started | Oct 15 11:04:50 AM UTC 24 |
| Finished | Oct 15 11:05:29 AM UTC 24 |
| Peak memory | 208532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401542324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.401542324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.1269957698 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5256666150 ps |
| CPU time | 4.62 seconds |
| Started | Oct 15 11:04:47 AM UTC 24 |
| Finished | Oct 15 11:04:53 AM UTC 24 |
| Peak memory | 205104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269957698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1269957698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_smoke.2347755264 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 6048651818 ps |
| CPU time | 33.13 seconds |
| Started | Oct 15 11:04:07 AM UTC 24 |
| Finished | Oct 15 11:04:42 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347755264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2347755264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_stress_all.1010294662 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 49296974246 ps |
| CPU time | 149.04 seconds |
| Started | Oct 15 11:04:54 AM UTC 24 |
| Finished | Oct 15 11:07:26 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010294662 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1010294662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.3964791820 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 28095675109 ps |
| CPU time | 59.64 seconds |
| Started | Oct 15 11:04:54 AM UTC 24 |
| Finished | Oct 15 11:05:56 AM UTC 24 |
| Peak memory | 225388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3964791820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all _with_rand_reset.3964791820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.3504018171 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 14301128680 ps |
| CPU time | 22.78 seconds |
| Started | Oct 15 11:04:50 AM UTC 24 |
| Finished | Oct 15 11:05:14 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504018171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3504018171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_tx_rx.2072868105 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 196441417017 ps |
| CPU time | 107.31 seconds |
| Started | Oct 15 11:04:16 AM UTC 24 |
| Finished | Oct 15 11:06:06 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072868105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2072868105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/25.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/251.uart_fifo_reset.2414796088 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 23080616487 ps |
| CPU time | 12.08 seconds |
| Started | Oct 15 11:23:23 AM UTC 24 |
| Finished | Oct 15 11:23:36 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414796088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2414796088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/251.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/252.uart_fifo_reset.2737918080 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 15931718627 ps |
| CPU time | 23.74 seconds |
| Started | Oct 15 11:23:28 AM UTC 24 |
| Finished | Oct 15 11:23:53 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737918080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2737918080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/252.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/253.uart_fifo_reset.2960147908 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 63903693407 ps |
| CPU time | 57.3 seconds |
| Started | Oct 15 11:23:34 AM UTC 24 |
| Finished | Oct 15 11:24:33 AM UTC 24 |
| Peak memory | 208676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960147908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2960147908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/253.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/254.uart_fifo_reset.1331875095 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 46114536220 ps |
| CPU time | 83.42 seconds |
| Started | Oct 15 11:23:36 AM UTC 24 |
| Finished | Oct 15 11:25:01 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331875095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1331875095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/254.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/255.uart_fifo_reset.1503247382 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 25731453991 ps |
| CPU time | 56.93 seconds |
| Started | Oct 15 11:23:37 AM UTC 24 |
| Finished | Oct 15 11:24:36 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503247382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1503247382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/255.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/256.uart_fifo_reset.1658024683 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 50076544659 ps |
| CPU time | 76.36 seconds |
| Started | Oct 15 11:23:37 AM UTC 24 |
| Finished | Oct 15 11:24:55 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658024683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1658024683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/256.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/257.uart_fifo_reset.3236673412 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 12874211398 ps |
| CPU time | 12.13 seconds |
| Started | Oct 15 11:23:37 AM UTC 24 |
| Finished | Oct 15 11:23:50 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236673412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3236673412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/257.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/258.uart_fifo_reset.2911882208 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 14718068453 ps |
| CPU time | 33.62 seconds |
| Started | Oct 15 11:23:38 AM UTC 24 |
| Finished | Oct 15 11:24:13 AM UTC 24 |
| Peak memory | 207808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911882208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2911882208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/258.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/259.uart_fifo_reset.4242642271 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 15934567657 ps |
| CPU time | 25.87 seconds |
| Started | Oct 15 11:23:39 AM UTC 24 |
| Finished | Oct 15 11:24:06 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242642271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.4242642271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/259.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_alert_test.185420446 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 17259020 ps |
| CPU time | 0.67 seconds |
| Started | Oct 15 11:05:07 AM UTC 24 |
| Finished | Oct 15 11:05:08 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185420446 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.185420446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_fifo_full.79242648 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 74634984215 ps |
| CPU time | 38.02 seconds |
| Started | Oct 15 11:04:55 AM UTC 24 |
| Finished | Oct 15 11:05:35 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79242648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.79242648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.3486388578 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 15930640661 ps |
| CPU time | 47.52 seconds |
| Started | Oct 15 11:04:56 AM UTC 24 |
| Finished | Oct 15 11:05:46 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486388578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3486388578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_fifo_reset.3439972987 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 67892325612 ps |
| CPU time | 40.59 seconds |
| Started | Oct 15 11:04:58 AM UTC 24 |
| Finished | Oct 15 11:05:40 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439972987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3439972987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_intr.352212944 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 217448221620 ps |
| CPU time | 159.22 seconds |
| Started | Oct 15 11:05:00 AM UTC 24 |
| Finished | Oct 15 11:07:42 AM UTC 24 |
| Peak memory | 207472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352212944 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.352212944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.1500209675 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 115976729666 ps |
| CPU time | 1209.99 seconds |
| Started | Oct 15 11:05:04 AM UTC 24 |
| Finished | Oct 15 11:25:29 AM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500209675 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1500209675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_loopback.3684943372 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 7550310348 ps |
| CPU time | 4.92 seconds |
| Started | Oct 15 11:05:03 AM UTC 24 |
| Finished | Oct 15 11:05:09 AM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684943372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3684943372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_noise_filter.3891945880 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 216360944898 ps |
| CPU time | 171 seconds |
| Started | Oct 15 11:05:00 AM UTC 24 |
| Finished | Oct 15 11:07:54 AM UTC 24 |
| Peak memory | 217792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891945880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3891945880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_perf.63112762 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 13782048931 ps |
| CPU time | 122.19 seconds |
| Started | Oct 15 11:05:04 AM UTC 24 |
| Finished | Oct 15 11:07:09 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63112762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.63112762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_rx_oversample.3569332544 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 6665361784 ps |
| CPU time | 32.33 seconds |
| Started | Oct 15 11:04:59 AM UTC 24 |
| Finished | Oct 15 11:05:32 AM UTC 24 |
| Peak memory | 208324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569332544 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3569332544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.298113651 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 118178693086 ps |
| CPU time | 372.89 seconds |
| Started | Oct 15 11:05:02 AM UTC 24 |
| Finished | Oct 15 11:11:20 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298113651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.298113651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.1586961577 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 4322051226 ps |
| CPU time | 4.22 seconds |
| Started | Oct 15 11:05:01 AM UTC 24 |
| Finished | Oct 15 11:05:06 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586961577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1586961577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_smoke.2011184041 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 5800775836 ps |
| CPU time | 14.01 seconds |
| Started | Oct 15 11:04:54 AM UTC 24 |
| Finished | Oct 15 11:05:09 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011184041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2011184041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_stress_all.3358641298 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 115841133752 ps |
| CPU time | 58.06 seconds |
| Started | Oct 15 11:05:06 AM UTC 24 |
| Finished | Oct 15 11:06:06 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358641298 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3358641298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.2876669249 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 2590179664 ps |
| CPU time | 2.62 seconds |
| Started | Oct 15 11:05:02 AM UTC 24 |
| Finished | Oct 15 11:05:06 AM UTC 24 |
| Peak memory | 207436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876669249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2876669249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_tx_rx.623594080 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 103651515160 ps |
| CPU time | 243.16 seconds |
| Started | Oct 15 11:04:55 AM UTC 24 |
| Finished | Oct 15 11:09:02 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623594080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.623594080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/260.uart_fifo_reset.1389384276 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 73000600411 ps |
| CPU time | 170.55 seconds |
| Started | Oct 15 11:23:41 AM UTC 24 |
| Finished | Oct 15 11:26:35 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389384276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1389384276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/260.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/261.uart_fifo_reset.2863840855 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 66543297021 ps |
| CPU time | 128.12 seconds |
| Started | Oct 15 11:23:42 AM UTC 24 |
| Finished | Oct 15 11:25:53 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863840855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2863840855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/261.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/262.uart_fifo_reset.4012736640 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 30516457469 ps |
| CPU time | 42.95 seconds |
| Started | Oct 15 11:23:43 AM UTC 24 |
| Finished | Oct 15 11:24:28 AM UTC 24 |
| Peak memory | 208560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012736640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.4012736640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/262.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/263.uart_fifo_reset.165827599 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 182236455542 ps |
| CPU time | 351 seconds |
| Started | Oct 15 11:23:46 AM UTC 24 |
| Finished | Oct 15 11:29:42 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165827599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.165827599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/263.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/265.uart_fifo_reset.3747931892 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 49770653798 ps |
| CPU time | 31.39 seconds |
| Started | Oct 15 11:23:51 AM UTC 24 |
| Finished | Oct 15 11:24:23 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747931892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3747931892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/265.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/266.uart_fifo_reset.3725605999 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 45734498476 ps |
| CPU time | 105.8 seconds |
| Started | Oct 15 11:23:51 AM UTC 24 |
| Finished | Oct 15 11:25:39 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725605999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3725605999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/266.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/267.uart_fifo_reset.933255858 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 16215856288 ps |
| CPU time | 12.22 seconds |
| Started | Oct 15 11:23:51 AM UTC 24 |
| Finished | Oct 15 11:24:04 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933255858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.933255858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/267.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/268.uart_fifo_reset.2699746749 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 46032335669 ps |
| CPU time | 116.64 seconds |
| Started | Oct 15 11:23:51 AM UTC 24 |
| Finished | Oct 15 11:25:50 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699746749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2699746749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/268.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/269.uart_fifo_reset.1614612902 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 269627817227 ps |
| CPU time | 169.22 seconds |
| Started | Oct 15 11:23:52 AM UTC 24 |
| Finished | Oct 15 11:26:44 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614612902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1614612902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/269.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_alert_test.3591825163 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 15372281 ps |
| CPU time | 0.84 seconds |
| Started | Oct 15 11:05:15 AM UTC 24 |
| Finished | Oct 15 11:05:17 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591825163 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3591825163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_fifo_full.1527115779 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 107483397470 ps |
| CPU time | 368.75 seconds |
| Started | Oct 15 11:05:08 AM UTC 24 |
| Finished | Oct 15 11:11:22 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527115779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1527115779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.836132268 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 50479693186 ps |
| CPU time | 131.17 seconds |
| Started | Oct 15 11:05:09 AM UTC 24 |
| Finished | Oct 15 11:07:23 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836132268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.836132268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_fifo_reset.216983987 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 17940142446 ps |
| CPU time | 56.13 seconds |
| Started | Oct 15 11:05:09 AM UTC 24 |
| Finished | Oct 15 11:06:07 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216983987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.216983987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_intr.2049641556 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 3922144093 ps |
| CPU time | 8.99 seconds |
| Started | Oct 15 11:05:10 AM UTC 24 |
| Finished | Oct 15 11:05:20 AM UTC 24 |
| Peak memory | 205296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049641556 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2049641556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.915095640 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 117106375516 ps |
| CPU time | 455.22 seconds |
| Started | Oct 15 11:05:12 AM UTC 24 |
| Finished | Oct 15 11:12:53 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915095640 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.915095640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_loopback.1562515413 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 4371493493 ps |
| CPU time | 5.72 seconds |
| Started | Oct 15 11:05:10 AM UTC 24 |
| Finished | Oct 15 11:05:17 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562515413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1562515413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_noise_filter.2474243405 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 8128925635 ps |
| CPU time | 25.44 seconds |
| Started | Oct 15 11:05:10 AM UTC 24 |
| Finished | Oct 15 11:05:37 AM UTC 24 |
| Peak memory | 207500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474243405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2474243405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_perf.1013715595 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 11832797862 ps |
| CPU time | 815.78 seconds |
| Started | Oct 15 11:05:12 AM UTC 24 |
| Finished | Oct 15 11:18:57 AM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013715595 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1013715595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_rx_oversample.339128376 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2754217075 ps |
| CPU time | 25.02 seconds |
| Started | Oct 15 11:05:09 AM UTC 24 |
| Finished | Oct 15 11:05:35 AM UTC 24 |
| Peak memory | 207460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339128376 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.339128376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.3063257895 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 38214909511 ps |
| CPU time | 21.32 seconds |
| Started | Oct 15 11:05:10 AM UTC 24 |
| Finished | Oct 15 11:05:33 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063257895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3063257895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.3979395413 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 3059805622 ps |
| CPU time | 3.03 seconds |
| Started | Oct 15 11:05:10 AM UTC 24 |
| Finished | Oct 15 11:05:14 AM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979395413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3979395413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_smoke.2290474366 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 929812602 ps |
| CPU time | 1.99 seconds |
| Started | Oct 15 11:05:07 AM UTC 24 |
| Finished | Oct 15 11:05:10 AM UTC 24 |
| Peak memory | 206256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290474366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2290474366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_stress_all.2604747186 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 291244366466 ps |
| CPU time | 453.15 seconds |
| Started | Oct 15 11:05:13 AM UTC 24 |
| Finished | Oct 15 11:12:52 AM UTC 24 |
| Peak memory | 217732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604747186 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2604747186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.3291123639 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 8284779232 ps |
| CPU time | 32.25 seconds |
| Started | Oct 15 11:05:12 AM UTC 24 |
| Finished | Oct 15 11:05:45 AM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3291123639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all _with_rand_reset.3291123639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.2366465796 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1431583203 ps |
| CPU time | 2.24 seconds |
| Started | Oct 15 11:05:10 AM UTC 24 |
| Finished | Oct 15 11:05:14 AM UTC 24 |
| Peak memory | 207484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366465796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2366465796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_tx_rx.2091408460 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 96615584959 ps |
| CPU time | 49.88 seconds |
| Started | Oct 15 11:05:07 AM UTC 24 |
| Finished | Oct 15 11:05:58 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091408460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2091408460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/27.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/270.uart_fifo_reset.589840435 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 123560345540 ps |
| CPU time | 258.8 seconds |
| Started | Oct 15 11:23:53 AM UTC 24 |
| Finished | Oct 15 11:28:15 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589840435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.589840435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/270.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/271.uart_fifo_reset.649229537 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 44587163182 ps |
| CPU time | 102.6 seconds |
| Started | Oct 15 11:23:55 AM UTC 24 |
| Finished | Oct 15 11:25:40 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649229537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.649229537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/271.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/272.uart_fifo_reset.2427454195 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 68989181805 ps |
| CPU time | 87.37 seconds |
| Started | Oct 15 11:23:59 AM UTC 24 |
| Finished | Oct 15 11:25:28 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427454195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2427454195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/272.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/273.uart_fifo_reset.2400457297 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 14187003527 ps |
| CPU time | 25.99 seconds |
| Started | Oct 15 11:24:00 AM UTC 24 |
| Finished | Oct 15 11:24:28 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400457297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2400457297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/273.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/274.uart_fifo_reset.2963125679 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 163864374429 ps |
| CPU time | 190.85 seconds |
| Started | Oct 15 11:24:02 AM UTC 24 |
| Finished | Oct 15 11:27:16 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963125679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2963125679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/274.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/275.uart_fifo_reset.15217564 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 157715477672 ps |
| CPU time | 63.05 seconds |
| Started | Oct 15 11:24:02 AM UTC 24 |
| Finished | Oct 15 11:25:07 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15217564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.15217564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/275.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/276.uart_fifo_reset.2882493954 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 114694610554 ps |
| CPU time | 70.35 seconds |
| Started | Oct 15 11:24:03 AM UTC 24 |
| Finished | Oct 15 11:25:16 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882493954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2882493954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/276.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/277.uart_fifo_reset.3845237846 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 42053481140 ps |
| CPU time | 31.26 seconds |
| Started | Oct 15 11:24:05 AM UTC 24 |
| Finished | Oct 15 11:24:37 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845237846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3845237846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/277.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/278.uart_fifo_reset.3138544550 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 51343195588 ps |
| CPU time | 32.58 seconds |
| Started | Oct 15 11:24:07 AM UTC 24 |
| Finished | Oct 15 11:24:41 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138544550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3138544550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/278.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2121096554 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 45755903282 ps |
| CPU time | 35.95 seconds |
| Started | Oct 15 11:24:07 AM UTC 24 |
| Finished | Oct 15 11:24:44 AM UTC 24 |
| Peak memory | 208812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121096554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2121096554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/279.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_alert_test.2516403604 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 13671362 ps |
| CPU time | 0.84 seconds |
| Started | Oct 15 11:05:22 AM UTC 24 |
| Finished | Oct 15 11:05:24 AM UTC 24 |
| Peak memory | 202340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516403604 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2516403604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_fifo_full.2671891925 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 75652723057 ps |
| CPU time | 173.59 seconds |
| Started | Oct 15 11:05:15 AM UTC 24 |
| Finished | Oct 15 11:08:12 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671891925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2671891925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.589860263 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 35137520967 ps |
| CPU time | 63.32 seconds |
| Started | Oct 15 11:05:15 AM UTC 24 |
| Finished | Oct 15 11:06:20 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589860263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.589860263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_fifo_reset.1563350579 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 108793452622 ps |
| CPU time | 212.15 seconds |
| Started | Oct 15 11:05:15 AM UTC 24 |
| Finished | Oct 15 11:08:51 AM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563350579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1563350579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_intr.3674621017 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 3030628369 ps |
| CPU time | 8.72 seconds |
| Started | Oct 15 11:05:16 AM UTC 24 |
| Finished | Oct 15 11:05:26 AM UTC 24 |
| Peak memory | 205308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674621017 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3674621017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.2023025750 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 227718237029 ps |
| CPU time | 166.16 seconds |
| Started | Oct 15 11:05:20 AM UTC 24 |
| Finished | Oct 15 11:08:09 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023025750 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2023025750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_loopback.2356354426 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 9729705040 ps |
| CPU time | 22.08 seconds |
| Started | Oct 15 11:05:19 AM UTC 24 |
| Finished | Oct 15 11:05:42 AM UTC 24 |
| Peak memory | 207532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356354426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2356354426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_noise_filter.1426993637 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 85845937539 ps |
| CPU time | 185.86 seconds |
| Started | Oct 15 11:05:18 AM UTC 24 |
| Finished | Oct 15 11:08:27 AM UTC 24 |
| Peak memory | 208924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426993637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1426993637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_perf.979876155 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 26530366365 ps |
| CPU time | 818.21 seconds |
| Started | Oct 15 11:05:20 AM UTC 24 |
| Finished | Oct 15 11:19:09 AM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979876155 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.979876155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_rx_oversample.2619316892 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 5675404091 ps |
| CPU time | 55.35 seconds |
| Started | Oct 15 11:05:16 AM UTC 24 |
| Finished | Oct 15 11:06:13 AM UTC 24 |
| Peak memory | 207440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619316892 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2619316892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.1204411493 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 301154515567 ps |
| CPU time | 150.85 seconds |
| Started | Oct 15 11:05:18 AM UTC 24 |
| Finished | Oct 15 11:07:51 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204411493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1204411493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.4099964992 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 3446265217 ps |
| CPU time | 6.02 seconds |
| Started | Oct 15 11:05:18 AM UTC 24 |
| Finished | Oct 15 11:05:25 AM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099964992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.4099964992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_smoke.3522216896 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 712312288 ps |
| CPU time | 5.47 seconds |
| Started | Oct 15 11:05:15 AM UTC 24 |
| Finished | Oct 15 11:05:22 AM UTC 24 |
| Peak memory | 207872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522216896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3522216896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_stress_all.788375471 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 67229734763 ps |
| CPU time | 124.51 seconds |
| Started | Oct 15 11:05:22 AM UTC 24 |
| Finished | Oct 15 11:07:29 AM UTC 24 |
| Peak memory | 208804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788375471 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.788375471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.2527707485 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 14915118260 ps |
| CPU time | 57.72 seconds |
| Started | Oct 15 11:05:21 AM UTC 24 |
| Finished | Oct 15 11:06:21 AM UTC 24 |
| Peak memory | 217728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2527707485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all _with_rand_reset.2527707485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.3042554798 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2372762263 ps |
| CPU time | 3.54 seconds |
| Started | Oct 15 11:05:18 AM UTC 24 |
| Finished | Oct 15 11:05:22 AM UTC 24 |
| Peak memory | 208112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042554798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3042554798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_tx_rx.223206755 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 16818264912 ps |
| CPU time | 43.37 seconds |
| Started | Oct 15 11:05:15 AM UTC 24 |
| Finished | Oct 15 11:06:00 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223206755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.223206755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/28.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/280.uart_fifo_reset.913313169 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 28547704762 ps |
| CPU time | 23.58 seconds |
| Started | Oct 15 11:24:10 AM UTC 24 |
| Finished | Oct 15 11:24:35 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913313169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.913313169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/280.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/281.uart_fifo_reset.3668861661 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 252475190140 ps |
| CPU time | 121.28 seconds |
| Started | Oct 15 11:24:14 AM UTC 24 |
| Finished | Oct 15 11:26:18 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668861661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3668861661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/281.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2824325849 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 120993647114 ps |
| CPU time | 216.34 seconds |
| Started | Oct 15 11:24:15 AM UTC 24 |
| Finished | Oct 15 11:27:55 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824325849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2824325849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/282.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/283.uart_fifo_reset.3632531456 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 95304586855 ps |
| CPU time | 108.34 seconds |
| Started | Oct 15 11:24:15 AM UTC 24 |
| Finished | Oct 15 11:26:05 AM UTC 24 |
| Peak memory | 207992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632531456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3632531456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/283.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/284.uart_fifo_reset.2942294066 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 17472438619 ps |
| CPU time | 20.8 seconds |
| Started | Oct 15 11:24:16 AM UTC 24 |
| Finished | Oct 15 11:24:38 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942294066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2942294066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/284.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/285.uart_fifo_reset.1721319774 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 103806144148 ps |
| CPU time | 127.61 seconds |
| Started | Oct 15 11:24:19 AM UTC 24 |
| Finished | Oct 15 11:26:29 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721319774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1721319774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/285.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/286.uart_fifo_reset.3471118056 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 132731981521 ps |
| CPU time | 253.83 seconds |
| Started | Oct 15 11:24:20 AM UTC 24 |
| Finished | Oct 15 11:28:38 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471118056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3471118056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/286.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/287.uart_fifo_reset.1641140145 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 156974319952 ps |
| CPU time | 66.47 seconds |
| Started | Oct 15 11:24:22 AM UTC 24 |
| Finished | Oct 15 11:25:31 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641140145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1641140145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/287.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/288.uart_fifo_reset.1588937238 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 191405247485 ps |
| CPU time | 65.72 seconds |
| Started | Oct 15 11:24:22 AM UTC 24 |
| Finished | Oct 15 11:25:30 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588937238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1588937238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/288.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/289.uart_fifo_reset.1818543809 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 36486742807 ps |
| CPU time | 69.29 seconds |
| Started | Oct 15 11:24:23 AM UTC 24 |
| Finished | Oct 15 11:25:35 AM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818543809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1818543809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/289.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_alert_test.3734399634 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 42881676 ps |
| CPU time | 0.81 seconds |
| Started | Oct 15 11:05:41 AM UTC 24 |
| Finished | Oct 15 11:05:43 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734399634 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3734399634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_fifo_full.2353999131 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 28210452082 ps |
| CPU time | 36.81 seconds |
| Started | Oct 15 11:05:27 AM UTC 24 |
| Finished | Oct 15 11:06:05 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353999131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2353999131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.2115597466 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 26353967655 ps |
| CPU time | 46.22 seconds |
| Started | Oct 15 11:05:28 AM UTC 24 |
| Finished | Oct 15 11:06:16 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115597466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2115597466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_fifo_reset.185637588 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 109553213209 ps |
| CPU time | 120.85 seconds |
| Started | Oct 15 11:05:30 AM UTC 24 |
| Finished | Oct 15 11:07:33 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185637588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.185637588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_intr.1609986289 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 15763481173 ps |
| CPU time | 5.4 seconds |
| Started | Oct 15 11:05:31 AM UTC 24 |
| Finished | Oct 15 11:05:38 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609986289 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1609986289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.1776688424 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 101555043602 ps |
| CPU time | 843.46 seconds |
| Started | Oct 15 11:05:38 AM UTC 24 |
| Finished | Oct 15 11:19:51 AM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776688424 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1776688424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_loopback.2075941122 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 105453140 ps |
| CPU time | 0.91 seconds |
| Started | Oct 15 11:05:36 AM UTC 24 |
| Finished | Oct 15 11:05:37 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075941122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2075941122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_noise_filter.2728311245 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 19108974674 ps |
| CPU time | 46.66 seconds |
| Started | Oct 15 11:05:32 AM UTC 24 |
| Finished | Oct 15 11:06:20 AM UTC 24 |
| Peak memory | 208104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728311245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2728311245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_perf.2488451011 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 3223409579 ps |
| CPU time | 119.52 seconds |
| Started | Oct 15 11:05:37 AM UTC 24 |
| Finished | Oct 15 11:07:39 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488451011 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2488451011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_rx_oversample.611782929 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 4526056095 ps |
| CPU time | 21.83 seconds |
| Started | Oct 15 11:05:31 AM UTC 24 |
| Finished | Oct 15 11:05:54 AM UTC 24 |
| Peak memory | 207680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611782929 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.611782929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.749298808 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 134208706946 ps |
| CPU time | 158.79 seconds |
| Started | Oct 15 11:05:33 AM UTC 24 |
| Finished | Oct 15 11:08:15 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749298808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.749298808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.1972951844 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 36403511827 ps |
| CPU time | 25 seconds |
| Started | Oct 15 11:05:33 AM UTC 24 |
| Finished | Oct 15 11:06:00 AM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972951844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1972951844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_smoke.1976381123 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 5620946854 ps |
| CPU time | 4.73 seconds |
| Started | Oct 15 11:05:24 AM UTC 24 |
| Finished | Oct 15 11:05:29 AM UTC 24 |
| Peak memory | 207740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976381123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1976381123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_stress_all.1180211012 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 258806757997 ps |
| CPU time | 298.1 seconds |
| Started | Oct 15 11:05:39 AM UTC 24 |
| Finished | Oct 15 11:10:41 AM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180211012 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1180211012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.2406008557 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 19215017505 ps |
| CPU time | 39.82 seconds |
| Started | Oct 15 11:05:39 AM UTC 24 |
| Finished | Oct 15 11:06:20 AM UTC 24 |
| Peak memory | 225368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2406008557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all _with_rand_reset.2406008557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.3094517069 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 6462350013 ps |
| CPU time | 21.63 seconds |
| Started | Oct 15 11:05:33 AM UTC 24 |
| Finished | Oct 15 11:05:56 AM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094517069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3094517069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_tx_rx.1145854499 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 84654461355 ps |
| CPU time | 50.57 seconds |
| Started | Oct 15 11:05:27 AM UTC 24 |
| Finished | Oct 15 11:06:19 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145854499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1145854499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/29.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/291.uart_fifo_reset.3110120071 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 35695232457 ps |
| CPU time | 58.76 seconds |
| Started | Oct 15 11:24:26 AM UTC 24 |
| Finished | Oct 15 11:25:26 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110120071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3110120071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/291.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/292.uart_fifo_reset.3308678884 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 109301274962 ps |
| CPU time | 46.97 seconds |
| Started | Oct 15 11:24:28 AM UTC 24 |
| Finished | Oct 15 11:25:16 AM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308678884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3308678884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/292.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/293.uart_fifo_reset.2364787055 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 55841794814 ps |
| CPU time | 70.18 seconds |
| Started | Oct 15 11:24:29 AM UTC 24 |
| Finished | Oct 15 11:25:41 AM UTC 24 |
| Peak memory | 208124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364787055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2364787055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/293.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/294.uart_fifo_reset.747769974 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 91607702519 ps |
| CPU time | 26.1 seconds |
| Started | Oct 15 11:24:29 AM UTC 24 |
| Finished | Oct 15 11:24:57 AM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747769974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.747769974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/294.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/295.uart_fifo_reset.786784143 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 190495654655 ps |
| CPU time | 304.37 seconds |
| Started | Oct 15 11:24:34 AM UTC 24 |
| Finished | Oct 15 11:29:42 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786784143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.786784143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/295.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/296.uart_fifo_reset.248750006 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 113619410691 ps |
| CPU time | 198.37 seconds |
| Started | Oct 15 11:24:35 AM UTC 24 |
| Finished | Oct 15 11:27:56 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248750006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.248750006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/296.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/297.uart_fifo_reset.3395294740 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 63302689366 ps |
| CPU time | 16.07 seconds |
| Started | Oct 15 11:24:35 AM UTC 24 |
| Finished | Oct 15 11:24:52 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395294740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3395294740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/297.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/299.uart_fifo_reset.1385126896 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 35213817963 ps |
| CPU time | 66.65 seconds |
| Started | Oct 15 11:24:36 AM UTC 24 |
| Finished | Oct 15 11:25:45 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385126896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1385126896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/299.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_alert_test.1864768433 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 30420216 ps |
| CPU time | 0.72 seconds |
| Started | Oct 15 10:31:36 AM UTC 24 |
| Finished | Oct 15 10:31:37 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864768433 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1864768433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_fifo_full.2908490165 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30060488789 ps |
| CPU time | 62.56 seconds |
| Started | Oct 15 10:30:15 AM UTC 24 |
| Finished | Oct 15 10:31:19 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908490165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2908490165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.2437733323 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 216970288620 ps |
| CPU time | 447.17 seconds |
| Started | Oct 15 10:30:17 AM UTC 24 |
| Finished | Oct 15 10:37:51 AM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437733323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2437733323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.1309002679 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 102406974546 ps |
| CPU time | 526.01 seconds |
| Started | Oct 15 10:31:32 AM UTC 24 |
| Finished | Oct 15 10:40:26 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309002679 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1309002679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_loopback.947602434 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 9904968348 ps |
| CPU time | 13.55 seconds |
| Started | Oct 15 10:31:20 AM UTC 24 |
| Finished | Oct 15 10:31:35 AM UTC 24 |
| Peak memory | 207376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947602434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 3.uart_loopback.947602434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_noise_filter.1435492427 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 79109696164 ps |
| CPU time | 91.45 seconds |
| Started | Oct 15 10:30:46 AM UTC 24 |
| Finished | Oct 15 10:32:20 AM UTC 24 |
| Peak memory | 207540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435492427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1435492427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_perf.624736440 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 12178235606 ps |
| CPU time | 190.38 seconds |
| Started | Oct 15 10:31:20 AM UTC 24 |
| Finished | Oct 15 10:34:34 AM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624736440 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.624736440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_rx_oversample.3133910009 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 4585003386 ps |
| CPU time | 5.02 seconds |
| Started | Oct 15 10:30:39 AM UTC 24 |
| Finished | Oct 15 10:30:45 AM UTC 24 |
| Peak memory | 207356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133910009 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3133910009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.580597195 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 133398146075 ps |
| CPU time | 141.46 seconds |
| Started | Oct 15 10:30:52 AM UTC 24 |
| Finished | Oct 15 10:33:16 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580597195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.580597195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.1222084302 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 4529030167 ps |
| CPU time | 3.24 seconds |
| Started | Oct 15 10:30:47 AM UTC 24 |
| Finished | Oct 15 10:30:52 AM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222084302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1222084302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_sec_cm.1989832603 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 176984312 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 10:31:36 AM UTC 24 |
| Finished | Oct 15 10:31:38 AM UTC 24 |
| Peak memory | 240056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989832603 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1989832603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_smoke.87268614 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 450204460 ps |
| CPU time | 2.89 seconds |
| Started | Oct 15 10:30:10 AM UTC 24 |
| Finished | Oct 15 10:30:14 AM UTC 24 |
| Peak memory | 207504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87268614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 3.uart_smoke.87268614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.4279968508 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 653414512 ps |
| CPU time | 13.4 seconds |
| Started | Oct 15 10:31:33 AM UTC 24 |
| Finished | Oct 15 10:31:48 AM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4279968508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_ with_rand_reset.4279968508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.114461358 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 6965552152 ps |
| CPU time | 26.07 seconds |
| Started | Oct 15 10:31:05 AM UTC 24 |
| Finished | Oct 15 10:31:33 AM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114461358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.114461358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/3.uart_tx_rx.2912936564 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 33057815338 ps |
| CPU time | 78.35 seconds |
| Started | Oct 15 10:30:11 AM UTC 24 |
| Finished | Oct 15 10:31:31 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912936564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2912936564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/3.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_alert_test.2447386266 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 22027423 ps |
| CPU time | 0.86 seconds |
| Started | Oct 15 11:06:05 AM UTC 24 |
| Finished | Oct 15 11:06:07 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447386266 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2447386266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_fifo_full.2089702510 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 98690697423 ps |
| CPU time | 155.56 seconds |
| Started | Oct 15 11:05:44 AM UTC 24 |
| Finished | Oct 15 11:08:23 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089702510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2089702510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.396080576 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 35883369067 ps |
| CPU time | 27.61 seconds |
| Started | Oct 15 11:05:46 AM UTC 24 |
| Finished | Oct 15 11:06:15 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396080576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.396080576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_fifo_reset.2591889418 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 96466168371 ps |
| CPU time | 183.08 seconds |
| Started | Oct 15 11:05:46 AM UTC 24 |
| Finished | Oct 15 11:08:53 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591889418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2591889418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_intr.2616534991 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 27587377635 ps |
| CPU time | 63.57 seconds |
| Started | Oct 15 11:05:50 AM UTC 24 |
| Finished | Oct 15 11:06:56 AM UTC 24 |
| Peak memory | 207884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616534991 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2616534991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.1481671017 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 148524818544 ps |
| CPU time | 1179.59 seconds |
| Started | Oct 15 11:06:01 AM UTC 24 |
| Finished | Oct 15 11:25:54 AM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481671017 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1481671017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_loopback.984454847 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 12685687330 ps |
| CPU time | 12.51 seconds |
| Started | Oct 15 11:05:59 AM UTC 24 |
| Finished | Oct 15 11:06:12 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984454847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 30.uart_loopback.984454847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_noise_filter.3228115434 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 75476589264 ps |
| CPU time | 236.02 seconds |
| Started | Oct 15 11:05:54 AM UTC 24 |
| Finished | Oct 15 11:09:53 AM UTC 24 |
| Peak memory | 208284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228115434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3228115434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_perf.704566503 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 18515011634 ps |
| CPU time | 95.06 seconds |
| Started | Oct 15 11:06:00 AM UTC 24 |
| Finished | Oct 15 11:07:37 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704566503 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.704566503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_rx_oversample.2031554063 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 6979998345 ps |
| CPU time | 4.2 seconds |
| Started | Oct 15 11:05:47 AM UTC 24 |
| Finished | Oct 15 11:05:53 AM UTC 24 |
| Peak memory | 207412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031554063 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2031554063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.1476269682 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 33560929618 ps |
| CPU time | 41.55 seconds |
| Started | Oct 15 11:05:57 AM UTC 24 |
| Finished | Oct 15 11:06:40 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476269682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1476269682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.4220703959 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1602099736 ps |
| CPU time | 3.46 seconds |
| Started | Oct 15 11:05:55 AM UTC 24 |
| Finished | Oct 15 11:05:59 AM UTC 24 |
| Peak memory | 205112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220703959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.4220703959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_smoke.1579909235 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 263159939 ps |
| CPU time | 2.46 seconds |
| Started | Oct 15 11:05:43 AM UTC 24 |
| Finished | Oct 15 11:05:47 AM UTC 24 |
| Peak memory | 208244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579909235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1579909235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_stress_all.3790308729 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 465634537134 ps |
| CPU time | 724.98 seconds |
| Started | Oct 15 11:06:01 AM UTC 24 |
| Finished | Oct 15 11:18:15 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790308729 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3790308729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.1957578559 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1208187987 ps |
| CPU time | 2.33 seconds |
| Started | Oct 15 11:05:57 AM UTC 24 |
| Finished | Oct 15 11:06:00 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957578559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1957578559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_tx_rx.2938769807 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 114162456444 ps |
| CPU time | 46.52 seconds |
| Started | Oct 15 11:05:43 AM UTC 24 |
| Finished | Oct 15 11:06:31 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938769807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2938769807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_alert_test.3814389029 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 53810705 ps |
| CPU time | 0.76 seconds |
| Started | Oct 15 11:06:22 AM UTC 24 |
| Finished | Oct 15 11:06:24 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814389029 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3814389029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_fifo_full.2006260692 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 175226868721 ps |
| CPU time | 88.59 seconds |
| Started | Oct 15 11:06:07 AM UTC 24 |
| Finished | Oct 15 11:07:38 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006260692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2006260692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.1934196794 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 22788501011 ps |
| CPU time | 21.47 seconds |
| Started | Oct 15 11:06:07 AM UTC 24 |
| Finished | Oct 15 11:06:30 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934196794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1934196794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_fifo_reset.2437674502 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 12445235999 ps |
| CPU time | 14.36 seconds |
| Started | Oct 15 11:06:08 AM UTC 24 |
| Finished | Oct 15 11:06:23 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437674502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2437674502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_intr.650879241 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 36157860672 ps |
| CPU time | 19.44 seconds |
| Started | Oct 15 11:06:14 AM UTC 24 |
| Finished | Oct 15 11:06:34 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650879241 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.650879241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.3001863098 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 58641980281 ps |
| CPU time | 592.1 seconds |
| Started | Oct 15 11:06:21 AM UTC 24 |
| Finished | Oct 15 11:16:21 AM UTC 24 |
| Peak memory | 208496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001863098 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3001863098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_loopback.1597760760 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 3979161737 ps |
| CPU time | 3.66 seconds |
| Started | Oct 15 11:06:21 AM UTC 24 |
| Finished | Oct 15 11:06:26 AM UTC 24 |
| Peak memory | 207488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597760760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1597760760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_noise_filter.3501075920 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 99985727809 ps |
| CPU time | 75.86 seconds |
| Started | Oct 15 11:06:15 AM UTC 24 |
| Finished | Oct 15 11:07:33 AM UTC 24 |
| Peak memory | 208936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501075920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3501075920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_perf.519233201 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 18951689651 ps |
| CPU time | 944.25 seconds |
| Started | Oct 15 11:06:21 AM UTC 24 |
| Finished | Oct 15 11:22:17 AM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519233201 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.519233201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_rx_oversample.4240959082 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 4228416239 ps |
| CPU time | 45.79 seconds |
| Started | Oct 15 11:06:12 AM UTC 24 |
| Finished | Oct 15 11:06:59 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240959082 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.4240959082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.1958734381 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 21066048105 ps |
| CPU time | 58.85 seconds |
| Started | Oct 15 11:06:17 AM UTC 24 |
| Finished | Oct 15 11:07:18 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958734381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1958734381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.858843893 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 5665213320 ps |
| CPU time | 2.81 seconds |
| Started | Oct 15 11:06:16 AM UTC 24 |
| Finished | Oct 15 11:06:21 AM UTC 24 |
| Peak memory | 207296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858843893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.858843893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_smoke.1175981447 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 469819231 ps |
| CPU time | 3.39 seconds |
| Started | Oct 15 11:06:06 AM UTC 24 |
| Finished | Oct 15 11:06:11 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175981447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1175981447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_stress_all.2979544099 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 719247672481 ps |
| CPU time | 285.44 seconds |
| Started | Oct 15 11:06:21 AM UTC 24 |
| Finished | Oct 15 11:11:11 AM UTC 24 |
| Peak memory | 208684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979544099 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2979544099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.4154359504 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 2872807261 ps |
| CPU time | 46.01 seconds |
| Started | Oct 15 11:06:21 AM UTC 24 |
| Finished | Oct 15 11:07:09 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4154359504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all _with_rand_reset.4154359504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.3819799410 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1109536324 ps |
| CPU time | 3.68 seconds |
| Started | Oct 15 11:06:20 AM UTC 24 |
| Finished | Oct 15 11:06:25 AM UTC 24 |
| Peak memory | 208228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819799410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3819799410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_tx_rx.1281253852 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 88821568051 ps |
| CPU time | 60.68 seconds |
| Started | Oct 15 11:06:06 AM UTC 24 |
| Finished | Oct 15 11:07:09 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281253852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1281253852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/31.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_alert_test.2392627439 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 35282283 ps |
| CPU time | 0.81 seconds |
| Started | Oct 15 11:07:01 AM UTC 24 |
| Finished | Oct 15 11:07:03 AM UTC 24 |
| Peak memory | 202340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392627439 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2392627439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_fifo_full.1541004162 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 27039964254 ps |
| CPU time | 33.12 seconds |
| Started | Oct 15 11:06:26 AM UTC 24 |
| Finished | Oct 15 11:07:00 AM UTC 24 |
| Peak memory | 208612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541004162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1541004162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.3130606119 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 31434975664 ps |
| CPU time | 35.13 seconds |
| Started | Oct 15 11:06:27 AM UTC 24 |
| Finished | Oct 15 11:07:04 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130606119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3130606119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_intr.1733517477 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 31371205132 ps |
| CPU time | 89.76 seconds |
| Started | Oct 15 11:06:32 AM UTC 24 |
| Finished | Oct 15 11:08:05 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733517477 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1733517477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.28914086 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 90169631440 ps |
| CPU time | 707.35 seconds |
| Started | Oct 15 11:06:54 AM UTC 24 |
| Finished | Oct 15 11:18:50 AM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28914086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.28914086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_loopback.3178481261 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1818826198 ps |
| CPU time | 7.91 seconds |
| Started | Oct 15 11:06:43 AM UTC 24 |
| Finished | Oct 15 11:06:52 AM UTC 24 |
| Peak memory | 208108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178481261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3178481261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_noise_filter.3336158196 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 30424671380 ps |
| CPU time | 71.88 seconds |
| Started | Oct 15 11:06:35 AM UTC 24 |
| Finished | Oct 15 11:07:49 AM UTC 24 |
| Peak memory | 208104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336158196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3336158196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_perf.4085410717 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 5590098165 ps |
| CPU time | 96.94 seconds |
| Started | Oct 15 11:06:43 AM UTC 24 |
| Finished | Oct 15 11:08:23 AM UTC 24 |
| Peak memory | 208960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085410717 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.4085410717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_rx_oversample.153899149 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 3359367248 ps |
| CPU time | 7.16 seconds |
| Started | Oct 15 11:06:31 AM UTC 24 |
| Finished | Oct 15 11:06:40 AM UTC 24 |
| Peak memory | 208276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153899149 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.153899149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.526675777 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 90990453968 ps |
| CPU time | 50.76 seconds |
| Started | Oct 15 11:06:40 AM UTC 24 |
| Finished | Oct 15 11:07:33 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526675777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.526675777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.1892386629 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2482345256 ps |
| CPU time | 3.29 seconds |
| Started | Oct 15 11:06:38 AM UTC 24 |
| Finished | Oct 15 11:06:42 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892386629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1892386629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_smoke.2715971572 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 322948515 ps |
| CPU time | 1.92 seconds |
| Started | Oct 15 11:06:24 AM UTC 24 |
| Finished | Oct 15 11:06:27 AM UTC 24 |
| Peak memory | 206252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715971572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2715971572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_stress_all.4044024619 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 296818633711 ps |
| CPU time | 281.35 seconds |
| Started | Oct 15 11:07:00 AM UTC 24 |
| Finished | Oct 15 11:11:45 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044024619 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.4044024619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.913668108 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 3087598007 ps |
| CPU time | 108.45 seconds |
| Started | Oct 15 11:06:57 AM UTC 24 |
| Finished | Oct 15 11:08:47 AM UTC 24 |
| Peak memory | 217840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=913668108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all_ with_rand_reset.913668108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.4161000552 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 7121278186 ps |
| CPU time | 25.76 seconds |
| Started | Oct 15 11:06:40 AM UTC 24 |
| Finished | Oct 15 11:07:07 AM UTC 24 |
| Peak memory | 208432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161000552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.4161000552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_tx_rx.766894327 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 16538942829 ps |
| CPU time | 11.09 seconds |
| Started | Oct 15 11:06:25 AM UTC 24 |
| Finished | Oct 15 11:06:37 AM UTC 24 |
| Peak memory | 207840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766894327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.766894327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/32.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_alert_test.1849996679 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 12957718 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 11:07:33 AM UTC 24 |
| Finished | Oct 15 11:07:35 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849996679 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1849996679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_fifo_full.700999891 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 113465862115 ps |
| CPU time | 209.94 seconds |
| Started | Oct 15 11:07:04 AM UTC 24 |
| Finished | Oct 15 11:10:37 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700999891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.700999891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.4019722269 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 167466558896 ps |
| CPU time | 74.6 seconds |
| Started | Oct 15 11:07:06 AM UTC 24 |
| Finished | Oct 15 11:08:23 AM UTC 24 |
| Peak memory | 208468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019722269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4019722269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_intr.1487923503 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 33303629241 ps |
| CPU time | 94.23 seconds |
| Started | Oct 15 11:07:10 AM UTC 24 |
| Finished | Oct 15 11:08:47 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487923503 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1487923503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.4036216160 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 54947766392 ps |
| CPU time | 82.22 seconds |
| Started | Oct 15 11:07:29 AM UTC 24 |
| Finished | Oct 15 11:08:53 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036216160 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.4036216160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_loopback.2849365825 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 928424122 ps |
| CPU time | 4.53 seconds |
| Started | Oct 15 11:07:26 AM UTC 24 |
| Finished | Oct 15 11:07:32 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849365825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2849365825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_noise_filter.767129855 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 6672768289 ps |
| CPU time | 8.04 seconds |
| Started | Oct 15 11:07:10 AM UTC 24 |
| Finished | Oct 15 11:07:19 AM UTC 24 |
| Peak memory | 203268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767129855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.767129855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_perf.3739278769 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 16568240262 ps |
| CPU time | 655.67 seconds |
| Started | Oct 15 11:07:27 AM UTC 24 |
| Finished | Oct 15 11:18:31 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739278769 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3739278769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_rx_oversample.1842159334 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 4957515695 ps |
| CPU time | 57.17 seconds |
| Started | Oct 15 11:07:09 AM UTC 24 |
| Finished | Oct 15 11:08:08 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842159334 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1842159334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.3461466608 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 231863239267 ps |
| CPU time | 110.52 seconds |
| Started | Oct 15 11:07:21 AM UTC 24 |
| Finished | Oct 15 11:09:14 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461466608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3461466608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.947171236 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 1854122689 ps |
| CPU time | 4.91 seconds |
| Started | Oct 15 11:07:19 AM UTC 24 |
| Finished | Oct 15 11:07:25 AM UTC 24 |
| Peak memory | 205120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947171236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.947171236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_smoke.809281790 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 472855973 ps |
| CPU time | 1.68 seconds |
| Started | Oct 15 11:07:03 AM UTC 24 |
| Finished | Oct 15 11:07:06 AM UTC 24 |
| Peak memory | 206264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809281790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 33.uart_smoke.809281790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_stress_all.3273592742 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 75184280754 ps |
| CPU time | 246.6 seconds |
| Started | Oct 15 11:07:32 AM UTC 24 |
| Finished | Oct 15 11:11:43 AM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273592742 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3273592742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.388403902 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 12803385254 ps |
| CPU time | 110.41 seconds |
| Started | Oct 15 11:07:30 AM UTC 24 |
| Finished | Oct 15 11:09:23 AM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=388403902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all_ with_rand_reset.388403902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.4234429069 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 993901530 ps |
| CPU time | 3.78 seconds |
| Started | Oct 15 11:07:24 AM UTC 24 |
| Finished | Oct 15 11:07:29 AM UTC 24 |
| Peak memory | 207856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234429069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.4234429069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_tx_rx.2160356284 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 99797935847 ps |
| CPU time | 68.67 seconds |
| Started | Oct 15 11:07:04 AM UTC 24 |
| Finished | Oct 15 11:08:15 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160356284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2160356284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/33.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_alert_test.3022551572 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 15075174 ps |
| CPU time | 0.8 seconds |
| Started | Oct 15 11:07:59 AM UTC 24 |
| Finished | Oct 15 11:08:01 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022551572 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3022551572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_fifo_full.453347131 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 32426887682 ps |
| CPU time | 19.67 seconds |
| Started | Oct 15 11:07:35 AM UTC 24 |
| Finished | Oct 15 11:07:56 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453347131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.453347131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.890597546 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 16830779551 ps |
| CPU time | 16.66 seconds |
| Started | Oct 15 11:07:38 AM UTC 24 |
| Finished | Oct 15 11:07:56 AM UTC 24 |
| Peak memory | 208556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890597546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.890597546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_fifo_reset.1607445780 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 52222222907 ps |
| CPU time | 51.57 seconds |
| Started | Oct 15 11:07:38 AM UTC 24 |
| Finished | Oct 15 11:08:31 AM UTC 24 |
| Peak memory | 208520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607445780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1607445780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_intr.3058644180 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 39247399722 ps |
| CPU time | 62.16 seconds |
| Started | Oct 15 11:07:40 AM UTC 24 |
| Finished | Oct 15 11:08:44 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058644180 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3058644180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.3951255350 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 125240932054 ps |
| CPU time | 742.69 seconds |
| Started | Oct 15 11:07:57 AM UTC 24 |
| Finished | Oct 15 11:20:29 AM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951255350 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3951255350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_loopback.2078146148 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 6167915522 ps |
| CPU time | 21.34 seconds |
| Started | Oct 15 11:07:54 AM UTC 24 |
| Finished | Oct 15 11:08:17 AM UTC 24 |
| Peak memory | 207336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078146148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2078146148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_noise_filter.3276886094 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 34979656427 ps |
| CPU time | 36.09 seconds |
| Started | Oct 15 11:07:40 AM UTC 24 |
| Finished | Oct 15 11:08:18 AM UTC 24 |
| Peak memory | 208928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276886094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3276886094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_perf.3272271115 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 5219366969 ps |
| CPU time | 375.45 seconds |
| Started | Oct 15 11:07:56 AM UTC 24 |
| Finished | Oct 15 11:14:17 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272271115 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3272271115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_rx_oversample.2423790386 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 4671948005 ps |
| CPU time | 42.18 seconds |
| Started | Oct 15 11:07:39 AM UTC 24 |
| Finished | Oct 15 11:08:22 AM UTC 24 |
| Peak memory | 207412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423790386 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2423790386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.95615310 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 20723675367 ps |
| CPU time | 75.18 seconds |
| Started | Oct 15 11:07:50 AM UTC 24 |
| Finished | Oct 15 11:09:07 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95615310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.95615310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.1321986593 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 3346183564 ps |
| CPU time | 12.29 seconds |
| Started | Oct 15 11:07:43 AM UTC 24 |
| Finished | Oct 15 11:07:57 AM UTC 24 |
| Peak memory | 205240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321986593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1321986593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_smoke.2608470734 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 447941530 ps |
| CPU time | 1.95 seconds |
| Started | Oct 15 11:07:33 AM UTC 24 |
| Finished | Oct 15 11:07:36 AM UTC 24 |
| Peak memory | 207204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608470734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2608470734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_stress_all.2959412478 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 64582699286 ps |
| CPU time | 52.67 seconds |
| Started | Oct 15 11:07:58 AM UTC 24 |
| Finished | Oct 15 11:08:53 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959412478 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2959412478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.3862089232 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 16919149143 ps |
| CPU time | 60.19 seconds |
| Started | Oct 15 11:07:57 AM UTC 24 |
| Finished | Oct 15 11:09:00 AM UTC 24 |
| Peak memory | 220068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3862089232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all _with_rand_reset.3862089232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.2817073497 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 2162546031 ps |
| CPU time | 3.61 seconds |
| Started | Oct 15 11:07:52 AM UTC 24 |
| Finished | Oct 15 11:07:57 AM UTC 24 |
| Peak memory | 207512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817073497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2817073497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_tx_rx.3144473738 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 77758841340 ps |
| CPU time | 138.99 seconds |
| Started | Oct 15 11:07:34 AM UTC 24 |
| Finished | Oct 15 11:09:56 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144473738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3144473738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/34.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_alert_test.1456974647 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 38861577 ps |
| CPU time | 0.84 seconds |
| Started | Oct 15 11:08:24 AM UTC 24 |
| Finished | Oct 15 11:08:26 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456974647 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1456974647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_fifo_full.3831231877 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 110786444785 ps |
| CPU time | 187.82 seconds |
| Started | Oct 15 11:08:05 AM UTC 24 |
| Finished | Oct 15 11:11:16 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831231877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3831231877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.1676440633 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 10935647920 ps |
| CPU time | 14.14 seconds |
| Started | Oct 15 11:08:06 AM UTC 24 |
| Finished | Oct 15 11:08:21 AM UTC 24 |
| Peak memory | 208580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676440633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1676440633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_fifo_reset.377312434 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 37076035033 ps |
| CPU time | 29.18 seconds |
| Started | Oct 15 11:08:09 AM UTC 24 |
| Finished | Oct 15 11:08:39 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377312434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.377312434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_intr.1623935693 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 52164520983 ps |
| CPU time | 28.39 seconds |
| Started | Oct 15 11:08:10 AM UTC 24 |
| Finished | Oct 15 11:08:40 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623935693 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1623935693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.1146983304 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 188911529934 ps |
| CPU time | 76.94 seconds |
| Started | Oct 15 11:08:22 AM UTC 24 |
| Finished | Oct 15 11:09:40 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146983304 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1146983304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_loopback.1572099589 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 5110248248 ps |
| CPU time | 7.73 seconds |
| Started | Oct 15 11:08:18 AM UTC 24 |
| Finished | Oct 15 11:08:27 AM UTC 24 |
| Peak memory | 207348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572099589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1572099589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_noise_filter.1446897063 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 9153516298 ps |
| CPU time | 18.81 seconds |
| Started | Oct 15 11:08:12 AM UTC 24 |
| Finished | Oct 15 11:08:32 AM UTC 24 |
| Peak memory | 205452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446897063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1446897063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_perf.1784810357 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 6023184231 ps |
| CPU time | 73.48 seconds |
| Started | Oct 15 11:08:20 AM UTC 24 |
| Finished | Oct 15 11:09:35 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784810357 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1784810357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_rx_oversample.3863259808 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3597732348 ps |
| CPU time | 22.4 seconds |
| Started | Oct 15 11:08:09 AM UTC 24 |
| Finished | Oct 15 11:08:33 AM UTC 24 |
| Peak memory | 208388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863259808 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3863259808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.55962359 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 183466031991 ps |
| CPU time | 32.7 seconds |
| Started | Oct 15 11:08:15 AM UTC 24 |
| Finished | Oct 15 11:08:49 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55962359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.55962359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.3896364093 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 36745274931 ps |
| CPU time | 85.25 seconds |
| Started | Oct 15 11:08:15 AM UTC 24 |
| Finished | Oct 15 11:09:42 AM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896364093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3896364093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_smoke.1450619007 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 102143223 ps |
| CPU time | 1.36 seconds |
| Started | Oct 15 11:08:02 AM UTC 24 |
| Finished | Oct 15 11:08:04 AM UTC 24 |
| Peak memory | 206308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450619007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1450619007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_stress_all.1528189157 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 374082436690 ps |
| CPU time | 659.02 seconds |
| Started | Oct 15 11:08:24 AM UTC 24 |
| Finished | Oct 15 11:19:30 AM UTC 24 |
| Peak memory | 212248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528189157 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1528189157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.351554689 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3697736531 ps |
| CPU time | 84.73 seconds |
| Started | Oct 15 11:08:24 AM UTC 24 |
| Finished | Oct 15 11:09:51 AM UTC 24 |
| Peak memory | 224648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=351554689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all_ with_rand_reset.351554689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.328484782 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 1348788271 ps |
| CPU time | 4.24 seconds |
| Started | Oct 15 11:08:17 AM UTC 24 |
| Finished | Oct 15 11:08:23 AM UTC 24 |
| Peak memory | 207412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328484782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.328484782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_tx_rx.660817941 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 49746949995 ps |
| CPU time | 45.53 seconds |
| Started | Oct 15 11:08:02 AM UTC 24 |
| Finished | Oct 15 11:08:49 AM UTC 24 |
| Peak memory | 208416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660817941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.660817941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/35.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_alert_test.128181538 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 21879984 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 11:08:50 AM UTC 24 |
| Finished | Oct 15 11:08:52 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128181538 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.128181538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_fifo_full.1784130845 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 74022081138 ps |
| CPU time | 53.78 seconds |
| Started | Oct 15 11:08:26 AM UTC 24 |
| Finished | Oct 15 11:09:21 AM UTC 24 |
| Peak memory | 208576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784130845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1784130845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.1636890085 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 294419031701 ps |
| CPU time | 55.26 seconds |
| Started | Oct 15 11:08:27 AM UTC 24 |
| Finished | Oct 15 11:09:24 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636890085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1636890085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_fifo_reset.3446182348 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 80500121976 ps |
| CPU time | 49.55 seconds |
| Started | Oct 15 11:08:28 AM UTC 24 |
| Finished | Oct 15 11:09:19 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446182348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3446182348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_intr.547669653 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 6675525610 ps |
| CPU time | 21.7 seconds |
| Started | Oct 15 11:08:33 AM UTC 24 |
| Finished | Oct 15 11:08:56 AM UTC 24 |
| Peak memory | 208684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547669653 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.547669653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.1885659591 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 93149466825 ps |
| CPU time | 186.21 seconds |
| Started | Oct 15 11:08:47 AM UTC 24 |
| Finished | Oct 15 11:11:56 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885659591 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1885659591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_loopback.1797769249 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 10864121519 ps |
| CPU time | 11.2 seconds |
| Started | Oct 15 11:08:44 AM UTC 24 |
| Finished | Oct 15 11:08:56 AM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797769249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1797769249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_noise_filter.640494602 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 205330665874 ps |
| CPU time | 185.41 seconds |
| Started | Oct 15 11:08:33 AM UTC 24 |
| Finished | Oct 15 11:11:42 AM UTC 24 |
| Peak memory | 208620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640494602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.640494602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_perf.1095156099 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 19395369986 ps |
| CPU time | 514.98 seconds |
| Started | Oct 15 11:08:45 AM UTC 24 |
| Finished | Oct 15 11:17:26 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095156099 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1095156099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_rx_oversample.173354150 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2035752486 ps |
| CPU time | 4.37 seconds |
| Started | Oct 15 11:08:31 AM UTC 24 |
| Finished | Oct 15 11:08:37 AM UTC 24 |
| Peak memory | 207296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173354150 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.173354150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.1393482457 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 100353902619 ps |
| CPU time | 276.12 seconds |
| Started | Oct 15 11:08:41 AM UTC 24 |
| Finished | Oct 15 11:13:21 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393482457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1393482457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.1814065616 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 4128674496 ps |
| CPU time | 4.21 seconds |
| Started | Oct 15 11:08:38 AM UTC 24 |
| Finished | Oct 15 11:08:43 AM UTC 24 |
| Peak memory | 205104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814065616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1814065616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_smoke.1332948356 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 11570725556 ps |
| CPU time | 33.25 seconds |
| Started | Oct 15 11:08:24 AM UTC 24 |
| Finished | Oct 15 11:08:59 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332948356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1332948356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_stress_all.2625445526 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 246294504538 ps |
| CPU time | 377.71 seconds |
| Started | Oct 15 11:08:48 AM UTC 24 |
| Finished | Oct 15 11:15:11 AM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625445526 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2625445526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.2116461152 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 2597549483 ps |
| CPU time | 95.5 seconds |
| Started | Oct 15 11:08:48 AM UTC 24 |
| Finished | Oct 15 11:10:26 AM UTC 24 |
| Peak memory | 223936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2116461152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all _with_rand_reset.2116461152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.1659341191 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 6462473529 ps |
| CPU time | 31.27 seconds |
| Started | Oct 15 11:08:41 AM UTC 24 |
| Finished | Oct 15 11:09:13 AM UTC 24 |
| Peak memory | 208452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659341191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1659341191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_tx_rx.2996414661 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 19259147856 ps |
| CPU time | 59.27 seconds |
| Started | Oct 15 11:08:24 AM UTC 24 |
| Finished | Oct 15 11:09:25 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996414661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2996414661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/36.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_alert_test.2719193700 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 12137942 ps |
| CPU time | 0.83 seconds |
| Started | Oct 15 11:09:07 AM UTC 24 |
| Finished | Oct 15 11:09:09 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719193700 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2719193700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_fifo_full.64419060 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 294183622985 ps |
| CPU time | 1041.7 seconds |
| Started | Oct 15 11:08:52 AM UTC 24 |
| Finished | Oct 15 11:26:26 AM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64419060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.64419060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.45653722 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 69138693985 ps |
| CPU time | 217.63 seconds |
| Started | Oct 15 11:08:54 AM UTC 24 |
| Finished | Oct 15 11:12:34 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45653722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.45653722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_fifo_reset.994381330 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 141206271598 ps |
| CPU time | 69.58 seconds |
| Started | Oct 15 11:08:54 AM UTC 24 |
| Finished | Oct 15 11:10:05 AM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994381330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.994381330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_intr.23540779 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 3990965767 ps |
| CPU time | 10.99 seconds |
| Started | Oct 15 11:08:55 AM UTC 24 |
| Finished | Oct 15 11:09:07 AM UTC 24 |
| Peak memory | 205184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23540779 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.23540779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.2217878823 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 125883812468 ps |
| CPU time | 569.31 seconds |
| Started | Oct 15 11:09:03 AM UTC 24 |
| Finished | Oct 15 11:18:40 AM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217878823 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2217878823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_loopback.2369860958 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 6840901754 ps |
| CPU time | 18.23 seconds |
| Started | Oct 15 11:09:01 AM UTC 24 |
| Finished | Oct 15 11:09:21 AM UTC 24 |
| Peak memory | 207844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369860958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2369860958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_noise_filter.3263772891 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 36062785118 ps |
| CPU time | 67.27 seconds |
| Started | Oct 15 11:08:56 AM UTC 24 |
| Finished | Oct 15 11:10:05 AM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263772891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3263772891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_perf.1327386311 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 14579265653 ps |
| CPU time | 441.46 seconds |
| Started | Oct 15 11:09:02 AM UTC 24 |
| Finished | Oct 15 11:16:30 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327386311 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1327386311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_rx_oversample.590715299 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 3535063350 ps |
| CPU time | 7.3 seconds |
| Started | Oct 15 11:08:54 AM UTC 24 |
| Finished | Oct 15 11:09:02 AM UTC 24 |
| Peak memory | 207628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590715299 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.590715299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.3752317300 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 143507349949 ps |
| CPU time | 116.08 seconds |
| Started | Oct 15 11:08:57 AM UTC 24 |
| Finished | Oct 15 11:10:55 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752317300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3752317300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.3347944147 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 2293145738 ps |
| CPU time | 2.91 seconds |
| Started | Oct 15 11:08:57 AM UTC 24 |
| Finished | Oct 15 11:09:01 AM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347944147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3347944147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_smoke.3947563386 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 517985304 ps |
| CPU time | 1.82 seconds |
| Started | Oct 15 11:08:50 AM UTC 24 |
| Finished | Oct 15 11:08:53 AM UTC 24 |
| Peak memory | 206900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947563386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3947563386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_stress_all.1800856940 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 220134746867 ps |
| CPU time | 122.96 seconds |
| Started | Oct 15 11:09:06 AM UTC 24 |
| Finished | Oct 15 11:11:12 AM UTC 24 |
| Peak memory | 225156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800856940 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1800856940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.157116488 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3277131901 ps |
| CPU time | 32.01 seconds |
| Started | Oct 15 11:09:03 AM UTC 24 |
| Finished | Oct 15 11:09:37 AM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=157116488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all_ with_rand_reset.157116488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.2303192838 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 959781460 ps |
| CPU time | 4.2 seconds |
| Started | Oct 15 11:09:00 AM UTC 24 |
| Finished | Oct 15 11:09:05 AM UTC 24 |
| Peak memory | 207404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303192838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2303192838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_tx_rx.2900118836 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 95719377970 ps |
| CPU time | 48.46 seconds |
| Started | Oct 15 11:08:51 AM UTC 24 |
| Finished | Oct 15 11:09:41 AM UTC 24 |
| Peak memory | 208884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900118836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2900118836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/37.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_alert_test.2991301140 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 17610550 ps |
| CPU time | 0.77 seconds |
| Started | Oct 15 11:09:42 AM UTC 24 |
| Finished | Oct 15 11:09:44 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991301140 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2991301140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_fifo_full.3692216061 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 26193000049 ps |
| CPU time | 60.67 seconds |
| Started | Oct 15 11:09:13 AM UTC 24 |
| Finished | Oct 15 11:10:15 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692216061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3692216061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.931466319 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 40944312438 ps |
| CPU time | 92.1 seconds |
| Started | Oct 15 11:09:14 AM UTC 24 |
| Finished | Oct 15 11:10:48 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931466319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.931466319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_fifo_reset.3031185524 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 84730169732 ps |
| CPU time | 56.32 seconds |
| Started | Oct 15 11:09:15 AM UTC 24 |
| Finished | Oct 15 11:10:13 AM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031185524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3031185524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_intr.925181348 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 48845056669 ps |
| CPU time | 11.77 seconds |
| Started | Oct 15 11:09:21 AM UTC 24 |
| Finished | Oct 15 11:09:34 AM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925181348 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.925181348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.3208405274 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 83092041436 ps |
| CPU time | 112.29 seconds |
| Started | Oct 15 11:09:35 AM UTC 24 |
| Finished | Oct 15 11:11:29 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208405274 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3208405274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_loopback.776385669 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 4638173037 ps |
| CPU time | 12.95 seconds |
| Started | Oct 15 11:09:26 AM UTC 24 |
| Finished | Oct 15 11:09:41 AM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776385669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 38.uart_loopback.776385669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_noise_filter.4107020337 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 149056744677 ps |
| CPU time | 251.9 seconds |
| Started | Oct 15 11:09:22 AM UTC 24 |
| Finished | Oct 15 11:13:38 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107020337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.4107020337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_perf.2830730048 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 19551372210 ps |
| CPU time | 1032.48 seconds |
| Started | Oct 15 11:09:28 AM UTC 24 |
| Finished | Oct 15 11:26:52 AM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830730048 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2830730048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_rx_oversample.2647297720 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2332225423 ps |
| CPU time | 26.76 seconds |
| Started | Oct 15 11:09:20 AM UTC 24 |
| Finished | Oct 15 11:09:48 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647297720 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2647297720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.2159816150 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 20900212406 ps |
| CPU time | 60.07 seconds |
| Started | Oct 15 11:09:24 AM UTC 24 |
| Finished | Oct 15 11:10:26 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159816150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2159816150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.2494680762 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 2153419830 ps |
| CPU time | 1.71 seconds |
| Started | Oct 15 11:09:24 AM UTC 24 |
| Finished | Oct 15 11:09:27 AM UTC 24 |
| Peak memory | 203884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494680762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2494680762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_smoke.654864699 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 516706522 ps |
| CPU time | 2.07 seconds |
| Started | Oct 15 11:09:09 AM UTC 24 |
| Finished | Oct 15 11:09:12 AM UTC 24 |
| Peak memory | 207332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654864699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 38.uart_smoke.654864699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_stress_all.2867746370 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 211744080658 ps |
| CPU time | 540.74 seconds |
| Started | Oct 15 11:09:38 AM UTC 24 |
| Finished | Oct 15 11:18:45 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867746370 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2867746370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.430678989 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 1703644069 ps |
| CPU time | 19.32 seconds |
| Started | Oct 15 11:09:36 AM UTC 24 |
| Finished | Oct 15 11:09:57 AM UTC 24 |
| Peak memory | 219972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=430678989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all_ with_rand_reset.430678989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.3975642237 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 6057666144 ps |
| CPU time | 34.8 seconds |
| Started | Oct 15 11:09:25 AM UTC 24 |
| Finished | Oct 15 11:10:02 AM UTC 24 |
| Peak memory | 208440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975642237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3975642237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_tx_rx.3327544833 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 30368812834 ps |
| CPU time | 48.41 seconds |
| Started | Oct 15 11:09:11 AM UTC 24 |
| Finished | Oct 15 11:10:01 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327544833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3327544833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/38.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_alert_test.509890170 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 35047436 ps |
| CPU time | 0.82 seconds |
| Started | Oct 15 11:10:06 AM UTC 24 |
| Finished | Oct 15 11:10:08 AM UTC 24 |
| Peak memory | 202300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509890170 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.509890170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_fifo_full.613316470 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 100055695967 ps |
| CPU time | 69.59 seconds |
| Started | Oct 15 11:09:43 AM UTC 24 |
| Finished | Oct 15 11:10:55 AM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613316470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.613316470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.4215110555 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 41887791904 ps |
| CPU time | 78.8 seconds |
| Started | Oct 15 11:09:44 AM UTC 24 |
| Finished | Oct 15 11:11:05 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215110555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.4215110555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_fifo_reset.162213117 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 13466094436 ps |
| CPU time | 29.05 seconds |
| Started | Oct 15 11:09:47 AM UTC 24 |
| Finished | Oct 15 11:10:18 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162213117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.162213117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_intr.2614686213 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 188933552516 ps |
| CPU time | 122.45 seconds |
| Started | Oct 15 11:09:51 AM UTC 24 |
| Finished | Oct 15 11:11:56 AM UTC 24 |
| Peak memory | 208660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614686213 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2614686213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.502762999 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 205358346750 ps |
| CPU time | 296.7 seconds |
| Started | Oct 15 11:10:05 AM UTC 24 |
| Finished | Oct 15 11:15:06 AM UTC 24 |
| Peak memory | 208632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502762999 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.502762999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_loopback.116593611 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1881341113 ps |
| CPU time | 2.91 seconds |
| Started | Oct 15 11:10:03 AM UTC 24 |
| Finished | Oct 15 11:10:07 AM UTC 24 |
| Peak memory | 205112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116593611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 39.uart_loopback.116593611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_noise_filter.993203259 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 28080685825 ps |
| CPU time | 18.08 seconds |
| Started | Oct 15 11:09:54 AM UTC 24 |
| Finished | Oct 15 11:10:14 AM UTC 24 |
| Peak memory | 205316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993203259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.993203259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_perf.1574379626 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 27151131717 ps |
| CPU time | 207.46 seconds |
| Started | Oct 15 11:10:03 AM UTC 24 |
| Finished | Oct 15 11:13:34 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574379626 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1574379626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_rx_oversample.3586769614 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1987308692 ps |
| CPU time | 13.2 seconds |
| Started | Oct 15 11:09:49 AM UTC 24 |
| Finished | Oct 15 11:10:04 AM UTC 24 |
| Peak memory | 207348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586769614 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3586769614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.2024810256 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 38324944124 ps |
| CPU time | 21.35 seconds |
| Started | Oct 15 11:09:58 AM UTC 24 |
| Finished | Oct 15 11:10:20 AM UTC 24 |
| Peak memory | 208656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024810256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2024810256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.2367722681 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 33729103079 ps |
| CPU time | 4.9 seconds |
| Started | Oct 15 11:09:57 AM UTC 24 |
| Finished | Oct 15 11:10:02 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367722681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2367722681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_smoke.3836271162 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 509823930 ps |
| CPU time | 2.99 seconds |
| Started | Oct 15 11:09:42 AM UTC 24 |
| Finished | Oct 15 11:09:46 AM UTC 24 |
| Peak memory | 207400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836271162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3836271162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_stress_all.2083041748 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 51442981021 ps |
| CPU time | 123.92 seconds |
| Started | Oct 15 11:10:06 AM UTC 24 |
| Finished | Oct 15 11:12:13 AM UTC 24 |
| Peak memory | 217696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083041748 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2083041748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.1142213393 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1377404627 ps |
| CPU time | 15.42 seconds |
| Started | Oct 15 11:10:06 AM UTC 24 |
| Finished | Oct 15 11:10:23 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1142213393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all _with_rand_reset.1142213393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.2804645075 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 253515224 ps |
| CPU time | 1.97 seconds |
| Started | Oct 15 11:10:02 AM UTC 24 |
| Finished | Oct 15 11:10:05 AM UTC 24 |
| Peak memory | 206308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804645075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2804645075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_tx_rx.2364421084 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 97099046117 ps |
| CPU time | 74.54 seconds |
| Started | Oct 15 11:09:42 AM UTC 24 |
| Finished | Oct 15 11:10:58 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364421084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2364421084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/39.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_alert_test.36451864 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 11097533 ps |
| CPU time | 0.71 seconds |
| Started | Oct 15 10:33:55 AM UTC 24 |
| Finished | Oct 15 10:33:57 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36451864 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.36451864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.1335425389 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 103359131282 ps |
| CPU time | 120.49 seconds |
| Started | Oct 15 10:31:48 AM UTC 24 |
| Finished | Oct 15 10:33:51 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335425389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1335425389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_intr.3981683404 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4029449022 ps |
| CPU time | 28.4 seconds |
| Started | Oct 15 10:32:21 AM UTC 24 |
| Finished | Oct 15 10:32:52 AM UTC 24 |
| Peak memory | 208580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981683404 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3981683404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.2515303642 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 73131778197 ps |
| CPU time | 173.09 seconds |
| Started | Oct 15 10:33:17 AM UTC 24 |
| Finished | Oct 15 10:36:13 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515303642 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2515303642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_loopback.362405266 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2082301317 ps |
| CPU time | 3.31 seconds |
| Started | Oct 15 10:32:55 AM UTC 24 |
| Finished | Oct 15 10:33:00 AM UTC 24 |
| Peak memory | 207096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362405266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 4.uart_loopback.362405266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_noise_filter.407809145 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 265119110519 ps |
| CPU time | 66.4 seconds |
| Started | Oct 15 10:32:28 AM UTC 24 |
| Finished | Oct 15 10:33:37 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407809145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.407809145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_perf.3161529100 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 7091511473 ps |
| CPU time | 310.53 seconds |
| Started | Oct 15 10:33:02 AM UTC 24 |
| Finished | Oct 15 10:38:18 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161529100 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3161529100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_rx_oversample.3965685537 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6605023184 ps |
| CPU time | 10.92 seconds |
| Started | Oct 15 10:32:15 AM UTC 24 |
| Finished | Oct 15 10:32:27 AM UTC 24 |
| Peak memory | 208324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965685537 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3965685537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.2351731916 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 42266405960 ps |
| CPU time | 103.25 seconds |
| Started | Oct 15 10:32:50 AM UTC 24 |
| Finished | Oct 15 10:34:36 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351731916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2351731916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.2480797861 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 3236893588 ps |
| CPU time | 3.34 seconds |
| Started | Oct 15 10:32:45 AM UTC 24 |
| Finished | Oct 15 10:32:50 AM UTC 24 |
| Peak memory | 205240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480797861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2480797861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_sec_cm.452265930 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 57223918 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 10:33:52 AM UTC 24 |
| Finished | Oct 15 10:33:54 AM UTC 24 |
| Peak memory | 239376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452265930 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.452265930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_smoke.3825325243 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 486513659 ps |
| CPU time | 1.8 seconds |
| Started | Oct 15 10:31:38 AM UTC 24 |
| Finished | Oct 15 10:31:41 AM UTC 24 |
| Peak memory | 207672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825325243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3825325243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.3783754647 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4069571949 ps |
| CPU time | 46.06 seconds |
| Started | Oct 15 10:33:21 AM UTC 24 |
| Finished | Oct 15 10:34:08 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3783754647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_ with_rand_reset.3783754647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.3785589562 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 816664418 ps |
| CPU time | 1.3 seconds |
| Started | Oct 15 10:32:52 AM UTC 24 |
| Finished | Oct 15 10:32:55 AM UTC 24 |
| Peak memory | 206312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785589562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3785589562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/4.uart_tx_rx.3699141753 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 40474420517 ps |
| CPU time | 98.94 seconds |
| Started | Oct 15 10:31:39 AM UTC 24 |
| Finished | Oct 15 10:33:20 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699141753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3699141753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/4.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_alert_test.1078025229 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 21155084 ps |
| CPU time | 0.83 seconds |
| Started | Oct 15 11:10:38 AM UTC 24 |
| Finished | Oct 15 11:10:39 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078025229 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1078025229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_fifo_full.1804628133 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 22152370139 ps |
| CPU time | 49.35 seconds |
| Started | Oct 15 11:10:13 AM UTC 24 |
| Finished | Oct 15 11:11:04 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804628133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1804628133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.1498094950 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 70138946534 ps |
| CPU time | 56.02 seconds |
| Started | Oct 15 11:10:14 AM UTC 24 |
| Finished | Oct 15 11:11:12 AM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498094950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1498094950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_fifo_reset.3017654435 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 21511351423 ps |
| CPU time | 37.82 seconds |
| Started | Oct 15 11:10:16 AM UTC 24 |
| Finished | Oct 15 11:10:55 AM UTC 24 |
| Peak memory | 208912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017654435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3017654435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_intr.258392129 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 154383638379 ps |
| CPU time | 236.24 seconds |
| Started | Oct 15 11:10:19 AM UTC 24 |
| Finished | Oct 15 11:14:19 AM UTC 24 |
| Peak memory | 207732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258392129 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.258392129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.1596470778 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 250781100652 ps |
| CPU time | 184.35 seconds |
| Started | Oct 15 11:10:29 AM UTC 24 |
| Finished | Oct 15 11:13:37 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596470778 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1596470778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_loopback.1024987279 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 9661561458 ps |
| CPU time | 41.27 seconds |
| Started | Oct 15 11:10:26 AM UTC 24 |
| Finished | Oct 15 11:11:09 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024987279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1024987279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_noise_filter.1888821775 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 79771260962 ps |
| CPU time | 244.34 seconds |
| Started | Oct 15 11:10:21 AM UTC 24 |
| Finished | Oct 15 11:14:29 AM UTC 24 |
| Peak memory | 208600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888821775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1888821775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_perf.2343188655 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 7910540539 ps |
| CPU time | 228.84 seconds |
| Started | Oct 15 11:10:27 AM UTC 24 |
| Finished | Oct 15 11:14:19 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343188655 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2343188655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_rx_oversample.3198054137 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 4449517232 ps |
| CPU time | 12.41 seconds |
| Started | Oct 15 11:10:18 AM UTC 24 |
| Finished | Oct 15 11:10:31 AM UTC 24 |
| Peak memory | 207720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198054137 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3198054137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.956039022 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 141359839561 ps |
| CPU time | 88.46 seconds |
| Started | Oct 15 11:10:24 AM UTC 24 |
| Finished | Oct 15 11:11:55 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956039022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.956039022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.1093051201 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4363613453 ps |
| CPU time | 5.27 seconds |
| Started | Oct 15 11:10:22 AM UTC 24 |
| Finished | Oct 15 11:10:28 AM UTC 24 |
| Peak memory | 205240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093051201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1093051201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_smoke.695284316 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5890913434 ps |
| CPU time | 12.5 seconds |
| Started | Oct 15 11:10:07 AM UTC 24 |
| Finished | Oct 15 11:10:21 AM UTC 24 |
| Peak memory | 208684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695284316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 40.uart_smoke.695284316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_stress_all.3140127175 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 98001526444 ps |
| CPU time | 219.79 seconds |
| Started | Oct 15 11:10:32 AM UTC 24 |
| Finished | Oct 15 11:14:15 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140127175 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3140127175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.1850476848 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 7318745233 ps |
| CPU time | 30.96 seconds |
| Started | Oct 15 11:10:30 AM UTC 24 |
| Finished | Oct 15 11:11:03 AM UTC 24 |
| Peak memory | 222052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1850476848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all _with_rand_reset.1850476848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.752820678 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 1418720848 ps |
| CPU time | 4.23 seconds |
| Started | Oct 15 11:10:24 AM UTC 24 |
| Finished | Oct 15 11:10:29 AM UTC 24 |
| Peak memory | 208676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752820678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.752820678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_tx_rx.4044287212 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 2049259424 ps |
| CPU time | 7.84 seconds |
| Started | Oct 15 11:10:08 AM UTC 24 |
| Finished | Oct 15 11:10:17 AM UTC 24 |
| Peak memory | 207092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044287212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4044287212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/40.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_alert_test.2821796249 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 14363304 ps |
| CPU time | 0.84 seconds |
| Started | Oct 15 11:11:14 AM UTC 24 |
| Finished | Oct 15 11:11:17 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821796249 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2821796249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_fifo_full.2357378223 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 114469189340 ps |
| CPU time | 140.37 seconds |
| Started | Oct 15 11:10:44 AM UTC 24 |
| Finished | Oct 15 11:13:07 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357378223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2357378223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.3454601121 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 44420176316 ps |
| CPU time | 98.35 seconds |
| Started | Oct 15 11:10:49 AM UTC 24 |
| Finished | Oct 15 11:12:29 AM UTC 24 |
| Peak memory | 208436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454601121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3454601121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_fifo_reset.1252498707 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 59760083603 ps |
| CPU time | 54.49 seconds |
| Started | Oct 15 11:10:55 AM UTC 24 |
| Finished | Oct 15 11:11:51 AM UTC 24 |
| Peak memory | 208456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252498707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1252498707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_intr.2096458973 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 203751714937 ps |
| CPU time | 319.17 seconds |
| Started | Oct 15 11:10:56 AM UTC 24 |
| Finished | Oct 15 11:16:19 AM UTC 24 |
| Peak memory | 208480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096458973 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2096458973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.1580011337 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 100188839218 ps |
| CPU time | 296.1 seconds |
| Started | Oct 15 11:11:12 AM UTC 24 |
| Finished | Oct 15 11:16:12 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580011337 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1580011337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_loopback.2856964915 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 5154715971 ps |
| CPU time | 23.7 seconds |
| Started | Oct 15 11:11:10 AM UTC 24 |
| Finished | Oct 15 11:11:35 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856964915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2856964915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_noise_filter.1269958686 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 87823617485 ps |
| CPU time | 39.71 seconds |
| Started | Oct 15 11:10:59 AM UTC 24 |
| Finished | Oct 15 11:11:40 AM UTC 24 |
| Peak memory | 207916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269958686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1269958686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_perf.4045653984 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 17471151454 ps |
| CPU time | 255.68 seconds |
| Started | Oct 15 11:11:10 AM UTC 24 |
| Finished | Oct 15 11:15:29 AM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045653984 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.4045653984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_rx_oversample.318432749 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 3484470461 ps |
| CPU time | 15.88 seconds |
| Started | Oct 15 11:10:56 AM UTC 24 |
| Finished | Oct 15 11:11:13 AM UTC 24 |
| Peak memory | 207420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318432749 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.318432749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.1642145229 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 14742178746 ps |
| CPU time | 38.02 seconds |
| Started | Oct 15 11:11:05 AM UTC 24 |
| Finished | Oct 15 11:11:45 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642145229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1642145229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.2833833712 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 40351307738 ps |
| CPU time | 32.94 seconds |
| Started | Oct 15 11:11:03 AM UTC 24 |
| Finished | Oct 15 11:11:38 AM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833833712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2833833712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_smoke.1409160991 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 298170616 ps |
| CPU time | 1.57 seconds |
| Started | Oct 15 11:10:41 AM UTC 24 |
| Finished | Oct 15 11:10:43 AM UTC 24 |
| Peak memory | 206696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409160991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1409160991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_stress_all.1502329809 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 87894488744 ps |
| CPU time | 1569.96 seconds |
| Started | Oct 15 11:11:13 AM UTC 24 |
| Finished | Oct 15 11:37:40 AM UTC 24 |
| Peak memory | 212236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502329809 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1502329809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.1291103464 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 24248402089 ps |
| CPU time | 59.2 seconds |
| Started | Oct 15 11:11:13 AM UTC 24 |
| Finished | Oct 15 11:12:14 AM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1291103464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all _with_rand_reset.1291103464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.3486770879 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 9103537240 ps |
| CPU time | 2.62 seconds |
| Started | Oct 15 11:11:05 AM UTC 24 |
| Finished | Oct 15 11:11:09 AM UTC 24 |
| Peak memory | 208356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486770879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3486770879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_tx_rx.1629270660 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 71046788408 ps |
| CPU time | 142.48 seconds |
| Started | Oct 15 11:10:42 AM UTC 24 |
| Finished | Oct 15 11:13:06 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629270660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1629270660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/41.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_alert_test.1482189763 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 12625391 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 11:11:55 AM UTC 24 |
| Finished | Oct 15 11:11:57 AM UTC 24 |
| Peak memory | 202340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482189763 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1482189763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_fifo_full.337856953 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 290205346727 ps |
| CPU time | 109.33 seconds |
| Started | Oct 15 11:11:20 AM UTC 24 |
| Finished | Oct 15 11:13:12 AM UTC 24 |
| Peak memory | 208812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337856953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.337856953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.616639354 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 78528819997 ps |
| CPU time | 38.86 seconds |
| Started | Oct 15 11:11:21 AM UTC 24 |
| Finished | Oct 15 11:12:02 AM UTC 24 |
| Peak memory | 208464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616639354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.616639354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_fifo_reset.2928952977 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 34273317270 ps |
| CPU time | 48.61 seconds |
| Started | Oct 15 11:11:22 AM UTC 24 |
| Finished | Oct 15 11:12:13 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928952977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2928952977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_intr.2019887629 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 89933808125 ps |
| CPU time | 63.03 seconds |
| Started | Oct 15 11:11:35 AM UTC 24 |
| Finished | Oct 15 11:12:40 AM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019887629 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2019887629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.193671456 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 170194502733 ps |
| CPU time | 883.44 seconds |
| Started | Oct 15 11:11:46 AM UTC 24 |
| Finished | Oct 15 11:26:39 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193671456 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.193671456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_loopback.2205087936 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 3615317164 ps |
| CPU time | 14.56 seconds |
| Started | Oct 15 11:11:46 AM UTC 24 |
| Finished | Oct 15 11:12:02 AM UTC 24 |
| Peak memory | 208412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205087936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2205087936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_noise_filter.3822834367 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 162828121275 ps |
| CPU time | 88.86 seconds |
| Started | Oct 15 11:11:39 AM UTC 24 |
| Finished | Oct 15 11:13:09 AM UTC 24 |
| Peak memory | 217672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822834367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3822834367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_perf.4047098850 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 10866739570 ps |
| CPU time | 575.34 seconds |
| Started | Oct 15 11:11:46 AM UTC 24 |
| Finished | Oct 15 11:21:28 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047098850 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.4047098850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_rx_oversample.2731938574 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 6634327768 ps |
| CPU time | 13.22 seconds |
| Started | Oct 15 11:11:30 AM UTC 24 |
| Finished | Oct 15 11:11:45 AM UTC 24 |
| Peak memory | 207432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731938574 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2731938574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.3747383267 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 158866685191 ps |
| CPU time | 76.17 seconds |
| Started | Oct 15 11:11:43 AM UTC 24 |
| Finished | Oct 15 11:13:01 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747383267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3747383267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.3915809549 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 31524383177 ps |
| CPU time | 66.48 seconds |
| Started | Oct 15 11:11:41 AM UTC 24 |
| Finished | Oct 15 11:12:49 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915809549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3915809549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_smoke.4070241680 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 314141694 ps |
| CPU time | 1.62 seconds |
| Started | Oct 15 11:11:16 AM UTC 24 |
| Finished | Oct 15 11:11:19 AM UTC 24 |
| Peak memory | 206252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070241680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.uart_smoke.4070241680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_stress_all.1810389545 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 307617166519 ps |
| CPU time | 380.94 seconds |
| Started | Oct 15 11:11:52 AM UTC 24 |
| Finished | Oct 15 11:18:18 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810389545 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1810389545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.561074343 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 4192304110 ps |
| CPU time | 12.8 seconds |
| Started | Oct 15 11:11:49 AM UTC 24 |
| Finished | Oct 15 11:12:03 AM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=561074343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all_ with_rand_reset.561074343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.4084442903 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 1520042225 ps |
| CPU time | 2.92 seconds |
| Started | Oct 15 11:11:44 AM UTC 24 |
| Finished | Oct 15 11:11:48 AM UTC 24 |
| Peak memory | 207868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084442903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.4084442903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_tx_rx.2198579177 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 60647422218 ps |
| CPU time | 42.34 seconds |
| Started | Oct 15 11:11:17 AM UTC 24 |
| Finished | Oct 15 11:12:01 AM UTC 24 |
| Peak memory | 207996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198579177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2198579177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/42.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_alert_test.1218408860 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 16368365 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 11:12:20 AM UTC 24 |
| Finished | Oct 15 11:12:21 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218408860 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1218408860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_fifo_full.2606286396 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 55021818333 ps |
| CPU time | 29.6 seconds |
| Started | Oct 15 11:11:58 AM UTC 24 |
| Finished | Oct 15 11:12:29 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606286396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2606286396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.1405533612 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 28425664334 ps |
| CPU time | 41.09 seconds |
| Started | Oct 15 11:12:02 AM UTC 24 |
| Finished | Oct 15 11:12:44 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405533612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1405533612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_fifo_reset.1114719517 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 10539250197 ps |
| CPU time | 26.62 seconds |
| Started | Oct 15 11:12:03 AM UTC 24 |
| Finished | Oct 15 11:12:31 AM UTC 24 |
| Peak memory | 208544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114719517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1114719517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_intr.60302037 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 4285005712 ps |
| CPU time | 17.48 seconds |
| Started | Oct 15 11:12:04 AM UTC 24 |
| Finished | Oct 15 11:12:22 AM UTC 24 |
| Peak memory | 208048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60302037 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.60302037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.2398360820 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 109493460448 ps |
| CPU time | 812.63 seconds |
| Started | Oct 15 11:12:15 AM UTC 24 |
| Finished | Oct 15 11:25:58 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398360820 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2398360820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_loopback.994801758 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 5118308711 ps |
| CPU time | 20.46 seconds |
| Started | Oct 15 11:12:13 AM UTC 24 |
| Finished | Oct 15 11:12:35 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994801758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 43.uart_loopback.994801758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_noise_filter.2268895278 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 168813747775 ps |
| CPU time | 80.33 seconds |
| Started | Oct 15 11:12:06 AM UTC 24 |
| Finished | Oct 15 11:13:28 AM UTC 24 |
| Peak memory | 208976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268895278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2268895278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_perf.511653963 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 8676587426 ps |
| CPU time | 134.98 seconds |
| Started | Oct 15 11:12:15 AM UTC 24 |
| Finished | Oct 15 11:14:33 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511653963 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.511653963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_rx_oversample.2922521544 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 4556582541 ps |
| CPU time | 7.72 seconds |
| Started | Oct 15 11:12:03 AM UTC 24 |
| Finished | Oct 15 11:12:12 AM UTC 24 |
| Peak memory | 207484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922521544 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2922521544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.2471953156 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 60288610410 ps |
| CPU time | 45.25 seconds |
| Started | Oct 15 11:12:12 AM UTC 24 |
| Finished | Oct 15 11:12:59 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471953156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2471953156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.422587419 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2841035273 ps |
| CPU time | 3.99 seconds |
| Started | Oct 15 11:12:09 AM UTC 24 |
| Finished | Oct 15 11:12:14 AM UTC 24 |
| Peak memory | 205184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422587419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.422587419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_smoke.3274124532 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 6237823952 ps |
| CPU time | 16.97 seconds |
| Started | Oct 15 11:11:56 AM UTC 24 |
| Finished | Oct 15 11:12:15 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274124532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3274124532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_stress_all.1827959550 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 188038654891 ps |
| CPU time | 463.28 seconds |
| Started | Oct 15 11:12:19 AM UTC 24 |
| Finished | Oct 15 11:20:07 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827959550 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1827959550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.1753174365 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 3591915254 ps |
| CPU time | 58.36 seconds |
| Started | Oct 15 11:12:15 AM UTC 24 |
| Finished | Oct 15 11:13:16 AM UTC 24 |
| Peak memory | 224596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1753174365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all _with_rand_reset.1753174365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.70890122 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 965788115 ps |
| CPU time | 4.11 seconds |
| Started | Oct 15 11:12:13 AM UTC 24 |
| Finished | Oct 15 11:12:18 AM UTC 24 |
| Peak memory | 207720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70890122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.70890122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_tx_rx.2640142045 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 6165800011 ps |
| CPU time | 6.21 seconds |
| Started | Oct 15 11:11:57 AM UTC 24 |
| Finished | Oct 15 11:12:05 AM UTC 24 |
| Peak memory | 208536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640142045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2640142045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/43.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_alert_test.3912407234 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 140822365 ps |
| CPU time | 0.82 seconds |
| Started | Oct 15 11:12:54 AM UTC 24 |
| Finished | Oct 15 11:12:56 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912407234 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3912407234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_fifo_full.3199458877 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 21440280416 ps |
| CPU time | 36.95 seconds |
| Started | Oct 15 11:12:26 AM UTC 24 |
| Finished | Oct 15 11:13:04 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199458877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3199458877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.2882723072 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 144069683736 ps |
| CPU time | 40.75 seconds |
| Started | Oct 15 11:12:29 AM UTC 24 |
| Finished | Oct 15 11:13:11 AM UTC 24 |
| Peak memory | 208352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882723072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2882723072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_fifo_reset.2250151551 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 22074854398 ps |
| CPU time | 52.25 seconds |
| Started | Oct 15 11:12:30 AM UTC 24 |
| Finished | Oct 15 11:13:24 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250151551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2250151551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_intr.564760435 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 18389591634 ps |
| CPU time | 40.56 seconds |
| Started | Oct 15 11:12:35 AM UTC 24 |
| Finished | Oct 15 11:13:17 AM UTC 24 |
| Peak memory | 208576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564760435 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.564760435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.373911810 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 128609196473 ps |
| CPU time | 230.79 seconds |
| Started | Oct 15 11:12:54 AM UTC 24 |
| Finished | Oct 15 11:16:49 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373911810 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.373911810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_loopback.2392064958 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 997458514 ps |
| CPU time | 1.45 seconds |
| Started | Oct 15 11:12:50 AM UTC 24 |
| Finished | Oct 15 11:12:53 AM UTC 24 |
| Peak memory | 206368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392064958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2392064958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_noise_filter.2039862041 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 80904748780 ps |
| CPU time | 98.64 seconds |
| Started | Oct 15 11:12:36 AM UTC 24 |
| Finished | Oct 15 11:14:17 AM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039862041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2039862041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_perf.3162890224 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 37619119887 ps |
| CPU time | 1872.91 seconds |
| Started | Oct 15 11:12:53 AM UTC 24 |
| Finished | Oct 15 11:44:28 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162890224 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3162890224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_rx_oversample.3622934672 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2348953531 ps |
| CPU time | 5.78 seconds |
| Started | Oct 15 11:12:31 AM UTC 24 |
| Finished | Oct 15 11:12:38 AM UTC 24 |
| Peak memory | 205356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622934672 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3622934672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.2982777783 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 50223937530 ps |
| CPU time | 153.23 seconds |
| Started | Oct 15 11:12:41 AM UTC 24 |
| Finished | Oct 15 11:15:17 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982777783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2982777783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.3151812077 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 3120877472 ps |
| CPU time | 12.4 seconds |
| Started | Oct 15 11:12:39 AM UTC 24 |
| Finished | Oct 15 11:12:53 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151812077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3151812077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_smoke.385459262 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 330206699 ps |
| CPU time | 1.51 seconds |
| Started | Oct 15 11:12:23 AM UTC 24 |
| Finished | Oct 15 11:12:25 AM UTC 24 |
| Peak memory | 206240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385459262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 44.uart_smoke.385459262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_stress_all.437583920 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 357981184821 ps |
| CPU time | 871.18 seconds |
| Started | Oct 15 11:12:54 AM UTC 24 |
| Finished | Oct 15 11:27:36 AM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437583920 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.437583920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.2793488813 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2857023789 ps |
| CPU time | 37.46 seconds |
| Started | Oct 15 11:12:54 AM UTC 24 |
| Finished | Oct 15 11:13:33 AM UTC 24 |
| Peak memory | 221996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2793488813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all _with_rand_reset.2793488813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.1161334500 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 813234306 ps |
| CPU time | 7.31 seconds |
| Started | Oct 15 11:12:45 AM UTC 24 |
| Finished | Oct 15 11:12:53 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161334500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1161334500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_tx_rx.2201666132 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 63954851510 ps |
| CPU time | 46.21 seconds |
| Started | Oct 15 11:12:24 AM UTC 24 |
| Finished | Oct 15 11:13:12 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201666132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2201666132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/44.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_alert_test.1876712824 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 49070066 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 11:13:21 AM UTC 24 |
| Finished | Oct 15 11:13:23 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876712824 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1876712824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_fifo_full.2324622008 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 187418662770 ps |
| CPU time | 32.09 seconds |
| Started | Oct 15 11:13:01 AM UTC 24 |
| Finished | Oct 15 11:13:35 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324622008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2324622008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.739267498 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 133989765118 ps |
| CPU time | 114.79 seconds |
| Started | Oct 15 11:13:05 AM UTC 24 |
| Finished | Oct 15 11:15:02 AM UTC 24 |
| Peak memory | 208592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739267498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.739267498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_fifo_reset.3484529089 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 115964949510 ps |
| CPU time | 96.87 seconds |
| Started | Oct 15 11:13:07 AM UTC 24 |
| Finished | Oct 15 11:14:46 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484529089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3484529089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_intr.4276638411 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 9781870381 ps |
| CPU time | 30.9 seconds |
| Started | Oct 15 11:13:10 AM UTC 24 |
| Finished | Oct 15 11:13:42 AM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276638411 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.4276638411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.3109471431 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 111828784957 ps |
| CPU time | 240.83 seconds |
| Started | Oct 15 11:13:18 AM UTC 24 |
| Finished | Oct 15 11:17:23 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109471431 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3109471431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_loopback.1270761758 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 3636381164 ps |
| CPU time | 5.29 seconds |
| Started | Oct 15 11:13:13 AM UTC 24 |
| Finished | Oct 15 11:13:20 AM UTC 24 |
| Peak memory | 207980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270761758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1270761758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_noise_filter.2884850281 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 50343616469 ps |
| CPU time | 32.32 seconds |
| Started | Oct 15 11:13:11 AM UTC 24 |
| Finished | Oct 15 11:13:45 AM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884850281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2884850281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_perf.963040743 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 16349922319 ps |
| CPU time | 162.12 seconds |
| Started | Oct 15 11:13:16 AM UTC 24 |
| Finished | Oct 15 11:16:01 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963040743 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.963040743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_rx_oversample.1283154535 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 4149254063 ps |
| CPU time | 30.43 seconds |
| Started | Oct 15 11:13:08 AM UTC 24 |
| Finished | Oct 15 11:13:39 AM UTC 24 |
| Peak memory | 207336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283154535 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1283154535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.3927453615 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 39095062551 ps |
| CPU time | 21.18 seconds |
| Started | Oct 15 11:13:12 AM UTC 24 |
| Finished | Oct 15 11:13:34 AM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927453615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3927453615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.2822921032 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 2094684330 ps |
| CPU time | 7.79 seconds |
| Started | Oct 15 11:13:12 AM UTC 24 |
| Finished | Oct 15 11:13:21 AM UTC 24 |
| Peak memory | 205040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822921032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2822921032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_smoke.2421521404 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 5575519975 ps |
| CPU time | 11.97 seconds |
| Started | Oct 15 11:12:57 AM UTC 24 |
| Finished | Oct 15 11:13:11 AM UTC 24 |
| Peak memory | 207428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421521404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2421521404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_stress_all.1481780037 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 142980515083 ps |
| CPU time | 92.67 seconds |
| Started | Oct 15 11:13:21 AM UTC 24 |
| Finished | Oct 15 11:14:56 AM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481780037 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1481780037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.3836609421 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 10211604302 ps |
| CPU time | 79.87 seconds |
| Started | Oct 15 11:13:20 AM UTC 24 |
| Finished | Oct 15 11:14:42 AM UTC 24 |
| Peak memory | 225376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3836609421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all _with_rand_reset.3836609421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.2075268536 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 6073675141 ps |
| CPU time | 24.9 seconds |
| Started | Oct 15 11:13:13 AM UTC 24 |
| Finished | Oct 15 11:13:39 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075268536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2075268536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_tx_rx.2158658055 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 94917971345 ps |
| CPU time | 281.61 seconds |
| Started | Oct 15 11:13:00 AM UTC 24 |
| Finished | Oct 15 11:17:46 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158658055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2158658055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/45.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_alert_test.1343754172 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 20321466 ps |
| CPU time | 0.76 seconds |
| Started | Oct 15 11:14:00 AM UTC 24 |
| Finished | Oct 15 11:14:01 AM UTC 24 |
| Peak memory | 204388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343754172 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1343754172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_fifo_full.1010269895 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 152256669356 ps |
| CPU time | 213.25 seconds |
| Started | Oct 15 11:13:29 AM UTC 24 |
| Finished | Oct 15 11:17:05 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010269895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1010269895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.1866991821 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 100636115702 ps |
| CPU time | 92.53 seconds |
| Started | Oct 15 11:13:29 AM UTC 24 |
| Finished | Oct 15 11:15:03 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866991821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1866991821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_fifo_reset.3048209416 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 49900487888 ps |
| CPU time | 24.07 seconds |
| Started | Oct 15 11:13:34 AM UTC 24 |
| Finished | Oct 15 11:13:59 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048209416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3048209416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_intr.4011533935 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 138935257484 ps |
| CPU time | 226.21 seconds |
| Started | Oct 15 11:13:35 AM UTC 24 |
| Finished | Oct 15 11:17:24 AM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011533935 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.4011533935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.4225963789 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 106853474686 ps |
| CPU time | 342.59 seconds |
| Started | Oct 15 11:13:44 AM UTC 24 |
| Finished | Oct 15 11:19:31 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225963789 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.4225963789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_loopback.359283397 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1329299853 ps |
| CPU time | 5.51 seconds |
| Started | Oct 15 11:13:40 AM UTC 24 |
| Finished | Oct 15 11:13:47 AM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359283397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 46.uart_loopback.359283397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_noise_filter.826628168 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 146225985067 ps |
| CPU time | 79.2 seconds |
| Started | Oct 15 11:13:36 AM UTC 24 |
| Finished | Oct 15 11:14:57 AM UTC 24 |
| Peak memory | 208516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826628168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.826628168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_perf.462214178 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 16176701595 ps |
| CPU time | 108.55 seconds |
| Started | Oct 15 11:13:43 AM UTC 24 |
| Finished | Oct 15 11:15:34 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462214178 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.462214178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_rx_oversample.2869916614 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 7143809900 ps |
| CPU time | 76.47 seconds |
| Started | Oct 15 11:13:35 AM UTC 24 |
| Finished | Oct 15 11:14:53 AM UTC 24 |
| Peak memory | 207412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869916614 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2869916614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.2217945071 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 54859284409 ps |
| CPU time | 102.9 seconds |
| Started | Oct 15 11:13:38 AM UTC 24 |
| Finished | Oct 15 11:15:23 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217945071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2217945071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.886620371 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 38466045335 ps |
| CPU time | 20.5 seconds |
| Started | Oct 15 11:13:37 AM UTC 24 |
| Finished | Oct 15 11:13:59 AM UTC 24 |
| Peak memory | 205248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886620371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.886620371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_smoke.2228513117 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 465349094 ps |
| CPU time | 2.46 seconds |
| Started | Oct 15 11:13:24 AM UTC 24 |
| Finished | Oct 15 11:13:28 AM UTC 24 |
| Peak memory | 208540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228513117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2228513117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_stress_all.1668415591 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 240887368037 ps |
| CPU time | 619.87 seconds |
| Started | Oct 15 11:13:48 AM UTC 24 |
| Finished | Oct 15 11:24:15 AM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668415591 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1668415591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.3456511509 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 2387621892 ps |
| CPU time | 41.57 seconds |
| Started | Oct 15 11:13:45 AM UTC 24 |
| Finished | Oct 15 11:14:28 AM UTC 24 |
| Peak memory | 208948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3456511509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all _with_rand_reset.3456511509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.1267969144 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 802726671 ps |
| CPU time | 2.17 seconds |
| Started | Oct 15 11:13:40 AM UTC 24 |
| Finished | Oct 15 11:13:43 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267969144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1267969144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_tx_rx.1274726002 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 165938976562 ps |
| CPU time | 453.82 seconds |
| Started | Oct 15 11:13:24 AM UTC 24 |
| Finished | Oct 15 11:21:04 AM UTC 24 |
| Peak memory | 208668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274726002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1274726002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/46.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_alert_test.1379558574 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 17110977 ps |
| CPU time | 0.8 seconds |
| Started | Oct 15 11:14:47 AM UTC 24 |
| Finished | Oct 15 11:14:49 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379558574 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1379558574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_fifo_full.2893205360 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 75234619890 ps |
| CPU time | 51.93 seconds |
| Started | Oct 15 11:14:03 AM UTC 24 |
| Finished | Oct 15 11:14:56 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893205360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2893205360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.3527591915 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 199921625162 ps |
| CPU time | 61.95 seconds |
| Started | Oct 15 11:14:14 AM UTC 24 |
| Finished | Oct 15 11:15:18 AM UTC 24 |
| Peak memory | 208804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527591915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3527591915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_fifo_reset.2400612231 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 106426102981 ps |
| CPU time | 130.05 seconds |
| Started | Oct 15 11:14:16 AM UTC 24 |
| Finished | Oct 15 11:16:28 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400612231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2400612231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_intr.179921551 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 85061895030 ps |
| CPU time | 22.8 seconds |
| Started | Oct 15 11:14:18 AM UTC 24 |
| Finished | Oct 15 11:14:42 AM UTC 24 |
| Peak memory | 205172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179921551 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.179921551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.1362649193 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 51109139151 ps |
| CPU time | 279.46 seconds |
| Started | Oct 15 11:14:40 AM UTC 24 |
| Finished | Oct 15 11:19:24 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362649193 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1362649193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_loopback.1924287381 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 5410550428 ps |
| CPU time | 21.27 seconds |
| Started | Oct 15 11:14:30 AM UTC 24 |
| Finished | Oct 15 11:14:52 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924287381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1924287381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_noise_filter.2735908495 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 67697935687 ps |
| CPU time | 66.65 seconds |
| Started | Oct 15 11:14:19 AM UTC 24 |
| Finished | Oct 15 11:15:28 AM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735908495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2735908495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_perf.3453876257 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 9744476379 ps |
| CPU time | 463.76 seconds |
| Started | Oct 15 11:14:34 AM UTC 24 |
| Finished | Oct 15 11:22:23 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453876257 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3453876257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_rx_oversample.4138728124 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 6118503230 ps |
| CPU time | 33.29 seconds |
| Started | Oct 15 11:14:18 AM UTC 24 |
| Finished | Oct 15 11:14:53 AM UTC 24 |
| Peak memory | 207412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138728124 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4138728124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.1347837393 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 27512307038 ps |
| CPU time | 44.8 seconds |
| Started | Oct 15 11:14:26 AM UTC 24 |
| Finished | Oct 15 11:15:12 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347837393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1347837393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.3717860431 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2523045515 ps |
| CPU time | 3.1 seconds |
| Started | Oct 15 11:14:20 AM UTC 24 |
| Finished | Oct 15 11:14:25 AM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717860431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3717860431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_smoke.1886128975 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 292265216 ps |
| CPU time | 1.65 seconds |
| Started | Oct 15 11:14:00 AM UTC 24 |
| Finished | Oct 15 11:14:02 AM UTC 24 |
| Peak memory | 206256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886128975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1886128975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_stress_all.1660792657 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 91054712549 ps |
| CPU time | 835.31 seconds |
| Started | Oct 15 11:14:43 AM UTC 24 |
| Finished | Oct 15 11:28:48 AM UTC 24 |
| Peak memory | 223228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660792657 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1660792657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.164343139 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 4035163696 ps |
| CPU time | 127.95 seconds |
| Started | Oct 15 11:14:43 AM UTC 24 |
| Finished | Oct 15 11:16:54 AM UTC 24 |
| Peak memory | 217916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=164343139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all_ with_rand_reset.164343139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.102623108 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1226693607 ps |
| CPU time | 8.39 seconds |
| Started | Oct 15 11:14:30 AM UTC 24 |
| Finished | Oct 15 11:14:39 AM UTC 24 |
| Peak memory | 207200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102623108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.102623108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_tx_rx.2039958692 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 154775814660 ps |
| CPU time | 451.9 seconds |
| Started | Oct 15 11:14:02 AM UTC 24 |
| Finished | Oct 15 11:21:40 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039958692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2039958692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/47.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_alert_test.2360396350 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 13885020 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 11:15:18 AM UTC 24 |
| Finished | Oct 15 11:15:20 AM UTC 24 |
| Peak memory | 202340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360396350 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2360396350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_fifo_full.1199574623 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 175766206605 ps |
| CPU time | 625.47 seconds |
| Started | Oct 15 11:14:53 AM UTC 24 |
| Finished | Oct 15 11:25:26 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199574623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1199574623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.666506445 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 49497696979 ps |
| CPU time | 33.1 seconds |
| Started | Oct 15 11:14:54 AM UTC 24 |
| Finished | Oct 15 11:15:29 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666506445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.666506445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_intr.4285152875 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 18866053318 ps |
| CPU time | 18.2 seconds |
| Started | Oct 15 11:14:58 AM UTC 24 |
| Finished | Oct 15 11:15:17 AM UTC 24 |
| Peak memory | 208960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285152875 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.4285152875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.418417300 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 130849284084 ps |
| CPU time | 168.47 seconds |
| Started | Oct 15 11:15:13 AM UTC 24 |
| Finished | Oct 15 11:18:05 AM UTC 24 |
| Peak memory | 208884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418417300 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.418417300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_loopback.1004947135 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 12538617269 ps |
| CPU time | 19.31 seconds |
| Started | Oct 15 11:15:12 AM UTC 24 |
| Finished | Oct 15 11:15:33 AM UTC 24 |
| Peak memory | 208608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004947135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1004947135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_noise_filter.2416402743 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 62954633898 ps |
| CPU time | 91.65 seconds |
| Started | Oct 15 11:15:04 AM UTC 24 |
| Finished | Oct 15 11:16:37 AM UTC 24 |
| Peak memory | 208544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416402743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2416402743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_perf.3418347402 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 15625140587 ps |
| CPU time | 174.75 seconds |
| Started | Oct 15 11:15:12 AM UTC 24 |
| Finished | Oct 15 11:18:10 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418347402 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3418347402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_rx_oversample.390129205 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 3034016671 ps |
| CPU time | 26.8 seconds |
| Started | Oct 15 11:14:58 AM UTC 24 |
| Finished | Oct 15 11:15:26 AM UTC 24 |
| Peak memory | 207356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390129205 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.390129205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.1735341571 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 11077802043 ps |
| CPU time | 25.26 seconds |
| Started | Oct 15 11:15:06 AM UTC 24 |
| Finished | Oct 15 11:15:32 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735341571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1735341571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.239043762 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 45073289597 ps |
| CPU time | 35.8 seconds |
| Started | Oct 15 11:15:04 AM UTC 24 |
| Finished | Oct 15 11:15:41 AM UTC 24 |
| Peak memory | 205184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239043762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.239043762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_smoke.3520999109 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 5641044670 ps |
| CPU time | 14.03 seconds |
| Started | Oct 15 11:14:50 AM UTC 24 |
| Finished | Oct 15 11:15:05 AM UTC 24 |
| Peak memory | 208608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520999109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3520999109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_stress_all.22223794 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 438028852681 ps |
| CPU time | 537.87 seconds |
| Started | Oct 15 11:15:18 AM UTC 24 |
| Finished | Oct 15 11:24:22 AM UTC 24 |
| Peak memory | 217792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22223794 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.22223794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.479911915 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 7384614545 ps |
| CPU time | 20.58 seconds |
| Started | Oct 15 11:15:18 AM UTC 24 |
| Finished | Oct 15 11:15:40 AM UTC 24 |
| Peak memory | 217748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=479911915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all_ with_rand_reset.479911915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.217499222 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 2023765218 ps |
| CPU time | 3.65 seconds |
| Started | Oct 15 11:15:07 AM UTC 24 |
| Finished | Oct 15 11:15:12 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217499222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.217499222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_tx_rx.2313980214 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 91376786934 ps |
| CPU time | 24.29 seconds |
| Started | Oct 15 11:14:53 AM UTC 24 |
| Finished | Oct 15 11:15:19 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313980214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2313980214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/48.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_alert_test.145038423 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 51174141 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 11:15:41 AM UTC 24 |
| Finished | Oct 15 11:15:43 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145038423 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.145038423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_fifo_full.1134651504 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 95479030584 ps |
| CPU time | 56.1 seconds |
| Started | Oct 15 11:15:21 AM UTC 24 |
| Finished | Oct 15 11:16:18 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134651504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1134651504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.1865202042 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 16260450493 ps |
| CPU time | 29.82 seconds |
| Started | Oct 15 11:15:23 AM UTC 24 |
| Finished | Oct 15 11:15:54 AM UTC 24 |
| Peak memory | 208632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865202042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1865202042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_intr.1107027758 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 13227468542 ps |
| CPU time | 3.44 seconds |
| Started | Oct 15 11:15:29 AM UTC 24 |
| Finished | Oct 15 11:15:33 AM UTC 24 |
| Peak memory | 205180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107027758 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1107027758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.337222965 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 303378779297 ps |
| CPU time | 287.82 seconds |
| Started | Oct 15 11:15:36 AM UTC 24 |
| Finished | Oct 15 11:20:28 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337222965 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.337222965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_loopback.3009130016 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 7377427629 ps |
| CPU time | 15.91 seconds |
| Started | Oct 15 11:15:34 AM UTC 24 |
| Finished | Oct 15 11:15:51 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009130016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3009130016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_noise_filter.1429343905 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 55046079952 ps |
| CPU time | 113.04 seconds |
| Started | Oct 15 11:15:30 AM UTC 24 |
| Finished | Oct 15 11:17:25 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429343905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1429343905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_perf.2655360198 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 2252910062 ps |
| CPU time | 128.5 seconds |
| Started | Oct 15 11:15:35 AM UTC 24 |
| Finished | Oct 15 11:17:46 AM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655360198 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2655360198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_rx_oversample.944298782 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 2953835205 ps |
| CPU time | 9.08 seconds |
| Started | Oct 15 11:15:27 AM UTC 24 |
| Finished | Oct 15 11:15:37 AM UTC 24 |
| Peak memory | 207420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944298782 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.944298782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.2639853439 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 26430511659 ps |
| CPU time | 22.85 seconds |
| Started | Oct 15 11:15:33 AM UTC 24 |
| Finished | Oct 15 11:15:57 AM UTC 24 |
| Peak memory | 208812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639853439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2639853439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.121408634 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 3149145252 ps |
| CPU time | 4.17 seconds |
| Started | Oct 15 11:15:30 AM UTC 24 |
| Finished | Oct 15 11:15:35 AM UTC 24 |
| Peak memory | 205312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121408634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.121408634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_smoke.1137468247 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 694237110 ps |
| CPU time | 1.93 seconds |
| Started | Oct 15 11:15:18 AM UTC 24 |
| Finished | Oct 15 11:15:21 AM UTC 24 |
| Peak memory | 206256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137468247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1137468247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_stress_all.3778191599 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 313020085767 ps |
| CPU time | 920.92 seconds |
| Started | Oct 15 11:15:39 AM UTC 24 |
| Finished | Oct 15 11:31:10 AM UTC 24 |
| Peak memory | 212044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778191599 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3778191599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.374847881 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 4270331233 ps |
| CPU time | 24.96 seconds |
| Started | Oct 15 11:15:37 AM UTC 24 |
| Finished | Oct 15 11:16:04 AM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=374847881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all_ with_rand_reset.374847881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.3599162141 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 10397673418 ps |
| CPU time | 3.14 seconds |
| Started | Oct 15 11:15:33 AM UTC 24 |
| Finished | Oct 15 11:15:37 AM UTC 24 |
| Peak memory | 207632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599162141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3599162141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_tx_rx.2797368075 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 101051717492 ps |
| CPU time | 212.33 seconds |
| Started | Oct 15 11:15:19 AM UTC 24 |
| Finished | Oct 15 11:18:55 AM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797368075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2797368075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/49.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_alert_test.3360953099 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 52716135 ps |
| CPU time | 0.74 seconds |
| Started | Oct 15 10:35:38 AM UTC 24 |
| Finished | Oct 15 10:35:40 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360953099 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3360953099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_fifo_full.2783269374 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 75175239779 ps |
| CPU time | 21.87 seconds |
| Started | Oct 15 10:34:09 AM UTC 24 |
| Finished | Oct 15 10:34:32 AM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783269374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2783269374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_fifo_reset.875114426 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 38830384919 ps |
| CPU time | 13.85 seconds |
| Started | Oct 15 10:34:36 AM UTC 24 |
| Finished | Oct 15 10:34:52 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875114426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.875114426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_intr.316005599 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 11520882052 ps |
| CPU time | 3.52 seconds |
| Started | Oct 15 10:34:52 AM UTC 24 |
| Finished | Oct 15 10:34:57 AM UTC 24 |
| Peak memory | 207232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316005599 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.316005599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_loopback.3269192746 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 8017300765 ps |
| CPU time | 8.37 seconds |
| Started | Oct 15 10:35:11 AM UTC 24 |
| Finished | Oct 15 10:35:20 AM UTC 24 |
| Peak memory | 208856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269192746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3269192746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_noise_filter.3217170047 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 38150173159 ps |
| CPU time | 20.46 seconds |
| Started | Oct 15 10:34:58 AM UTC 24 |
| Finished | Oct 15 10:35:20 AM UTC 24 |
| Peak memory | 205320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217170047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3217170047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_perf.2395738229 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 6126746850 ps |
| CPU time | 338.06 seconds |
| Started | Oct 15 10:35:15 AM UTC 24 |
| Finished | Oct 15 10:40:58 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395738229 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2395738229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_rx_oversample.364641242 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 5065657972 ps |
| CPU time | 24.45 seconds |
| Started | Oct 15 10:34:36 AM UTC 24 |
| Finished | Oct 15 10:35:02 AM UTC 24 |
| Peak memory | 208364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364641242 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.364641242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.224883480 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 81720087471 ps |
| CPU time | 180.77 seconds |
| Started | Oct 15 10:35:03 AM UTC 24 |
| Finished | Oct 15 10:38:07 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224883480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.224883480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.349870695 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2377985313 ps |
| CPU time | 6.16 seconds |
| Started | Oct 15 10:35:03 AM UTC 24 |
| Finished | Oct 15 10:35:10 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349870695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.349870695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_smoke.492964079 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 279843807 ps |
| CPU time | 1.5 seconds |
| Started | Oct 15 10:33:57 AM UTC 24 |
| Finished | Oct 15 10:34:00 AM UTC 24 |
| Peak memory | 206684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492964079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 5.uart_smoke.492964079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_stress_all.2746604839 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 25376940355 ps |
| CPU time | 531.45 seconds |
| Started | Oct 15 10:35:25 AM UTC 24 |
| Finished | Oct 15 10:44:24 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746604839 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2746604839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.1686772122 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 12461353380 ps |
| CPU time | 51.41 seconds |
| Started | Oct 15 10:35:21 AM UTC 24 |
| Finished | Oct 15 10:36:14 AM UTC 24 |
| Peak memory | 217420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1686772122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_ with_rand_reset.1686772122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.442783649 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 7537691932 ps |
| CPU time | 11.61 seconds |
| Started | Oct 15 10:35:11 AM UTC 24 |
| Finished | Oct 15 10:35:23 AM UTC 24 |
| Peak memory | 208452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442783649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.442783649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/5.uart_tx_rx.1826178605 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 100405345838 ps |
| CPU time | 60.24 seconds |
| Started | Oct 15 10:34:00 AM UTC 24 |
| Finished | Oct 15 10:35:02 AM UTC 24 |
| Peak memory | 208632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826178605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1826178605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/50.uart_fifo_reset.2906120289 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 125313429207 ps |
| CPU time | 37.86 seconds |
| Started | Oct 15 11:15:42 AM UTC 24 |
| Finished | Oct 15 11:16:21 AM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906120289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2906120289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/50.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.1225297767 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 10547149368 ps |
| CPU time | 42.89 seconds |
| Started | Oct 15 11:15:43 AM UTC 24 |
| Finished | Oct 15 11:16:27 AM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1225297767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all _with_rand_reset.1225297767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/51.uart_fifo_reset.1746545416 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 63271399070 ps |
| CPU time | 48.56 seconds |
| Started | Oct 15 11:15:44 AM UTC 24 |
| Finished | Oct 15 11:16:34 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746545416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1746545416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/51.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.810120972 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 1836647014 ps |
| CPU time | 21.87 seconds |
| Started | Oct 15 11:15:52 AM UTC 24 |
| Finished | Oct 15 11:16:15 AM UTC 24 |
| Peak memory | 217728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=810120972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all_ with_rand_reset.810120972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/52.uart_fifo_reset.3965358189 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 18343866489 ps |
| CPU time | 59.73 seconds |
| Started | Oct 15 11:15:55 AM UTC 24 |
| Finished | Oct 15 11:16:56 AM UTC 24 |
| Peak memory | 208560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965358189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3965358189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/52.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.3461683124 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 2035027581 ps |
| CPU time | 40.48 seconds |
| Started | Oct 15 11:15:58 AM UTC 24 |
| Finished | Oct 15 11:16:40 AM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3461683124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all _with_rand_reset.3461683124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/53.uart_fifo_reset.503953501 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 17679689723 ps |
| CPU time | 37.8 seconds |
| Started | Oct 15 11:16:01 AM UTC 24 |
| Finished | Oct 15 11:16:41 AM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503953501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.503953501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/53.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.4252183833 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3551297295 ps |
| CPU time | 25.49 seconds |
| Started | Oct 15 11:16:02 AM UTC 24 |
| Finished | Oct 15 11:16:30 AM UTC 24 |
| Peak memory | 219868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4252183833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all _with_rand_reset.4252183833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/54.uart_fifo_reset.1429815168 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 207934133981 ps |
| CPU time | 28.6 seconds |
| Started | Oct 15 11:16:04 AM UTC 24 |
| Finished | Oct 15 11:16:35 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429815168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1429815168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/54.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.4085366429 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 31163990718 ps |
| CPU time | 37.66 seconds |
| Started | Oct 15 11:16:13 AM UTC 24 |
| Finished | Oct 15 11:16:52 AM UTC 24 |
| Peak memory | 222024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4085366429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all _with_rand_reset.4085366429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/55.uart_fifo_reset.907453838 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 231616481580 ps |
| CPU time | 79.03 seconds |
| Started | Oct 15 11:16:16 AM UTC 24 |
| Finished | Oct 15 11:17:37 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907453838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.907453838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/55.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.2804624665 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 1104531751 ps |
| CPU time | 15.53 seconds |
| Started | Oct 15 11:16:20 AM UTC 24 |
| Finished | Oct 15 11:16:37 AM UTC 24 |
| Peak memory | 220032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2804624665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all _with_rand_reset.2804624665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/56.uart_fifo_reset.1396476823 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 6918587192 ps |
| CPU time | 6.9 seconds |
| Started | Oct 15 11:16:21 AM UTC 24 |
| Finished | Oct 15 11:16:29 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396476823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1396476823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/56.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.4182611130 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 9971529091 ps |
| CPU time | 32.53 seconds |
| Started | Oct 15 11:16:22 AM UTC 24 |
| Finished | Oct 15 11:16:56 AM UTC 24 |
| Peak memory | 218856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4182611130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all _with_rand_reset.4182611130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/57.uart_fifo_reset.3571087767 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 94402802672 ps |
| CPU time | 55.83 seconds |
| Started | Oct 15 11:16:22 AM UTC 24 |
| Finished | Oct 15 11:17:20 AM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571087767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3571087767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/57.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.3962236767 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 9270293816 ps |
| CPU time | 50.41 seconds |
| Started | Oct 15 11:16:28 AM UTC 24 |
| Finished | Oct 15 11:17:20 AM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3962236767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all _with_rand_reset.3962236767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/58.uart_fifo_reset.3409971836 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 9268368198 ps |
| CPU time | 17.34 seconds |
| Started | Oct 15 11:16:29 AM UTC 24 |
| Finished | Oct 15 11:16:48 AM UTC 24 |
| Peak memory | 208580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409971836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3409971836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/58.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.1532527870 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 9341088871 ps |
| CPU time | 149.86 seconds |
| Started | Oct 15 11:16:30 AM UTC 24 |
| Finished | Oct 15 11:19:03 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1532527870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all _with_rand_reset.1532527870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/59.uart_fifo_reset.4120781510 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 220571178297 ps |
| CPU time | 403.56 seconds |
| Started | Oct 15 11:16:30 AM UTC 24 |
| Finished | Oct 15 11:23:19 AM UTC 24 |
| Peak memory | 208884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120781510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.4120781510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/59.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.1739291891 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 21409628112 ps |
| CPU time | 38.89 seconds |
| Started | Oct 15 11:16:30 AM UTC 24 |
| Finished | Oct 15 11:17:11 AM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1739291891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all _with_rand_reset.1739291891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_alert_test.3616918610 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 12243002 ps |
| CPU time | 0.75 seconds |
| Started | Oct 15 10:37:57 AM UTC 24 |
| Finished | Oct 15 10:38:00 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616918610 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3616918610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_fifo_full.1519374800 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 66327970808 ps |
| CPU time | 76.68 seconds |
| Started | Oct 15 10:35:44 AM UTC 24 |
| Finished | Oct 15 10:37:03 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519374800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1519374800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.2256965376 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 71050603956 ps |
| CPU time | 164.1 seconds |
| Started | Oct 15 10:36:09 AM UTC 24 |
| Finished | Oct 15 10:38:57 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256965376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2256965376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_intr.1258126818 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 56643490688 ps |
| CPU time | 126.45 seconds |
| Started | Oct 15 10:36:23 AM UTC 24 |
| Finished | Oct 15 10:38:32 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258126818 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1258126818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.3834241882 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 108423736793 ps |
| CPU time | 461.02 seconds |
| Started | Oct 15 10:37:38 AM UTC 24 |
| Finished | Oct 15 10:45:26 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834241882 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3834241882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_loopback.1318446775 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2028390094 ps |
| CPU time | 4.27 seconds |
| Started | Oct 15 10:37:37 AM UTC 24 |
| Finished | Oct 15 10:37:42 AM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318446775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1318446775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_noise_filter.3594702703 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 74197246457 ps |
| CPU time | 109.51 seconds |
| Started | Oct 15 10:37:04 AM UTC 24 |
| Finished | Oct 15 10:38:56 AM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594702703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3594702703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_perf.2874300666 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 16453150187 ps |
| CPU time | 933.18 seconds |
| Started | Oct 15 10:37:37 AM UTC 24 |
| Finished | Oct 15 10:53:23 AM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874300666 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2874300666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_rx_oversample.259448123 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2664913311 ps |
| CPU time | 6.2 seconds |
| Started | Oct 15 10:36:15 AM UTC 24 |
| Finished | Oct 15 10:36:22 AM UTC 24 |
| Peak memory | 207432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259448123 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.259448123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.3333133519 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 35037310296 ps |
| CPU time | 76.42 seconds |
| Started | Oct 15 10:37:25 AM UTC 24 |
| Finished | Oct 15 10:38:44 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333133519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3333133519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.4202590916 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 6207048104 ps |
| CPU time | 4.37 seconds |
| Started | Oct 15 10:37:19 AM UTC 24 |
| Finished | Oct 15 10:37:24 AM UTC 24 |
| Peak memory | 205312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202590916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.4202590916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_smoke.1788908467 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 737997080 ps |
| CPU time | 1.91 seconds |
| Started | Oct 15 10:35:40 AM UTC 24 |
| Finished | Oct 15 10:35:43 AM UTC 24 |
| Peak memory | 207168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788908467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1788908467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.946402430 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1195145354 ps |
| CPU time | 5.14 seconds |
| Started | Oct 15 10:37:30 AM UTC 24 |
| Finished | Oct 15 10:37:36 AM UTC 24 |
| Peak memory | 208632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946402430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.946402430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/6.uart_tx_rx.729256067 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 52755454736 ps |
| CPU time | 110.07 seconds |
| Started | Oct 15 10:35:43 AM UTC 24 |
| Finished | Oct 15 10:37:36 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729256067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.729256067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/6.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/60.uart_fifo_reset.2911247517 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 365661163343 ps |
| CPU time | 85.25 seconds |
| Started | Oct 15 11:16:35 AM UTC 24 |
| Finished | Oct 15 11:18:03 AM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911247517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2911247517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/60.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.2724189065 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 18457715911 ps |
| CPU time | 35.03 seconds |
| Started | Oct 15 11:16:35 AM UTC 24 |
| Finished | Oct 15 11:17:12 AM UTC 24 |
| Peak memory | 217852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2724189065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all _with_rand_reset.2724189065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/61.uart_fifo_reset.2087448610 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 24396747458 ps |
| CPU time | 73.93 seconds |
| Started | Oct 15 11:16:37 AM UTC 24 |
| Finished | Oct 15 11:17:53 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087448610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2087448610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/61.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.1487767945 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 3876798901 ps |
| CPU time | 64.38 seconds |
| Started | Oct 15 11:16:39 AM UTC 24 |
| Finished | Oct 15 11:17:45 AM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1487767945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all _with_rand_reset.1487767945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/62.uart_fifo_reset.3085840829 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 101194125742 ps |
| CPU time | 105.99 seconds |
| Started | Oct 15 11:16:42 AM UTC 24 |
| Finished | Oct 15 11:18:30 AM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085840829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3085840829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/62.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.264357722 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 2899704319 ps |
| CPU time | 12.75 seconds |
| Started | Oct 15 11:16:42 AM UTC 24 |
| Finished | Oct 15 11:16:56 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=264357722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all_ with_rand_reset.264357722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/63.uart_fifo_reset.1958836444 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 33981782872 ps |
| CPU time | 64.17 seconds |
| Started | Oct 15 11:16:49 AM UTC 24 |
| Finished | Oct 15 11:17:55 AM UTC 24 |
| Peak memory | 208964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958836444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1958836444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/63.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.3960240731 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 14116709776 ps |
| CPU time | 112.6 seconds |
| Started | Oct 15 11:16:50 AM UTC 24 |
| Finished | Oct 15 11:18:45 AM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3960240731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all _with_rand_reset.3960240731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/64.uart_fifo_reset.4059295986 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 8428987915 ps |
| CPU time | 30.24 seconds |
| Started | Oct 15 11:16:53 AM UTC 24 |
| Finished | Oct 15 11:17:25 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059295986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.4059295986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/64.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.1724926312 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 5952372612 ps |
| CPU time | 54.18 seconds |
| Started | Oct 15 11:16:54 AM UTC 24 |
| Finished | Oct 15 11:17:50 AM UTC 24 |
| Peak memory | 220036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1724926312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all _with_rand_reset.1724926312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/65.uart_fifo_reset.3876114873 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 45113800893 ps |
| CPU time | 28.38 seconds |
| Started | Oct 15 11:16:56 AM UTC 24 |
| Finished | Oct 15 11:17:26 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876114873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3876114873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/65.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.3099477847 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 4465696000 ps |
| CPU time | 18.69 seconds |
| Started | Oct 15 11:16:57 AM UTC 24 |
| Finished | Oct 15 11:17:17 AM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3099477847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all _with_rand_reset.3099477847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/66.uart_fifo_reset.3178220431 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 67505798277 ps |
| CPU time | 57.21 seconds |
| Started | Oct 15 11:16:57 AM UTC 24 |
| Finished | Oct 15 11:17:56 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178220431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3178220431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/66.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.3401908089 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 4346549464 ps |
| CPU time | 36.72 seconds |
| Started | Oct 15 11:17:05 AM UTC 24 |
| Finished | Oct 15 11:17:43 AM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3401908089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all _with_rand_reset.3401908089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/67.uart_fifo_reset.314722038 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 161261532971 ps |
| CPU time | 197.95 seconds |
| Started | Oct 15 11:17:11 AM UTC 24 |
| Finished | Oct 15 11:20:32 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314722038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.314722038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/67.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.1399486004 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 8124414950 ps |
| CPU time | 32.52 seconds |
| Started | Oct 15 11:17:13 AM UTC 24 |
| Finished | Oct 15 11:17:46 AM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1399486004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all _with_rand_reset.1399486004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/68.uart_fifo_reset.979562441 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 33129992363 ps |
| CPU time | 56.21 seconds |
| Started | Oct 15 11:17:18 AM UTC 24 |
| Finished | Oct 15 11:18:15 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979562441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.979562441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/68.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.148185981 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 1306874096 ps |
| CPU time | 17.75 seconds |
| Started | Oct 15 11:17:19 AM UTC 24 |
| Finished | Oct 15 11:17:38 AM UTC 24 |
| Peak memory | 208948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=148185981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all_ with_rand_reset.148185981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/69.uart_fifo_reset.829901609 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 20879048515 ps |
| CPU time | 19.09 seconds |
| Started | Oct 15 11:17:21 AM UTC 24 |
| Finished | Oct 15 11:17:41 AM UTC 24 |
| Peak memory | 208484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829901609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.829901609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/69.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.3140235549 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 9215191658 ps |
| CPU time | 35.19 seconds |
| Started | Oct 15 11:17:21 AM UTC 24 |
| Finished | Oct 15 11:17:57 AM UTC 24 |
| Peak memory | 225296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3140235549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all _with_rand_reset.3140235549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_alert_test.741741915 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 11917909 ps |
| CPU time | 0.71 seconds |
| Started | Oct 15 10:39:19 AM UTC 24 |
| Finished | Oct 15 10:39:21 AM UTC 24 |
| Peak memory | 204316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741741915 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.741741915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_fifo_full.2201690035 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 112594368029 ps |
| CPU time | 69.84 seconds |
| Started | Oct 15 10:38:10 AM UTC 24 |
| Finished | Oct 15 10:39:21 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201690035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2201690035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.2688384115 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 232932882089 ps |
| CPU time | 46.39 seconds |
| Started | Oct 15 10:38:19 AM UTC 24 |
| Finished | Oct 15 10:39:07 AM UTC 24 |
| Peak memory | 208428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688384115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2688384115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_intr.235499810 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 48397582241 ps |
| CPU time | 47.92 seconds |
| Started | Oct 15 10:38:33 AM UTC 24 |
| Finished | Oct 15 10:39:23 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235499810 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.235499810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.2151883891 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 120262761082 ps |
| CPU time | 605.32 seconds |
| Started | Oct 15 10:39:03 AM UTC 24 |
| Finished | Oct 15 10:49:17 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151883891 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2151883891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_loopback.4031095716 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 6331999966 ps |
| CPU time | 20.34 seconds |
| Started | Oct 15 10:38:57 AM UTC 24 |
| Finished | Oct 15 10:39:19 AM UTC 24 |
| Peak memory | 207428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031095716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.uart_loopback.4031095716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_noise_filter.3417849134 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 193957382574 ps |
| CPU time | 181.71 seconds |
| Started | Oct 15 10:38:40 AM UTC 24 |
| Finished | Oct 15 10:41:45 AM UTC 24 |
| Peak memory | 208968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417849134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3417849134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_perf.1231267749 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 10781551533 ps |
| CPU time | 352.42 seconds |
| Started | Oct 15 10:39:00 AM UTC 24 |
| Finished | Oct 15 10:44:58 AM UTC 24 |
| Peak memory | 208684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231267749 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1231267749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_rx_oversample.104164694 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 6492369261 ps |
| CPU time | 32.16 seconds |
| Started | Oct 15 10:38:28 AM UTC 24 |
| Finished | Oct 15 10:39:02 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104164694 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.104164694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.1062390769 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 171152294820 ps |
| CPU time | 89.75 seconds |
| Started | Oct 15 10:38:50 AM UTC 24 |
| Finished | Oct 15 10:40:22 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062390769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1062390769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.595073229 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 4584118620 ps |
| CPU time | 3.52 seconds |
| Started | Oct 15 10:38:44 AM UTC 24 |
| Finished | Oct 15 10:38:49 AM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595073229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.595073229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_smoke.2554706366 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 11059229127 ps |
| CPU time | 24.98 seconds |
| Started | Oct 15 10:38:01 AM UTC 24 |
| Finished | Oct 15 10:38:27 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554706366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2554706366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.333106030 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2997598630 ps |
| CPU time | 34.75 seconds |
| Started | Oct 15 10:39:08 AM UTC 24 |
| Finished | Oct 15 10:39:44 AM UTC 24 |
| Peak memory | 225480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=333106030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_w ith_rand_reset.333106030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.2530477732 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3733050540 ps |
| CPU time | 2.7 seconds |
| Started | Oct 15 10:38:56 AM UTC 24 |
| Finished | Oct 15 10:39:00 AM UTC 24 |
| Peak memory | 208292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530477732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2530477732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/7.uart_tx_rx.2841522887 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 43973417464 ps |
| CPU time | 74.75 seconds |
| Started | Oct 15 10:38:08 AM UTC 24 |
| Finished | Oct 15 10:39:24 AM UTC 24 |
| Peak memory | 208956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841522887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2841522887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/7.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/70.uart_fifo_reset.1546981661 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 76636603065 ps |
| CPU time | 33.72 seconds |
| Started | Oct 15 11:17:23 AM UTC 24 |
| Finished | Oct 15 11:17:58 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546981661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1546981661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/70.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.1149950399 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 8539743232 ps |
| CPU time | 34.11 seconds |
| Started | Oct 15 11:17:25 AM UTC 24 |
| Finished | Oct 15 11:18:01 AM UTC 24 |
| Peak memory | 219768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1149950399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all _with_rand_reset.1149950399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/71.uart_fifo_reset.3358535273 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 79874077270 ps |
| CPU time | 94.2 seconds |
| Started | Oct 15 11:17:25 AM UTC 24 |
| Finished | Oct 15 11:19:01 AM UTC 24 |
| Peak memory | 208512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358535273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3358535273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/71.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.2613273497 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 11737151793 ps |
| CPU time | 90.71 seconds |
| Started | Oct 15 11:17:26 AM UTC 24 |
| Finished | Oct 15 11:18:59 AM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2613273497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all _with_rand_reset.2613273497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/72.uart_fifo_reset.2946799711 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 35240828642 ps |
| CPU time | 82 seconds |
| Started | Oct 15 11:17:26 AM UTC 24 |
| Finished | Oct 15 11:18:50 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946799711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2946799711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/72.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.899896197 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 27635748713 ps |
| CPU time | 64.97 seconds |
| Started | Oct 15 11:17:27 AM UTC 24 |
| Finished | Oct 15 11:18:34 AM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=899896197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all_ with_rand_reset.899896197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/73.uart_fifo_reset.4175871947 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 102637279082 ps |
| CPU time | 72.62 seconds |
| Started | Oct 15 11:17:37 AM UTC 24 |
| Finished | Oct 15 11:18:52 AM UTC 24 |
| Peak memory | 208584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175871947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.4175871947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/73.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.1723622248 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 21868581710 ps |
| CPU time | 28.49 seconds |
| Started | Oct 15 11:17:39 AM UTC 24 |
| Finished | Oct 15 11:18:08 AM UTC 24 |
| Peak memory | 219908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1723622248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all _with_rand_reset.1723622248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/74.uart_fifo_reset.880229690 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 34243359241 ps |
| CPU time | 53 seconds |
| Started | Oct 15 11:17:42 AM UTC 24 |
| Finished | Oct 15 11:18:36 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880229690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.880229690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/74.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.905586015 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 1235907253 ps |
| CPU time | 56.09 seconds |
| Started | Oct 15 11:17:45 AM UTC 24 |
| Finished | Oct 15 11:18:42 AM UTC 24 |
| Peak memory | 217796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=905586015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all_ with_rand_reset.905586015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.968785093 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 2013761249 ps |
| CPU time | 29.78 seconds |
| Started | Oct 15 11:17:47 AM UTC 24 |
| Finished | Oct 15 11:18:18 AM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=968785093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all_ with_rand_reset.968785093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/76.uart_fifo_reset.711258054 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 111407296831 ps |
| CPU time | 52.88 seconds |
| Started | Oct 15 11:17:47 AM UTC 24 |
| Finished | Oct 15 11:18:42 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711258054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.711258054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/76.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.526202473 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 5917806601 ps |
| CPU time | 25.9 seconds |
| Started | Oct 15 11:17:47 AM UTC 24 |
| Finished | Oct 15 11:18:14 AM UTC 24 |
| Peak memory | 217972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=526202473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all_ with_rand_reset.526202473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.3545686978 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 21849985401 ps |
| CPU time | 59.9 seconds |
| Started | Oct 15 11:17:54 AM UTC 24 |
| Finished | Oct 15 11:18:56 AM UTC 24 |
| Peak memory | 225348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3545686978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all _with_rand_reset.3545686978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/78.uart_fifo_reset.3229288328 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 9562667108 ps |
| CPU time | 34.7 seconds |
| Started | Oct 15 11:17:55 AM UTC 24 |
| Finished | Oct 15 11:18:31 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229288328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3229288328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/78.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/79.uart_fifo_reset.537466670 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 57634483003 ps |
| CPU time | 68.96 seconds |
| Started | Oct 15 11:17:58 AM UTC 24 |
| Finished | Oct 15 11:19:09 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537466670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.537466670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/79.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.1882334365 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 2186650299 ps |
| CPU time | 34.36 seconds |
| Started | Oct 15 11:17:58 AM UTC 24 |
| Finished | Oct 15 11:18:34 AM UTC 24 |
| Peak memory | 217760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1882334365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all _with_rand_reset.1882334365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_alert_test.4280262483 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 136814455 ps |
| CPU time | 0.76 seconds |
| Started | Oct 15 10:40:23 AM UTC 24 |
| Finished | Oct 15 10:40:25 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280262483 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.4280262483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_fifo_full.3662303794 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 97876079180 ps |
| CPU time | 61.29 seconds |
| Started | Oct 15 10:39:22 AM UTC 24 |
| Finished | Oct 15 10:40:25 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662303794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3662303794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.2682739100 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 70058214571 ps |
| CPU time | 70.76 seconds |
| Started | Oct 15 10:39:23 AM UTC 24 |
| Finished | Oct 15 10:40:36 AM UTC 24 |
| Peak memory | 208440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682739100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2682739100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_fifo_reset.4148963744 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 32461407479 ps |
| CPU time | 35.68 seconds |
| Started | Oct 15 10:39:24 AM UTC 24 |
| Finished | Oct 15 10:40:01 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148963744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.4148963744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_intr.2602420562 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 160742067141 ps |
| CPU time | 216.15 seconds |
| Started | Oct 15 10:39:44 AM UTC 24 |
| Finished | Oct 15 10:43:24 AM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602420562 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2602420562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.2229778860 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 138530232886 ps |
| CPU time | 891.81 seconds |
| Started | Oct 15 10:40:15 AM UTC 24 |
| Finished | Oct 15 10:55:19 AM UTC 24 |
| Peak memory | 212232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229778860 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2229778860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_loopback.2643572026 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 7000736364 ps |
| CPU time | 8.3 seconds |
| Started | Oct 15 10:40:11 AM UTC 24 |
| Finished | Oct 15 10:40:20 AM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643572026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2643572026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_noise_filter.4118062923 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 17755533494 ps |
| CPU time | 18.08 seconds |
| Started | Oct 15 10:39:54 AM UTC 24 |
| Finished | Oct 15 10:40:14 AM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118062923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.4118062923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_perf.2063684113 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 16990933693 ps |
| CPU time | 243 seconds |
| Started | Oct 15 10:40:14 AM UTC 24 |
| Finished | Oct 15 10:44:21 AM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063684113 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2063684113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_rx_oversample.3657309729 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 7251974609 ps |
| CPU time | 35.28 seconds |
| Started | Oct 15 10:39:25 AM UTC 24 |
| Finished | Oct 15 10:40:02 AM UTC 24 |
| Peak memory | 207284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657309729 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3657309729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.4059624019 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 30263343481 ps |
| CPU time | 21.26 seconds |
| Started | Oct 15 10:40:04 AM UTC 24 |
| Finished | Oct 15 10:40:26 AM UTC 24 |
| Peak memory | 208632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059624019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.4059624019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.941477510 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2472191423 ps |
| CPU time | 2.06 seconds |
| Started | Oct 15 10:40:02 AM UTC 24 |
| Finished | Oct 15 10:40:06 AM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941477510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.941477510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_smoke.626013260 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 491016949 ps |
| CPU time | 1.58 seconds |
| Started | Oct 15 10:39:20 AM UTC 24 |
| Finished | Oct 15 10:39:22 AM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626013260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 8.uart_smoke.626013260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.338372627 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13670958056 ps |
| CPU time | 57.6 seconds |
| Started | Oct 15 10:40:20 AM UTC 24 |
| Finished | Oct 15 10:41:20 AM UTC 24 |
| Peak memory | 217924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=338372627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_w ith_rand_reset.338372627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.2527708205 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3468490850 ps |
| CPU time | 1.83 seconds |
| Started | Oct 15 10:40:07 AM UTC 24 |
| Finished | Oct 15 10:40:10 AM UTC 24 |
| Peak memory | 207624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527708205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2527708205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/8.uart_tx_rx.3499873015 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 21042822018 ps |
| CPU time | 50.47 seconds |
| Started | Oct 15 10:39:21 AM UTC 24 |
| Finished | Oct 15 10:40:13 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499873015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3499873015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/8.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/80.uart_fifo_reset.3996436191 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 38816347290 ps |
| CPU time | 17.99 seconds |
| Started | Oct 15 11:18:02 AM UTC 24 |
| Finished | Oct 15 11:18:21 AM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996436191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3996436191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/80.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.1526397518 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 22420359690 ps |
| CPU time | 88.06 seconds |
| Started | Oct 15 11:18:04 AM UTC 24 |
| Finished | Oct 15 11:19:34 AM UTC 24 |
| Peak memory | 225424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1526397518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all _with_rand_reset.1526397518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/81.uart_fifo_reset.714562672 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 20899226117 ps |
| CPU time | 68.3 seconds |
| Started | Oct 15 11:18:06 AM UTC 24 |
| Finished | Oct 15 11:19:16 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714562672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.714562672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/81.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.676376771 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 1225653020 ps |
| CPU time | 26.83 seconds |
| Started | Oct 15 11:18:07 AM UTC 24 |
| Finished | Oct 15 11:18:35 AM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=676376771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all_ with_rand_reset.676376771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/82.uart_fifo_reset.1681797564 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 32093660266 ps |
| CPU time | 34.94 seconds |
| Started | Oct 15 11:18:07 AM UTC 24 |
| Finished | Oct 15 11:18:43 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681797564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1681797564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/82.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.2283670501 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 8187114314 ps |
| CPU time | 73.98 seconds |
| Started | Oct 15 11:18:09 AM UTC 24 |
| Finished | Oct 15 11:19:25 AM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2283670501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all _with_rand_reset.2283670501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/83.uart_fifo_reset.3513020646 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 11294185844 ps |
| CPU time | 21.83 seconds |
| Started | Oct 15 11:18:11 AM UTC 24 |
| Finished | Oct 15 11:18:34 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513020646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3513020646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/83.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.3812706849 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 3848647534 ps |
| CPU time | 24.04 seconds |
| Started | Oct 15 11:18:15 AM UTC 24 |
| Finished | Oct 15 11:18:40 AM UTC 24 |
| Peak memory | 208960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3812706849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all _with_rand_reset.3812706849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/84.uart_fifo_reset.617443323 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 22093946565 ps |
| CPU time | 38.34 seconds |
| Started | Oct 15 11:18:16 AM UTC 24 |
| Finished | Oct 15 11:18:56 AM UTC 24 |
| Peak memory | 208472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617443323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.617443323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/84.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.902572111 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 3622381482 ps |
| CPU time | 50.96 seconds |
| Started | Oct 15 11:18:16 AM UTC 24 |
| Finished | Oct 15 11:19:09 AM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=902572111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all_ with_rand_reset.902572111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/85.uart_fifo_reset.296281462 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 50375427930 ps |
| CPU time | 85.39 seconds |
| Started | Oct 15 11:18:19 AM UTC 24 |
| Finished | Oct 15 11:19:47 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296281462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.296281462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/85.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.3414975992 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 5481151924 ps |
| CPU time | 23.55 seconds |
| Started | Oct 15 11:18:19 AM UTC 24 |
| Finished | Oct 15 11:18:44 AM UTC 24 |
| Peak memory | 219932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3414975992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all _with_rand_reset.3414975992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/86.uart_fifo_reset.3154373798 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 28434907411 ps |
| CPU time | 59.05 seconds |
| Started | Oct 15 11:18:22 AM UTC 24 |
| Finished | Oct 15 11:19:22 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154373798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3154373798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/86.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.2215813319 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 3792576156 ps |
| CPU time | 9.32 seconds |
| Started | Oct 15 11:18:31 AM UTC 24 |
| Finished | Oct 15 11:18:41 AM UTC 24 |
| Peak memory | 219908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2215813319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all _with_rand_reset.2215813319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/87.uart_fifo_reset.2213436612 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 55169644885 ps |
| CPU time | 106.56 seconds |
| Started | Oct 15 11:18:32 AM UTC 24 |
| Finished | Oct 15 11:20:21 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213436612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2213436612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/87.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.1543220795 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 2323497280 ps |
| CPU time | 13.55 seconds |
| Started | Oct 15 11:18:33 AM UTC 24 |
| Finished | Oct 15 11:18:48 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1543220795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all _with_rand_reset.1543220795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/88.uart_fifo_reset.4272245792 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 119433765260 ps |
| CPU time | 53.47 seconds |
| Started | Oct 15 11:18:35 AM UTC 24 |
| Finished | Oct 15 11:19:30 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272245792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.4272245792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/88.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.620761683 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 15483556429 ps |
| CPU time | 102.23 seconds |
| Started | Oct 15 11:18:35 AM UTC 24 |
| Finished | Oct 15 11:20:19 AM UTC 24 |
| Peak memory | 217856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=620761683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all_ with_rand_reset.620761683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/89.uart_fifo_reset.4234882473 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 66876733540 ps |
| CPU time | 43.33 seconds |
| Started | Oct 15 11:18:35 AM UTC 24 |
| Finished | Oct 15 11:19:20 AM UTC 24 |
| Peak memory | 208740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234882473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.4234882473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/89.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.2332740276 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 4424033972 ps |
| CPU time | 67.92 seconds |
| Started | Oct 15 11:18:36 AM UTC 24 |
| Finished | Oct 15 11:19:46 AM UTC 24 |
| Peak memory | 221916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2332740276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all _with_rand_reset.2332740276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_alert_test.1087754960 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 19668972 ps |
| CPU time | 0.7 seconds |
| Started | Oct 15 10:41:46 AM UTC 24 |
| Finished | Oct 15 10:41:48 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087754960 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1087754960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.3186522288 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 146618157826 ps |
| CPU time | 76.7 seconds |
| Started | Oct 15 10:40:27 AM UTC 24 |
| Finished | Oct 15 10:41:46 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186522288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3186522288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_fifo_reset.913428199 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 60087568450 ps |
| CPU time | 135.5 seconds |
| Started | Oct 15 10:40:36 AM UTC 24 |
| Finished | Oct 15 10:42:55 AM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913428199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.913428199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_intr.2709293229 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 46057243156 ps |
| CPU time | 22.31 seconds |
| Started | Oct 15 10:40:59 AM UTC 24 |
| Finished | Oct 15 10:41:22 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709293229 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2709293229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.97716011 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 75213981614 ps |
| CPU time | 209.27 seconds |
| Started | Oct 15 10:41:29 AM UTC 24 |
| Finished | Oct 15 10:45:03 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97716011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.97716011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_loopback.1629214376 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 115125472 ps |
| CPU time | 0.87 seconds |
| Started | Oct 15 10:41:26 AM UTC 24 |
| Finished | Oct 15 10:41:28 AM UTC 24 |
| Peak memory | 204384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629214376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1629214376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_noise_filter.3936178433 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 14503313061 ps |
| CPU time | 24.64 seconds |
| Started | Oct 15 10:41:00 AM UTC 24 |
| Finished | Oct 15 10:41:26 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936178433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3936178433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_perf.394661382 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 21319497522 ps |
| CPU time | 1152.91 seconds |
| Started | Oct 15 10:41:29 AM UTC 24 |
| Finished | Oct 15 11:00:59 AM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394661382 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.394661382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_rx_oversample.574721865 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2833386968 ps |
| CPU time | 12.91 seconds |
| Started | Oct 15 10:40:48 AM UTC 24 |
| Finished | Oct 15 10:41:02 AM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574721865 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.574721865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.1758495225 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 9035532011 ps |
| CPU time | 23.03 seconds |
| Started | Oct 15 10:41:21 AM UTC 24 |
| Finished | Oct 15 10:41:45 AM UTC 24 |
| Peak memory | 208024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758495225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1758495225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.1602412734 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 32277531871 ps |
| CPU time | 59 seconds |
| Started | Oct 15 10:41:04 AM UTC 24 |
| Finished | Oct 15 10:42:04 AM UTC 24 |
| Peak memory | 205176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602412734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1602412734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_smoke.29533630 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 6000761769 ps |
| CPU time | 20.18 seconds |
| Started | Oct 15 10:40:26 AM UTC 24 |
| Finished | Oct 15 10:40:48 AM UTC 24 |
| Peak memory | 208452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29533630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 9.uart_smoke.29533630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.2141956088 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 381860365 ps |
| CPU time | 5.77 seconds |
| Started | Oct 15 10:41:37 AM UTC 24 |
| Finished | Oct 15 10:41:44 AM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2141956088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_ with_rand_reset.2141956088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.3154723621 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1042684273 ps |
| CPU time | 3.91 seconds |
| Started | Oct 15 10:41:23 AM UTC 24 |
| Finished | Oct 15 10:41:28 AM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154723621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3154723621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/9.uart_tx_rx.1120092151 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 32453083573 ps |
| CPU time | 30.86 seconds |
| Started | Oct 15 10:40:26 AM UTC 24 |
| Finished | Oct 15 10:40:58 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120092151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1120092151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/9.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/90.uart_fifo_reset.2051498129 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 98039081205 ps |
| CPU time | 69.4 seconds |
| Started | Oct 15 11:18:37 AM UTC 24 |
| Finished | Oct 15 11:19:48 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051498129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2051498129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/90.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.3759696610 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 1032607823 ps |
| CPU time | 13.2 seconds |
| Started | Oct 15 11:18:40 AM UTC 24 |
| Finished | Oct 15 11:18:55 AM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3759696610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all _with_rand_reset.3759696610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/91.uart_fifo_reset.3733742637 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 17005406795 ps |
| CPU time | 38.07 seconds |
| Started | Oct 15 11:18:41 AM UTC 24 |
| Finished | Oct 15 11:19:21 AM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733742637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3733742637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/91.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.4199489883 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 3941732882 ps |
| CPU time | 94.96 seconds |
| Started | Oct 15 11:18:42 AM UTC 24 |
| Finished | Oct 15 11:20:20 AM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4199489883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all _with_rand_reset.4199489883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/92.uart_fifo_reset.4034127850 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 17557906328 ps |
| CPU time | 9.57 seconds |
| Started | Oct 15 11:18:42 AM UTC 24 |
| Finished | Oct 15 11:18:53 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034127850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4034127850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/92.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.26817717 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 12911967449 ps |
| CPU time | 49.46 seconds |
| Started | Oct 15 11:18:44 AM UTC 24 |
| Finished | Oct 15 11:19:34 AM UTC 24 |
| Peak memory | 219932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=26817717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all_w ith_rand_reset.26817717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/93.uart_fifo_reset.4144727520 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 58699875737 ps |
| CPU time | 20.49 seconds |
| Started | Oct 15 11:18:44 AM UTC 24 |
| Finished | Oct 15 11:19:05 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144727520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.4144727520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/93.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.710922064 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 2182687179 ps |
| CPU time | 45.76 seconds |
| Started | Oct 15 11:18:45 AM UTC 24 |
| Finished | Oct 15 11:19:32 AM UTC 24 |
| Peak memory | 219872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=710922064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all_ with_rand_reset.710922064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/94.uart_fifo_reset.2848785360 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 58291188507 ps |
| CPU time | 38.37 seconds |
| Started | Oct 15 11:18:46 AM UTC 24 |
| Finished | Oct 15 11:19:26 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848785360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2848785360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/94.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.2172266506 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 8230482904 ps |
| CPU time | 34.15 seconds |
| Started | Oct 15 11:18:46 AM UTC 24 |
| Finished | Oct 15 11:19:21 AM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2172266506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all _with_rand_reset.2172266506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/95.uart_fifo_reset.2111423306 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 73834649836 ps |
| CPU time | 28.2 seconds |
| Started | Oct 15 11:18:48 AM UTC 24 |
| Finished | Oct 15 11:19:17 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111423306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2111423306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/95.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.3927218202 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 24487116639 ps |
| CPU time | 47.99 seconds |
| Started | Oct 15 11:18:50 AM UTC 24 |
| Finished | Oct 15 11:19:39 AM UTC 24 |
| Peak memory | 217776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3927218202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all _with_rand_reset.3927218202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/96.uart_fifo_reset.1052414876 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 28602395497 ps |
| CPU time | 12.71 seconds |
| Started | Oct 15 11:18:51 AM UTC 24 |
| Finished | Oct 15 11:19:05 AM UTC 24 |
| Peak memory | 208620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052414876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1052414876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/96.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.2820966841 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 17067135677 ps |
| CPU time | 54.04 seconds |
| Started | Oct 15 11:18:53 AM UTC 24 |
| Finished | Oct 15 11:19:49 AM UTC 24 |
| Peak memory | 224732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2820966841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all _with_rand_reset.2820966841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/97.uart_fifo_reset.2419058342 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 113134715676 ps |
| CPU time | 206.03 seconds |
| Started | Oct 15 11:18:54 AM UTC 24 |
| Finished | Oct 15 11:22:23 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419058342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2419058342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/97.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.2354561399 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 3608242749 ps |
| CPU time | 35.83 seconds |
| Started | Oct 15 11:18:55 AM UTC 24 |
| Finished | Oct 15 11:19:33 AM UTC 24 |
| Peak memory | 219876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2354561399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all _with_rand_reset.2354561399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/98.uart_fifo_reset.4114645814 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 159566310633 ps |
| CPU time | 27.01 seconds |
| Started | Oct 15 11:18:56 AM UTC 24 |
| Finished | Oct 15 11:19:25 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114645814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.4114645814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/98.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.3136636129 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 3454561221 ps |
| CPU time | 50.34 seconds |
| Started | Oct 15 11:18:56 AM UTC 24 |
| Finished | Oct 15 11:19:48 AM UTC 24 |
| Peak memory | 218040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3136636129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all _with_rand_reset.3136636129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.2277253244 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 16511302851 ps |
| CPU time | 43.36 seconds |
| Started | Oct 15 11:18:58 AM UTC 24 |
| Finished | Oct 15 11:19:43 AM UTC 24 |
| Peak memory | 224788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2277253244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all _with_rand_reset.2277253244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest |
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