| T646 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_intr.2616534991 |
|
|
Oct 15 11:05:50 AM UTC 24 |
Oct 15 11:06:56 AM UTC 24 |
27587377635 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_rx_oversample.4240959082 |
|
|
Oct 15 11:06:12 AM UTC 24 |
Oct 15 11:06:59 AM UTC 24 |
4228416239 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_fifo_full.1541004162 |
|
|
Oct 15 11:06:26 AM UTC 24 |
Oct 15 11:07:00 AM UTC 24 |
27039964254 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_perf.2689664219 |
|
|
Oct 15 11:03:48 AM UTC 24 |
Oct 15 11:07:02 AM UTC 24 |
11649878517 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_alert_test.2392627439 |
|
|
Oct 15 11:07:01 AM UTC 24 |
Oct 15 11:07:03 AM UTC 24 |
35282283 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.3130606119 |
|
|
Oct 15 11:06:27 AM UTC 24 |
Oct 15 11:07:04 AM UTC 24 |
31434975664 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_smoke.809281790 |
|
|
Oct 15 11:07:03 AM UTC 24 |
Oct 15 11:07:06 AM UTC 24 |
472855973 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.4161000552 |
|
|
Oct 15 11:06:40 AM UTC 24 |
Oct 15 11:07:07 AM UTC 24 |
7121278186 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_tx_rx.1281253852 |
|
|
Oct 15 11:06:06 AM UTC 24 |
Oct 15 11:07:09 AM UTC 24 |
88821568051 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.4154359504 |
|
|
Oct 15 11:06:21 AM UTC 24 |
Oct 15 11:07:09 AM UTC 24 |
2872807261 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_perf.63112762 |
|
|
Oct 15 11:05:04 AM UTC 24 |
Oct 15 11:07:09 AM UTC 24 |
13782048931 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.1958734381 |
|
|
Oct 15 11:06:17 AM UTC 24 |
Oct 15 11:07:18 AM UTC 24 |
21066048105 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_noise_filter.767129855 |
|
|
Oct 15 11:07:10 AM UTC 24 |
Oct 15 11:07:19 AM UTC 24 |
6672768289 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.836132268 |
|
|
Oct 15 11:05:09 AM UTC 24 |
Oct 15 11:07:23 AM UTC 24 |
50479693186 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.947171236 |
|
|
Oct 15 11:07:19 AM UTC 24 |
Oct 15 11:07:25 AM UTC 24 |
1854122689 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_stress_all.1010294662 |
|
|
Oct 15 11:04:54 AM UTC 24 |
Oct 15 11:07:26 AM UTC 24 |
49296974246 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.4234429069 |
|
|
Oct 15 11:07:24 AM UTC 24 |
Oct 15 11:07:29 AM UTC 24 |
993901530 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_stress_all.788375471 |
|
|
Oct 15 11:05:22 AM UTC 24 |
Oct 15 11:07:29 AM UTC 24 |
67229734763 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_loopback.2849365825 |
|
|
Oct 15 11:07:26 AM UTC 24 |
Oct 15 11:07:32 AM UTC 24 |
928424122 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.526675777 |
|
|
Oct 15 11:06:40 AM UTC 24 |
Oct 15 11:07:33 AM UTC 24 |
90990453968 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_noise_filter.3501075920 |
|
|
Oct 15 11:06:15 AM UTC 24 |
Oct 15 11:07:33 AM UTC 24 |
99985727809 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_fifo_reset.185637588 |
|
|
Oct 15 11:05:30 AM UTC 24 |
Oct 15 11:07:33 AM UTC 24 |
109553213209 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_alert_test.1849996679 |
|
|
Oct 15 11:07:33 AM UTC 24 |
Oct 15 11:07:35 AM UTC 24 |
12957718 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_smoke.2608470734 |
|
|
Oct 15 11:07:33 AM UTC 24 |
Oct 15 11:07:36 AM UTC 24 |
447941530 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_perf.704566503 |
|
|
Oct 15 11:06:00 AM UTC 24 |
Oct 15 11:07:37 AM UTC 24 |
18515011634 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_fifo_full.2006260692 |
|
|
Oct 15 11:06:07 AM UTC 24 |
Oct 15 11:07:38 AM UTC 24 |
175226868721 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_perf.2488451011 |
|
|
Oct 15 11:05:37 AM UTC 24 |
Oct 15 11:07:39 AM UTC 24 |
3223409579 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/21.uart_perf.2553398657 |
|
|
Oct 15 11:00:08 AM UTC 24 |
Oct 15 11:07:39 AM UTC 24 |
11769005948 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_intr.352212944 |
|
|
Oct 15 11:05:00 AM UTC 24 |
Oct 15 11:07:42 AM UTC 24 |
217448221620 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_noise_filter.3336158196 |
|
|
Oct 15 11:06:35 AM UTC 24 |
Oct 15 11:07:49 AM UTC 24 |
30424671380 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.1204411493 |
|
|
Oct 15 11:05:18 AM UTC 24 |
Oct 15 11:07:51 AM UTC 24 |
301154515567 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_noise_filter.3891945880 |
|
|
Oct 15 11:05:00 AM UTC 24 |
Oct 15 11:07:54 AM UTC 24 |
216360944898 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.890597546 |
|
|
Oct 15 11:07:38 AM UTC 24 |
Oct 15 11:07:56 AM UTC 24 |
16830779551 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_fifo_full.453347131 |
|
|
Oct 15 11:07:35 AM UTC 24 |
Oct 15 11:07:56 AM UTC 24 |
32426887682 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_fifo_full.2357378223 |
|
|
Oct 15 11:10:44 AM UTC 24 |
Oct 15 11:13:07 AM UTC 24 |
114469189340 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.1321986593 |
|
|
Oct 15 11:07:43 AM UTC 24 |
Oct 15 11:07:57 AM UTC 24 |
3346183564 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_fifo_reset.3607957500 |
|
|
Oct 15 11:06:28 AM UTC 24 |
Oct 15 11:08:00 AM UTC 24 |
23507652698 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_alert_test.3022551572 |
|
|
Oct 15 11:07:59 AM UTC 24 |
Oct 15 11:08:01 AM UTC 24 |
15075174 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_smoke.1450619007 |
|
|
Oct 15 11:08:02 AM UTC 24 |
Oct 15 11:08:04 AM UTC 24 |
102143223 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_intr.1733517477 |
|
|
Oct 15 11:06:32 AM UTC 24 |
Oct 15 11:08:05 AM UTC 24 |
31371205132 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_perf.2572804406 |
|
|
Oct 15 11:04:51 AM UTC 24 |
Oct 15 11:08:08 AM UTC 24 |
9706793053 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_rx_oversample.1842159334 |
|
|
Oct 15 11:07:09 AM UTC 24 |
Oct 15 11:08:08 AM UTC 24 |
4957515695 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.2023025750 |
|
|
Oct 15 11:05:20 AM UTC 24 |
Oct 15 11:08:09 AM UTC 24 |
227718237029 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_fifo_full.2671891925 |
|
|
Oct 15 11:05:15 AM UTC 24 |
Oct 15 11:08:12 AM UTC 24 |
75652723057 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_tx_rx.2160356284 |
|
|
Oct 15 11:07:04 AM UTC 24 |
Oct 15 11:08:15 AM UTC 24 |
99797935847 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.749298808 |
|
|
Oct 15 11:05:33 AM UTC 24 |
Oct 15 11:08:15 AM UTC 24 |
134208706946 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_loopback.2078146148 |
|
|
Oct 15 11:07:54 AM UTC 24 |
Oct 15 11:08:17 AM UTC 24 |
6167915522 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_noise_filter.3276886094 |
|
|
Oct 15 11:07:40 AM UTC 24 |
Oct 15 11:08:18 AM UTC 24 |
34979656427 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.1676440633 |
|
|
Oct 15 11:08:06 AM UTC 24 |
Oct 15 11:08:21 AM UTC 24 |
10935647920 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_rx_oversample.2423790386 |
|
|
Oct 15 11:07:39 AM UTC 24 |
Oct 15 11:08:22 AM UTC 24 |
4671948005 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_fifo_full.2089702510 |
|
|
Oct 15 11:05:44 AM UTC 24 |
Oct 15 11:08:23 AM UTC 24 |
98690697423 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_perf.4085410717 |
|
|
Oct 15 11:06:43 AM UTC 24 |
Oct 15 11:08:23 AM UTC 24 |
5590098165 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.4019722269 |
|
|
Oct 15 11:07:06 AM UTC 24 |
Oct 15 11:08:23 AM UTC 24 |
167466558896 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.328484782 |
|
|
Oct 15 11:08:17 AM UTC 24 |
Oct 15 11:08:23 AM UTC 24 |
1348788271 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_alert_test.1456974647 |
|
|
Oct 15 11:08:24 AM UTC 24 |
Oct 15 11:08:26 AM UTC 24 |
38861577 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_noise_filter.1426993637 |
|
|
Oct 15 11:05:18 AM UTC 24 |
Oct 15 11:08:27 AM UTC 24 |
85845937539 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_loopback.1572099589 |
|
|
Oct 15 11:08:18 AM UTC 24 |
Oct 15 11:08:27 AM UTC 24 |
5110248248 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_fifo_reset.1607445780 |
|
|
Oct 15 11:07:38 AM UTC 24 |
Oct 15 11:08:31 AM UTC 24 |
52222222907 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_noise_filter.1446897063 |
|
|
Oct 15 11:08:12 AM UTC 24 |
Oct 15 11:08:32 AM UTC 24 |
9153516298 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_rx_oversample.3863259808 |
|
|
Oct 15 11:08:09 AM UTC 24 |
Oct 15 11:08:33 AM UTC 24 |
3597732348 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_rx_oversample.173354150 |
|
|
Oct 15 11:08:31 AM UTC 24 |
Oct 15 11:08:37 AM UTC 24 |
2035752486 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_fifo_reset.377312434 |
|
|
Oct 15 11:08:09 AM UTC 24 |
Oct 15 11:08:39 AM UTC 24 |
37076035033 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_intr.1623935693 |
|
|
Oct 15 11:08:10 AM UTC 24 |
Oct 15 11:08:40 AM UTC 24 |
52164520983 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.1814065616 |
|
|
Oct 15 11:08:38 AM UTC 24 |
Oct 15 11:08:43 AM UTC 24 |
4128674496 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_intr.3058644180 |
|
|
Oct 15 11:07:40 AM UTC 24 |
Oct 15 11:08:44 AM UTC 24 |
39247399722 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/25.uart_noise_filter.3633165531 |
|
|
Oct 15 11:04:47 AM UTC 24 |
Oct 15 11:08:46 AM UTC 24 |
97370539694 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_intr.1487923503 |
|
|
Oct 15 11:07:10 AM UTC 24 |
Oct 15 11:08:47 AM UTC 24 |
33303629241 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.913668108 |
|
|
Oct 15 11:06:57 AM UTC 24 |
Oct 15 11:08:47 AM UTC 24 |
3087598007 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_tx_rx.660817941 |
|
|
Oct 15 11:08:02 AM UTC 24 |
Oct 15 11:08:49 AM UTC 24 |
49746949995 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.55962359 |
|
|
Oct 15 11:08:15 AM UTC 24 |
Oct 15 11:08:49 AM UTC 24 |
183466031991 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/28.uart_fifo_reset.1563350579 |
|
|
Oct 15 11:05:15 AM UTC 24 |
Oct 15 11:08:51 AM UTC 24 |
108793452622 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_alert_test.128181538 |
|
|
Oct 15 11:08:50 AM UTC 24 |
Oct 15 11:08:52 AM UTC 24 |
21879984 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_fifo_reset.2591889418 |
|
|
Oct 15 11:05:46 AM UTC 24 |
Oct 15 11:08:53 AM UTC 24 |
96466168371 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_smoke.3947563386 |
|
|
Oct 15 11:08:50 AM UTC 24 |
Oct 15 11:08:53 AM UTC 24 |
517985304 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_stress_all.2959412478 |
|
|
Oct 15 11:07:58 AM UTC 24 |
Oct 15 11:08:53 AM UTC 24 |
64582699286 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.4036216160 |
|
|
Oct 15 11:07:29 AM UTC 24 |
Oct 15 11:08:53 AM UTC 24 |
54947766392 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/22.uart_stress_all.2263684899 |
|
|
Oct 15 11:01:34 AM UTC 24 |
Oct 15 11:08:55 AM UTC 24 |
199139794632 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_loopback.1797769249 |
|
|
Oct 15 11:08:44 AM UTC 24 |
Oct 15 11:08:56 AM UTC 24 |
10864121519 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_intr.547669653 |
|
|
Oct 15 11:08:33 AM UTC 24 |
Oct 15 11:08:56 AM UTC 24 |
6675525610 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_smoke.1332948356 |
|
|
Oct 15 11:08:24 AM UTC 24 |
Oct 15 11:08:59 AM UTC 24 |
11570725556 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.3862089232 |
|
|
Oct 15 11:07:57 AM UTC 24 |
Oct 15 11:09:00 AM UTC 24 |
16919149143 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.3347944147 |
|
|
Oct 15 11:08:57 AM UTC 24 |
Oct 15 11:09:01 AM UTC 24 |
2293145738 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_rx_oversample.590715299 |
|
|
Oct 15 11:08:54 AM UTC 24 |
Oct 15 11:09:02 AM UTC 24 |
3535063350 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_tx_rx.623594080 |
|
|
Oct 15 11:04:55 AM UTC 24 |
Oct 15 11:09:02 AM UTC 24 |
103651515160 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.2303192838 |
|
|
Oct 15 11:09:00 AM UTC 24 |
Oct 15 11:09:05 AM UTC 24 |
959781460 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_intr.23540779 |
|
|
Oct 15 11:08:55 AM UTC 24 |
Oct 15 11:09:07 AM UTC 24 |
3990965767 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.95615310 |
|
|
Oct 15 11:07:50 AM UTC 24 |
Oct 15 11:09:07 AM UTC 24 |
20723675367 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_alert_test.2719193700 |
|
|
Oct 15 11:09:07 AM UTC 24 |
Oct 15 11:09:09 AM UTC 24 |
12137942 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_smoke.654864699 |
|
|
Oct 15 11:09:09 AM UTC 24 |
Oct 15 11:09:12 AM UTC 24 |
516706522 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.1659341191 |
|
|
Oct 15 11:08:41 AM UTC 24 |
Oct 15 11:09:13 AM UTC 24 |
6462473529 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.3461466608 |
|
|
Oct 15 11:07:21 AM UTC 24 |
Oct 15 11:09:14 AM UTC 24 |
231863239267 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_fifo_reset.3446182348 |
|
|
Oct 15 11:08:28 AM UTC 24 |
Oct 15 11:09:19 AM UTC 24 |
80500121976 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_loopback.2369860958 |
|
|
Oct 15 11:09:01 AM UTC 24 |
Oct 15 11:09:21 AM UTC 24 |
6840901754 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_fifo_full.1784130845 |
|
|
Oct 15 11:08:26 AM UTC 24 |
Oct 15 11:09:21 AM UTC 24 |
74022081138 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.388403902 |
|
|
Oct 15 11:07:30 AM UTC 24 |
Oct 15 11:09:23 AM UTC 24 |
12803385254 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/19.uart_stress_all.2234969328 |
|
|
Oct 15 10:57:16 AM UTC 24 |
Oct 15 11:09:23 AM UTC 24 |
305782616311 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.1636890085 |
|
|
Oct 15 11:08:27 AM UTC 24 |
Oct 15 11:09:24 AM UTC 24 |
294419031701 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_tx_rx.2996414661 |
|
|
Oct 15 11:08:24 AM UTC 24 |
Oct 15 11:09:25 AM UTC 24 |
19259147856 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.2494680762 |
|
|
Oct 15 11:09:24 AM UTC 24 |
Oct 15 11:09:27 AM UTC 24 |
2153419830 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_intr.925181348 |
|
|
Oct 15 11:09:21 AM UTC 24 |
Oct 15 11:09:34 AM UTC 24 |
48845056669 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_perf.1784810357 |
|
|
Oct 15 11:08:20 AM UTC 24 |
Oct 15 11:09:35 AM UTC 24 |
6023184231 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.157116488 |
|
|
Oct 15 11:09:03 AM UTC 24 |
Oct 15 11:09:37 AM UTC 24 |
3277131901 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.1146983304 |
|
|
Oct 15 11:08:22 AM UTC 24 |
Oct 15 11:09:40 AM UTC 24 |
188911529934 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_loopback.776385669 |
|
|
Oct 15 11:09:26 AM UTC 24 |
Oct 15 11:09:41 AM UTC 24 |
4638173037 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_tx_rx.2900118836 |
|
|
Oct 15 11:08:51 AM UTC 24 |
Oct 15 11:09:41 AM UTC 24 |
95719377970 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.3896364093 |
|
|
Oct 15 11:08:15 AM UTC 24 |
Oct 15 11:09:42 AM UTC 24 |
36745274931 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_alert_test.2991301140 |
|
|
Oct 15 11:09:42 AM UTC 24 |
Oct 15 11:09:44 AM UTC 24 |
17610550 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_smoke.3836271162 |
|
|
Oct 15 11:09:42 AM UTC 24 |
Oct 15 11:09:46 AM UTC 24 |
509823930 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_rx_oversample.2647297720 |
|
|
Oct 15 11:09:20 AM UTC 24 |
Oct 15 11:09:48 AM UTC 24 |
2332225423 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.351554689 |
|
|
Oct 15 11:08:24 AM UTC 24 |
Oct 15 11:09:51 AM UTC 24 |
3697736531 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_noise_filter.3228115434 |
|
|
Oct 15 11:05:54 AM UTC 24 |
Oct 15 11:09:53 AM UTC 24 |
75476589264 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_tx_rx.3144473738 |
|
|
Oct 15 11:07:34 AM UTC 24 |
Oct 15 11:09:56 AM UTC 24 |
77758841340 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.430678989 |
|
|
Oct 15 11:09:36 AM UTC 24 |
Oct 15 11:09:57 AM UTC 24 |
1703644069 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_tx_rx.3327544833 |
|
|
Oct 15 11:09:11 AM UTC 24 |
Oct 15 11:10:01 AM UTC 24 |
30368812834 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.3975642237 |
|
|
Oct 15 11:09:25 AM UTC 24 |
Oct 15 11:10:02 AM UTC 24 |
6057666144 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.2367722681 |
|
|
Oct 15 11:09:57 AM UTC 24 |
Oct 15 11:10:02 AM UTC 24 |
33729103079 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_rx_oversample.3586769614 |
|
|
Oct 15 11:09:49 AM UTC 24 |
Oct 15 11:10:04 AM UTC 24 |
1987308692 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_noise_filter.3263772891 |
|
|
Oct 15 11:08:56 AM UTC 24 |
Oct 15 11:10:05 AM UTC 24 |
36062785118 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.2804645075 |
|
|
Oct 15 11:10:02 AM UTC 24 |
Oct 15 11:10:05 AM UTC 24 |
253515224 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_fifo_reset.994381330 |
|
|
Oct 15 11:08:54 AM UTC 24 |
Oct 15 11:10:05 AM UTC 24 |
141206271598 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_loopback.116593611 |
|
|
Oct 15 11:10:03 AM UTC 24 |
Oct 15 11:10:07 AM UTC 24 |
1881341113 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_alert_test.509890170 |
|
|
Oct 15 11:10:06 AM UTC 24 |
Oct 15 11:10:08 AM UTC 24 |
35047436 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_fifo_reset.3031185524 |
|
|
Oct 15 11:09:15 AM UTC 24 |
Oct 15 11:10:13 AM UTC 24 |
84730169732 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_noise_filter.993203259 |
|
|
Oct 15 11:09:54 AM UTC 24 |
Oct 15 11:10:14 AM UTC 24 |
28080685825 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_fifo_full.3692216061 |
|
|
Oct 15 11:09:13 AM UTC 24 |
Oct 15 11:10:15 AM UTC 24 |
26193000049 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_tx_rx.4044287212 |
|
|
Oct 15 11:10:08 AM UTC 24 |
Oct 15 11:10:17 AM UTC 24 |
2049259424 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_fifo_reset.162213117 |
|
|
Oct 15 11:09:47 AM UTC 24 |
Oct 15 11:10:18 AM UTC 24 |
13466094436 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.2024810256 |
|
|
Oct 15 11:09:58 AM UTC 24 |
Oct 15 11:10:20 AM UTC 24 |
38324944124 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_smoke.695284316 |
|
|
Oct 15 11:10:07 AM UTC 24 |
Oct 15 11:10:21 AM UTC 24 |
5890913434 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.1142213393 |
|
|
Oct 15 11:10:06 AM UTC 24 |
Oct 15 11:10:23 AM UTC 24 |
1377404627 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/24.uart_stress_all.762312123 |
|
|
Oct 15 11:04:02 AM UTC 24 |
Oct 15 11:10:23 AM UTC 24 |
182704488537 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.2116461152 |
|
|
Oct 15 11:08:48 AM UTC 24 |
Oct 15 11:10:26 AM UTC 24 |
2597549483 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.2159816150 |
|
|
Oct 15 11:09:24 AM UTC 24 |
Oct 15 11:10:26 AM UTC 24 |
20900212406 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.1093051201 |
|
|
Oct 15 11:10:22 AM UTC 24 |
Oct 15 11:10:28 AM UTC 24 |
4363613453 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.752820678 |
|
|
Oct 15 11:10:24 AM UTC 24 |
Oct 15 11:10:29 AM UTC 24 |
1418720848 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_rx_oversample.3198054137 |
|
|
Oct 15 11:10:18 AM UTC 24 |
Oct 15 11:10:31 AM UTC 24 |
4449517232 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_fifo_full.700999891 |
|
|
Oct 15 11:07:04 AM UTC 24 |
Oct 15 11:10:37 AM UTC 24 |
113465862115 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_alert_test.1078025229 |
|
|
Oct 15 11:10:38 AM UTC 24 |
Oct 15 11:10:39 AM UTC 24 |
21155084 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/29.uart_stress_all.1180211012 |
|
|
Oct 15 11:05:39 AM UTC 24 |
Oct 15 11:10:41 AM UTC 24 |
258806757997 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_smoke.1409160991 |
|
|
Oct 15 11:10:41 AM UTC 24 |
Oct 15 11:10:43 AM UTC 24 |
298170616 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.931466319 |
|
|
Oct 15 11:09:14 AM UTC 24 |
Oct 15 11:10:48 AM UTC 24 |
40944312438 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_fifo_full.613316470 |
|
|
Oct 15 11:09:43 AM UTC 24 |
Oct 15 11:10:55 AM UTC 24 |
100055695967 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_fifo_reset.3017654435 |
|
|
Oct 15 11:10:16 AM UTC 24 |
Oct 15 11:10:55 AM UTC 24 |
21511351423 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.3752317300 |
|
|
Oct 15 11:08:57 AM UTC 24 |
Oct 15 11:10:55 AM UTC 24 |
143507349949 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_tx_rx.2364421084 |
|
|
Oct 15 11:09:42 AM UTC 24 |
Oct 15 11:10:58 AM UTC 24 |
97099046117 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.1850476848 |
|
|
Oct 15 11:10:30 AM UTC 24 |
Oct 15 11:11:03 AM UTC 24 |
7318745233 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_fifo_full.1804628133 |
|
|
Oct 15 11:10:13 AM UTC 24 |
Oct 15 11:11:04 AM UTC 24 |
22152370139 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.4215110555 |
|
|
Oct 15 11:09:44 AM UTC 24 |
Oct 15 11:11:05 AM UTC 24 |
41887791904 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_loopback.1024987279 |
|
|
Oct 15 11:10:26 AM UTC 24 |
Oct 15 11:11:09 AM UTC 24 |
9661561458 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.3486770879 |
|
|
Oct 15 11:11:05 AM UTC 24 |
Oct 15 11:11:09 AM UTC 24 |
9103537240 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_stress_all.2979544099 |
|
|
Oct 15 11:06:21 AM UTC 24 |
Oct 15 11:11:11 AM UTC 24 |
719247672481 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_stress_all.1800856940 |
|
|
Oct 15 11:09:06 AM UTC 24 |
Oct 15 11:11:12 AM UTC 24 |
220134746867 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.1498094950 |
|
|
Oct 15 11:10:14 AM UTC 24 |
Oct 15 11:11:12 AM UTC 24 |
70138946534 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_rx_oversample.318432749 |
|
|
Oct 15 11:10:56 AM UTC 24 |
Oct 15 11:11:13 AM UTC 24 |
3484470461 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/35.uart_fifo_full.3831231877 |
|
|
Oct 15 11:08:05 AM UTC 24 |
Oct 15 11:11:16 AM UTC 24 |
110786444785 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_alert_test.2821796249 |
|
|
Oct 15 11:11:14 AM UTC 24 |
Oct 15 11:11:17 AM UTC 24 |
14363304 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_smoke.4070241680 |
|
|
Oct 15 11:11:16 AM UTC 24 |
Oct 15 11:11:19 AM UTC 24 |
314141694 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.298113651 |
|
|
Oct 15 11:05:02 AM UTC 24 |
Oct 15 11:11:20 AM UTC 24 |
118178693086 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_fifo_full.1527115779 |
|
|
Oct 15 11:05:08 AM UTC 24 |
Oct 15 11:11:22 AM UTC 24 |
107483397470 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.3208405274 |
|
|
Oct 15 11:09:35 AM UTC 24 |
Oct 15 11:11:29 AM UTC 24 |
83092041436 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_loopback.2856964915 |
|
|
Oct 15 11:11:10 AM UTC 24 |
Oct 15 11:11:35 AM UTC 24 |
5154715971 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.2833833712 |
|
|
Oct 15 11:11:03 AM UTC 24 |
Oct 15 11:11:38 AM UTC 24 |
40351307738 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_noise_filter.1269958686 |
|
|
Oct 15 11:10:59 AM UTC 24 |
Oct 15 11:11:40 AM UTC 24 |
87823617485 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_noise_filter.640494602 |
|
|
Oct 15 11:08:33 AM UTC 24 |
Oct 15 11:11:42 AM UTC 24 |
205330665874 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/33.uart_stress_all.3273592742 |
|
|
Oct 15 11:07:32 AM UTC 24 |
Oct 15 11:11:43 AM UTC 24 |
75184280754 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.1642145229 |
|
|
Oct 15 11:11:05 AM UTC 24 |
Oct 15 11:11:45 AM UTC 24 |
14742178746 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_rx_oversample.2731938574 |
|
|
Oct 15 11:11:30 AM UTC 24 |
Oct 15 11:11:45 AM UTC 24 |
6634327768 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/32.uart_stress_all.4044024619 |
|
|
Oct 15 11:07:00 AM UTC 24 |
Oct 15 11:11:45 AM UTC 24 |
296818633711 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.4084442903 |
|
|
Oct 15 11:11:44 AM UTC 24 |
Oct 15 11:11:48 AM UTC 24 |
1520042225 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_fifo_reset.1252498707 |
|
|
Oct 15 11:10:55 AM UTC 24 |
Oct 15 11:11:51 AM UTC 24 |
59760083603 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.956039022 |
|
|
Oct 15 11:10:24 AM UTC 24 |
Oct 15 11:11:55 AM UTC 24 |
141359839561 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_intr.2614686213 |
|
|
Oct 15 11:09:51 AM UTC 24 |
Oct 15 11:11:56 AM UTC 24 |
188933552516 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.1885659591 |
|
|
Oct 15 11:08:47 AM UTC 24 |
Oct 15 11:11:56 AM UTC 24 |
93149466825 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_alert_test.1482189763 |
|
|
Oct 15 11:11:55 AM UTC 24 |
Oct 15 11:11:57 AM UTC 24 |
12625391 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_tx_rx.2198579177 |
|
|
Oct 15 11:11:17 AM UTC 24 |
Oct 15 11:12:01 AM UTC 24 |
60647422218 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.616639354 |
|
|
Oct 15 11:11:21 AM UTC 24 |
Oct 15 11:12:02 AM UTC 24 |
78528819997 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_loopback.2205087936 |
|
|
Oct 15 11:11:46 AM UTC 24 |
Oct 15 11:12:02 AM UTC 24 |
3615317164 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.561074343 |
|
|
Oct 15 11:11:49 AM UTC 24 |
Oct 15 11:12:03 AM UTC 24 |
4192304110 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_tx_rx.2640142045 |
|
|
Oct 15 11:11:57 AM UTC 24 |
Oct 15 11:12:05 AM UTC 24 |
6165800011 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.1448617786 |
|
|
Oct 15 10:58:49 AM UTC 24 |
Oct 15 11:12:09 AM UTC 24 |
90331267584 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_rx_oversample.2922521544 |
|
|
Oct 15 11:12:03 AM UTC 24 |
Oct 15 11:12:12 AM UTC 24 |
4556582541 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_fifo_reset.2928952977 |
|
|
Oct 15 11:11:22 AM UTC 24 |
Oct 15 11:12:13 AM UTC 24 |
34273317270 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_stress_all.2083041748 |
|
|
Oct 15 11:10:06 AM UTC 24 |
Oct 15 11:12:13 AM UTC 24 |
51442981021 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.422587419 |
|
|
Oct 15 11:12:09 AM UTC 24 |
Oct 15 11:12:14 AM UTC 24 |
2841035273 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.1291103464 |
|
|
Oct 15 11:11:13 AM UTC 24 |
Oct 15 11:12:14 AM UTC 24 |
24248402089 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_smoke.3274124532 |
|
|
Oct 15 11:11:56 AM UTC 24 |
Oct 15 11:12:15 AM UTC 24 |
6237823952 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.3206937651 |
|
|
Oct 15 11:02:31 AM UTC 24 |
Oct 15 11:12:18 AM UTC 24 |
113358921606 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.70890122 |
|
|
Oct 15 11:12:13 AM UTC 24 |
Oct 15 11:12:18 AM UTC 24 |
965788115 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_alert_test.1218408860 |
|
|
Oct 15 11:12:20 AM UTC 24 |
Oct 15 11:12:21 AM UTC 24 |
16368365 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_intr.60302037 |
|
|
Oct 15 11:12:04 AM UTC 24 |
Oct 15 11:12:22 AM UTC 24 |
4285005712 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_smoke.385459262 |
|
|
Oct 15 11:12:23 AM UTC 24 |
Oct 15 11:12:25 AM UTC 24 |
330206699 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_fifo_full.2606286396 |
|
|
Oct 15 11:11:58 AM UTC 24 |
Oct 15 11:12:29 AM UTC 24 |
55021818333 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.3454601121 |
|
|
Oct 15 11:10:49 AM UTC 24 |
Oct 15 11:12:29 AM UTC 24 |
44420176316 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_fifo_reset.1114719517 |
|
|
Oct 15 11:12:03 AM UTC 24 |
Oct 15 11:12:31 AM UTC 24 |
10539250197 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.45653722 |
|
|
Oct 15 11:08:54 AM UTC 24 |
Oct 15 11:12:34 AM UTC 24 |
69138693985 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_loopback.994801758 |
|
|
Oct 15 11:12:13 AM UTC 24 |
Oct 15 11:12:35 AM UTC 24 |
5118308711 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_rx_oversample.3622934672 |
|
|
Oct 15 11:12:31 AM UTC 24 |
Oct 15 11:12:38 AM UTC 24 |
2348953531 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_intr.2019887629 |
|
|
Oct 15 11:11:35 AM UTC 24 |
Oct 15 11:12:40 AM UTC 24 |
89933808125 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.1405533612 |
|
|
Oct 15 11:12:02 AM UTC 24 |
Oct 15 11:12:44 AM UTC 24 |
28425664334 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.3915809549 |
|
|
Oct 15 11:11:41 AM UTC 24 |
Oct 15 11:12:49 AM UTC 24 |
31524383177 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_stress_all.2604747186 |
|
|
Oct 15 11:05:13 AM UTC 24 |
Oct 15 11:12:52 AM UTC 24 |
291244366466 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_loopback.2392064958 |
|
|
Oct 15 11:12:50 AM UTC 24 |
Oct 15 11:12:53 AM UTC 24 |
997458514 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.1161334500 |
|
|
Oct 15 11:12:45 AM UTC 24 |
Oct 15 11:12:53 AM UTC 24 |
813234306 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.915095640 |
|
|
Oct 15 11:05:12 AM UTC 24 |
Oct 15 11:12:53 AM UTC 24 |
117106375516 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.3151812077 |
|
|
Oct 15 11:12:39 AM UTC 24 |
Oct 15 11:12:53 AM UTC 24 |
3120877472 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_alert_test.3912407234 |
|
|
Oct 15 11:12:54 AM UTC 24 |
Oct 15 11:12:56 AM UTC 24 |
140822365 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.2471953156 |
|
|
Oct 15 11:12:12 AM UTC 24 |
Oct 15 11:12:59 AM UTC 24 |
60288610410 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.3747383267 |
|
|
Oct 15 11:11:43 AM UTC 24 |
Oct 15 11:13:01 AM UTC 24 |
158866685191 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_fifo_full.3199458877 |
|
|
Oct 15 11:12:26 AM UTC 24 |
Oct 15 11:13:04 AM UTC 24 |
21440280416 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_tx_rx.1629270660 |
|
|
Oct 15 11:10:42 AM UTC 24 |
Oct 15 11:13:06 AM UTC 24 |
71046788408 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_perf.3835688760 |
|
|
Oct 15 11:02:25 AM UTC 24 |
Oct 15 11:13:09 AM UTC 24 |
19651972545 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_noise_filter.3822834367 |
|
|
Oct 15 11:11:39 AM UTC 24 |
Oct 15 11:13:09 AM UTC 24 |
162828121275 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_smoke.2421521404 |
|
|
Oct 15 11:12:57 AM UTC 24 |
Oct 15 11:13:11 AM UTC 24 |
5575519975 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.2882723072 |
|
|
Oct 15 11:12:29 AM UTC 24 |
Oct 15 11:13:11 AM UTC 24 |
144069683736 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_fifo_full.337856953 |
|
|
Oct 15 11:11:20 AM UTC 24 |
Oct 15 11:13:12 AM UTC 24 |
290205346727 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_tx_rx.2201666132 |
|
|
Oct 15 11:12:24 AM UTC 24 |
Oct 15 11:13:12 AM UTC 24 |
63954851510 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.1753174365 |
|
|
Oct 15 11:12:15 AM UTC 24 |
Oct 15 11:13:16 AM UTC 24 |
3591915254 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_intr.564760435 |
|
|
Oct 15 11:12:35 AM UTC 24 |
Oct 15 11:13:17 AM UTC 24 |
18389591634 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_loopback.1270761758 |
|
|
Oct 15 11:13:13 AM UTC 24 |
Oct 15 11:13:20 AM UTC 24 |
3636381164 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.1393482457 |
|
|
Oct 15 11:08:41 AM UTC 24 |
Oct 15 11:13:21 AM UTC 24 |
100353902619 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.2822921032 |
|
|
Oct 15 11:13:12 AM UTC 24 |
Oct 15 11:13:21 AM UTC 24 |
2094684330 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_alert_test.1876712824 |
|
|
Oct 15 11:13:21 AM UTC 24 |
Oct 15 11:13:23 AM UTC 24 |
49070066 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_fifo_reset.2250151551 |
|
|
Oct 15 11:12:30 AM UTC 24 |
Oct 15 11:13:24 AM UTC 24 |
22074854398 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_noise_filter.2268895278 |
|
|
Oct 15 11:12:06 AM UTC 24 |
Oct 15 11:13:28 AM UTC 24 |
168813747775 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_smoke.2228513117 |
|
|
Oct 15 11:13:24 AM UTC 24 |
Oct 15 11:13:28 AM UTC 24 |
465349094 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.2793488813 |
|
|
Oct 15 11:12:54 AM UTC 24 |
Oct 15 11:13:33 AM UTC 24 |
2857023789 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/39.uart_perf.1574379626 |
|
|
Oct 15 11:10:03 AM UTC 24 |
Oct 15 11:13:34 AM UTC 24 |
27151131717 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.3927453615 |
|
|
Oct 15 11:13:12 AM UTC 24 |
Oct 15 11:13:34 AM UTC 24 |
39095062551 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_fifo_full.2324622008 |
|
|
Oct 15 11:13:01 AM UTC 24 |
Oct 15 11:13:35 AM UTC 24 |
187418662770 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.1596470778 |
|
|
Oct 15 11:10:29 AM UTC 24 |
Oct 15 11:13:37 AM UTC 24 |
250781100652 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_noise_filter.4107020337 |
|
|
Oct 15 11:09:22 AM UTC 24 |
Oct 15 11:13:38 AM UTC 24 |
149056744677 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_rx_oversample.1283154535 |
|
|
Oct 15 11:13:08 AM UTC 24 |
Oct 15 11:13:39 AM UTC 24 |
4149254063 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.2075268536 |
|
|
Oct 15 11:13:13 AM UTC 24 |
Oct 15 11:13:39 AM UTC 24 |
6073675141 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_intr.4276638411 |
|
|
Oct 15 11:13:10 AM UTC 24 |
Oct 15 11:13:42 AM UTC 24 |
9781870381 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.1267969144 |
|
|
Oct 15 11:13:40 AM UTC 24 |
Oct 15 11:13:43 AM UTC 24 |
802726671 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/45.uart_noise_filter.2884850281 |
|
|
Oct 15 11:13:11 AM UTC 24 |
Oct 15 11:13:45 AM UTC 24 |
50343616469 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_loopback.359283397 |
|
|
Oct 15 11:13:40 AM UTC 24 |
Oct 15 11:13:47 AM UTC 24 |
1329299853 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.886620371 |
|
|
Oct 15 11:13:37 AM UTC 24 |
Oct 15 11:13:59 AM UTC 24 |
38466045335 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_fifo_reset.3048209416 |
|
|
Oct 15 11:13:34 AM UTC 24 |
Oct 15 11:13:59 AM UTC 24 |
49900487888 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_alert_test.1343754172 |
|
|
Oct 15 11:14:00 AM UTC 24 |
Oct 15 11:14:01 AM UTC 24 |
20321466 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_smoke.1886128975 |
|
|
Oct 15 11:14:00 AM UTC 24 |
Oct 15 11:14:02 AM UTC 24 |
292265216 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/23.uart_stress_all.1925936432 |
|
|
Oct 15 11:02:37 AM UTC 24 |
Oct 15 11:14:13 AM UTC 24 |
209777794771 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_stress_all.3140127175 |
|
|
Oct 15 11:10:32 AM UTC 24 |
Oct 15 11:14:15 AM UTC 24 |
98001526444 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_noise_filter.2039862041 |
|
|
Oct 15 11:12:36 AM UTC 24 |
Oct 15 11:14:17 AM UTC 24 |
80904748780 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/34.uart_perf.3272271115 |
|
|
Oct 15 11:07:56 AM UTC 24 |
Oct 15 11:14:17 AM UTC 24 |
5219366969 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_intr.258392129 |
|
|
Oct 15 11:10:19 AM UTC 24 |
Oct 15 11:14:19 AM UTC 24 |
154383638379 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_perf.2343188655 |
|
|
Oct 15 11:10:27 AM UTC 24 |
Oct 15 11:14:19 AM UTC 24 |
7910540539 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.3717860431 |
|
|
Oct 15 11:14:20 AM UTC 24 |
Oct 15 11:14:25 AM UTC 24 |
2523045515 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.3456511509 |
|
|
Oct 15 11:13:45 AM UTC 24 |
Oct 15 11:14:28 AM UTC 24 |
2387621892 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/40.uart_noise_filter.1888821775 |
|
|
Oct 15 11:10:21 AM UTC 24 |
Oct 15 11:14:29 AM UTC 24 |
79771260962 ps |