| T655 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_loopback.3813835287 |
|
|
Feb 09 07:05:55 AM UTC 25 |
Feb 09 07:06:10 AM UTC 25 |
11783911989 ps |
| T656 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.2196505763 |
|
|
Feb 09 07:05:01 AM UTC 25 |
Feb 09 07:06:16 AM UTC 25 |
30183871638 ps |
| T657 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_tx_rx.1614354918 |
|
|
Feb 09 07:04:42 AM UTC 25 |
Feb 09 07:06:19 AM UTC 25 |
129316476975 ps |
| T658 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_alert_test.4051737330 |
|
|
Feb 09 07:06:20 AM UTC 25 |
Feb 09 07:06:22 AM UTC 25 |
36891924 ps |
| T659 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_smoke.51621500 |
|
|
Feb 09 07:06:23 AM UTC 25 |
Feb 09 07:06:26 AM UTC 25 |
504005529 ps |
| T660 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/18.uart_fifo_reset.2492167730 |
|
|
Feb 09 06:52:12 AM UTC 25 |
Feb 09 07:06:27 AM UTC 25 |
105081744996 ps |
| T661 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.957730362 |
|
|
Feb 09 07:02:52 AM UTC 25 |
Feb 09 07:06:28 AM UTC 25 |
383239147176 ps |
| T662 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_noise_filter.1866843499 |
|
|
Feb 09 07:05:37 AM UTC 25 |
Feb 09 07:06:31 AM UTC 25 |
62243436634 ps |
| T116 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.1482256737 |
|
|
Feb 09 07:02:04 AM UTC 25 |
Feb 09 07:06:42 AM UTC 25 |
64048724350 ps |
| T663 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_fifo_full.552312767 |
|
|
Feb 09 07:04:44 AM UTC 25 |
Feb 09 07:06:53 AM UTC 25 |
119311828168 ps |
| T664 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_perf.1719203330 |
|
|
Feb 09 07:01:09 AM UTC 25 |
Feb 09 07:06:54 AM UTC 25 |
15069090462 ps |
| T665 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_rx_oversample.2518997678 |
|
|
Feb 09 07:06:43 AM UTC 25 |
Feb 09 07:06:55 AM UTC 25 |
6872152741 ps |
| T188 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.3149642052 |
|
|
Feb 09 07:05:48 AM UTC 25 |
Feb 09 07:07:02 AM UTC 25 |
82110499926 ps |
| T400 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.3810193619 |
|
|
Feb 09 07:04:37 AM UTC 25 |
Feb 09 07:07:07 AM UTC 25 |
23871251704 ps |
| T666 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_perf.534266071 |
|
|
Feb 09 06:44:49 AM UTC 25 |
Feb 09 07:07:09 AM UTC 25 |
28593570637 ps |
| T170 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_stress_all.3867682842 |
|
|
Feb 09 06:54:14 AM UTC 25 |
Feb 09 07:07:10 AM UTC 25 |
501182255385 ps |
| T667 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.2072684472 |
|
|
Feb 09 07:05:30 AM UTC 25 |
Feb 09 07:07:10 AM UTC 25 |
60903893800 ps |
| T668 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_stress_all.3751348913 |
|
|
Feb 09 07:00:19 AM UTC 25 |
Feb 09 07:07:14 AM UTC 25 |
216684556544 ps |
| T669 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_fifo_reset.2789442192 |
|
|
Feb 09 07:03:09 AM UTC 25 |
Feb 09 07:07:17 AM UTC 25 |
92412444254 ps |
| T670 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.2293450289 |
|
|
Feb 09 06:58:03 AM UTC 25 |
Feb 09 07:07:22 AM UTC 25 |
106746654011 ps |
| T671 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.2667174494 |
|
|
Feb 09 07:07:07 AM UTC 25 |
Feb 09 07:07:23 AM UTC 25 |
7383820175 ps |
| T672 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_alert_test.3409175147 |
|
|
Feb 09 07:07:23 AM UTC 25 |
Feb 09 07:07:25 AM UTC 25 |
19385883 ps |
| T673 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_tx_rx.1907852882 |
|
|
Feb 09 07:06:27 AM UTC 25 |
Feb 09 07:07:25 AM UTC 25 |
139891796523 ps |
| T674 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.434807392 |
|
|
Feb 09 07:07:03 AM UTC 25 |
Feb 09 07:07:26 AM UTC 25 |
10472352575 ps |
| T675 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_smoke.239328801 |
|
|
Feb 09 07:07:24 AM UTC 25 |
Feb 09 07:07:28 AM UTC 25 |
525635576 ps |
| T676 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_loopback.1310557095 |
|
|
Feb 09 07:07:09 AM UTC 25 |
Feb 09 07:07:28 AM UTC 25 |
7390166900 ps |
| T677 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.775233588 |
|
|
Feb 09 06:54:13 AM UTC 25 |
Feb 09 07:07:29 AM UTC 25 |
64048268527 ps |
| T180 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.182782699 |
|
|
Feb 09 07:01:02 AM UTC 25 |
Feb 09 07:07:30 AM UTC 25 |
108865580299 ps |
| T421 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_fifo_full.2970198510 |
|
|
Feb 09 07:06:28 AM UTC 25 |
Feb 09 07:07:31 AM UTC 25 |
23449645610 ps |
| T678 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_fifo_full.4106109832 |
|
|
Feb 09 07:07:26 AM UTC 25 |
Feb 09 07:07:37 AM UTC 25 |
10728900646 ps |
| T679 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.2402927022 |
|
|
Feb 09 07:05:02 AM UTC 25 |
Feb 09 07:07:41 AM UTC 25 |
150122716600 ps |
| T680 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.4186996717 |
|
|
Feb 09 07:07:32 AM UTC 25 |
Feb 09 07:07:43 AM UTC 25 |
29804798972 ps |
| T186 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_stress_all.805095891 |
|
|
Feb 09 06:41:29 AM UTC 25 |
Feb 09 07:07:46 AM UTC 25 |
470022323094 ps |
| T681 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.1514543389 |
|
|
Feb 09 07:07:41 AM UTC 25 |
Feb 09 07:07:47 AM UTC 25 |
1381160742 ps |
| T168 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.2113987292 |
|
|
Feb 09 07:06:29 AM UTC 25 |
Feb 09 07:07:47 AM UTC 25 |
101971931429 ps |
| T230 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_fifo_reset.2428671586 |
|
|
Feb 09 07:07:28 AM UTC 25 |
Feb 09 07:07:51 AM UTC 25 |
16965285203 ps |
| T682 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_rx_oversample.2674227514 |
|
|
Feb 09 07:07:28 AM UTC 25 |
Feb 09 07:07:52 AM UTC 25 |
4157620519 ps |
| T683 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_noise_filter.3287843826 |
|
|
Feb 09 07:06:54 AM UTC 25 |
Feb 09 07:07:54 AM UTC 25 |
275100744325 ps |
| T684 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_loopback.3756666367 |
|
|
Feb 09 07:07:44 AM UTC 25 |
Feb 09 07:07:54 AM UTC 25 |
8018830568 ps |
| T685 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_alert_test.3066794140 |
|
|
Feb 09 07:07:53 AM UTC 25 |
Feb 09 07:07:55 AM UTC 25 |
12907171 ps |
| T686 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.2615502667 |
|
|
Feb 09 07:06:56 AM UTC 25 |
Feb 09 07:07:55 AM UTC 25 |
35584188819 ps |
| T687 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_smoke.782123453 |
|
|
Feb 09 07:07:55 AM UTC 25 |
Feb 09 07:07:58 AM UTC 25 |
246917359 ps |
| T688 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_intr.864882240 |
|
|
Feb 09 07:07:30 AM UTC 25 |
Feb 09 07:08:04 AM UTC 25 |
14618978371 ps |
| T203 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_fifo_reset.631990995 |
|
|
Feb 09 07:05:30 AM UTC 25 |
Feb 09 07:08:04 AM UTC 25 |
52475153368 ps |
| T689 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_intr.3353587109 |
|
|
Feb 09 07:06:54 AM UTC 25 |
Feb 09 07:08:07 AM UTC 25 |
31436149248 ps |
| T690 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_rx_oversample.3563283936 |
|
|
Feb 09 07:08:04 AM UTC 25 |
Feb 09 07:08:08 AM UTC 25 |
1823791121 ps |
| T117 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.716850516 |
|
|
Feb 09 06:56:57 AM UTC 25 |
Feb 09 07:08:09 AM UTC 25 |
301529528870 ps |
| T691 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_tx_rx.2417406917 |
|
|
Feb 09 07:07:26 AM UTC 25 |
Feb 09 07:08:11 AM UTC 25 |
106051142253 ps |
| T399 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.2279647164 |
|
|
Feb 09 07:03:43 AM UTC 25 |
Feb 09 07:08:11 AM UTC 25 |
53513738071 ps |
| T183 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.3972249974 |
|
|
Feb 09 06:50:31 AM UTC 25 |
Feb 09 07:08:13 AM UTC 25 |
334854420181 ps |
| T692 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_intr.1877777377 |
|
|
Feb 09 07:08:05 AM UTC 25 |
Feb 09 07:08:19 AM UTC 25 |
4471956206 ps |
| T693 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.1421875936 |
|
|
Feb 09 07:08:12 AM UTC 25 |
Feb 09 07:08:22 AM UTC 25 |
10989157932 ps |
| T694 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_loopback.2037439045 |
|
|
Feb 09 07:08:12 AM UTC 25 |
Feb 09 07:08:28 AM UTC 25 |
3793154440 ps |
| T695 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_tx_rx.4173450582 |
|
|
Feb 09 07:07:55 AM UTC 25 |
Feb 09 07:08:28 AM UTC 25 |
19109885095 ps |
| T696 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_alert_test.975120953 |
|
|
Feb 09 07:08:30 AM UTC 25 |
Feb 09 07:08:32 AM UTC 25 |
18011009 ps |
| T697 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.1916843119 |
|
|
Feb 09 07:08:09 AM UTC 25 |
Feb 09 07:08:33 AM UTC 25 |
38869208350 ps |
| T698 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_stress_all.2831448975 |
|
|
Feb 09 07:02:06 AM UTC 25 |
Feb 09 07:08:37 AM UTC 25 |
197464275403 ps |
| T699 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_stress_all.360545576 |
|
|
Feb 09 07:01:14 AM UTC 25 |
Feb 09 07:08:40 AM UTC 25 |
214316896440 ps |
| T700 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_smoke.2086670633 |
|
|
Feb 09 07:08:30 AM UTC 25 |
Feb 09 07:08:48 AM UTC 25 |
5889028259 ps |
| T701 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.385334780 |
|
|
Feb 09 07:06:03 AM UTC 25 |
Feb 09 07:08:49 AM UTC 25 |
81301872190 ps |
| T702 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_fifo_full.4045684834 |
|
|
Feb 09 07:05:29 AM UTC 25 |
Feb 09 07:08:50 AM UTC 25 |
128814659767 ps |
| T212 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_fifo_reset.1318338785 |
|
|
Feb 09 07:07:59 AM UTC 25 |
Feb 09 07:08:50 AM UTC 25 |
14538147941 ps |
| T703 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_stress_all.394911925 |
|
|
Feb 09 07:07:18 AM UTC 25 |
Feb 09 07:08:52 AM UTC 25 |
108918966376 ps |
| T704 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.1475175337 |
|
|
Feb 09 07:08:51 AM UTC 25 |
Feb 09 07:08:56 AM UTC 25 |
3048779018 ps |
| T193 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_stress_all.3834941561 |
|
|
Feb 09 07:08:22 AM UTC 25 |
Feb 09 07:08:56 AM UTC 25 |
37710039992 ps |
| T705 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.2544646306 |
|
|
Feb 09 07:07:27 AM UTC 25 |
Feb 09 07:08:59 AM UTC 25 |
149847484949 ps |
| T706 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.992148935 |
|
|
Feb 09 07:08:56 AM UTC 25 |
Feb 09 07:09:02 AM UTC 25 |
660707727 ps |
| T707 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_rx_oversample.958033948 |
|
|
Feb 09 07:08:49 AM UTC 25 |
Feb 09 07:09:07 AM UTC 25 |
5457002706 ps |
| T708 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_loopback.1599098380 |
|
|
Feb 09 07:08:57 AM UTC 25 |
Feb 09 07:09:09 AM UTC 25 |
3118637398 ps |
| T709 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_tx_rx.2225703632 |
|
|
Feb 09 07:08:33 AM UTC 25 |
Feb 09 07:09:10 AM UTC 25 |
50906829867 ps |
| T710 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.4291530742 |
|
|
Feb 09 06:55:10 AM UTC 25 |
Feb 09 07:09:10 AM UTC 25 |
78086123668 ps |
| T420 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_fifo_reset.3319801462 |
|
|
Feb 09 07:08:41 AM UTC 25 |
Feb 09 07:09:11 AM UTC 25 |
88648146026 ps |
| T711 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_alert_test.2440965656 |
|
|
Feb 09 07:09:11 AM UTC 25 |
Feb 09 07:09:13 AM UTC 25 |
13050150 ps |
| T712 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.68124527 |
|
|
Feb 09 07:07:56 AM UTC 25 |
Feb 09 07:09:13 AM UTC 25 |
85547137385 ps |
| T713 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.2033208573 |
|
|
Feb 09 07:02:21 AM UTC 25 |
Feb 09 07:09:29 AM UTC 25 |
124275735685 ps |
| T714 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_smoke.531710715 |
|
|
Feb 09 07:09:11 AM UTC 25 |
Feb 09 07:09:30 AM UTC 25 |
6159878280 ps |
| T715 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_perf.3067850016 |
|
|
Feb 09 07:08:14 AM UTC 25 |
Feb 09 07:09:32 AM UTC 25 |
5407189791 ps |
| T716 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.223703181 |
|
|
Feb 09 07:07:16 AM UTC 25 |
Feb 09 07:09:37 AM UTC 25 |
25027726559 ps |
| T717 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.2468988912 |
|
|
Feb 09 07:08:38 AM UTC 25 |
Feb 09 07:09:37 AM UTC 25 |
32779248404 ps |
| T718 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_noise_filter.3179019417 |
|
|
Feb 09 07:08:50 AM UTC 25 |
Feb 09 07:09:40 AM UTC 25 |
13053117200 ps |
| T719 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_noise_filter.2274197070 |
|
|
Feb 09 07:08:08 AM UTC 25 |
Feb 09 07:09:41 AM UTC 25 |
170734315130 ps |
| T118 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.1343282954 |
|
|
Feb 09 07:00:17 AM UTC 25 |
Feb 09 07:09:42 AM UTC 25 |
54322026699 ps |
| T720 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.1734910946 |
|
|
Feb 09 07:03:38 AM UTC 25 |
Feb 09 07:09:43 AM UTC 25 |
112374008317 ps |
| T721 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_intr.1081016268 |
|
|
Feb 09 07:08:50 AM UTC 25 |
Feb 09 07:09:45 AM UTC 25 |
51080510952 ps |
| T722 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_loopback.3461653112 |
|
|
Feb 09 07:09:43 AM UTC 25 |
Feb 09 07:09:46 AM UTC 25 |
1097809128 ps |
| T723 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.3961992193 |
|
|
Feb 09 07:09:38 AM UTC 25 |
Feb 09 07:09:49 AM UTC 25 |
2823619795 ps |
| T724 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_fifo_full.4175249547 |
|
|
Feb 09 07:08:34 AM UTC 25 |
Feb 09 07:09:50 AM UTC 25 |
66187870842 ps |
| T725 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.2957820042 |
|
|
Feb 09 07:09:42 AM UTC 25 |
Feb 09 07:09:50 AM UTC 25 |
887795428 ps |
| T726 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_alert_test.3730993946 |
|
|
Feb 09 07:09:51 AM UTC 25 |
Feb 09 07:09:53 AM UTC 25 |
43178611 ps |
| T58 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.1044221258 |
|
|
Feb 09 06:45:45 AM UTC 25 |
Feb 09 07:09:53 AM UTC 25 |
114177392474 ps |
| T59 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.1907258992 |
|
|
Feb 09 07:05:16 AM UTC 25 |
Feb 09 07:09:56 AM UTC 25 |
83888884831 ps |
| T60 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/29.uart_perf.4130971295 |
|
|
Feb 09 07:03:31 AM UTC 25 |
Feb 09 07:10:02 AM UTC 25 |
11340987963 ps |
| T61 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_fifo_full.772778192 |
|
|
Feb 09 07:07:56 AM UTC 25 |
Feb 09 07:10:02 AM UTC 25 |
215896858383 ps |
| T62 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_smoke.3659948149 |
|
|
Feb 09 07:09:51 AM UTC 25 |
Feb 09 07:10:06 AM UTC 25 |
6044698920 ps |
| T63 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_perf.3227410559 |
|
|
Feb 09 07:01:57 AM UTC 25 |
Feb 09 07:10:08 AM UTC 25 |
10106654451 ps |
| T64 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_fifo_reset.4132374042 |
|
|
Feb 09 07:09:30 AM UTC 25 |
Feb 09 07:10:10 AM UTC 25 |
89464277917 ps |
| T65 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.214946894 |
|
|
Feb 09 07:10:10 AM UTC 25 |
Feb 09 07:10:14 AM UTC 25 |
4554480947 ps |
| T66 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_rx_oversample.4211365220 |
|
|
Feb 09 07:10:03 AM UTC 25 |
Feb 09 07:10:14 AM UTC 25 |
4479096554 ps |
| T67 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.2361777360 |
|
|
Feb 09 06:47:34 AM UTC 25 |
Feb 09 07:10:18 AM UTC 25 |
148777030442 ps |
| T727 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.2211017357 |
|
|
Feb 09 07:10:15 AM UTC 25 |
Feb 09 07:10:18 AM UTC 25 |
973245965 ps |
| T728 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.1378227615 |
|
|
Feb 09 07:09:14 AM UTC 25 |
Feb 09 07:10:18 AM UTC 25 |
23661229135 ps |
| T194 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_fifo_full.3266649849 |
|
|
Feb 09 07:09:54 AM UTC 25 |
Feb 09 07:10:22 AM UTC 25 |
34452910616 ps |
| T729 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_loopback.3560973185 |
|
|
Feb 09 07:10:20 AM UTC 25 |
Feb 09 07:10:26 AM UTC 25 |
1328514901 ps |
| T730 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.405162474 |
|
|
Feb 09 07:04:11 AM UTC 25 |
Feb 09 07:10:28 AM UTC 25 |
115405122419 ps |
| T731 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_rx_oversample.623536558 |
|
|
Feb 09 07:09:31 AM UTC 25 |
Feb 09 07:10:29 AM UTC 25 |
5727364910 ps |
| T732 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_alert_test.3979137108 |
|
|
Feb 09 07:10:30 AM UTC 25 |
Feb 09 07:10:32 AM UTC 25 |
11475713 ps |
| T733 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_noise_filter.3623576238 |
|
|
Feb 09 07:07:30 AM UTC 25 |
Feb 09 07:10:34 AM UTC 25 |
91665664351 ps |
| T271 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_fifo_reset.2394804882 |
|
|
Feb 09 07:06:32 AM UTC 25 |
Feb 09 07:10:34 AM UTC 25 |
274472803608 ps |
| T734 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_smoke.314349181 |
|
|
Feb 09 07:10:32 AM UTC 25 |
Feb 09 07:10:36 AM UTC 25 |
851577085 ps |
| T735 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_tx_rx.3786553621 |
|
|
Feb 09 07:09:54 AM UTC 25 |
Feb 09 07:10:37 AM UTC 25 |
17294689034 ps |
| T736 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.3272521717 |
|
|
Feb 09 07:01:12 AM UTC 25 |
Feb 09 07:10:45 AM UTC 25 |
163819309717 ps |
| T737 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_noise_filter.4024730189 |
|
|
Feb 09 07:10:09 AM UTC 25 |
Feb 09 07:10:49 AM UTC 25 |
69182598653 ps |
| T169 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_stress_all.4226272074 |
|
|
Feb 09 07:09:50 AM UTC 25 |
Feb 09 07:10:50 AM UTC 25 |
151689271308 ps |
| T738 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_intr.309968800 |
|
|
Feb 09 07:10:06 AM UTC 25 |
Feb 09 07:10:54 AM UTC 25 |
78521078271 ps |
| T739 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_intr.2861571249 |
|
|
Feb 09 07:10:46 AM UTC 25 |
Feb 09 07:11:06 AM UTC 25 |
15661329804 ps |
| T740 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.3453564645 |
|
|
Feb 09 07:09:41 AM UTC 25 |
Feb 09 07:11:06 AM UTC 25 |
208417289421 ps |
| T741 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_noise_filter.77770298 |
|
|
Feb 09 07:09:37 AM UTC 25 |
Feb 09 07:11:08 AM UTC 25 |
97862149154 ps |
| T742 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.3858601935 |
|
|
Feb 09 07:10:50 AM UTC 25 |
Feb 09 07:11:11 AM UTC 25 |
31328895575 ps |
| T743 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_loopback.4090447854 |
|
|
Feb 09 07:11:08 AM UTC 25 |
Feb 09 07:11:11 AM UTC 25 |
316427804 ps |
| T744 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_rx_oversample.1163967680 |
|
|
Feb 09 07:10:38 AM UTC 25 |
Feb 09 07:11:12 AM UTC 25 |
4993592967 ps |
| T745 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_tx_rx.1919852830 |
|
|
Feb 09 07:09:12 AM UTC 25 |
Feb 09 07:11:12 AM UTC 25 |
54064639976 ps |
| T746 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.560921035 |
|
|
Feb 09 07:11:08 AM UTC 25 |
Feb 09 07:11:12 AM UTC 25 |
1353800812 ps |
| T747 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.2501653781 |
|
|
Feb 09 07:09:56 AM UTC 25 |
Feb 09 07:11:13 AM UTC 25 |
36301914263 ps |
| T748 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_alert_test.272928055 |
|
|
Feb 09 07:11:12 AM UTC 25 |
Feb 09 07:11:14 AM UTC 25 |
50246738 ps |
| T749 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_smoke.1183673835 |
|
|
Feb 09 07:11:13 AM UTC 25 |
Feb 09 07:11:17 AM UTC 25 |
464312393 ps |
| T176 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.2152560150 |
|
|
Feb 09 07:10:36 AM UTC 25 |
Feb 09 07:11:18 AM UTC 25 |
47469956256 ps |
| T750 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.1732158413 |
|
|
Feb 09 07:08:52 AM UTC 25 |
Feb 09 07:11:25 AM UTC 25 |
154249632187 ps |
| T751 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_rx_oversample.936446610 |
|
|
Feb 09 07:11:20 AM UTC 25 |
Feb 09 07:11:30 AM UTC 25 |
1697426103 ps |
| T752 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_intr.1720923263 |
|
|
Feb 09 07:11:26 AM UTC 25 |
Feb 09 07:11:34 AM UTC 25 |
7770912195 ps |
| T753 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_intr.661020510 |
|
|
Feb 09 07:09:33 AM UTC 25 |
Feb 09 07:11:35 AM UTC 25 |
307368760790 ps |
| T754 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.1560824094 |
|
|
Feb 09 07:11:35 AM UTC 25 |
Feb 09 07:11:39 AM UTC 25 |
4239054688 ps |
| T755 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.1678299896 |
|
|
Feb 09 07:11:40 AM UTC 25 |
Feb 09 07:11:46 AM UTC 25 |
1353639819 ps |
| T756 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_fifo_reset.2562676597 |
|
|
Feb 09 07:10:03 AM UTC 25 |
Feb 09 07:11:47 AM UTC 25 |
168430858124 ps |
| T757 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_stress_all.812899364 |
|
|
Feb 09 07:06:17 AM UTC 25 |
Feb 09 07:11:48 AM UTC 25 |
308294355732 ps |
| T758 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/19.uart_perf.284540245 |
|
|
Feb 09 06:54:10 AM UTC 25 |
Feb 09 07:11:57 AM UTC 25 |
20418964186 ps |
| T759 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_loopback.673632357 |
|
|
Feb 09 07:11:47 AM UTC 25 |
Feb 09 07:12:04 AM UTC 25 |
9622202018 ps |
| T760 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.1805108308 |
|
|
Feb 09 07:07:48 AM UTC 25 |
Feb 09 07:12:04 AM UTC 25 |
49693027747 ps |
| T761 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_alert_test.4027983775 |
|
|
Feb 09 07:12:05 AM UTC 25 |
Feb 09 07:12:07 AM UTC 25 |
12634416 ps |
| T410 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_tx_rx.1302426759 |
|
|
Feb 09 07:11:13 AM UTC 25 |
Feb 09 07:12:07 AM UTC 25 |
24285654540 ps |
| T762 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_fifo_full.2331432658 |
|
|
Feb 09 07:09:14 AM UTC 25 |
Feb 09 07:12:10 AM UTC 25 |
63225404713 ps |
| T763 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.3503137485 |
|
|
Feb 09 06:58:15 AM UTC 25 |
Feb 09 07:12:11 AM UTC 25 |
87168700767 ps |
| T119 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.578294739 |
|
|
Feb 09 07:07:49 AM UTC 25 |
Feb 09 07:12:13 AM UTC 25 |
29940296505 ps |
| T764 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_smoke.398741140 |
|
|
Feb 09 07:12:08 AM UTC 25 |
Feb 09 07:12:13 AM UTC 25 |
745585191 ps |
| T765 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.2497037774 |
|
|
Feb 09 07:01:58 AM UTC 25 |
Feb 09 07:12:13 AM UTC 25 |
69816512697 ps |
| T418 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.1970259761 |
|
|
Feb 09 06:55:10 AM UTC 25 |
Feb 09 07:12:13 AM UTC 25 |
329800774819 ps |
| T766 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_tx_rx.2823418246 |
|
|
Feb 09 07:10:34 AM UTC 25 |
Feb 09 07:12:15 AM UTC 25 |
38674807616 ps |
| T767 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.3260567695 |
|
|
Feb 09 07:08:17 AM UTC 25 |
Feb 09 07:12:20 AM UTC 25 |
94224978829 ps |
| T768 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_perf.1100590874 |
|
|
Feb 09 07:04:32 AM UTC 25 |
Feb 09 07:12:20 AM UTC 25 |
35938693073 ps |
| T187 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.2879571502 |
|
|
Feb 09 07:11:15 AM UTC 25 |
Feb 09 07:12:23 AM UTC 25 |
72558748529 ps |
| T769 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_fifo_full.2251486711 |
|
|
Feb 09 07:11:14 AM UTC 25 |
Feb 09 07:12:24 AM UTC 25 |
36496946531 ps |
| T770 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.2417798438 |
|
|
Feb 09 07:12:21 AM UTC 25 |
Feb 09 07:12:26 AM UTC 25 |
867931335 ps |
| T426 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.2897497858 |
|
|
Feb 09 07:10:15 AM UTC 25 |
Feb 09 07:12:33 AM UTC 25 |
104950814933 ps |
| T771 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_rx_oversample.1876246342 |
|
|
Feb 09 07:12:14 AM UTC 25 |
Feb 09 07:12:38 AM UTC 25 |
6611813451 ps |
| T772 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.272349554 |
|
|
Feb 09 07:08:09 AM UTC 25 |
Feb 09 07:12:38 AM UTC 25 |
110724975708 ps |
| T773 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_fifo_full.2049250283 |
|
|
Feb 09 07:10:36 AM UTC 25 |
Feb 09 07:12:39 AM UTC 25 |
49145462616 ps |
| T774 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_alert_test.985014437 |
|
|
Feb 09 07:12:39 AM UTC 25 |
Feb 09 07:12:41 AM UTC 25 |
30685460 ps |
| T775 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_noise_filter.87088170 |
|
|
Feb 09 07:11:31 AM UTC 25 |
Feb 09 07:12:43 AM UTC 25 |
99406405399 ps |
| T776 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_loopback.1165558568 |
|
|
Feb 09 07:12:24 AM UTC 25 |
Feb 09 07:12:46 AM UTC 25 |
10915842110 ps |
| T406 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_stress_all.2844322922 |
|
|
Feb 09 06:36:55 AM UTC 25 |
Feb 09 07:12:46 AM UTC 25 |
212429076377 ps |
| T777 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.3943735526 |
|
|
Feb 09 07:10:56 AM UTC 25 |
Feb 09 07:12:48 AM UTC 25 |
197295203898 ps |
| T778 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_fifo_full.331661127 |
|
|
Feb 09 07:12:11 AM UTC 25 |
Feb 09 07:12:52 AM UTC 25 |
44037203165 ps |
| T779 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_noise_filter.964586380 |
|
|
Feb 09 07:12:15 AM UTC 25 |
Feb 09 07:12:52 AM UTC 25 |
18602276832 ps |
| T413 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_fifo_reset.2019638963 |
|
|
Feb 09 07:10:38 AM UTC 25 |
Feb 09 07:12:53 AM UTC 25 |
105039990491 ps |
| T780 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_tx_rx.3520827473 |
|
|
Feb 09 07:12:43 AM UTC 25 |
Feb 09 07:12:57 AM UTC 25 |
27191964309 ps |
| T781 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_smoke.3185672630 |
|
|
Feb 09 07:12:40 AM UTC 25 |
Feb 09 07:12:58 AM UTC 25 |
5981765548 ps |
| T782 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_perf.3589994860 |
|
|
Feb 09 07:08:59 AM UTC 25 |
Feb 09 07:12:59 AM UTC 25 |
8022061231 ps |
| T783 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_rx_oversample.3047425964 |
|
|
Feb 09 07:12:49 AM UTC 25 |
Feb 09 07:13:00 AM UTC 25 |
5469555117 ps |
| T784 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_loopback.2716197313 |
|
|
Feb 09 07:13:00 AM UTC 25 |
Feb 09 07:13:03 AM UTC 25 |
927837939 ps |
| T785 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.4147342378 |
|
|
Feb 09 07:12:16 AM UTC 25 |
Feb 09 07:13:07 AM UTC 25 |
28362059593 ps |
| T786 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.2847608070 |
|
|
Feb 09 07:12:58 AM UTC 25 |
Feb 09 07:13:08 AM UTC 25 |
7624234382 ps |
| T189 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.1046896813 |
|
|
Feb 09 07:07:37 AM UTC 25 |
Feb 09 07:13:11 AM UTC 25 |
166829414070 ps |
| T787 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_alert_test.1939125703 |
|
|
Feb 09 07:13:11 AM UTC 25 |
Feb 09 07:13:14 AM UTC 25 |
34168527 ps |
| T209 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_fifo_reset.840373263 |
|
|
Feb 09 07:12:14 AM UTC 25 |
Feb 09 07:13:15 AM UTC 25 |
146443479444 ps |
| T788 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.1839969181 |
|
|
Feb 09 07:04:34 AM UTC 25 |
Feb 09 07:13:15 AM UTC 25 |
95230983774 ps |
| T789 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_smoke.2427675994 |
|
|
Feb 09 07:13:15 AM UTC 25 |
Feb 09 07:13:18 AM UTC 25 |
445933795 ps |
| T790 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.685003933 |
|
|
Feb 09 07:06:11 AM UTC 25 |
Feb 09 07:13:20 AM UTC 25 |
59964936446 ps |
| T791 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_tx_rx.1162441269 |
|
|
Feb 09 07:13:16 AM UTC 25 |
Feb 09 07:13:40 AM UTC 25 |
21598487330 ps |
| T792 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_perf.3604843186 |
|
|
Feb 09 07:10:20 AM UTC 25 |
Feb 09 07:13:41 AM UTC 25 |
14084767319 ps |
| T793 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_fifo_reset.4250052423 |
|
|
Feb 09 07:13:21 AM UTC 25 |
Feb 09 07:13:44 AM UTC 25 |
8844783566 ps |
| T794 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_tx_rx.1180133162 |
|
|
Feb 09 07:12:08 AM UTC 25 |
Feb 09 07:13:50 AM UTC 25 |
105210537159 ps |
| T795 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.3647481917 |
|
|
Feb 09 07:12:54 AM UTC 25 |
Feb 09 07:13:52 AM UTC 25 |
45921637926 ps |
| T796 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.1571077719 |
|
|
Feb 09 07:11:36 AM UTC 25 |
Feb 09 07:13:52 AM UTC 25 |
232790803763 ps |
| T797 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_stress_all.2984606754 |
|
|
Feb 09 07:11:12 AM UTC 25 |
Feb 09 07:13:54 AM UTC 25 |
281377231761 ps |
| T798 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.1033616377 |
|
|
Feb 09 07:13:53 AM UTC 25 |
Feb 09 07:13:58 AM UTC 25 |
2109521028 ps |
| T799 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.3066597169 |
|
|
Feb 09 07:12:47 AM UTC 25 |
Feb 09 07:13:59 AM UTC 25 |
122311245784 ps |
| T800 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_perf.1283969459 |
|
|
Feb 09 07:11:10 AM UTC 25 |
Feb 09 07:14:00 AM UTC 25 |
9266142811 ps |
| T801 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_perf.1906403337 |
|
|
Feb 09 07:07:10 AM UTC 25 |
Feb 09 07:14:01 AM UTC 25 |
30156701670 ps |
| T802 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/25.uart_perf.2583396330 |
|
|
Feb 09 07:00:17 AM UTC 25 |
Feb 09 07:14:02 AM UTC 25 |
29654444693 ps |
| T803 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_loopback.2465795122 |
|
|
Feb 09 07:13:53 AM UTC 25 |
Feb 09 07:14:02 AM UTC 25 |
6948344789 ps |
| T804 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_alert_test.2119198383 |
|
|
Feb 09 07:14:01 AM UTC 25 |
Feb 09 07:14:03 AM UTC 25 |
14489812 ps |
| T805 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.2480401476 |
|
|
Feb 09 07:13:52 AM UTC 25 |
Feb 09 07:14:04 AM UTC 25 |
2597153482 ps |
| T806 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.951505671 |
|
|
Feb 09 07:12:58 AM UTC 25 |
Feb 09 07:14:09 AM UTC 25 |
113784258778 ps |
| T807 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_smoke.2709328526 |
|
|
Feb 09 07:14:03 AM UTC 25 |
Feb 09 07:14:10 AM UTC 25 |
890657127 ps |
| T808 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.1810316902 |
|
|
Feb 09 07:11:58 AM UTC 25 |
Feb 09 07:14:10 AM UTC 25 |
27555998504 ps |
| T809 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.598531374 |
|
|
Feb 09 07:13:19 AM UTC 25 |
Feb 09 07:14:13 AM UTC 25 |
48728123701 ps |
| T810 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_fifo_reset.785689672 |
|
|
Feb 09 07:11:17 AM UTC 25 |
Feb 09 07:14:18 AM UTC 25 |
271770606981 ps |
| T811 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.53380155 |
|
|
Feb 09 07:11:49 AM UTC 25 |
Feb 09 07:14:21 AM UTC 25 |
122520135493 ps |
| T812 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.322175253 |
|
|
Feb 09 07:14:20 AM UTC 25 |
Feb 09 07:14:23 AM UTC 25 |
1797932017 ps |
| T813 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_stress_all.1969368414 |
|
|
Feb 09 07:10:28 AM UTC 25 |
Feb 09 07:14:25 AM UTC 25 |
409887365633 ps |
| T814 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_rx_oversample.886565964 |
|
|
Feb 09 07:14:11 AM UTC 25 |
Feb 09 07:14:26 AM UTC 25 |
2011547664 ps |
| T815 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.1241232638 |
|
|
Feb 09 07:14:24 AM UTC 25 |
Feb 09 07:14:28 AM UTC 25 |
1403485695 ps |
| T185 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_fifo_reset.976068264 |
|
|
Feb 09 07:12:47 AM UTC 25 |
Feb 09 07:14:30 AM UTC 25 |
201453549876 ps |
| T207 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_fifo_reset.14175209 |
|
|
Feb 09 07:14:11 AM UTC 25 |
Feb 09 07:14:33 AM UTC 25 |
19797562799 ps |
| T816 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_stress_all.4144519251 |
|
|
Feb 09 07:09:10 AM UTC 25 |
Feb 09 07:14:37 AM UTC 25 |
152161640449 ps |
| T817 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_loopback.3393329973 |
|
|
Feb 09 07:14:26 AM UTC 25 |
Feb 09 07:14:38 AM UTC 25 |
4902284664 ps |
| T818 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_smoke.2903170720 |
|
|
Feb 09 07:14:38 AM UTC 25 |
Feb 09 07:15:03 AM UTC 25 |
5915172531 ps |
| T819 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_alert_test.2257833920 |
|
|
Feb 09 07:14:37 AM UTC 25 |
Feb 09 07:14:39 AM UTC 25 |
12933998 ps |
| T820 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.251074888 |
|
|
Feb 09 07:10:20 AM UTC 25 |
Feb 09 07:14:44 AM UTC 25 |
183466934190 ps |
| T821 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_rx_oversample.3880426561 |
|
|
Feb 09 07:13:41 AM UTC 25 |
Feb 09 07:14:44 AM UTC 25 |
6773651666 ps |
| T272 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_stress_all.3386090434 |
|
|
Feb 09 07:12:04 AM UTC 25 |
Feb 09 07:14:52 AM UTC 25 |
279400119842 ps |
| T822 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.3237494321 |
|
|
Feb 09 07:12:11 AM UTC 25 |
Feb 09 07:14:54 AM UTC 25 |
71912903504 ps |
| T414 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_noise_filter.428366159 |
|
|
Feb 09 07:13:45 AM UTC 25 |
Feb 09 07:14:55 AM UTC 25 |
106951950137 ps |
| T823 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_intr.163761534 |
|
|
Feb 09 07:12:14 AM UTC 25 |
Feb 09 07:15:06 AM UTC 25 |
168180371683 ps |
| T824 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_noise_filter.3833379352 |
|
|
Feb 09 07:10:50 AM UTC 25 |
Feb 09 07:15:23 AM UTC 25 |
122020206160 ps |
| T825 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.2698666133 |
|
|
Feb 09 07:14:04 AM UTC 25 |
Feb 09 07:15:24 AM UTC 25 |
38967042299 ps |
| T826 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.3062274561 |
|
|
Feb 09 07:15:05 AM UTC 25 |
Feb 09 07:15:24 AM UTC 25 |
4070916518 ps |
| T827 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.1831214114 |
|
|
Feb 09 07:11:11 AM UTC 25 |
Feb 09 07:15:24 AM UTC 25 |
47774573155 ps |
| T828 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.972879234 |
|
|
Feb 09 06:39:38 AM UTC 25 |
Feb 09 07:15:31 AM UTC 25 |
80858131428 ps |
| T829 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_loopback.2351829193 |
|
|
Feb 09 07:15:24 AM UTC 25 |
Feb 09 07:15:32 AM UTC 25 |
7016656862 ps |
| T830 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_fifo_full.3144426139 |
|
|
Feb 09 07:14:40 AM UTC 25 |
Feb 09 07:15:37 AM UTC 25 |
39279795532 ps |
| T831 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_tx_rx.1959089458 |
|
|
Feb 09 07:14:03 AM UTC 25 |
Feb 09 07:15:40 AM UTC 25 |
115600756999 ps |
| T832 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_alert_test.4062329142 |
|
|
Feb 09 07:15:38 AM UTC 25 |
Feb 09 07:15:41 AM UTC 25 |
27460487 ps |
| T833 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_rx_oversample.156058329 |
|
|
Feb 09 07:14:53 AM UTC 25 |
Feb 09 07:15:44 AM UTC 25 |
5921422114 ps |
| T834 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_smoke.4159260109 |
|
|
Feb 09 07:15:42 AM UTC 25 |
Feb 09 07:15:45 AM UTC 25 |
953989556 ps |
| T835 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_tx_rx.1285861455 |
|
|
Feb 09 07:14:39 AM UTC 25 |
Feb 09 07:15:46 AM UTC 25 |
244931691390 ps |
| T836 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.1140222028 |
|
|
Feb 09 07:15:23 AM UTC 25 |
Feb 09 07:15:47 AM UTC 25 |
7094640597 ps |
| T837 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.3185157718 |
|
|
Feb 09 07:09:03 AM UTC 25 |
Feb 09 07:15:56 AM UTC 25 |
81462277680 ps |
| T838 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.1328917797 |
|
|
Feb 09 07:14:22 AM UTC 25 |
Feb 09 07:16:05 AM UTC 25 |
213988630143 ps |
| T839 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_intr.4159018340 |
|
|
Feb 09 07:14:12 AM UTC 25 |
Feb 09 07:16:13 AM UTC 25 |
55438935798 ps |
| T840 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_fifo_full.3013848352 |
|
|
Feb 09 07:15:45 AM UTC 25 |
Feb 09 07:16:24 AM UTC 25 |
41668509984 ps |
| T841 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_stress_all.2883709775 |
|
|
Feb 09 07:15:32 AM UTC 25 |
Feb 09 07:16:26 AM UTC 25 |
106339831008 ps |
| T842 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.1245074567 |
|
|
Feb 09 07:16:13 AM UTC 25 |
Feb 09 07:16:28 AM UTC 25 |
4756261114 ps |
| T843 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_rx_oversample.2317480985 |
|
|
Feb 09 07:15:48 AM UTC 25 |
Feb 09 07:16:33 AM UTC 25 |
3679694652 ps |
| T844 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_loopback.2185788559 |
|
|
Feb 09 07:16:29 AM UTC 25 |
Feb 09 07:16:33 AM UTC 25 |
4189976437 ps |
| T845 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.3365664356 |
|
|
Feb 09 07:05:14 AM UTC 25 |
Feb 09 07:16:35 AM UTC 25 |
130379367544 ps |
| T846 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.1304410930 |
|
|
Feb 09 07:13:52 AM UTC 25 |
Feb 09 07:16:43 AM UTC 25 |
291393364935 ps |
| T847 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.3517709881 |
|
|
Feb 09 07:15:46 AM UTC 25 |
Feb 09 07:16:44 AM UTC 25 |
11557725225 ps |
| T848 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_alert_test.4000372288 |
|
|
Feb 09 07:16:45 AM UTC 25 |
Feb 09 07:16:47 AM UTC 25 |
40392099 ps |
| T849 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.1423784435 |
|
|
Feb 09 07:10:24 AM UTC 25 |
Feb 09 07:16:52 AM UTC 25 |
79924143925 ps |
| T850 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_noise_filter.1559149101 |
|
|
Feb 09 07:14:14 AM UTC 25 |
Feb 09 07:16:54 AM UTC 25 |
160412312298 ps |
| T851 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_smoke.4204397796 |
|
|
Feb 09 07:16:48 AM UTC 25 |
Feb 09 07:16:54 AM UTC 25 |
650557268 ps |
| T68 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.4016658739 |
|
|
Feb 09 06:48:19 AM UTC 25 |
Feb 09 07:16:55 AM UTC 25 |
263438874080 ps |
| T852 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.1019010655 |
|
|
Feb 09 07:16:26 AM UTC 25 |
Feb 09 07:17:00 AM UTC 25 |
6866399752 ps |
| T853 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.1633262536 |
|
|
Feb 09 07:08:19 AM UTC 25 |
Feb 09 07:17:02 AM UTC 25 |
268260789417 ps |
| T854 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_noise_filter.4191822553 |
|
|
Feb 09 07:16:06 AM UTC 25 |
Feb 09 07:17:05 AM UTC 25 |
67535850184 ps |
| T855 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_fifo_reset.1925986933 |
|
|
Feb 09 07:14:45 AM UTC 25 |
Feb 09 07:17:07 AM UTC 25 |
140032938835 ps |
| T856 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_perf.2045260958 |
|
|
Feb 09 07:13:55 AM UTC 25 |
Feb 09 07:17:10 AM UTC 25 |
10348378377 ps |
| T857 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_fifo_full.2750157800 |
|
|
Feb 09 07:16:54 AM UTC 25 |
Feb 09 07:17:10 AM UTC 25 |
12006087953 ps |
| T858 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_noise_filter.832484138 |
|
|
Feb 09 07:12:53 AM UTC 25 |
Feb 09 07:17:12 AM UTC 25 |
94738827013 ps |
| T859 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.1086879862 |
|
|
Feb 09 07:15:32 AM UTC 25 |
Feb 09 07:17:13 AM UTC 25 |
5520266076 ps |