| T860 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.2361406896 |
|
|
Feb 09 07:17:10 AM UTC 25 |
Feb 09 07:17:15 AM UTC 25 |
901399166 ps |
| T861 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_tx_rx.4008249810 |
|
|
Feb 09 07:16:53 AM UTC 25 |
Feb 09 07:17:16 AM UTC 25 |
41916895435 ps |
| T862 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_rx_oversample.1973387339 |
|
|
Feb 09 07:17:01 AM UTC 25 |
Feb 09 07:17:17 AM UTC 25 |
1898421506 ps |
| T424 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.1318663669 |
|
|
Feb 09 07:15:06 AM UTC 25 |
Feb 09 07:17:22 AM UTC 25 |
137687890937 ps |
| T208 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_fifo_reset.1530694503 |
|
|
Feb 09 07:16:56 AM UTC 25 |
Feb 09 07:17:22 AM UTC 25 |
26191152439 ps |
| T863 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_fifo_full.2822405877 |
|
|
Feb 09 07:12:44 AM UTC 25 |
Feb 09 07:17:23 AM UTC 25 |
124690525576 ps |
| T864 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_fifo_full.3126824811 |
|
|
Feb 09 07:14:04 AM UTC 25 |
Feb 09 07:17:23 AM UTC 25 |
273759785725 ps |
| T865 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_loopback.787181933 |
|
|
Feb 09 07:17:13 AM UTC 25 |
Feb 09 07:17:24 AM UTC 25 |
9654674665 ps |
| T866 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.2829533564 |
|
|
Feb 09 07:17:08 AM UTC 25 |
Feb 09 07:17:24 AM UTC 25 |
19196900293 ps |
| T867 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_alert_test.1129258053 |
|
|
Feb 09 07:17:23 AM UTC 25 |
Feb 09 07:17:25 AM UTC 25 |
62928459 ps |
| T868 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_smoke.3844139116 |
|
|
Feb 09 07:17:23 AM UTC 25 |
Feb 09 07:17:26 AM UTC 25 |
292508401 ps |
| T869 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.3213920533 |
|
|
Feb 09 07:17:10 AM UTC 25 |
Feb 09 07:17:33 AM UTC 25 |
32063019585 ps |
| T870 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_rx_oversample.1768072980 |
|
|
Feb 09 07:17:26 AM UTC 25 |
Feb 09 07:17:37 AM UTC 25 |
4614868958 ps |
| T871 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.2210390508 |
|
|
Feb 09 07:07:11 AM UTC 25 |
Feb 09 07:17:38 AM UTC 25 |
83644152406 ps |
| T872 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_intr.3852415990 |
|
|
Feb 09 07:13:42 AM UTC 25 |
Feb 09 07:17:39 AM UTC 25 |
147381586054 ps |
| T873 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.114359312 |
|
|
Feb 09 07:17:37 AM UTC 25 |
Feb 09 07:17:40 AM UTC 25 |
2861762084 ps |
| T874 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.3195995792 |
|
|
Feb 09 07:12:20 AM UTC 25 |
Feb 09 07:17:44 AM UTC 25 |
191354004338 ps |
| T425 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.310769830 |
|
|
Feb 09 07:16:25 AM UTC 25 |
Feb 09 07:17:46 AM UTC 25 |
57703851538 ps |
| T875 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_perf.3886397662 |
|
|
Feb 09 07:15:24 AM UTC 25 |
Feb 09 07:17:48 AM UTC 25 |
11532230641 ps |
| T876 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_loopback.850231718 |
|
|
Feb 09 07:17:42 AM UTC 25 |
Feb 09 07:17:57 AM UTC 25 |
10165643878 ps |
| T877 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.1781707866 |
|
|
Feb 09 07:17:41 AM UTC 25 |
Feb 09 07:17:58 AM UTC 25 |
7137073012 ps |
| T878 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_intr.170760719 |
|
|
Feb 09 07:17:03 AM UTC 25 |
Feb 09 07:18:00 AM UTC 25 |
29071122653 ps |
| T879 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_tx_rx.3737585441 |
|
|
Feb 09 07:15:42 AM UTC 25 |
Feb 09 07:18:00 AM UTC 25 |
289460604749 ps |
| T880 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_alert_test.202632568 |
|
|
Feb 09 07:17:59 AM UTC 25 |
Feb 09 07:18:01 AM UTC 25 |
12717138 ps |
| T881 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.1492387268 |
|
|
Feb 09 06:59:32 AM UTC 25 |
Feb 09 07:18:03 AM UTC 25 |
87006594430 ps |
| T882 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_smoke.3688502676 |
|
|
Feb 09 07:18:00 AM UTC 25 |
Feb 09 07:18:04 AM UTC 25 |
967981486 ps |
| T883 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_tx_rx.1349573830 |
|
|
Feb 09 07:17:23 AM UTC 25 |
Feb 09 07:18:05 AM UTC 25 |
21142484320 ps |
| T884 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.3907732318 |
|
|
Feb 09 07:13:59 AM UTC 25 |
Feb 09 07:18:07 AM UTC 25 |
99720689608 ps |
| T885 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_intr.2930573404 |
|
|
Feb 09 07:17:27 AM UTC 25 |
Feb 09 07:18:10 AM UTC 25 |
50621852830 ps |
| T886 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_rx_oversample.262671632 |
|
|
Feb 09 07:18:06 AM UTC 25 |
Feb 09 07:18:13 AM UTC 25 |
5175423959 ps |
| T887 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/32.uart_perf.768715666 |
|
|
Feb 09 07:05:57 AM UTC 25 |
Feb 09 07:18:19 AM UTC 25 |
15166987601 ps |
| T888 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_noise_filter.1754178074 |
|
|
Feb 09 07:17:05 AM UTC 25 |
Feb 09 07:18:23 AM UTC 25 |
54298585870 ps |
| T889 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.486404813 |
|
|
Feb 09 07:18:14 AM UTC 25 |
Feb 09 07:18:26 AM UTC 25 |
6073328038 ps |
| T890 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.2274307005 |
|
|
Feb 09 07:18:24 AM UTC 25 |
Feb 09 07:18:28 AM UTC 25 |
650426897 ps |
| T891 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_loopback.1499358620 |
|
|
Feb 09 07:18:27 AM UTC 25 |
Feb 09 07:18:31 AM UTC 25 |
2315216461 ps |
| T892 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_noise_filter.3259341970 |
|
|
Feb 09 07:14:56 AM UTC 25 |
Feb 09 07:18:36 AM UTC 25 |
86866449197 ps |
| T893 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_fifo_full.2918497414 |
|
|
Feb 09 07:17:24 AM UTC 25 |
Feb 09 07:18:39 AM UTC 25 |
84765410524 ps |
| T894 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_tx_rx.1069000096 |
|
|
Feb 09 07:18:01 AM UTC 25 |
Feb 09 07:18:41 AM UTC 25 |
61058563263 ps |
| T895 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_alert_test.2991918806 |
|
|
Feb 09 07:18:41 AM UTC 25 |
Feb 09 07:18:43 AM UTC 25 |
25186304 ps |
| T896 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.1783425135 |
|
|
Feb 09 07:09:47 AM UTC 25 |
Feb 09 07:18:47 AM UTC 25 |
123081344341 ps |
| T190 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.340352764 |
|
|
Feb 09 07:17:38 AM UTC 25 |
Feb 09 07:18:48 AM UTC 25 |
126203208920 ps |
| T897 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.4251068733 |
|
|
Feb 09 07:17:25 AM UTC 25 |
Feb 09 07:18:49 AM UTC 25 |
85474819061 ps |
| T898 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_intr.2207473385 |
|
|
Feb 09 07:15:57 AM UTC 25 |
Feb 09 07:18:50 AM UTC 25 |
229015719093 ps |
| T899 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_stress_all.473557258 |
|
|
Feb 09 07:05:18 AM UTC 25 |
Feb 09 07:18:57 AM UTC 25 |
1043258071529 ps |
| T900 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.1850385877 |
|
|
Feb 09 07:14:45 AM UTC 25 |
Feb 09 07:18:57 AM UTC 25 |
108643583566 ps |
| T255 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_stress_all.2007487649 |
|
|
Feb 09 07:13:08 AM UTC 25 |
Feb 09 07:19:03 AM UTC 25 |
82239618564 ps |
| T901 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_stress_all.3821919938 |
|
|
Feb 09 07:18:40 AM UTC 25 |
Feb 09 07:19:10 AM UTC 25 |
60933217859 ps |
| T902 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/50.uart_fifo_reset.4113311600 |
|
|
Feb 09 07:18:44 AM UTC 25 |
Feb 09 07:19:12 AM UTC 25 |
15550814989 ps |
| T210 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_stress_all.378608247 |
|
|
Feb 09 07:12:39 AM UTC 25 |
Feb 09 07:19:19 AM UTC 25 |
117810285328 ps |
| T903 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_perf.1760017656 |
|
|
Feb 09 07:13:00 AM UTC 25 |
Feb 09 07:19:20 AM UTC 25 |
9031790952 ps |
| T904 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.2382279029 |
|
|
Feb 09 07:18:03 AM UTC 25 |
Feb 09 07:19:23 AM UTC 25 |
63965565656 ps |
| T905 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.2084331620 |
|
|
Feb 09 07:14:00 AM UTC 25 |
Feb 09 07:19:29 AM UTC 25 |
31041263918 ps |
| T201 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.1554437380 |
|
|
Feb 09 06:38:38 AM UTC 25 |
Feb 09 07:19:32 AM UTC 25 |
230854349596 ps |
| T216 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_fifo_reset.2097424246 |
|
|
Feb 09 07:17:25 AM UTC 25 |
Feb 09 07:19:33 AM UTC 25 |
109579512575 ps |
| T906 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.4204991049 |
|
|
Feb 09 07:13:03 AM UTC 25 |
Feb 09 07:19:34 AM UTC 25 |
116550322150 ps |
| T907 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/53.uart_fifo_reset.2140208329 |
|
|
Feb 09 07:18:58 AM UTC 25 |
Feb 09 07:19:35 AM UTC 25 |
57346611267 ps |
| T908 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.1911200522 |
|
|
Feb 09 07:18:20 AM UTC 25 |
Feb 09 07:19:35 AM UTC 25 |
80522105519 ps |
| T909 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_fifo_full.3117369923 |
|
|
Feb 09 07:18:02 AM UTC 25 |
Feb 09 07:19:36 AM UTC 25 |
31639465003 ps |
| T220 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_fifo_reset.3465510017 |
|
|
Feb 09 07:15:47 AM UTC 25 |
Feb 09 07:19:42 AM UTC 25 |
72683225619 ps |
| T910 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_intr.3622858205 |
|
|
Feb 09 07:18:09 AM UTC 25 |
Feb 09 07:19:46 AM UTC 25 |
40065534482 ps |
| T911 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_fifo_full.3672879403 |
|
|
Feb 09 07:13:17 AM UTC 25 |
Feb 09 07:19:47 AM UTC 25 |
318830918496 ps |
| T246 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/51.uart_fifo_reset.3661945937 |
|
|
Feb 09 07:18:49 AM UTC 25 |
Feb 09 07:19:58 AM UTC 25 |
46505888904 ps |
| T912 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_perf.4158200999 |
|
|
Feb 09 07:05:11 AM UTC 25 |
Feb 09 07:20:03 AM UTC 25 |
16397529132 ps |
| T199 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/56.uart_fifo_reset.3414133984 |
|
|
Feb 09 07:19:24 AM UTC 25 |
Feb 09 07:20:04 AM UTC 25 |
228827506947 ps |
| T913 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_stress_all.3769255741 |
|
|
Feb 09 07:14:34 AM UTC 25 |
Feb 09 07:20:05 AM UTC 25 |
427517348365 ps |
| T914 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/59.uart_fifo_reset.1775068893 |
|
|
Feb 09 07:19:37 AM UTC 25 |
Feb 09 07:20:06 AM UTC 25 |
31201104345 ps |
| T915 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_noise_filter.3970262710 |
|
|
Feb 09 07:17:33 AM UTC 25 |
Feb 09 07:20:08 AM UTC 25 |
90731733666 ps |
| T396 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.3958985281 |
|
|
Feb 09 06:55:57 AM UTC 25 |
Feb 09 07:20:16 AM UTC 25 |
410750081395 ps |
| T268 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/63.uart_fifo_reset.1574276776 |
|
|
Feb 09 07:20:06 AM UTC 25 |
Feb 09 07:20:23 AM UTC 25 |
45101248312 ps |
| T916 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.3969964083 |
|
|
Feb 09 07:17:47 AM UTC 25 |
Feb 09 07:20:28 AM UTC 25 |
152115254725 ps |
| T204 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/58.uart_fifo_reset.1672427692 |
|
|
Feb 09 07:19:35 AM UTC 25 |
Feb 09 07:20:30 AM UTC 25 |
14513832562 ps |
| T917 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_fifo_reset.40952571 |
|
|
Feb 09 07:18:04 AM UTC 25 |
Feb 09 07:20:30 AM UTC 25 |
91822473860 ps |
| T918 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/60.uart_fifo_reset.3879680288 |
|
|
Feb 09 07:19:44 AM UTC 25 |
Feb 09 07:20:40 AM UTC 25 |
19672245800 ps |
| T919 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_perf.1074284119 |
|
|
Feb 09 07:17:14 AM UTC 25 |
Feb 09 07:20:44 AM UTC 25 |
14592818239 ps |
| T920 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/54.uart_fifo_reset.1798869054 |
|
|
Feb 09 07:19:11 AM UTC 25 |
Feb 09 07:20:46 AM UTC 25 |
22079006200 ps |
| T921 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.3726093046 |
|
|
Feb 09 07:18:32 AM UTC 25 |
Feb 09 07:20:48 AM UTC 25 |
154269833224 ps |
| T922 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_perf.1868904777 |
|
|
Feb 09 07:14:27 AM UTC 25 |
Feb 09 07:20:51 AM UTC 25 |
23614212871 ps |
| T923 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/52.uart_fifo_reset.3041708461 |
|
|
Feb 09 07:18:51 AM UTC 25 |
Feb 09 07:20:59 AM UTC 25 |
127372294479 ps |
| T924 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_perf.2709572792 |
|
|
Feb 09 07:07:47 AM UTC 25 |
Feb 09 07:21:00 AM UTC 25 |
16529232580 ps |
| T250 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/67.uart_fifo_reset.839604097 |
|
|
Feb 09 07:20:41 AM UTC 25 |
Feb 09 07:21:07 AM UTC 25 |
34406408228 ps |
| T213 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/64.uart_fifo_reset.1390563790 |
|
|
Feb 09 07:20:08 AM UTC 25 |
Feb 09 07:21:08 AM UTC 25 |
17081288889 ps |
| T233 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/57.uart_fifo_reset.2362932332 |
|
|
Feb 09 07:19:32 AM UTC 25 |
Feb 09 07:21:09 AM UTC 25 |
228950415070 ps |
| T925 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_noise_filter.2784780697 |
|
|
Feb 09 07:18:11 AM UTC 25 |
Feb 09 07:21:09 AM UTC 25 |
94357506984 ps |
| T926 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/66.uart_fifo_reset.1932212035 |
|
|
Feb 09 07:20:31 AM UTC 25 |
Feb 09 07:21:22 AM UTC 25 |
60856876018 ps |
| T244 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/65.uart_fifo_reset.3476929287 |
|
|
Feb 09 07:20:23 AM UTC 25 |
Feb 09 07:21:28 AM UTC 25 |
124949382104 ps |
| T927 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/69.uart_fifo_reset.1725694386 |
|
|
Feb 09 07:20:52 AM UTC 25 |
Feb 09 07:21:28 AM UTC 25 |
10167509250 ps |
| T928 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/72.uart_fifo_reset.3939435349 |
|
|
Feb 09 07:21:09 AM UTC 25 |
Feb 09 07:21:29 AM UTC 25 |
19511344683 ps |
| T929 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/62.uart_fifo_reset.4265088003 |
|
|
Feb 09 07:20:04 AM UTC 25 |
Feb 09 07:21:30 AM UTC 25 |
41267904128 ps |
| T930 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.1150362650 |
|
|
Feb 09 07:16:55 AM UTC 25 |
Feb 09 07:21:36 AM UTC 25 |
145136813982 ps |
| T931 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/61.uart_fifo_reset.2553417934 |
|
|
Feb 09 07:19:48 AM UTC 25 |
Feb 09 07:21:40 AM UTC 25 |
88948382138 ps |
| T932 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_perf.952079627 |
|
|
Feb 09 07:18:29 AM UTC 25 |
Feb 09 07:21:41 AM UTC 25 |
6805385502 ps |
| T933 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.2133333969 |
|
|
Feb 09 07:11:11 AM UTC 25 |
Feb 09 07:21:41 AM UTC 25 |
66186600201 ps |
| T934 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/55.uart_fifo_reset.75493112 |
|
|
Feb 09 07:19:20 AM UTC 25 |
Feb 09 07:21:44 AM UTC 25 |
69946151051 ps |
| T935 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.742233353 |
|
|
Feb 09 07:16:34 AM UTC 25 |
Feb 09 07:21:45 AM UTC 25 |
81895471023 ps |
| T936 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/70.uart_fifo_reset.3274288007 |
|
|
Feb 09 07:21:01 AM UTC 25 |
Feb 09 07:21:52 AM UTC 25 |
62751943240 ps |
| T274 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/74.uart_fifo_reset.1031902724 |
|
|
Feb 09 07:21:30 AM UTC 25 |
Feb 09 07:22:01 AM UTC 25 |
27231264535 ps |
| T937 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.3966515098 |
|
|
Feb 09 07:19:21 AM UTC 25 |
Feb 09 07:22:03 AM UTC 25 |
16113105698 ps |
| T938 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/77.uart_fifo_reset.2334263031 |
|
|
Feb 09 07:21:45 AM UTC 25 |
Feb 09 07:22:11 AM UTC 25 |
79244955786 ps |
| T939 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.2952348876 |
|
|
Feb 09 07:19:05 AM UTC 25 |
Feb 09 07:22:15 AM UTC 25 |
69822946184 ps |
| T940 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_intr.1978546659 |
|
|
Feb 09 07:14:55 AM UTC 25 |
Feb 09 07:22:15 AM UTC 25 |
184434269985 ps |
| T941 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.2012934031 |
|
|
Feb 09 07:17:49 AM UTC 25 |
Feb 09 07:22:32 AM UTC 25 |
30266095086 ps |
| T942 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.2223350456 |
|
|
Feb 09 07:12:26 AM UTC 25 |
Feb 09 07:22:36 AM UTC 25 |
68735744748 ps |
| T943 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/80.uart_fifo_reset.2473509163 |
|
|
Feb 09 07:22:13 AM UTC 25 |
Feb 09 07:22:57 AM UTC 25 |
40306458416 ps |
| T206 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/76.uart_fifo_reset.3374737116 |
|
|
Feb 09 07:21:42 AM UTC 25 |
Feb 09 07:23:02 AM UTC 25 |
67777217329 ps |
| T944 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_perf.1388513838 |
|
|
Feb 09 07:12:25 AM UTC 25 |
Feb 09 07:23:07 AM UTC 25 |
14792410596 ps |
| T945 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/71.uart_fifo_reset.2773898477 |
|
|
Feb 09 07:21:08 AM UTC 25 |
Feb 09 07:23:10 AM UTC 25 |
66739501175 ps |
| T946 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.3937624209 |
|
|
Feb 09 07:09:47 AM UTC 25 |
Feb 09 07:23:13 AM UTC 25 |
152819744664 ps |
| T947 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/78.uart_fifo_reset.2904613093 |
|
|
Feb 09 07:21:53 AM UTC 25 |
Feb 09 07:23:15 AM UTC 25 |
133462310671 ps |
| T948 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.572149490 |
|
|
Feb 09 07:14:31 AM UTC 25 |
Feb 09 07:23:23 AM UTC 25 |
140607808679 ps |
| T215 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/81.uart_fifo_reset.1280447184 |
|
|
Feb 09 07:22:16 AM UTC 25 |
Feb 09 07:23:23 AM UTC 25 |
83760992364 ps |
| T221 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.630816097 |
|
|
Feb 09 07:09:09 AM UTC 25 |
Feb 09 07:23:25 AM UTC 25 |
215987976812 ps |
| T949 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.1399985790 |
|
|
Feb 09 07:21:31 AM UTC 25 |
Feb 09 07:23:53 AM UTC 25 |
11760058444 ps |
| T950 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/68.uart_fifo_reset.979296495 |
|
|
Feb 09 07:20:47 AM UTC 25 |
Feb 09 07:23:59 AM UTC 25 |
263900542494 ps |
| T951 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.1571612225 |
|
|
Feb 09 07:15:25 AM UTC 25 |
Feb 09 07:24:04 AM UTC 25 |
208549665172 ps |
| T227 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/43.uart_stress_all.2101874605 |
|
|
Feb 09 07:14:00 AM UTC 25 |
Feb 09 07:24:05 AM UTC 25 |
134780251546 ps |
| T952 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.2627202958 |
|
|
Feb 09 07:13:07 AM UTC 25 |
Feb 09 07:24:05 AM UTC 25 |
224010086154 ps |
| T953 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/34.uart_stress_all.138085228 |
|
|
Feb 09 07:07:52 AM UTC 25 |
Feb 09 07:24:07 AM UTC 25 |
311665443419 ps |
| T954 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/73.uart_fifo_reset.448382939 |
|
|
Feb 09 07:21:29 AM UTC 25 |
Feb 09 07:24:09 AM UTC 25 |
85454474019 ps |
| T228 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/86.uart_fifo_reset.3428114391 |
|
|
Feb 09 07:23:24 AM UTC 25 |
Feb 09 07:24:23 AM UTC 25 |
15530882465 ps |
| T955 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.1624113659 |
|
|
Feb 09 07:19:47 AM UTC 25 |
Feb 09 07:24:36 AM UTC 25 |
18267587794 ps |
| T956 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/82.uart_fifo_reset.211524112 |
|
|
Feb 09 07:22:37 AM UTC 25 |
Feb 09 07:24:43 AM UTC 25 |
189545202556 ps |
| T957 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.2554335831 |
|
|
Feb 09 07:22:16 AM UTC 25 |
Feb 09 07:24:48 AM UTC 25 |
19670974706 ps |
| T958 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/40.uart_perf.3923164170 |
|
|
Feb 09 07:11:48 AM UTC 25 |
Feb 09 07:24:59 AM UTC 25 |
15721954686 ps |
| T959 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/87.uart_fifo_reset.42478842 |
|
|
Feb 09 07:23:54 AM UTC 25 |
Feb 09 07:25:00 AM UTC 25 |
177816451803 ps |
| T960 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.3437865807 |
|
|
Feb 09 07:16:37 AM UTC 25 |
Feb 09 07:25:00 AM UTC 25 |
63519349196 ps |
| T961 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_stress_all.2839114978 |
|
|
Feb 09 07:17:18 AM UTC 25 |
Feb 09 07:25:10 AM UTC 25 |
321418400790 ps |
| T962 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/89.uart_fifo_reset.2633445123 |
|
|
Feb 09 07:24:06 AM UTC 25 |
Feb 09 07:25:11 AM UTC 25 |
40959045237 ps |
| T963 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/92.uart_fifo_reset.3162261412 |
|
|
Feb 09 07:24:49 AM UTC 25 |
Feb 09 07:25:18 AM UTC 25 |
154295448930 ps |
| T964 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/93.uart_fifo_reset.2015952233 |
|
|
Feb 09 07:25:01 AM UTC 25 |
Feb 09 07:25:21 AM UTC 25 |
63240031122 ps |
| T965 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/84.uart_fifo_reset.1276913436 |
|
|
Feb 09 07:23:11 AM UTC 25 |
Feb 09 07:25:34 AM UTC 25 |
122369063058 ps |
| T966 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/85.uart_fifo_reset.84657225 |
|
|
Feb 09 07:23:15 AM UTC 25 |
Feb 09 07:25:40 AM UTC 25 |
122384399061 ps |
| T967 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/90.uart_fifo_reset.20397237 |
|
|
Feb 09 07:24:09 AM UTC 25 |
Feb 09 07:25:41 AM UTC 25 |
86673856564 ps |
| T968 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/75.uart_fifo_reset.1441815365 |
|
|
Feb 09 07:21:37 AM UTC 25 |
Feb 09 07:25:46 AM UTC 25 |
112365467254 ps |
| T69 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.3483514007 |
|
|
Feb 09 07:17:17 AM UTC 25 |
Feb 09 07:25:50 AM UTC 25 |
87669170888 ps |
| T422 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/79.uart_fifo_reset.423435825 |
|
|
Feb 09 07:22:02 AM UTC 25 |
Feb 09 07:26:03 AM UTC 25 |
112848165098 ps |
| T969 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/91.uart_fifo_reset.2710684747 |
|
|
Feb 09 07:24:36 AM UTC 25 |
Feb 09 07:26:05 AM UTC 25 |
24872574720 ps |
| T970 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/97.uart_fifo_reset.2551010837 |
|
|
Feb 09 07:25:41 AM UTC 25 |
Feb 09 07:26:07 AM UTC 25 |
30194038592 ps |
| T971 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_stress_all.499885060 |
|
|
Feb 09 07:17:58 AM UTC 25 |
Feb 09 07:26:11 AM UTC 25 |
49300858957 ps |
| T972 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/83.uart_fifo_reset.1311470905 |
|
|
Feb 09 07:23:03 AM UTC 25 |
Feb 09 07:26:16 AM UTC 25 |
61490254890 ps |
| T240 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/95.uart_fifo_reset.427833764 |
|
|
Feb 09 07:25:18 AM UTC 25 |
Feb 09 07:26:19 AM UTC 25 |
66067247705 ps |
| T973 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.3526341212 |
|
|
Feb 09 07:20:49 AM UTC 25 |
Feb 09 07:26:27 AM UTC 25 |
47191587795 ps |
| T231 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/100.uart_fifo_reset.4153218526 |
|
|
Feb 09 07:26:12 AM UTC 25 |
Feb 09 07:26:29 AM UTC 25 |
14176266458 ps |
| T974 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.2523124836 |
|
|
Feb 09 07:19:33 AM UTC 25 |
Feb 09 07:26:37 AM UTC 25 |
164074339022 ps |
| T975 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_perf.3315691752 |
|
|
Feb 09 06:51:47 AM UTC 25 |
Feb 09 07:26:43 AM UTC 25 |
31468707757 ps |
| T976 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/23.uart_perf.1893094192 |
|
|
Feb 09 06:58:13 AM UTC 25 |
Feb 09 07:26:55 AM UTC 25 |
29814226443 ps |
| T977 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/99.uart_fifo_reset.972922376 |
|
|
Feb 09 07:26:06 AM UTC 25 |
Feb 09 07:26:57 AM UTC 25 |
25949025869 ps |
| T978 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/106.uart_fifo_reset.3169158665 |
|
|
Feb 09 07:26:43 AM UTC 25 |
Feb 09 07:27:05 AM UTC 25 |
21426029243 ps |
| T979 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/103.uart_fifo_reset.2870390865 |
|
|
Feb 09 07:26:28 AM UTC 25 |
Feb 09 07:27:06 AM UTC 25 |
9697445312 ps |
| T191 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/96.uart_fifo_reset.82145565 |
|
|
Feb 09 07:25:35 AM UTC 25 |
Feb 09 07:27:10 AM UTC 25 |
61711184043 ps |
| T980 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/107.uart_fifo_reset.2752144445 |
|
|
Feb 09 07:26:56 AM UTC 25 |
Feb 09 07:27:14 AM UTC 25 |
31402938141 ps |
| T981 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.1510673529 |
|
|
Feb 09 07:18:37 AM UTC 25 |
Feb 09 07:27:14 AM UTC 25 |
49740879719 ps |
| T982 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/88.uart_fifo_reset.933326500 |
|
|
Feb 09 07:24:05 AM UTC 25 |
Feb 09 07:27:17 AM UTC 25 |
227550561428 ps |
| T276 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/102.uart_fifo_reset.3898618192 |
|
|
Feb 09 07:26:20 AM UTC 25 |
Feb 09 07:27:18 AM UTC 25 |
60277553390 ps |
| T983 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/101.uart_fifo_reset.2157227563 |
|
|
Feb 09 07:26:17 AM UTC 25 |
Feb 09 07:27:18 AM UTC 25 |
66540724850 ps |
| T984 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.2890624049 |
|
|
Feb 09 07:24:44 AM UTC 25 |
Feb 09 07:27:20 AM UTC 25 |
22204328366 ps |
| T985 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/108.uart_fifo_reset.446872951 |
|
|
Feb 09 07:26:57 AM UTC 25 |
Feb 09 07:27:41 AM UTC 25 |
96032330986 ps |
| T986 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.3887966879 |
|
|
Feb 09 07:24:05 AM UTC 25 |
Feb 09 07:27:45 AM UTC 25 |
13500787014 ps |
| T987 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/109.uart_fifo_reset.2319104426 |
|
|
Feb 09 07:27:06 AM UTC 25 |
Feb 09 07:27:59 AM UTC 25 |
29438558560 ps |
| T238 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/115.uart_fifo_reset.1299278367 |
|
|
Feb 09 07:27:19 AM UTC 25 |
Feb 09 07:28:05 AM UTC 25 |
18521546947 ps |
| T988 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.3969267670 |
|
|
Feb 09 07:23:26 AM UTC 25 |
Feb 09 07:28:25 AM UTC 25 |
32802657809 ps |
| T989 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/94.uart_fifo_reset.2725770449 |
|
|
Feb 09 07:25:11 AM UTC 25 |
Feb 09 07:28:29 AM UTC 25 |
74816791720 ps |
| T990 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.1105796544 |
|
|
Feb 09 07:21:54 AM UTC 25 |
Feb 09 07:28:30 AM UTC 25 |
36281589962 ps |
| T991 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/119.uart_fifo_reset.437673951 |
|
|
Feb 09 07:27:45 AM UTC 25 |
Feb 09 07:28:30 AM UTC 25 |
24448536793 ps |
| T992 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.281336067 |
|
|
Feb 09 07:14:29 AM UTC 25 |
Feb 09 07:28:31 AM UTC 25 |
107689767846 ps |
| T993 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/48.uart_perf.2511986878 |
|
|
Feb 09 07:17:45 AM UTC 25 |
Feb 09 07:28:36 AM UTC 25 |
11320484836 ps |
| T994 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/104.uart_fifo_reset.3568933479 |
|
|
Feb 09 07:26:30 AM UTC 25 |
Feb 09 07:28:38 AM UTC 25 |
142131277907 ps |
| T995 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.4004521064 |
|
|
Feb 09 07:21:08 AM UTC 25 |
Feb 09 07:28:39 AM UTC 25 |
32509857719 ps |
| T217 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/113.uart_fifo_reset.267354892 |
|
|
Feb 09 07:27:15 AM UTC 25 |
Feb 09 07:28:42 AM UTC 25 |
194945543087 ps |
| T996 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/122.uart_fifo_reset.264053881 |
|
|
Feb 09 07:28:26 AM UTC 25 |
Feb 09 07:28:46 AM UTC 25 |
11935806660 ps |
| T248 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/118.uart_fifo_reset.3344670421 |
|
|
Feb 09 07:27:41 AM UTC 25 |
Feb 09 07:28:50 AM UTC 25 |
31809088487 ps |
| T997 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/128.uart_fifo_reset.1321977851 |
|
|
Feb 09 07:28:39 AM UTC 25 |
Feb 09 07:28:51 AM UTC 25 |
27799639267 ps |
| T998 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/120.uart_fifo_reset.1651401027 |
|
|
Feb 09 07:28:00 AM UTC 25 |
Feb 09 07:28:56 AM UTC 25 |
23206861958 ps |
| T999 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.939200040 |
|
|
Feb 09 07:18:50 AM UTC 25 |
Feb 09 07:29:03 AM UTC 25 |
414679004289 ps |
| T1000 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.193686724 |
|
|
Feb 09 07:24:08 AM UTC 25 |
Feb 09 07:29:06 AM UTC 25 |
91222775707 ps |
| T1001 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.1288467266 |
|
|
Feb 09 07:21:45 AM UTC 25 |
Feb 09 07:29:08 AM UTC 25 |
197744105144 ps |
| T1002 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/127.uart_fifo_reset.2808761113 |
|
|
Feb 09 07:28:37 AM UTC 25 |
Feb 09 07:29:09 AM UTC 25 |
7896643627 ps |
| T224 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/116.uart_fifo_reset.2771655849 |
|
|
Feb 09 07:27:19 AM UTC 25 |
Feb 09 07:29:10 AM UTC 25 |
131510105169 ps |
| T1003 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.820177910 |
|
|
Feb 09 07:22:03 AM UTC 25 |
Feb 09 07:29:13 AM UTC 25 |
71577034711 ps |
| T70 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.3223618790 |
|
|
Feb 09 07:20:06 AM UTC 25 |
Feb 09 07:29:16 AM UTC 25 |
43316881835 ps |
| T1004 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.1655247912 |
|
|
Feb 09 07:23:08 AM UTC 25 |
Feb 09 07:29:18 AM UTC 25 |
31481796984 ps |
| T1005 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/123.uart_fifo_reset.203442597 |
|
|
Feb 09 07:28:30 AM UTC 25 |
Feb 09 07:29:22 AM UTC 25 |
52952542796 ps |
| T1006 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.1384600391 |
|
|
Feb 09 07:19:59 AM UTC 25 |
Feb 09 07:29:29 AM UTC 25 |
37023497488 ps |
| T1007 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.2144323580 |
|
|
Feb 09 07:20:31 AM UTC 25 |
Feb 09 07:29:29 AM UTC 25 |
116547702088 ps |
| T1008 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/124.uart_fifo_reset.1940720939 |
|
|
Feb 09 07:28:31 AM UTC 25 |
Feb 09 07:29:32 AM UTC 25 |
184865093628 ps |
| T1009 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/135.uart_fifo_reset.306574578 |
|
|
Feb 09 07:29:03 AM UTC 25 |
Feb 09 07:29:33 AM UTC 25 |
26603127547 ps |
| T247 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/111.uart_fifo_reset.4210932681 |
|
|
Feb 09 07:27:11 AM UTC 25 |
Feb 09 07:29:33 AM UTC 25 |
142904837382 ps |
| T1010 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/133.uart_fifo_reset.2958735983 |
|
|
Feb 09 07:28:52 AM UTC 25 |
Feb 09 07:29:39 AM UTC 25 |
29894149645 ps |
| T1011 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/126.uart_fifo_reset.2662096957 |
|
|
Feb 09 07:28:32 AM UTC 25 |
Feb 09 07:29:43 AM UTC 25 |
28840382943 ps |
| T1012 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/139.uart_fifo_reset.3544418174 |
|
|
Feb 09 07:29:12 AM UTC 25 |
Feb 09 07:29:46 AM UTC 25 |
11015650956 ps |
| T258 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.3307661663 |
|
|
Feb 09 07:19:29 AM UTC 25 |
Feb 09 07:29:46 AM UTC 25 |
227483536096 ps |
| T1013 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/131.uart_fifo_reset.1723601075 |
|
|
Feb 09 07:28:46 AM UTC 25 |
Feb 09 07:29:46 AM UTC 25 |
70047474222 ps |
| T234 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/130.uart_fifo_reset.2293019736 |
|
|
Feb 09 07:28:42 AM UTC 25 |
Feb 09 07:29:50 AM UTC 25 |
50224891617 ps |
| T1014 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/110.uart_fifo_reset.3678125048 |
|
|
Feb 09 07:27:08 AM UTC 25 |
Feb 09 07:29:54 AM UTC 25 |
166753780440 ps |
| T239 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/121.uart_fifo_reset.3650883419 |
|
|
Feb 09 07:28:05 AM UTC 25 |
Feb 09 07:29:55 AM UTC 25 |
140503919952 ps |
| T1015 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.1686789914 |
|
|
Feb 09 07:21:00 AM UTC 25 |
Feb 09 07:29:57 AM UTC 25 |
700851823547 ps |
| T241 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/143.uart_fifo_reset.354529783 |
|
|
Feb 09 07:29:23 AM UTC 25 |
Feb 09 07:29:57 AM UTC 25 |
40298049856 ps |
| T236 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/136.uart_fifo_reset.1254201117 |
|
|
Feb 09 07:29:07 AM UTC 25 |
Feb 09 07:29:59 AM UTC 25 |
33628517134 ps |
| T254 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/134.uart_fifo_reset.3654809736 |
|
|
Feb 09 07:28:56 AM UTC 25 |
Feb 09 07:30:02 AM UTC 25 |
165749284942 ps |
| T1016 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/28.uart_perf.3138153810 |
|
|
Feb 09 07:02:51 AM UTC 25 |
Feb 09 07:30:05 AM UTC 25 |
31143506920 ps |
| T1017 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/132.uart_fifo_reset.3348261915 |
|
|
Feb 09 07:28:50 AM UTC 25 |
Feb 09 07:30:18 AM UTC 25 |
100065765698 ps |
| T1018 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/146.uart_fifo_reset.3125682281 |
|
|
Feb 09 07:29:32 AM UTC 25 |
Feb 09 07:30:19 AM UTC 25 |
32370330205 ps |
| T1019 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/151.uart_fifo_reset.3024425425 |
|
|
Feb 09 07:29:47 AM UTC 25 |
Feb 09 07:30:19 AM UTC 25 |
11430583222 ps |
| T1020 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/105.uart_fifo_reset.1653851780 |
|
|
Feb 09 07:26:38 AM UTC 25 |
Feb 09 07:30:21 AM UTC 25 |
227543798675 ps |
| T1021 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/159.uart_fifo_reset.2050313367 |
|
|
Feb 09 07:30:00 AM UTC 25 |
Feb 09 07:30:25 AM UTC 25 |
32151060030 ps |
| T1022 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/145.uart_fifo_reset.607375752 |
|
|
Feb 09 07:29:30 AM UTC 25 |
Feb 09 07:30:30 AM UTC 25 |
33298716513 ps |
| T262 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/160.uart_fifo_reset.1535751401 |
|
|
Feb 09 07:30:02 AM UTC 25 |
Feb 09 07:30:32 AM UTC 25 |
106114114963 ps |
| T1023 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/156.uart_fifo_reset.1426253698 |
|
|
Feb 09 07:29:56 AM UTC 25 |
Feb 09 07:30:36 AM UTC 25 |
17782172838 ps |
| T1024 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_perf.3478615192 |
|
|
Feb 09 07:16:33 AM UTC 25 |
Feb 09 07:30:38 AM UTC 25 |
17298837154 ps |
| T1025 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/163.uart_fifo_reset.355215229 |
|
|
Feb 09 07:30:20 AM UTC 25 |
Feb 09 07:30:40 AM UTC 25 |
6980101975 ps |
| T1026 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/112.uart_fifo_reset.2898003084 |
|
|
Feb 09 07:27:15 AM UTC 25 |
Feb 09 07:30:41 AM UTC 25 |
107652133846 ps |
| T71 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.3811238504 |
|
|
Feb 09 07:20:30 AM UTC 25 |
Feb 09 07:30:44 AM UTC 25 |
64070409364 ps |
| T281 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/161.uart_fifo_reset.2663635528 |
|
|
Feb 09 07:30:05 AM UTC 25 |
Feb 09 07:30:45 AM UTC 25 |
21458021910 ps |
| T1027 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/137.uart_fifo_reset.1525628949 |
|
|
Feb 09 07:29:09 AM UTC 25 |
Feb 09 07:30:47 AM UTC 25 |
45120829599 ps |
| T1028 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/168.uart_fifo_reset.964533968 |
|
|
Feb 09 07:30:33 AM UTC 25 |
Feb 09 07:30:48 AM UTC 25 |
12213978150 ps |
| T1029 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/157.uart_fifo_reset.2102990406 |
|
|
Feb 09 07:29:58 AM UTC 25 |
Feb 09 07:30:58 AM UTC 25 |
85070112086 ps |
| T1030 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/173.uart_fifo_reset.973315456 |
|
|
Feb 09 07:30:45 AM UTC 25 |
Feb 09 07:31:07 AM UTC 25 |
11177476910 ps |
| T242 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/170.uart_fifo_reset.1833640852 |
|
|
Feb 09 07:30:39 AM UTC 25 |
Feb 09 07:31:09 AM UTC 25 |
17903168835 ps |
| T263 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/162.uart_fifo_reset.593545758 |
|
|
Feb 09 07:30:18 AM UTC 25 |
Feb 09 07:31:09 AM UTC 25 |
91379966335 ps |
| T275 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/171.uart_fifo_reset.1813752941 |
|
|
Feb 09 07:30:41 AM UTC 25 |
Feb 09 07:31:10 AM UTC 25 |
23654602199 ps |
| T1031 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.4168564732 |
|
|
Feb 09 07:24:23 AM UTC 25 |
Feb 09 07:31:12 AM UTC 25 |
184610000220 ps |
| T1032 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/142.uart_fifo_reset.184237489 |
|
|
Feb 09 07:29:19 AM UTC 25 |
Feb 09 07:31:12 AM UTC 25 |
202575991333 ps |
| T1033 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/152.uart_fifo_reset.697653971 |
|
|
Feb 09 07:29:47 AM UTC 25 |
Feb 09 07:31:19 AM UTC 25 |
20588022825 ps |
| T229 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/164.uart_fifo_reset.3558832618 |
|
|
Feb 09 07:30:20 AM UTC 25 |
Feb 09 07:31:19 AM UTC 25 |
27814108524 ps |
| T1034 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/175.uart_fifo_reset.3787658581 |
|
|
Feb 09 07:30:48 AM UTC 25 |
Feb 09 07:31:20 AM UTC 25 |
15572257758 ps |
| T1035 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/178.uart_fifo_reset.750962236 |
|
|
Feb 09 07:31:08 AM UTC 25 |
Feb 09 07:31:23 AM UTC 25 |
56449286641 ps |
| T1036 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/149.uart_fifo_reset.3084720520 |
|
|
Feb 09 07:29:39 AM UTC 25 |
Feb 09 07:31:23 AM UTC 25 |
34146083115 ps |
| T1037 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/167.uart_fifo_reset.3657080088 |
|
|
Feb 09 07:30:31 AM UTC 25 |
Feb 09 07:31:25 AM UTC 25 |
53871423097 ps |
| T1038 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/174.uart_fifo_reset.2870212302 |
|
|
Feb 09 07:30:46 AM UTC 25 |
Feb 09 07:31:34 AM UTC 25 |
56886925077 ps |
| T218 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/172.uart_fifo_reset.1647658522 |
|
|
Feb 09 07:30:42 AM UTC 25 |
Feb 09 07:31:34 AM UTC 25 |
68332283150 ps |
| T223 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/114.uart_fifo_reset.2127077373 |
|
|
Feb 09 07:27:18 AM UTC 25 |
Feb 09 07:31:34 AM UTC 25 |
92226662978 ps |
| T1039 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/188.uart_fifo_reset.2369243857 |
|
|
Feb 09 07:31:24 AM UTC 25 |
Feb 09 07:31:40 AM UTC 25 |
72996109435 ps |
| T1040 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/138.uart_fifo_reset.4052209307 |
|
|
Feb 09 07:29:10 AM UTC 25 |
Feb 09 07:31:44 AM UTC 25 |
88104123686 ps |
| T1041 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/140.uart_fifo_reset.3593286359 |
|
|
Feb 09 07:29:14 AM UTC 25 |
Feb 09 07:31:45 AM UTC 25 |
57554434956 ps |
| T1042 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/183.uart_fifo_reset.1842612954 |
|
|
Feb 09 07:31:14 AM UTC 25 |
Feb 09 07:31:47 AM UTC 25 |
29656392699 ps |
| T1043 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/182.uart_fifo_reset.956819996 |
|
|
Feb 09 07:31:14 AM UTC 25 |
Feb 09 07:31:49 AM UTC 25 |
74608489537 ps |
| T1044 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.2646712721 |
|
|
Feb 09 07:21:42 AM UTC 25 |
Feb 09 07:31:57 AM UTC 25 |
40806861219 ps |
| T1045 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.3149223789 |
|
|
Feb 09 07:26:08 AM UTC 25 |
Feb 09 07:31:58 AM UTC 25 |
108559981795 ps |
| T1046 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.2785903085 |
|
|
Feb 09 07:21:41 AM UTC 25 |
Feb 09 07:32:01 AM UTC 25 |
122155885588 ps |
| T1047 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/176.uart_fifo_reset.413618432 |
|
|
Feb 09 07:30:49 AM UTC 25 |
Feb 09 07:32:03 AM UTC 25 |
123661120230 ps |
| T1048 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/155.uart_fifo_reset.4145016442 |
|
|
Feb 09 07:29:55 AM UTC 25 |
Feb 09 07:32:04 AM UTC 25 |
383483688699 ps |
| T1049 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/180.uart_fifo_reset.3354971160 |
|
|
Feb 09 07:31:10 AM UTC 25 |
Feb 09 07:32:06 AM UTC 25 |
30296370655 ps |
| T243 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/181.uart_fifo_reset.650480493 |
|
|
Feb 09 07:31:12 AM UTC 25 |
Feb 09 07:32:06 AM UTC 25 |
73458276827 ps |
| T279 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/141.uart_fifo_reset.3715709987 |
|
|
Feb 09 07:29:17 AM UTC 25 |
Feb 09 07:32:06 AM UTC 25 |
83858251687 ps |
| T1050 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/192.uart_fifo_reset.4126551325 |
|
|
Feb 09 07:31:37 AM UTC 25 |
Feb 09 07:32:06 AM UTC 25 |
39275742114 ps |
| T1051 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/191.uart_fifo_reset.1785302357 |
|
|
Feb 09 07:31:35 AM UTC 25 |
Feb 09 07:32:07 AM UTC 25 |
29044805608 ps |
| T232 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/195.uart_fifo_reset.317709299 |
|
|
Feb 09 07:31:47 AM UTC 25 |
Feb 09 07:32:11 AM UTC 25 |
10781625344 ps |
| T1052 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/194.uart_fifo_reset.2250349013 |
|
|
Feb 09 07:31:45 AM UTC 25 |
Feb 09 07:32:12 AM UTC 25 |
35204445800 ps |
| T1053 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/196.uart_fifo_reset.3286116698 |
|
|
Feb 09 07:31:49 AM UTC 25 |
Feb 09 07:32:14 AM UTC 25 |
42032187773 ps |
| T1054 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/247.uart_fifo_reset.3521478734 |
|
|
Feb 09 07:33:41 AM UTC 25 |
Feb 09 07:34:03 AM UTC 25 |
110548284068 ps |
| T270 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/148.uart_fifo_reset.359779513 |
|
|
Feb 09 07:29:33 AM UTC 25 |
Feb 09 07:32:15 AM UTC 25 |
70985320919 ps |