| T1062 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/152.uart_fifo_reset.4276313001 |
|
|
Oct 15 11:20:20 AM UTC 24 |
Oct 15 11:22:05 AM UTC 24 |
212159370585 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/136.uart_fifo_reset.48082445 |
|
|
Oct 15 11:19:48 AM UTC 24 |
Oct 15 11:22:06 AM UTC 24 |
106016299530 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/159.uart_fifo_reset.3549974473 |
|
|
Oct 15 11:20:30 AM UTC 24 |
Oct 15 11:22:07 AM UTC 24 |
254106834679 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/203.uart_fifo_reset.993918189 |
|
|
Oct 15 11:21:45 AM UTC 24 |
Oct 15 11:22:07 AM UTC 24 |
17422114220 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/143.uart_fifo_reset.10604169 |
|
|
Oct 15 11:19:58 AM UTC 24 |
Oct 15 11:22:08 AM UTC 24 |
41550275957 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/205.uart_fifo_reset.2237194891 |
|
|
Oct 15 11:21:50 AM UTC 24 |
Oct 15 11:22:12 AM UTC 24 |
38745326151 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/185.uart_fifo_reset.159705035 |
|
|
Oct 15 11:21:19 AM UTC 24 |
Oct 15 11:22:16 AM UTC 24 |
60879094528 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/31.uart_perf.519233201 |
|
|
Oct 15 11:06:21 AM UTC 24 |
Oct 15 11:22:17 AM UTC 24 |
18951689651 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/190.uart_fifo_reset.788680145 |
|
|
Oct 15 11:21:29 AM UTC 24 |
Oct 15 11:22:19 AM UTC 24 |
231992007674 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2791111068 |
|
|
Oct 15 11:21:47 AM UTC 24 |
Oct 15 11:22:19 AM UTC 24 |
17984105102 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2481379867 |
|
|
Oct 15 11:21:51 AM UTC 24 |
Oct 15 11:22:23 AM UTC 24 |
12990167427 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/101.uart_fifo_reset.3523403530 |
|
|
Oct 15 11:19:02 AM UTC 24 |
Oct 15 11:22:23 AM UTC 24 |
185970609975 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/97.uart_fifo_reset.2419058342 |
|
|
Oct 15 11:18:54 AM UTC 24 |
Oct 15 11:22:23 AM UTC 24 |
113134715676 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_perf.3453876257 |
|
|
Oct 15 11:14:34 AM UTC 24 |
Oct 15 11:22:23 AM UTC 24 |
9744476379 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/193.uart_fifo_reset.848085893 |
|
|
Oct 15 11:21:38 AM UTC 24 |
Oct 15 11:22:24 AM UTC 24 |
105663290787 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/197.uart_fifo_reset.1381064816 |
|
|
Oct 15 11:21:42 AM UTC 24 |
Oct 15 11:22:24 AM UTC 24 |
71149514337 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/175.uart_fifo_reset.1029166373 |
|
|
Oct 15 11:20:54 AM UTC 24 |
Oct 15 11:22:31 AM UTC 24 |
151429969339 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/186.uart_fifo_reset.154804903 |
|
|
Oct 15 11:21:21 AM UTC 24 |
Oct 15 11:22:31 AM UTC 24 |
94531112324 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/210.uart_fifo_reset.3685260327 |
|
|
Oct 15 11:22:05 AM UTC 24 |
Oct 15 11:22:33 AM UTC 24 |
87646976998 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/133.uart_fifo_reset.2687328690 |
|
|
Oct 15 11:19:43 AM UTC 24 |
Oct 15 11:22:34 AM UTC 24 |
207439561976 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/195.uart_fifo_reset.2106190720 |
|
|
Oct 15 11:21:40 AM UTC 24 |
Oct 15 11:22:39 AM UTC 24 |
69155435003 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/198.uart_fifo_reset.952977332 |
|
|
Oct 15 11:21:44 AM UTC 24 |
Oct 15 11:22:39 AM UTC 24 |
16203720184 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2329276726 |
|
|
Oct 15 11:21:51 AM UTC 24 |
Oct 15 11:22:44 AM UTC 24 |
26340628118 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/220.uart_fifo_reset.1500828076 |
|
|
Oct 15 11:22:19 AM UTC 24 |
Oct 15 11:22:46 AM UTC 24 |
27590906843 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3688666920 |
|
|
Oct 15 11:21:45 AM UTC 24 |
Oct 15 11:22:51 AM UTC 24 |
107076110779 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/213.uart_fifo_reset.413417113 |
|
|
Oct 15 11:22:07 AM UTC 24 |
Oct 15 11:22:51 AM UTC 24 |
19474679861 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/217.uart_fifo_reset.2255098002 |
|
|
Oct 15 11:22:12 AM UTC 24 |
Oct 15 11:22:52 AM UTC 24 |
25050222924 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/146.uart_fifo_reset.1573674103 |
|
|
Oct 15 11:20:06 AM UTC 24 |
Oct 15 11:22:52 AM UTC 24 |
76957261011 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/176.uart_fifo_reset.1347949682 |
|
|
Oct 15 11:21:00 AM UTC 24 |
Oct 15 11:22:54 AM UTC 24 |
38917426166 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/229.uart_fifo_reset.3867030506 |
|
|
Oct 15 11:22:32 AM UTC 24 |
Oct 15 11:22:55 AM UTC 24 |
8271562492 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/214.uart_fifo_reset.2713166225 |
|
|
Oct 15 11:22:08 AM UTC 24 |
Oct 15 11:23:02 AM UTC 24 |
102963644141 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/209.uart_fifo_reset.3439371379 |
|
|
Oct 15 11:22:02 AM UTC 24 |
Oct 15 11:23:03 AM UTC 24 |
76893639022 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/226.uart_fifo_reset.2720857247 |
|
|
Oct 15 11:22:25 AM UTC 24 |
Oct 15 11:23:06 AM UTC 24 |
237592903280 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/191.uart_fifo_reset.2906775050 |
|
|
Oct 15 11:21:33 AM UTC 24 |
Oct 15 11:23:11 AM UTC 24 |
97091656396 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/211.uart_fifo_reset.3343396357 |
|
|
Oct 15 11:22:05 AM UTC 24 |
Oct 15 11:23:13 AM UTC 24 |
71521452791 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/235.uart_fifo_reset.983098435 |
|
|
Oct 15 11:22:47 AM UTC 24 |
Oct 15 11:23:14 AM UTC 24 |
14667947911 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/232.uart_fifo_reset.21556542 |
|
|
Oct 15 11:22:39 AM UTC 24 |
Oct 15 11:23:14 AM UTC 24 |
15167079167 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/59.uart_fifo_reset.4120781510 |
|
|
Oct 15 11:16:30 AM UTC 24 |
Oct 15 11:23:19 AM UTC 24 |
220571178297 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/215.uart_fifo_reset.2758611605 |
|
|
Oct 15 11:22:08 AM UTC 24 |
Oct 15 11:23:20 AM UTC 24 |
135617030152 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/171.uart_fifo_reset.4243099502 |
|
|
Oct 15 11:20:47 AM UTC 24 |
Oct 15 11:23:21 AM UTC 24 |
64496390742 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/236.uart_fifo_reset.2871590462 |
|
|
Oct 15 11:22:51 AM UTC 24 |
Oct 15 11:23:27 AM UTC 24 |
49960736086 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/172.uart_fifo_reset.2623327821 |
|
|
Oct 15 11:20:49 AM UTC 24 |
Oct 15 11:23:33 AM UTC 24 |
99597182614 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/233.uart_fifo_reset.3802121252 |
|
|
Oct 15 11:22:40 AM UTC 24 |
Oct 15 11:23:35 AM UTC 24 |
72467218917 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/223.uart_fifo_reset.2033098988 |
|
|
Oct 15 11:22:23 AM UTC 24 |
Oct 15 11:23:36 AM UTC 24 |
82606385085 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/251.uart_fifo_reset.2414796088 |
|
|
Oct 15 11:23:23 AM UTC 24 |
Oct 15 11:23:36 AM UTC 24 |
23080616487 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/244.uart_fifo_reset.2533116868 |
|
|
Oct 15 11:23:07 AM UTC 24 |
Oct 15 11:23:36 AM UTC 24 |
63412492649 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/228.uart_fifo_reset.1147941108 |
|
|
Oct 15 11:22:31 AM UTC 24 |
Oct 15 11:23:38 AM UTC 24 |
33504008953 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/181.uart_fifo_reset.1399941897 |
|
|
Oct 15 11:21:05 AM UTC 24 |
Oct 15 11:23:39 AM UTC 24 |
209916486193 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/174.uart_fifo_reset.764588564 |
|
|
Oct 15 11:20:52 AM UTC 24 |
Oct 15 11:23:40 AM UTC 24 |
188797502663 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/77.uart_fifo_reset.3367833793 |
|
|
Oct 15 11:17:51 AM UTC 24 |
Oct 15 11:23:41 AM UTC 24 |
213174156149 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/227.uart_fifo_reset.2694337312 |
|
|
Oct 15 11:22:25 AM UTC 24 |
Oct 15 11:23:42 AM UTC 24 |
124739401290 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/248.uart_fifo_reset.2252376506 |
|
|
Oct 15 11:23:15 AM UTC 24 |
Oct 15 11:23:46 AM UTC 24 |
105200901652 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3744511235 |
|
|
Oct 15 11:22:34 AM UTC 24 |
Oct 15 11:23:48 AM UTC 24 |
150476144361 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/249.uart_fifo_reset.447457046 |
|
|
Oct 15 11:23:19 AM UTC 24 |
Oct 15 11:23:49 AM UTC 24 |
33180982653 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/187.uart_fifo_reset.2439217617 |
|
|
Oct 15 11:21:21 AM UTC 24 |
Oct 15 11:23:50 AM UTC 24 |
78949354606 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3107061188 |
|
|
Oct 15 11:23:12 AM UTC 24 |
Oct 15 11:23:50 AM UTC 24 |
102415993561 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/257.uart_fifo_reset.3236673412 |
|
|
Oct 15 11:23:37 AM UTC 24 |
Oct 15 11:23:50 AM UTC 24 |
12874211398 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/246.uart_fifo_reset.2692226339 |
|
|
Oct 15 11:23:14 AM UTC 24 |
Oct 15 11:23:51 AM UTC 24 |
55878435343 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/252.uart_fifo_reset.2737918080 |
|
|
Oct 15 11:23:28 AM UTC 24 |
Oct 15 11:23:53 AM UTC 24 |
15931718627 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/242.uart_fifo_reset.1997045213 |
|
|
Oct 15 11:23:03 AM UTC 24 |
Oct 15 11:23:54 AM UTC 24 |
420126763409 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/234.uart_fifo_reset.31772048 |
|
|
Oct 15 11:22:45 AM UTC 24 |
Oct 15 11:23:58 AM UTC 24 |
102068689208 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/247.uart_fifo_reset.1377549621 |
|
|
Oct 15 11:23:14 AM UTC 24 |
Oct 15 11:23:59 AM UTC 24 |
23104313571 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/243.uart_fifo_reset.3365047269 |
|
|
Oct 15 11:23:04 AM UTC 24 |
Oct 15 11:24:01 AM UTC 24 |
98274931155 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/179.uart_fifo_reset.3687142193 |
|
|
Oct 15 11:21:04 AM UTC 24 |
Oct 15 11:24:02 AM UTC 24 |
212194739355 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/180.uart_fifo_reset.4005561712 |
|
|
Oct 15 11:21:04 AM UTC 24 |
Oct 15 11:24:03 AM UTC 24 |
72706493066 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/267.uart_fifo_reset.933255858 |
|
|
Oct 15 11:23:51 AM UTC 24 |
Oct 15 11:24:04 AM UTC 24 |
16215856288 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/240.uart_fifo_reset.2221480193 |
|
|
Oct 15 11:22:55 AM UTC 24 |
Oct 15 11:24:06 AM UTC 24 |
20736802486 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/259.uart_fifo_reset.4242642271 |
|
|
Oct 15 11:23:39 AM UTC 24 |
Oct 15 11:24:06 AM UTC 24 |
15934567657 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/170.uart_fifo_reset.2731258513 |
|
|
Oct 15 11:20:47 AM UTC 24 |
Oct 15 11:24:09 AM UTC 24 |
215457200771 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/258.uart_fifo_reset.2911882208 |
|
|
Oct 15 11:23:38 AM UTC 24 |
Oct 15 11:24:13 AM UTC 24 |
14718068453 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/219.uart_fifo_reset.1554503850 |
|
|
Oct 15 11:22:18 AM UTC 24 |
Oct 15 11:24:14 AM UTC 24 |
122465764498 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/46.uart_stress_all.1668415591 |
|
|
Oct 15 11:13:48 AM UTC 24 |
Oct 15 11:24:15 AM UTC 24 |
240887368037 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/188.uart_fifo_reset.1499418751 |
|
|
Oct 15 11:21:24 AM UTC 24 |
Oct 15 11:24:15 AM UTC 24 |
63411291695 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/142.uart_fifo_reset.339474973 |
|
|
Oct 15 11:19:54 AM UTC 24 |
Oct 15 11:24:19 AM UTC 24 |
132811422241 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/212.uart_fifo_reset.1539634296 |
|
|
Oct 15 11:22:07 AM UTC 24 |
Oct 15 11:24:19 AM UTC 24 |
98963516200 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/224.uart_fifo_reset.2973741276 |
|
|
Oct 15 11:22:25 AM UTC 24 |
Oct 15 11:24:22 AM UTC 24 |
123249040061 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/158.uart_fifo_reset.3877306131 |
|
|
Oct 15 11:20:29 AM UTC 24 |
Oct 15 11:24:22 AM UTC 24 |
100590316610 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_stress_all.22223794 |
|
|
Oct 15 11:15:18 AM UTC 24 |
Oct 15 11:24:22 AM UTC 24 |
438028852681 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/265.uart_fifo_reset.3747931892 |
|
|
Oct 15 11:23:51 AM UTC 24 |
Oct 15 11:24:23 AM UTC 24 |
49770653798 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/225.uart_fifo_reset.1996521414 |
|
|
Oct 15 11:22:25 AM UTC 24 |
Oct 15 11:24:24 AM UTC 24 |
56682124073 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/216.uart_fifo_reset.2359368129 |
|
|
Oct 15 11:22:09 AM UTC 24 |
Oct 15 11:24:26 AM UTC 24 |
60600022087 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/273.uart_fifo_reset.2400457297 |
|
|
Oct 15 11:24:00 AM UTC 24 |
Oct 15 11:24:28 AM UTC 24 |
14187003527 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/262.uart_fifo_reset.4012736640 |
|
|
Oct 15 11:23:43 AM UTC 24 |
Oct 15 11:24:28 AM UTC 24 |
30516457469 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/253.uart_fifo_reset.2960147908 |
|
|
Oct 15 11:23:34 AM UTC 24 |
Oct 15 11:24:33 AM UTC 24 |
63903693407 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/196.uart_fifo_reset.3826955204 |
|
|
Oct 15 11:21:41 AM UTC 24 |
Oct 15 11:24:34 AM UTC 24 |
89429762799 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/280.uart_fifo_reset.913313169 |
|
|
Oct 15 11:24:10 AM UTC 24 |
Oct 15 11:24:35 AM UTC 24 |
28547704762 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/250.uart_fifo_reset.4127677769 |
|
|
Oct 15 11:23:21 AM UTC 24 |
Oct 15 11:24:35 AM UTC 24 |
25195717263 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/255.uart_fifo_reset.1503247382 |
|
|
Oct 15 11:23:37 AM UTC 24 |
Oct 15 11:24:36 AM UTC 24 |
25731453991 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/277.uart_fifo_reset.3845237846 |
|
|
Oct 15 11:24:05 AM UTC 24 |
Oct 15 11:24:37 AM UTC 24 |
42053481140 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/284.uart_fifo_reset.2942294066 |
|
|
Oct 15 11:24:16 AM UTC 24 |
Oct 15 11:24:38 AM UTC 24 |
17472438619 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/208.uart_fifo_reset.1552559449 |
|
|
Oct 15 11:21:59 AM UTC 24 |
Oct 15 11:24:39 AM UTC 24 |
215778471063 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/278.uart_fifo_reset.3138544550 |
|
|
Oct 15 11:24:07 AM UTC 24 |
Oct 15 11:24:41 AM UTC 24 |
51343195588 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/238.uart_fifo_reset.728348325 |
|
|
Oct 15 11:22:53 AM UTC 24 |
Oct 15 11:24:42 AM UTC 24 |
90833298120 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/201.uart_fifo_reset.2116352972 |
|
|
Oct 15 11:21:44 AM UTC 24 |
Oct 15 11:24:44 AM UTC 24 |
81941649348 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2121096554 |
|
|
Oct 15 11:24:07 AM UTC 24 |
Oct 15 11:24:44 AM UTC 24 |
45755903282 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/221.uart_fifo_reset.3468992393 |
|
|
Oct 15 11:22:19 AM UTC 24 |
Oct 15 11:24:46 AM UTC 24 |
68066726286 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/297.uart_fifo_reset.3395294740 |
|
|
Oct 15 11:24:35 AM UTC 24 |
Oct 15 11:24:52 AM UTC 24 |
63302689366 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/256.uart_fifo_reset.1658024683 |
|
|
Oct 15 11:23:37 AM UTC 24 |
Oct 15 11:24:55 AM UTC 24 |
50076544659 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/294.uart_fifo_reset.747769974 |
|
|
Oct 15 11:24:29 AM UTC 24 |
Oct 15 11:24:57 AM UTC 24 |
91607702519 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/254.uart_fifo_reset.1331875095 |
|
|
Oct 15 11:23:36 AM UTC 24 |
Oct 15 11:25:01 AM UTC 24 |
46114536220 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/264.uart_fifo_reset.3499821666 |
|
|
Oct 15 11:23:49 AM UTC 24 |
Oct 15 11:25:03 AM UTC 24 |
55447299962 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/239.uart_fifo_reset.3615724806 |
|
|
Oct 15 11:22:53 AM UTC 24 |
Oct 15 11:25:05 AM UTC 24 |
265587937399 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/275.uart_fifo_reset.15217564 |
|
|
Oct 15 11:24:02 AM UTC 24 |
Oct 15 11:25:07 AM UTC 24 |
157715477672 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/290.uart_fifo_reset.1735830244 |
|
|
Oct 15 11:24:25 AM UTC 24 |
Oct 15 11:25:10 AM UTC 24 |
96450558396 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/222.uart_fifo_reset.3298019224 |
|
|
Oct 15 11:22:23 AM UTC 24 |
Oct 15 11:25:12 AM UTC 24 |
219152417170 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/241.uart_fifo_reset.940687850 |
|
|
Oct 15 11:22:56 AM UTC 24 |
Oct 15 11:25:13 AM UTC 24 |
296987159944 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/276.uart_fifo_reset.2882493954 |
|
|
Oct 15 11:24:03 AM UTC 24 |
Oct 15 11:25:16 AM UTC 24 |
114694610554 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/292.uart_fifo_reset.3308678884 |
|
|
Oct 15 11:24:28 AM UTC 24 |
Oct 15 11:25:16 AM UTC 24 |
109301274962 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/291.uart_fifo_reset.3110120071 |
|
|
Oct 15 11:24:26 AM UTC 24 |
Oct 15 11:25:26 AM UTC 24 |
35695232457 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/48.uart_fifo_full.1199574623 |
|
|
Oct 15 11:14:53 AM UTC 24 |
Oct 15 11:25:26 AM UTC 24 |
175766206605 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/272.uart_fifo_reset.2427454195 |
|
|
Oct 15 11:23:59 AM UTC 24 |
Oct 15 11:25:28 AM UTC 24 |
68989181805 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.1500209675 |
|
|
Oct 15 11:05:04 AM UTC 24 |
Oct 15 11:25:29 AM UTC 24 |
115976729666 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/288.uart_fifo_reset.1588937238 |
|
|
Oct 15 11:24:22 AM UTC 24 |
Oct 15 11:25:30 AM UTC 24 |
191405247485 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/287.uart_fifo_reset.1641140145 |
|
|
Oct 15 11:24:22 AM UTC 24 |
Oct 15 11:25:31 AM UTC 24 |
156974319952 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/289.uart_fifo_reset.1818543809 |
|
|
Oct 15 11:24:23 AM UTC 24 |
Oct 15 11:25:35 AM UTC 24 |
36486742807 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/266.uart_fifo_reset.3725605999 |
|
|
Oct 15 11:23:51 AM UTC 24 |
Oct 15 11:25:39 AM UTC 24 |
45734498476 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/271.uart_fifo_reset.649229537 |
|
|
Oct 15 11:23:55 AM UTC 24 |
Oct 15 11:25:40 AM UTC 24 |
44587163182 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/293.uart_fifo_reset.2364787055 |
|
|
Oct 15 11:24:29 AM UTC 24 |
Oct 15 11:25:41 AM UTC 24 |
55841794814 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/299.uart_fifo_reset.1385126896 |
|
|
Oct 15 11:24:36 AM UTC 24 |
Oct 15 11:25:45 AM UTC 24 |
35213817963 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/118.uart_fifo_reset.3479675829 |
|
|
Oct 15 11:19:26 AM UTC 24 |
Oct 15 11:25:49 AM UTC 24 |
160263786549 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/268.uart_fifo_reset.2699746749 |
|
|
Oct 15 11:23:51 AM UTC 24 |
Oct 15 11:25:50 AM UTC 24 |
46032335669 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/124.uart_fifo_reset.793614009 |
|
|
Oct 15 11:19:33 AM UTC 24 |
Oct 15 11:25:51 AM UTC 24 |
239970374739 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/261.uart_fifo_reset.2863840855 |
|
|
Oct 15 11:23:42 AM UTC 24 |
Oct 15 11:25:53 AM UTC 24 |
66543297021 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.1481671017 |
|
|
Oct 15 11:06:01 AM UTC 24 |
Oct 15 11:25:54 AM UTC 24 |
148524818544 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.2398360820 |
|
|
Oct 15 11:12:15 AM UTC 24 |
Oct 15 11:25:58 AM UTC 24 |
109493460448 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/283.uart_fifo_reset.3632531456 |
|
|
Oct 15 11:24:15 AM UTC 24 |
Oct 15 11:26:05 AM UTC 24 |
95304586855 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/199.uart_fifo_reset.253760653 |
|
|
Oct 15 11:21:44 AM UTC 24 |
Oct 15 11:26:16 AM UTC 24 |
114685340430 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/281.uart_fifo_reset.3668861661 |
|
|
Oct 15 11:24:14 AM UTC 24 |
Oct 15 11:26:18 AM UTC 24 |
252475190140 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/37.uart_fifo_full.64419060 |
|
|
Oct 15 11:08:52 AM UTC 24 |
Oct 15 11:26:26 AM UTC 24 |
294183622985 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/237.uart_fifo_reset.3111225667 |
|
|
Oct 15 11:22:52 AM UTC 24 |
Oct 15 11:26:28 AM UTC 24 |
120649453164 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/285.uart_fifo_reset.1721319774 |
|
|
Oct 15 11:24:19 AM UTC 24 |
Oct 15 11:26:29 AM UTC 24 |
103806144148 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/260.uart_fifo_reset.1389384276 |
|
|
Oct 15 11:23:41 AM UTC 24 |
Oct 15 11:26:35 AM UTC 24 |
73000600411 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.193671456 |
|
|
Oct 15 11:11:46 AM UTC 24 |
Oct 15 11:26:39 AM UTC 24 |
170194502733 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/269.uart_fifo_reset.1614612902 |
|
|
Oct 15 11:23:52 AM UTC 24 |
Oct 15 11:26:44 AM UTC 24 |
269627817227 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/38.uart_perf.2830730048 |
|
|
Oct 15 11:09:28 AM UTC 24 |
Oct 15 11:26:52 AM UTC 24 |
19551372210 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/231.uart_fifo_reset.87046779 |
|
|
Oct 15 11:22:35 AM UTC 24 |
Oct 15 11:27:05 AM UTC 24 |
112656320801 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/168.uart_fifo_reset.1415064681 |
|
|
Oct 15 11:20:42 AM UTC 24 |
Oct 15 11:27:07 AM UTC 24 |
178866120325 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/274.uart_fifo_reset.2963125679 |
|
|
Oct 15 11:24:02 AM UTC 24 |
Oct 15 11:27:16 AM UTC 24 |
163864374429 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/218.uart_fifo_reset.3904120837 |
|
|
Oct 15 11:22:16 AM UTC 24 |
Oct 15 11:27:18 AM UTC 24 |
158953315872 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_stress_all.437583920 |
|
|
Oct 15 11:12:54 AM UTC 24 |
Oct 15 11:27:36 AM UTC 24 |
357981184821 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/189.uart_fifo_reset.1325571210 |
|
|
Oct 15 11:21:29 AM UTC 24 |
Oct 15 11:27:36 AM UTC 24 |
177753960158 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/298.uart_fifo_reset.3806641501 |
|
|
Oct 15 11:24:36 AM UTC 24 |
Oct 15 11:27:43 AM UTC 24 |
87403519393 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2824325849 |
|
|
Oct 15 11:24:15 AM UTC 24 |
Oct 15 11:27:55 AM UTC 24 |
120993647114 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/296.uart_fifo_reset.248750006 |
|
|
Oct 15 11:24:35 AM UTC 24 |
Oct 15 11:27:56 AM UTC 24 |
113619410691 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/270.uart_fifo_reset.589840435 |
|
|
Oct 15 11:23:53 AM UTC 24 |
Oct 15 11:28:15 AM UTC 24 |
123560345540 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/286.uart_fifo_reset.3471118056 |
|
|
Oct 15 11:24:20 AM UTC 24 |
Oct 15 11:28:38 AM UTC 24 |
132731981521 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/47.uart_stress_all.1660792657 |
|
|
Oct 15 11:14:43 AM UTC 24 |
Oct 15 11:28:48 AM UTC 24 |
91054712549 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/263.uart_fifo_reset.165827599 |
|
|
Oct 15 11:23:46 AM UTC 24 |
Oct 15 11:29:42 AM UTC 24 |
182236455542 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/295.uart_fifo_reset.786784143 |
|
|
Oct 15 11:24:34 AM UTC 24 |
Oct 15 11:29:42 AM UTC 24 |
190495654655 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/49.uart_stress_all.3778191599 |
|
|
Oct 15 11:15:39 AM UTC 24 |
Oct 15 11:31:10 AM UTC 24 |
313020085767 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/41.uart_stress_all.1502329809 |
|
|
Oct 15 11:11:13 AM UTC 24 |
Oct 15 11:37:40 AM UTC 24 |
87894488744 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/default/44.uart_perf.3162890224 |
|
|
Oct 15 11:12:53 AM UTC 24 |
Oct 15 11:44:28 AM UTC 24 |
37619119887 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.2176563352 |
|
|
Oct 15 11:29:09 AM UTC 24 |
Oct 15 11:29:12 AM UTC 24 |
12058343 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.2099932248 |
|
|
Oct 15 11:29:09 AM UTC 24 |
Oct 15 11:29:12 AM UTC 24 |
39498783 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.2976117294 |
|
|
Oct 15 11:29:10 AM UTC 24 |
Oct 15 11:29:12 AM UTC 24 |
16262671 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2096886822 |
|
|
Oct 15 11:29:09 AM UTC 24 |
Oct 15 11:29:12 AM UTC 24 |
243406736 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.3526870765 |
|
|
Oct 15 11:29:09 AM UTC 24 |
Oct 15 11:29:12 AM UTC 24 |
84407244 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.4284944526 |
|
|
Oct 15 11:29:09 AM UTC 24 |
Oct 15 11:29:13 AM UTC 24 |
1034958207 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.1832218601 |
|
|
Oct 15 11:29:09 AM UTC 24 |
Oct 15 11:29:13 AM UTC 24 |
74407126 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3835873178 |
|
|
Oct 15 11:29:12 AM UTC 24 |
Oct 15 11:29:14 AM UTC 24 |
59711703 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3875536031 |
|
|
Oct 15 11:29:12 AM UTC 24 |
Oct 15 11:29:14 AM UTC 24 |
22169962 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.1863742472 |
|
|
Oct 15 11:29:12 AM UTC 24 |
Oct 15 11:29:15 AM UTC 24 |
710057978 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.942958752 |
|
|
Oct 15 11:29:12 AM UTC 24 |
Oct 15 11:29:15 AM UTC 24 |
70001914 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.2204354055 |
|
|
Oct 15 11:29:15 AM UTC 24 |
Oct 15 11:29:17 AM UTC 24 |
47752939 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2767683477 |
|
|
Oct 15 11:29:15 AM UTC 24 |
Oct 15 11:29:17 AM UTC 24 |
44328104 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.702660410 |
|
|
Oct 15 11:29:15 AM UTC 24 |
Oct 15 11:29:17 AM UTC 24 |
13154015 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.510032938 |
|
|
Oct 15 11:29:15 AM UTC 24 |
Oct 15 11:29:17 AM UTC 24 |
65650638 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.3284475668 |
|
|
Oct 15 11:29:15 AM UTC 24 |
Oct 15 11:29:17 AM UTC 24 |
167520232 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2162434721 |
|
|
Oct 15 11:29:15 AM UTC 24 |
Oct 15 11:29:17 AM UTC 24 |
63865435 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.1702245442 |
|
|
Oct 15 11:29:37 AM UTC 24 |
Oct 15 11:29:42 AM UTC 24 |
49910074 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3222011924 |
|
|
Oct 15 11:29:16 AM UTC 24 |
Oct 15 11:29:21 AM UTC 24 |
57869252 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.1126236374 |
|
|
Oct 15 11:29:16 AM UTC 24 |
Oct 15 11:29:21 AM UTC 24 |
69313485 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.4080201892 |
|
|
Oct 15 11:29:16 AM UTC 24 |
Oct 15 11:29:21 AM UTC 24 |
45744908 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.3941243570 |
|
|
Oct 15 11:29:16 AM UTC 24 |
Oct 15 11:29:21 AM UTC 24 |
233905026 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.850201092 |
|
|
Oct 15 11:29:16 AM UTC 24 |
Oct 15 11:29:21 AM UTC 24 |
163862870 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.3533847994 |
|
|
Oct 15 11:29:16 AM UTC 24 |
Oct 15 11:29:21 AM UTC 24 |
334896568 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.3525744332 |
|
|
Oct 15 11:29:16 AM UTC 24 |
Oct 15 11:29:21 AM UTC 24 |
39042116 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.507363166 |
|
|
Oct 15 11:29:13 AM UTC 24 |
Oct 15 11:29:22 AM UTC 24 |
75578953 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.503148928 |
|
|
Oct 15 11:29:17 AM UTC 24 |
Oct 15 11:29:22 AM UTC 24 |
247714307 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.3696157238 |
|
|
Oct 15 11:29:17 AM UTC 24 |
Oct 15 11:29:22 AM UTC 24 |
129150346 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.329643385 |
|
|
Oct 15 11:29:17 AM UTC 24 |
Oct 15 11:29:23 AM UTC 24 |
35553686 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.22113840 |
|
|
Oct 15 11:29:22 AM UTC 24 |
Oct 15 11:29:26 AM UTC 24 |
38869359 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.1938635446 |
|
|
Oct 15 11:29:22 AM UTC 24 |
Oct 15 11:29:26 AM UTC 24 |
116113554 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.3599174566 |
|
|
Oct 15 11:29:22 AM UTC 24 |
Oct 15 11:29:26 AM UTC 24 |
15841770 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.1982331861 |
|
|
Oct 15 11:29:22 AM UTC 24 |
Oct 15 11:29:27 AM UTC 24 |
55381135 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1786659547 |
|
|
Oct 15 11:29:22 AM UTC 24 |
Oct 15 11:29:27 AM UTC 24 |
77784028 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.3227666421 |
|
|
Oct 15 11:29:22 AM UTC 24 |
Oct 15 11:29:27 AM UTC 24 |
467596482 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2193730238 |
|
|
Oct 15 11:29:19 AM UTC 24 |
Oct 15 11:29:27 AM UTC 24 |
24492652 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2988811572 |
|
|
Oct 15 11:29:15 AM UTC 24 |
Oct 15 11:29:27 AM UTC 24 |
17632824 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.1103341510 |
|
|
Oct 15 11:29:15 AM UTC 24 |
Oct 15 11:29:27 AM UTC 24 |
13709739 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.1682444036 |
|
|
Oct 15 11:29:15 AM UTC 24 |
Oct 15 11:29:27 AM UTC 24 |
57495119 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2968571670 |
|
|
Oct 15 11:29:15 AM UTC 24 |
Oct 15 11:29:28 AM UTC 24 |
54383838 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.3527367641 |
|
|
Oct 15 11:29:23 AM UTC 24 |
Oct 15 11:29:28 AM UTC 24 |
17213967 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.2871198839 |
|
|
Oct 15 11:29:23 AM UTC 24 |
Oct 15 11:29:28 AM UTC 24 |
51432052 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.3481506935 |
|
|
Oct 15 11:29:19 AM UTC 24 |
Oct 15 11:29:28 AM UTC 24 |
237155297 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2178556058 |
|
|
Oct 15 11:29:23 AM UTC 24 |
Oct 15 11:29:28 AM UTC 24 |
50283795 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.1527213407 |
|
|
Oct 15 11:29:15 AM UTC 24 |
Oct 15 11:29:28 AM UTC 24 |
1262686991 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.1212236138 |
|
|
Oct 15 11:29:19 AM UTC 24 |
Oct 15 11:29:28 AM UTC 24 |
29607994 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.4201497636 |
|
|
Oct 15 11:29:22 AM UTC 24 |
Oct 15 11:29:28 AM UTC 24 |
610705154 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.2073870089 |
|
|
Oct 15 11:29:29 AM UTC 24 |
Oct 15 11:29:31 AM UTC 24 |
14646511 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.2704777965 |
|
|
Oct 15 11:29:29 AM UTC 24 |
Oct 15 11:29:31 AM UTC 24 |
44371257 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.2724008770 |
|
|
Oct 15 11:29:29 AM UTC 24 |
Oct 15 11:29:31 AM UTC 24 |
54252793 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.2002457297 |
|
|
Oct 15 11:29:29 AM UTC 24 |
Oct 15 11:29:31 AM UTC 24 |
17716359 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.944953173 |
|
|
Oct 15 11:29:29 AM UTC 24 |
Oct 15 11:29:32 AM UTC 24 |
42821336 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3921652633 |
|
|
Oct 15 11:29:29 AM UTC 24 |
Oct 15 11:29:32 AM UTC 24 |
28772609 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.536751903 |
|
|
Oct 15 11:29:23 AM UTC 24 |
Oct 15 11:29:32 AM UTC 24 |
233506496 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.3372779350 |
|
|
Oct 15 11:29:29 AM UTC 24 |
Oct 15 11:29:32 AM UTC 24 |
33071600 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1685781497 |
|
|
Oct 15 11:29:29 AM UTC 24 |
Oct 15 11:29:32 AM UTC 24 |
53149842 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.1613455818 |
|
|
Oct 15 11:29:30 AM UTC 24 |
Oct 15 11:29:32 AM UTC 24 |
156017508 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.34016334 |
|
|
Oct 15 11:29:27 AM UTC 24 |
Oct 15 11:29:32 AM UTC 24 |
14183669 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.1600699524 |
|
|
Oct 15 11:29:13 AM UTC 24 |
Oct 15 11:29:32 AM UTC 24 |
56065193 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.4059573968 |
|
|
Oct 15 11:29:27 AM UTC 24 |
Oct 15 11:29:32 AM UTC 24 |
29463576 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.2469388768 |
|
|
Oct 15 11:29:27 AM UTC 24 |
Oct 15 11:29:32 AM UTC 24 |
42343257 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.3885957119 |
|
|
Oct 15 11:29:13 AM UTC 24 |
Oct 15 11:29:32 AM UTC 24 |
13881014 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.2858622821 |
|
|
Oct 15 11:29:29 AM UTC 24 |
Oct 15 11:29:32 AM UTC 24 |
428825800 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2770740965 |
|
|
Oct 15 11:29:17 AM UTC 24 |
Oct 15 11:29:32 AM UTC 24 |
19076828 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.1497272958 |
|
|
Oct 15 11:29:27 AM UTC 24 |
Oct 15 11:29:33 AM UTC 24 |
160184523 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.4261731240 |
|
|
Oct 15 11:29:29 AM UTC 24 |
Oct 15 11:29:33 AM UTC 24 |
192613694 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3794467935 |
|
|
Oct 15 11:29:29 AM UTC 24 |
Oct 15 11:29:33 AM UTC 24 |
75699614 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.2518459542 |
|
|
Oct 15 11:29:13 AM UTC 24 |
Oct 15 11:29:33 AM UTC 24 |
92998073 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.2973299121 |
|
|
Oct 15 11:29:34 AM UTC 24 |
Oct 15 11:29:36 AM UTC 24 |
16693431 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.2391175086 |
|
|
Oct 15 11:29:34 AM UTC 24 |
Oct 15 11:29:36 AM UTC 24 |
18921396 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.3121168446 |
|
|
Oct 15 11:29:34 AM UTC 24 |
Oct 15 11:29:37 AM UTC 24 |
23448366 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2530411868 |
|
|
Oct 15 11:29:34 AM UTC 24 |
Oct 15 11:29:37 AM UTC 24 |
50155191 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2375558635 |
|
|
Oct 15 11:29:34 AM UTC 24 |
Oct 15 11:29:37 AM UTC 24 |
70027202 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.2368207956 |
|
|
Oct 15 11:29:34 AM UTC 24 |
Oct 15 11:29:37 AM UTC 24 |
13838896 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.2546371760 |
|
|
Oct 15 11:29:34 AM UTC 24 |
Oct 15 11:29:37 AM UTC 24 |
48519287 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3442325043 |
|
|
Oct 15 11:29:34 AM UTC 24 |
Oct 15 11:29:37 AM UTC 24 |
103227755 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1745614381 |
|
|
Oct 15 11:29:34 AM UTC 24 |
Oct 15 11:29:37 AM UTC 24 |
22906958 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.1547016602 |
|
|
Oct 15 11:29:34 AM UTC 24 |
Oct 15 11:29:37 AM UTC 24 |
173228957 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.987735281 |
|
|
Oct 15 11:29:34 AM UTC 24 |
Oct 15 11:29:38 AM UTC 24 |
117934044 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.2064878394 |
|
|
Oct 15 11:29:37 AM UTC 24 |
Oct 15 11:29:42 AM UTC 24 |
11189651 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.91329251 |
|
|
Oct 15 11:29:37 AM UTC 24 |
Oct 15 11:29:42 AM UTC 24 |
45599065 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.1150708967 |
|
|
Oct 15 11:29:37 AM UTC 24 |
Oct 15 11:29:42 AM UTC 24 |
175183131 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2349068451 |
|
|
Oct 15 11:29:37 AM UTC 24 |
Oct 15 11:29:42 AM UTC 24 |
80728645 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2692558248 |
|
|
Oct 15 11:29:27 AM UTC 24 |
Oct 15 11:29:42 AM UTC 24 |
46311384 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4224577955 |
|
|
Oct 15 11:29:37 AM UTC 24 |
Oct 15 11:29:42 AM UTC 24 |
20303134 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3830724876 |
|
|
Oct 15 11:29:37 AM UTC 24 |
Oct 15 11:29:42 AM UTC 24 |
123055972 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.3779362087 |
|
|
Oct 15 11:29:39 AM UTC 24 |
Oct 15 11:29:43 AM UTC 24 |
35268349 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.3137847085 |
|
|
Oct 15 11:29:39 AM UTC 24 |
Oct 15 11:29:43 AM UTC 24 |
24767594 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.3119743670 |
|
|
Oct 15 11:29:39 AM UTC 24 |
Oct 15 11:29:43 AM UTC 24 |
40467343 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.1573526901 |
|
|
Oct 15 11:29:32 AM UTC 24 |
Oct 15 11:29:44 AM UTC 24 |
36513737 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.175738722 |
|
|
Oct 15 11:29:39 AM UTC 24 |
Oct 15 11:29:44 AM UTC 24 |
143251073 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1761200291 |
|
|
Oct 15 11:29:32 AM UTC 24 |
Oct 15 11:29:44 AM UTC 24 |
12558002 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.969037324 |
|
|
Oct 15 11:29:32 AM UTC 24 |
Oct 15 11:29:44 AM UTC 24 |
15912970 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.3048776945 |
|
|
Oct 15 11:29:33 AM UTC 24 |
Oct 15 11:29:44 AM UTC 24 |
11652047 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.2617232656 |
|
|
Oct 15 11:29:32 AM UTC 24 |
Oct 15 11:29:44 AM UTC 24 |
17225730 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1759105052 |
|
|
Oct 15 11:29:32 AM UTC 24 |
Oct 15 11:29:44 AM UTC 24 |
111149495 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.3010068732 |
|
|
Oct 15 11:29:32 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2000501410 |
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Oct 15 11:29:33 AM UTC 24 |
Oct 15 11:29:45 AM UTC 24 |
66013991 ps |