| T1055 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/189.uart_fifo_reset.3085315217 |
|
|
Feb 09 07:31:26 AM UTC 25 |
Feb 09 07:32:27 AM UTC 25 |
65418086966 ps |
| T1056 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/185.uart_fifo_reset.4155782291 |
|
|
Feb 09 07:31:20 AM UTC 25 |
Feb 09 07:32:29 AM UTC 25 |
41759187644 ps |
| T1057 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/169.uart_fifo_reset.3860730226 |
|
|
Feb 09 07:30:37 AM UTC 25 |
Feb 09 07:32:30 AM UTC 25 |
66500575871 ps |
| T72 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.2704123627 |
|
|
Feb 09 07:19:35 AM UTC 25 |
Feb 09 07:32:32 AM UTC 25 |
76012666005 ps |
| T1058 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/201.uart_fifo_reset.4251983455 |
|
|
Feb 09 07:32:04 AM UTC 25 |
Feb 09 07:32:32 AM UTC 25 |
14338341042 ps |
| T1059 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/205.uart_fifo_reset.200064153 |
|
|
Feb 09 07:32:07 AM UTC 25 |
Feb 09 07:32:33 AM UTC 25 |
8913687899 ps |
| T1060 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/203.uart_fifo_reset.3972996599 |
|
|
Feb 09 07:32:05 AM UTC 25 |
Feb 09 07:32:36 AM UTC 25 |
43993231769 ps |
| T1061 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/184.uart_fifo_reset.3804742251 |
|
|
Feb 09 07:31:20 AM UTC 25 |
Feb 09 07:32:46 AM UTC 25 |
153243071927 ps |
| T1062 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/197.uart_fifo_reset.639771268 |
|
|
Feb 09 07:31:51 AM UTC 25 |
Feb 09 07:32:48 AM UTC 25 |
38402101255 ps |
| T1063 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/158.uart_fifo_reset.3540766480 |
|
|
Feb 09 07:29:58 AM UTC 25 |
Feb 09 07:32:48 AM UTC 25 |
125828324598 ps |
| T261 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/186.uart_fifo_reset.955116584 |
|
|
Feb 09 07:31:22 AM UTC 25 |
Feb 09 07:32:53 AM UTC 25 |
132552997120 ps |
| T197 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/144.uart_fifo_reset.3012550564 |
|
|
Feb 09 07:29:29 AM UTC 25 |
Feb 09 07:32:57 AM UTC 25 |
93872501292 ps |
| T1064 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/179.uart_fifo_reset.74105750 |
|
|
Feb 09 07:31:10 AM UTC 25 |
Feb 09 07:33:02 AM UTC 25 |
92163298323 ps |
| T264 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/214.uart_fifo_reset.1830342725 |
|
|
Feb 09 07:32:30 AM UTC 25 |
Feb 09 07:33:06 AM UTC 25 |
18121233235 ps |
| T1065 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/198.uart_fifo_reset.271297751 |
|
|
Feb 09 07:31:58 AM UTC 25 |
Feb 09 07:33:09 AM UTC 25 |
34550279652 ps |
| T1066 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/210.uart_fifo_reset.1640282071 |
|
|
Feb 09 07:32:13 AM UTC 25 |
Feb 09 07:33:11 AM UTC 25 |
123279452227 ps |
| T1067 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/215.uart_fifo_reset.1635493034 |
|
|
Feb 09 07:32:31 AM UTC 25 |
Feb 09 07:33:13 AM UTC 25 |
189796045608 ps |
| T277 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/200.uart_fifo_reset.1664042672 |
|
|
Feb 09 07:32:02 AM UTC 25 |
Feb 09 07:33:13 AM UTC 25 |
61776927250 ps |
| T1068 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/206.uart_fifo_reset.4285764653 |
|
|
Feb 09 07:32:07 AM UTC 25 |
Feb 09 07:33:13 AM UTC 25 |
35370708439 ps |
| T1069 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/153.uart_fifo_reset.1598471717 |
|
|
Feb 09 07:29:47 AM UTC 25 |
Feb 09 07:33:14 AM UTC 25 |
102714387202 ps |
| T1070 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/219.uart_fifo_reset.2490683273 |
|
|
Feb 09 07:32:36 AM UTC 25 |
Feb 09 07:33:15 AM UTC 25 |
35839620387 ps |
| T1071 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/154.uart_fifo_reset.4219548645 |
|
|
Feb 09 07:29:51 AM UTC 25 |
Feb 09 07:33:17 AM UTC 25 |
85558615985 ps |
| T1072 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/187.uart_fifo_reset.337024176 |
|
|
Feb 09 07:31:24 AM UTC 25 |
Feb 09 07:33:18 AM UTC 25 |
136620256153 ps |
| T1073 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1993734109 |
|
|
Feb 09 07:32:34 AM UTC 25 |
Feb 09 07:33:20 AM UTC 25 |
22737993769 ps |
| T1074 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/147.uart_fifo_reset.1184957552 |
|
|
Feb 09 07:29:33 AM UTC 25 |
Feb 09 07:33:24 AM UTC 25 |
124450743748 ps |
| T1075 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/223.uart_fifo_reset.3082031888 |
|
|
Feb 09 07:32:54 AM UTC 25 |
Feb 09 07:33:24 AM UTC 25 |
47276465504 ps |
| T225 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/199.uart_fifo_reset.1370346641 |
|
|
Feb 09 07:32:00 AM UTC 25 |
Feb 09 07:33:31 AM UTC 25 |
41693852475 ps |
| T1076 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/222.uart_fifo_reset.3553766783 |
|
|
Feb 09 07:32:49 AM UTC 25 |
Feb 09 07:33:32 AM UTC 25 |
84117011832 ps |
| T1077 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/177.uart_fifo_reset.293340281 |
|
|
Feb 09 07:31:02 AM UTC 25 |
Feb 09 07:33:34 AM UTC 25 |
98981994795 ps |
| T1078 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.2441443807 |
|
|
Feb 09 07:12:33 AM UTC 25 |
Feb 09 07:33:35 AM UTC 25 |
68144104290 ps |
| T1079 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/226.uart_fifo_reset.1730595143 |
|
|
Feb 09 07:33:07 AM UTC 25 |
Feb 09 07:33:36 AM UTC 25 |
41197638321 ps |
| T1080 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2951213332 |
|
|
Feb 09 07:32:08 AM UTC 25 |
Feb 09 07:33:36 AM UTC 25 |
37238005436 ps |
| T278 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/229.uart_fifo_reset.2415127226 |
|
|
Feb 09 07:33:13 AM UTC 25 |
Feb 09 07:33:37 AM UTC 25 |
24826866019 ps |
| T1081 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/235.uart_fifo_reset.3897303068 |
|
|
Feb 09 07:33:19 AM UTC 25 |
Feb 09 07:33:38 AM UTC 25 |
33069934368 ps |
| T1082 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/216.uart_fifo_reset.1618499941 |
|
|
Feb 09 07:32:32 AM UTC 25 |
Feb 09 07:33:40 AM UTC 25 |
26320878658 ps |
| T1083 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/98.uart_fifo_reset.2044922072 |
|
|
Feb 09 07:25:50 AM UTC 25 |
Feb 09 07:33:41 AM UTC 25 |
171398705575 ps |
| T1084 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/240.uart_fifo_reset.837202133 |
|
|
Feb 09 07:33:33 AM UTC 25 |
Feb 09 07:33:44 AM UTC 25 |
18534846551 ps |
| T1085 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/236.uart_fifo_reset.143858372 |
|
|
Feb 09 07:33:21 AM UTC 25 |
Feb 09 07:33:51 AM UTC 25 |
39528292498 ps |
| T1086 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/212.uart_fifo_reset.3136824680 |
|
|
Feb 09 07:32:15 AM UTC 25 |
Feb 09 07:33:51 AM UTC 25 |
143860857849 ps |
| T1087 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/224.uart_fifo_reset.323287742 |
|
|
Feb 09 07:32:58 AM UTC 25 |
Feb 09 07:33:53 AM UTC 25 |
68116878272 ps |
| T1088 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/225.uart_fifo_reset.2648638435 |
|
|
Feb 09 07:33:03 AM UTC 25 |
Feb 09 07:33:53 AM UTC 25 |
14902788631 ps |
| T1089 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/211.uart_fifo_reset.2567786276 |
|
|
Feb 09 07:32:14 AM UTC 25 |
Feb 09 07:33:58 AM UTC 25 |
59971506598 ps |
| T1090 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/220.uart_fifo_reset.1968068355 |
|
|
Feb 09 07:32:47 AM UTC 25 |
Feb 09 07:34:02 AM UTC 25 |
151120585116 ps |
| T260 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/125.uart_fifo_reset.3182735461 |
|
|
Feb 09 07:28:31 AM UTC 25 |
Feb 09 07:34:04 AM UTC 25 |
143220813238 ps |
| T267 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/231.uart_fifo_reset.1498752483 |
|
|
Feb 09 07:33:14 AM UTC 25 |
Feb 09 07:34:05 AM UTC 25 |
100363328495 ps |
| T1091 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/242.uart_fifo_reset.2468010377 |
|
|
Feb 09 07:33:35 AM UTC 25 |
Feb 09 07:34:05 AM UTC 25 |
27274995553 ps |
| T269 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/239.uart_fifo_reset.698459910 |
|
|
Feb 09 07:33:32 AM UTC 25 |
Feb 09 07:34:05 AM UTC 25 |
16733140881 ps |
| T1092 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2687334523 |
|
|
Feb 09 07:33:16 AM UTC 25 |
Feb 09 07:34:05 AM UTC 25 |
186792001652 ps |
| T1093 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/190.uart_fifo_reset.3112811889 |
|
|
Feb 09 07:31:34 AM UTC 25 |
Feb 09 07:34:09 AM UTC 25 |
49235110385 ps |
| T1094 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/227.uart_fifo_reset.1652787282 |
|
|
Feb 09 07:33:09 AM UTC 25 |
Feb 09 07:34:10 AM UTC 25 |
14548660138 ps |
| T1095 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/238.uart_fifo_reset.1905785415 |
|
|
Feb 09 07:33:25 AM UTC 25 |
Feb 09 07:34:17 AM UTC 25 |
24629267778 ps |
| T1096 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.3239164708 |
|
|
Feb 09 07:24:00 AM UTC 25 |
Feb 09 07:34:17 AM UTC 25 |
145951503913 ps |
| T1097 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/232.uart_fifo_reset.2698935690 |
|
|
Feb 09 07:33:15 AM UTC 25 |
Feb 09 07:34:18 AM UTC 25 |
23525493203 ps |
| T1098 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/165.uart_fifo_reset.2499144746 |
|
|
Feb 09 07:30:21 AM UTC 25 |
Feb 09 07:34:20 AM UTC 25 |
90711785198 ps |
| T1099 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.1275775901 |
|
|
Feb 09 07:18:58 AM UTC 25 |
Feb 09 07:34:21 AM UTC 25 |
66015314245 ps |
| T237 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/250.uart_fifo_reset.1888702378 |
|
|
Feb 09 07:33:52 AM UTC 25 |
Feb 09 07:34:23 AM UTC 25 |
19624196258 ps |
| T1100 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/245.uart_fifo_reset.1424062695 |
|
|
Feb 09 07:33:37 AM UTC 25 |
Feb 09 07:34:32 AM UTC 25 |
26546013577 ps |
| T1101 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/259.uart_fifo_reset.2817702400 |
|
|
Feb 09 07:34:06 AM UTC 25 |
Feb 09 07:34:33 AM UTC 25 |
30506040505 ps |
| T1102 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/254.uart_fifo_reset.1168590346 |
|
|
Feb 09 07:33:59 AM UTC 25 |
Feb 09 07:34:33 AM UTC 25 |
114484256082 ps |
| T1103 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/257.uart_fifo_reset.1072862521 |
|
|
Feb 09 07:34:05 AM UTC 25 |
Feb 09 07:34:33 AM UTC 25 |
60360048790 ps |
| T1104 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/265.uart_fifo_reset.4054785165 |
|
|
Feb 09 07:34:18 AM UTC 25 |
Feb 09 07:34:42 AM UTC 25 |
33126864449 ps |
| T257 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/256.uart_fifo_reset.3309000697 |
|
|
Feb 09 07:34:04 AM UTC 25 |
Feb 09 07:34:42 AM UTC 25 |
62036558132 ps |
| T1105 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/193.uart_fifo_reset.4137178950 |
|
|
Feb 09 07:31:41 AM UTC 25 |
Feb 09 07:34:42 AM UTC 25 |
150424645231 ps |
| T1106 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/269.uart_fifo_reset.752716608 |
|
|
Feb 09 07:34:24 AM UTC 25 |
Feb 09 07:34:43 AM UTC 25 |
67975095329 ps |
| T1107 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3476682810 |
|
|
Feb 09 07:33:41 AM UTC 25 |
Feb 09 07:34:46 AM UTC 25 |
18365992707 ps |
| T1108 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/266.uart_fifo_reset.3609180268 |
|
|
Feb 09 07:34:18 AM UTC 25 |
Feb 09 07:34:47 AM UTC 25 |
48121625050 ps |
| T1109 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/272.uart_fifo_reset.466422021 |
|
|
Feb 09 07:34:34 AM UTC 25 |
Feb 09 07:34:50 AM UTC 25 |
21378238302 ps |
| T1110 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/117.uart_fifo_reset.1160417491 |
|
|
Feb 09 07:27:21 AM UTC 25 |
Feb 09 07:34:50 AM UTC 25 |
215442576479 ps |
| T249 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/213.uart_fifo_reset.1600215739 |
|
|
Feb 09 07:32:28 AM UTC 25 |
Feb 09 07:34:51 AM UTC 25 |
84581410163 ps |
| T1111 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3100757579 |
|
|
Feb 09 07:33:14 AM UTC 25 |
Feb 09 07:34:51 AM UTC 25 |
194135052636 ps |
| T1112 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/204.uart_fifo_reset.3747000377 |
|
|
Feb 09 07:32:06 AM UTC 25 |
Feb 09 07:34:52 AM UTC 25 |
68194112517 ps |
| T1113 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/252.uart_fifo_reset.779718605 |
|
|
Feb 09 07:33:54 AM UTC 25 |
Feb 09 07:34:56 AM UTC 25 |
154668930839 ps |
| T1114 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/208.uart_fifo_reset.658873986 |
|
|
Feb 09 07:32:09 AM UTC 25 |
Feb 09 07:34:58 AM UTC 25 |
88606489749 ps |
| T1115 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/37.uart_perf.3034236503 |
|
|
Feb 09 07:09:44 AM UTC 25 |
Feb 09 07:34:59 AM UTC 25 |
28385718564 ps |
| T1116 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/249.uart_fifo_reset.440490418 |
|
|
Feb 09 07:33:44 AM UTC 25 |
Feb 09 07:35:04 AM UTC 25 |
153947884299 ps |
| T1117 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/278.uart_fifo_reset.2586801711 |
|
|
Feb 09 07:34:47 AM UTC 25 |
Feb 09 07:35:05 AM UTC 25 |
46922979900 ps |
| T256 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/270.uart_fifo_reset.835863678 |
|
|
Feb 09 07:34:33 AM UTC 25 |
Feb 09 07:35:05 AM UTC 25 |
203869379441 ps |
| T1118 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/244.uart_fifo_reset.3127010315 |
|
|
Feb 09 07:33:37 AM UTC 25 |
Feb 09 07:35:06 AM UTC 25 |
29619370671 ps |
| T1119 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/209.uart_fifo_reset.2777762565 |
|
|
Feb 09 07:32:12 AM UTC 25 |
Feb 09 07:35:10 AM UTC 25 |
73222974211 ps |
| T1120 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3066870272 |
|
|
Feb 09 07:32:04 AM UTC 25 |
Feb 09 07:35:10 AM UTC 25 |
99268637411 ps |
| T1121 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.258346344 |
|
|
Feb 09 07:20:45 AM UTC 25 |
Feb 09 07:35:11 AM UTC 25 |
48465674900 ps |
| T1122 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/260.uart_fifo_reset.3485405772 |
|
|
Feb 09 07:34:06 AM UTC 25 |
Feb 09 07:35:12 AM UTC 25 |
21097969719 ps |
| T1123 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.3201670795 |
|
|
Feb 09 07:19:37 AM UTC 25 |
Feb 09 07:35:12 AM UTC 25 |
331008492568 ps |
| T1124 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/274.uart_fifo_reset.2273868226 |
|
|
Feb 09 07:34:43 AM UTC 25 |
Feb 09 07:35:16 AM UTC 25 |
20660243041 ps |
| T1125 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/221.uart_fifo_reset.1173419303 |
|
|
Feb 09 07:32:49 AM UTC 25 |
Feb 09 07:35:17 AM UTC 25 |
57895092623 ps |
| T1126 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/258.uart_fifo_reset.1545789775 |
|
|
Feb 09 07:34:05 AM UTC 25 |
Feb 09 07:35:18 AM UTC 25 |
19842390979 ps |
| T1127 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/273.uart_fifo_reset.3361737401 |
|
|
Feb 09 07:34:34 AM UTC 25 |
Feb 09 07:35:20 AM UTC 25 |
50433217590 ps |
| T1128 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/286.uart_fifo_reset.3886719907 |
|
|
Feb 09 07:34:59 AM UTC 25 |
Feb 09 07:35:26 AM UTC 25 |
31461490941 ps |
| T1129 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/280.uart_fifo_reset.268125199 |
|
|
Feb 09 07:34:50 AM UTC 25 |
Feb 09 07:35:27 AM UTC 25 |
31903176262 ps |
| T1130 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/255.uart_fifo_reset.1000265338 |
|
|
Feb 09 07:34:04 AM UTC 25 |
Feb 09 07:35:28 AM UTC 25 |
102927807841 ps |
| T1131 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/241.uart_fifo_reset.4036255487 |
|
|
Feb 09 07:33:35 AM UTC 25 |
Feb 09 07:35:29 AM UTC 25 |
43177577854 ps |
| T1132 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/284.uart_fifo_reset.3620702369 |
|
|
Feb 09 07:34:53 AM UTC 25 |
Feb 09 07:35:30 AM UTC 25 |
28167094327 ps |
| T1133 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/281.uart_fifo_reset.3992857345 |
|
|
Feb 09 07:34:50 AM UTC 25 |
Feb 09 07:35:34 AM UTC 25 |
51807180612 ps |
| T1134 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/298.uart_fifo_reset.778968992 |
|
|
Feb 09 07:35:18 AM UTC 25 |
Feb 09 07:35:35 AM UTC 25 |
29788216938 ps |
| T1135 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/282.uart_fifo_reset.1955028537 |
|
|
Feb 09 07:34:52 AM UTC 25 |
Feb 09 07:35:37 AM UTC 25 |
14431528056 ps |
| T1136 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/275.uart_fifo_reset.1052759112 |
|
|
Feb 09 07:34:43 AM UTC 25 |
Feb 09 07:35:37 AM UTC 25 |
27718703531 ps |
| T1137 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/289.uart_fifo_reset.624158662 |
|
|
Feb 09 07:35:05 AM UTC 25 |
Feb 09 07:35:38 AM UTC 25 |
119349243808 ps |
| T1138 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/293.uart_fifo_reset.396132828 |
|
|
Feb 09 07:35:10 AM UTC 25 |
Feb 09 07:35:38 AM UTC 25 |
36642807591 ps |
| T1139 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/246.uart_fifo_reset.606139273 |
|
|
Feb 09 07:33:38 AM UTC 25 |
Feb 09 07:35:40 AM UTC 25 |
96056969835 ps |
| T1140 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/268.uart_fifo_reset.3410639715 |
|
|
Feb 09 07:34:22 AM UTC 25 |
Feb 09 07:35:43 AM UTC 25 |
50330603857 ps |
| T1141 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/287.uart_fifo_reset.4009084408 |
|
|
Feb 09 07:35:00 AM UTC 25 |
Feb 09 07:35:43 AM UTC 25 |
78799246128 ps |
| T265 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/285.uart_fifo_reset.1827174361 |
|
|
Feb 09 07:34:58 AM UTC 25 |
Feb 09 07:35:43 AM UTC 25 |
62585986990 ps |
| T1142 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1644954501 |
|
|
Feb 09 07:34:34 AM UTC 25 |
Feb 09 07:35:48 AM UTC 25 |
88314823195 ps |
| T1143 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/228.uart_fifo_reset.968427787 |
|
|
Feb 09 07:33:12 AM UTC 25 |
Feb 09 07:35:48 AM UTC 25 |
103050872610 ps |
| T1144 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/296.uart_fifo_reset.871045278 |
|
|
Feb 09 07:35:13 AM UTC 25 |
Feb 09 07:35:55 AM UTC 25 |
374057164025 ps |
| T1145 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/297.uart_fifo_reset.1579993415 |
|
|
Feb 09 07:35:17 AM UTC 25 |
Feb 09 07:35:58 AM UTC 25 |
107476761526 ps |
| T226 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/294.uart_fifo_reset.1327921798 |
|
|
Feb 09 07:35:11 AM UTC 25 |
Feb 09 07:36:02 AM UTC 25 |
27652300595 ps |
| T1146 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/267.uart_fifo_reset.293081910 |
|
|
Feb 09 07:34:20 AM UTC 25 |
Feb 09 07:36:02 AM UTC 25 |
155845621190 ps |
| T1147 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/295.uart_fifo_reset.2127077298 |
|
|
Feb 09 07:35:13 AM UTC 25 |
Feb 09 07:36:08 AM UTC 25 |
27513944708 ps |
| T1148 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/237.uart_fifo_reset.2653930021 |
|
|
Feb 09 07:33:25 AM UTC 25 |
Feb 09 07:36:08 AM UTC 25 |
86668503869 ps |
| T1149 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/263.uart_fifo_reset.2099669848 |
|
|
Feb 09 07:34:10 AM UTC 25 |
Feb 09 07:36:13 AM UTC 25 |
65503664148 ps |
| T1150 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/129.uart_fifo_reset.3659519196 |
|
|
Feb 09 07:28:40 AM UTC 25 |
Feb 09 07:36:15 AM UTC 25 |
238373953698 ps |
| T1151 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/277.uart_fifo_reset.3495540721 |
|
|
Feb 09 07:34:44 AM UTC 25 |
Feb 09 07:36:19 AM UTC 25 |
433708098964 ps |
| T251 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2039293091 |
|
|
Feb 09 07:35:06 AM UTC 25 |
Feb 09 07:36:19 AM UTC 25 |
159500917339 ps |
| T1152 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/288.uart_fifo_reset.703946971 |
|
|
Feb 09 07:35:05 AM UTC 25 |
Feb 09 07:36:21 AM UTC 25 |
108977675970 ps |
| T1153 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/150.uart_fifo_reset.309835913 |
|
|
Feb 09 07:29:44 AM UTC 25 |
Feb 09 07:36:24 AM UTC 25 |
180846995987 ps |
| T1154 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/253.uart_fifo_reset.1392633141 |
|
|
Feb 09 07:33:54 AM UTC 25 |
Feb 09 07:36:29 AM UTC 25 |
71983804807 ps |
| T1155 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.3643642100 |
|
|
Feb 09 07:26:05 AM UTC 25 |
Feb 09 07:36:37 AM UTC 25 |
44242304766 ps |
| T1156 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/299.uart_fifo_reset.1042699172 |
|
|
Feb 09 07:35:19 AM UTC 25 |
Feb 09 07:36:39 AM UTC 25 |
48219535320 ps |
| T1157 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2105816590 |
|
|
Feb 09 07:34:48 AM UTC 25 |
Feb 09 07:36:42 AM UTC 25 |
132501289640 ps |
| T252 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/261.uart_fifo_reset.1557875770 |
|
|
Feb 09 07:34:06 AM UTC 25 |
Feb 09 07:36:47 AM UTC 25 |
144166727434 ps |
| T1158 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/262.uart_fifo_reset.2354601697 |
|
|
Feb 09 07:34:10 AM UTC 25 |
Feb 09 07:36:58 AM UTC 25 |
68930358549 ps |
| T280 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/234.uart_fifo_reset.116790189 |
|
|
Feb 09 07:33:17 AM UTC 25 |
Feb 09 07:37:02 AM UTC 25 |
90689687907 ps |
| T1159 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/292.uart_fifo_reset.2230984921 |
|
|
Feb 09 07:35:10 AM UTC 25 |
Feb 09 07:37:11 AM UTC 25 |
164119267680 ps |
| T259 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.2846993520 |
|
|
Feb 09 07:25:01 AM UTC 25 |
Feb 09 07:37:13 AM UTC 25 |
316843889035 ps |
| T1160 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/243.uart_fifo_reset.3402416612 |
|
|
Feb 09 07:33:36 AM UTC 25 |
Feb 09 07:37:17 AM UTC 25 |
128952276809 ps |
| T1161 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/251.uart_fifo_reset.3147193294 |
|
|
Feb 09 07:33:52 AM UTC 25 |
Feb 09 07:37:21 AM UTC 25 |
111555233264 ps |
| T1162 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.677559511 |
|
|
Feb 09 07:20:16 AM UTC 25 |
Feb 09 07:37:22 AM UTC 25 |
576975472472 ps |
| T1163 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/276.uart_fifo_reset.796570711 |
|
|
Feb 09 07:34:43 AM UTC 25 |
Feb 09 07:37:37 AM UTC 25 |
104272197066 ps |
| T1164 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/283.uart_fifo_reset.836292381 |
|
|
Feb 09 07:34:53 AM UTC 25 |
Feb 09 07:38:02 AM UTC 25 |
111065772190 ps |
| T1165 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/264.uart_fifo_reset.221119339 |
|
|
Feb 09 07:34:18 AM UTC 25 |
Feb 09 07:38:04 AM UTC 25 |
111505415000 ps |
| T1166 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.2969979724 |
|
|
Feb 09 07:23:13 AM UTC 25 |
Feb 09 07:38:22 AM UTC 25 |
49331526220 ps |
| T1167 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/291.uart_fifo_reset.520863828 |
|
|
Feb 09 07:35:07 AM UTC 25 |
Feb 09 07:38:24 AM UTC 25 |
157171147082 ps |
| T266 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/166.uart_fifo_reset.3476646592 |
|
|
Feb 09 07:30:26 AM UTC 25 |
Feb 09 07:38:56 AM UTC 25 |
244196774896 ps |
| T1168 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.2557878561 |
|
|
Feb 09 07:25:41 AM UTC 25 |
Feb 09 07:39:00 AM UTC 25 |
90918673285 ps |
| T1169 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.1002688192 |
|
|
Feb 09 07:21:09 AM UTC 25 |
Feb 09 07:39:03 AM UTC 25 |
271867200072 ps |
| T1170 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/217.uart_fifo_reset.3705060886 |
|
|
Feb 09 07:32:33 AM UTC 25 |
Feb 09 07:39:16 AM UTC 25 |
265599509195 ps |
| T1171 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.3252714274 |
|
|
Feb 09 07:25:22 AM UTC 25 |
Feb 09 07:40:55 AM UTC 25 |
185144647040 ps |
| T1172 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.3476444469 |
|
|
Feb 09 07:22:33 AM UTC 25 |
Feb 09 07:41:00 AM UTC 25 |
199014886677 ps |
| T73 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.1889460404 |
|
|
Feb 09 07:18:48 AM UTC 25 |
Feb 09 07:41:02 AM UTC 25 |
472646495384 ps |
| T74 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.889591593 |
|
|
Feb 09 07:23:23 AM UTC 25 |
Feb 09 07:41:46 AM UTC 25 |
78033732124 ps |
| T75 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.1530796245 |
|
|
Feb 09 07:20:05 AM UTC 25 |
Feb 09 07:42:48 AM UTC 25 |
88749456602 ps |
| T1173 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.3937091542 |
|
|
Feb 09 07:22:57 AM UTC 25 |
Feb 09 07:42:55 AM UTC 25 |
434938055745 ps |
| T1174 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.3737743631 |
|
|
Feb 09 07:21:29 AM UTC 25 |
Feb 09 07:43:33 AM UTC 25 |
320047383749 ps |
| T1175 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.2269185647 |
|
|
Feb 09 07:25:46 AM UTC 25 |
Feb 09 07:43:51 AM UTC 25 |
55920871923 ps |
| T1176 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.603313898 |
|
|
Feb 09 07:17:16 AM UTC 25 |
Feb 09 07:44:32 AM UTC 25 |
189876930926 ps |
| T1177 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.1695317190 |
|
|
Feb 09 07:25:00 AM UTC 25 |
Feb 09 07:44:37 AM UTC 25 |
62025056102 ps |
| T1178 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.4144478019 |
|
|
Feb 09 07:25:12 AM UTC 25 |
Feb 09 07:45:14 AM UTC 25 |
83799793545 ps |
| T76 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.964858975 |
|
|
Feb 09 07:21:24 AM UTC 25 |
Feb 09 07:45:31 AM UTC 25 |
2496901405595 ps |
| T1179 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_stress_all.4158379933 |
|
|
Feb 09 07:16:45 AM UTC 25 |
Feb 09 08:15:02 AM UTC 25 |
874938258622 ps |
| T1180 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2088037488 |
|
|
Feb 09 07:35:21 AM UTC 25 |
Feb 09 07:35:25 AM UTC 25 |
295813993 ps |
| T1181 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.1358196796 |
|
|
Feb 09 07:35:27 AM UTC 25 |
Feb 09 07:35:29 AM UTC 25 |
55095371 ps |
| T104 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.3686660520 |
|
|
Feb 09 07:35:26 AM UTC 25 |
Feb 09 07:35:29 AM UTC 25 |
138702659 ps |
| T1182 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.1392127817 |
|
|
Feb 09 07:35:28 AM UTC 25 |
Feb 09 07:35:30 AM UTC 25 |
16373291 ps |
| T77 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.3682740130 |
|
|
Feb 09 07:35:29 AM UTC 25 |
Feb 09 07:35:31 AM UTC 25 |
14959413 ps |
| T1183 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.651995232 |
|
|
Feb 09 07:35:30 AM UTC 25 |
Feb 09 07:35:32 AM UTC 25 |
79929054 ps |
| T90 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3809620522 |
|
|
Feb 09 07:35:30 AM UTC 25 |
Feb 09 07:35:32 AM UTC 25 |
124916095 ps |
| T1184 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.434696277 |
|
|
Feb 09 07:35:29 AM UTC 25 |
Feb 09 07:35:33 AM UTC 25 |
445789335 ps |
| T1185 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2778293449 |
|
|
Feb 09 07:35:31 AM UTC 25 |
Feb 09 07:35:34 AM UTC 25 |
28340533 ps |
| T1186 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.3569326131 |
|
|
Feb 09 07:35:33 AM UTC 25 |
Feb 09 07:35:35 AM UTC 25 |
45526097 ps |
| T105 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.3029046450 |
|
|
Feb 09 07:35:32 AM UTC 25 |
Feb 09 07:35:35 AM UTC 25 |
87254124 ps |
| T87 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3698094083 |
|
|
Feb 09 07:35:33 AM UTC 25 |
Feb 09 07:35:35 AM UTC 25 |
45882990 ps |
| T78 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.1191106604 |
|
|
Feb 09 07:35:33 AM UTC 25 |
Feb 09 07:35:36 AM UTC 25 |
16793628 ps |
| T1187 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1888694860 |
|
|
Feb 09 07:35:31 AM UTC 25 |
Feb 09 07:35:36 AM UTC 25 |
50763413 ps |
| T91 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.2502096782 |
|
|
Feb 09 07:35:36 AM UTC 25 |
Feb 09 07:35:38 AM UTC 25 |
15272064 ps |
| T88 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.806699457 |
|
|
Feb 09 07:35:36 AM UTC 25 |
Feb 09 07:35:38 AM UTC 25 |
47580222 ps |
| T1188 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.3516491755 |
|
|
Feb 09 07:35:37 AM UTC 25 |
Feb 09 07:35:39 AM UTC 25 |
11627001 ps |
| T79 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.2210785393 |
|
|
Feb 09 07:35:37 AM UTC 25 |
Feb 09 07:35:39 AM UTC 25 |
48659689 ps |
| T1189 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2768348818 |
|
|
Feb 09 07:35:37 AM UTC 25 |
Feb 09 07:35:39 AM UTC 25 |
234785233 ps |
| T106 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.4015733321 |
|
|
Feb 09 07:35:37 AM UTC 25 |
Feb 09 07:35:40 AM UTC 25 |
171347833 ps |
| T1190 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.2638985004 |
|
|
Feb 09 07:35:37 AM UTC 25 |
Feb 09 07:35:40 AM UTC 25 |
233063894 ps |
| T92 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.2716433503 |
|
|
Feb 09 07:35:38 AM UTC 25 |
Feb 09 07:35:40 AM UTC 25 |
74806969 ps |
| T80 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.2955149507 |
|
|
Feb 09 07:35:38 AM UTC 25 |
Feb 09 07:35:40 AM UTC 25 |
21383804 ps |
| T93 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.3323335185 |
|
|
Feb 09 07:35:38 AM UTC 25 |
Feb 09 07:35:40 AM UTC 25 |
71284930 ps |
| T1191 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.4045979972 |
|
|
Feb 09 07:35:36 AM UTC 25 |
Feb 09 07:35:41 AM UTC 25 |
1746620934 ps |
| T1192 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.259197650 |
|
|
Feb 09 07:35:38 AM UTC 25 |
Feb 09 07:35:41 AM UTC 25 |
118531880 ps |
| T89 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.18198305 |
|
|
Feb 09 07:35:40 AM UTC 25 |
Feb 09 07:35:42 AM UTC 25 |
25264058 ps |
| T1193 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.298768831 |
|
|
Feb 09 07:35:40 AM UTC 25 |
Feb 09 07:35:42 AM UTC 25 |
17907100 ps |
| T109 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.679374597 |
|
|
Feb 09 07:35:52 AM UTC 25 |
Feb 09 07:35:55 AM UTC 25 |
487114968 ps |
| T110 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.2974403774 |
|
|
Feb 09 07:35:40 AM UTC 25 |
Feb 09 07:35:43 AM UTC 25 |
251004313 ps |
| T94 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2878872694 |
|
|
Feb 09 07:35:41 AM UTC 25 |
Feb 09 07:35:43 AM UTC 25 |
70949137 ps |
| T1194 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2415851483 |
|
|
Feb 09 07:35:41 AM UTC 25 |
Feb 09 07:35:43 AM UTC 25 |
87178433 ps |
| T81 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.3944602384 |
|
|
Feb 09 07:35:41 AM UTC 25 |
Feb 09 07:35:43 AM UTC 25 |
70177530 ps |
| T95 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.3396854962 |
|
|
Feb 09 07:35:41 AM UTC 25 |
Feb 09 07:35:43 AM UTC 25 |
29722523 ps |
| T82 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.1090986231 |
|
|
Feb 09 07:35:38 AM UTC 25 |
Feb 09 07:35:43 AM UTC 25 |
265061514 ps |
| T1195 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.2161897325 |
|
|
Feb 09 07:35:40 AM UTC 25 |
Feb 09 07:35:44 AM UTC 25 |
430733386 ps |
| T1196 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.3645706491 |
|
|
Feb 09 07:35:42 AM UTC 25 |
Feb 09 07:35:44 AM UTC 25 |
45048248 ps |
| T1197 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.2588803404 |
|
|
Feb 09 07:35:42 AM UTC 25 |
Feb 09 07:35:44 AM UTC 25 |
38447270 ps |
| T96 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.3120924891 |
|
|
Feb 09 07:35:42 AM UTC 25 |
Feb 09 07:35:44 AM UTC 25 |
39307190 ps |
| T1198 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.1603641873 |
|
|
Feb 09 07:35:41 AM UTC 25 |
Feb 09 07:35:45 AM UTC 25 |
111305673 ps |
| T1199 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.980548302 |
|
|
Feb 09 07:35:42 AM UTC 25 |
Feb 09 07:35:45 AM UTC 25 |
41813427 ps |
| T140 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.4263986317 |
|
|
Feb 09 07:35:42 AM UTC 25 |
Feb 09 07:35:45 AM UTC 25 |
253741770 ps |
| T1200 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1740894580 |
|
|
Feb 09 07:35:44 AM UTC 25 |
Feb 09 07:35:46 AM UTC 25 |
23195309 ps |
| T1201 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.2432282669 |
|
|
Feb 09 07:35:44 AM UTC 25 |
Feb 09 07:35:46 AM UTC 25 |
29097216 ps |
| T1202 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.873558691 |
|
|
Feb 09 07:35:44 AM UTC 25 |
Feb 09 07:35:46 AM UTC 25 |
70453533 ps |
| T1203 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.1954163211 |
|
|
Feb 09 07:35:44 AM UTC 25 |
Feb 09 07:35:46 AM UTC 25 |
32392757 ps |
| T97 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2254905108 |
|
|
Feb 09 07:35:44 AM UTC 25 |
Feb 09 07:35:46 AM UTC 25 |
82992075 ps |
| T111 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.1041207716 |
|
|
Feb 09 07:35:44 AM UTC 25 |
Feb 09 07:35:47 AM UTC 25 |
108116074 ps |
| T1204 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.1930460167 |
|
|
Feb 09 07:35:45 AM UTC 25 |
Feb 09 07:35:47 AM UTC 25 |
15115397 ps |
| T1205 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.252245894 |
|
|
Feb 09 07:35:45 AM UTC 25 |
Feb 09 07:35:47 AM UTC 25 |
26062590 ps |
| T1206 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.1344673456 |
|
|
Feb 09 07:35:44 AM UTC 25 |
Feb 09 07:35:47 AM UTC 25 |
42459918 ps |
| T83 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.4085211060 |
|
|
Feb 09 07:35:45 AM UTC 25 |
Feb 09 07:35:47 AM UTC 25 |
20438771 ps |
| T1207 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3103504375 |
|
|
Feb 09 07:35:45 AM UTC 25 |
Feb 09 07:35:47 AM UTC 25 |
107734736 ps |
| T1208 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.1640057907 |
|
|
Feb 09 07:35:45 AM UTC 25 |
Feb 09 07:35:48 AM UTC 25 |
163158328 ps |
| T84 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.1182694626 |
|
|
Feb 09 07:35:44 AM UTC 25 |
Feb 09 07:35:48 AM UTC 25 |
291396377 ps |
| T1209 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.2017400756 |
|
|
Feb 09 07:35:45 AM UTC 25 |
Feb 09 07:35:48 AM UTC 25 |
190637263 ps |
| T1210 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.736135528 |
|
|
Feb 09 07:35:47 AM UTC 25 |
Feb 09 07:35:49 AM UTC 25 |
45117200 ps |
| T1211 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.258168843 |
|
|
Feb 09 07:35:47 AM UTC 25 |
Feb 09 07:35:49 AM UTC 25 |
96110473 ps |
| T1212 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.1140339423 |
|
|
Feb 09 07:35:47 AM UTC 25 |
Feb 09 07:35:49 AM UTC 25 |
27150275 ps |
| T1213 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.4034597707 |
|
|
Feb 09 07:35:47 AM UTC 25 |
Feb 09 07:35:49 AM UTC 25 |
18074992 ps |
| T1214 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.290467942 |
|
|
Feb 09 07:35:47 AM UTC 25 |
Feb 09 07:35:49 AM UTC 25 |
155234295 ps |
| T1215 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.823623693 |
|
|
Feb 09 07:35:47 AM UTC 25 |
Feb 09 07:35:49 AM UTC 25 |
133133845 ps |
| T1216 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.1885514829 |
|
|
Feb 09 07:35:54 AM UTC 25 |
Feb 09 07:35:56 AM UTC 25 |
14065776 ps |
| T1217 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.367683268 |
|
|
Feb 09 07:35:47 AM UTC 25 |
Feb 09 07:35:50 AM UTC 25 |
99975957 ps |
| T85 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.1257689681 |
|
|
Feb 09 07:35:48 AM UTC 25 |
Feb 09 07:35:50 AM UTC 25 |
53193458 ps |
| T1218 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.2185508759 |
|
|
Feb 09 07:35:48 AM UTC 25 |
Feb 09 07:35:50 AM UTC 25 |
41452389 ps |
| T1219 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.1997157040 |
|
|
Feb 09 07:35:48 AM UTC 25 |
Feb 09 07:35:51 AM UTC 25 |
97196671 ps |
| T1220 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1431954191 |
|
|
Feb 09 07:35:48 AM UTC 25 |
Feb 09 07:35:51 AM UTC 25 |
34042897 ps |
| T1221 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2604410261 |
|
|
Feb 09 07:35:48 AM UTC 25 |
Feb 09 07:35:51 AM UTC 25 |
43292287 ps |
| T1222 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.234395430 |
|
|
Feb 09 07:35:48 AM UTC 25 |
Feb 09 07:35:51 AM UTC 25 |
49833382 ps |
| T1223 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1529483365 |
|
|
Feb 09 07:35:48 AM UTC 25 |
Feb 09 07:35:51 AM UTC 25 |
414065683 ps |
| T1224 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.2434652586 |
|
|
Feb 09 07:35:50 AM UTC 25 |
Feb 09 07:35:52 AM UTC 25 |
40088181 ps |
| T1225 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.1516700491 |
|
|
Feb 09 07:35:50 AM UTC 25 |
Feb 09 07:35:52 AM UTC 25 |
20418463 ps |
| T1226 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.3476519255 |
|
|
Feb 09 07:35:50 AM UTC 25 |
Feb 09 07:35:52 AM UTC 25 |
32719089 ps |
| T1227 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.356446922 |
|
|
Feb 09 07:35:50 AM UTC 25 |
Feb 09 07:35:52 AM UTC 25 |
20263289 ps |
| T1228 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.3291326040 |
|
|
Feb 09 07:35:50 AM UTC 25 |
Feb 09 07:35:52 AM UTC 25 |
14132113 ps |
| T1229 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.4066575713 |
|
|
Feb 09 07:35:50 AM UTC 25 |
Feb 09 07:35:53 AM UTC 25 |
83761113 ps |
| T1230 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.3959115583 |
|
|
Feb 09 07:35:50 AM UTC 25 |
Feb 09 07:35:53 AM UTC 25 |
92139530 ps |
| T1231 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.3686218218 |
|
|
Feb 09 07:35:50 AM UTC 25 |
Feb 09 07:35:53 AM UTC 25 |
155495924 ps |
| T1232 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.225982597 |
|
|
Feb 09 07:35:50 AM UTC 25 |
Feb 09 07:35:53 AM UTC 25 |
184876438 ps |
| T1233 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.2351209030 |
|
|
Feb 09 07:35:50 AM UTC 25 |
Feb 09 07:35:53 AM UTC 25 |
45626569 ps |
| T1234 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.2833816551 |
|
|
Feb 09 07:35:52 AM UTC 25 |
Feb 09 07:35:54 AM UTC 25 |
26453703 ps |
| T1235 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.391743141 |
|
|
Feb 09 07:35:52 AM UTC 25 |
Feb 09 07:35:54 AM UTC 25 |
27174526 ps |
| T1236 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.2795671033 |
|
|
Feb 09 07:35:52 AM UTC 25 |
Feb 09 07:35:54 AM UTC 25 |
115797665 ps |
| T1237 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.701831732 |
|
|
Feb 09 07:35:52 AM UTC 25 |
Feb 09 07:35:54 AM UTC 25 |
46287491 ps |
| T1238 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3213425968 |
|
|
Feb 09 07:35:52 AM UTC 25 |
Feb 09 07:35:56 AM UTC 25 |
36063035 ps |
| T1239 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4003176442 |
|
|
Feb 09 07:35:52 AM UTC 25 |
Feb 09 07:35:54 AM UTC 25 |
85412892 ps |
| T86 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.545646214 |
|
|
Feb 09 07:35:54 AM UTC 25 |
Feb 09 07:35:56 AM UTC 25 |
143308486 ps |
| T1240 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2725828 |
|
|
Feb 09 07:35:54 AM UTC 25 |
Feb 09 07:35:56 AM UTC 25 |
20396045 ps |
| T1241 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.929756013 |
|
|
Feb 09 07:35:54 AM UTC 25 |
Feb 09 07:35:56 AM UTC 25 |
114142681 ps |
| T1242 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.290078415 |
|
|
Feb 09 07:35:54 AM UTC 25 |
Feb 09 07:35:56 AM UTC 25 |
83713089 ps |
| T1243 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.2223675276 |
|
|
Feb 09 07:35:54 AM UTC 25 |
Feb 09 07:35:56 AM UTC 25 |
14806153 ps |
| T1244 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.4066338993 |
|
|
Feb 09 07:35:54 AM UTC 25 |
Feb 09 07:35:56 AM UTC 25 |
49835894 ps |
| T141 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.1740230293 |
|
|
Feb 09 07:35:54 AM UTC 25 |
Feb 09 07:35:57 AM UTC 25 |
76784276 ps |
| T1245 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.1925686549 |
|
|
Feb 09 07:35:54 AM UTC 25 |
Feb 09 07:35:57 AM UTC 25 |
89583720 ps |
| T1246 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.3911406026 |
|
|
Feb 09 07:35:54 AM UTC 25 |
Feb 09 07:35:58 AM UTC 25 |
104301664 ps |
| T1247 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.2136816420 |
|
|
Feb 09 07:35:56 AM UTC 25 |
Feb 09 07:35:58 AM UTC 25 |
27218002 ps |
| T1248 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.4026509253 |
|
|
Feb 09 07:35:56 AM UTC 25 |
Feb 09 07:35:58 AM UTC 25 |
29039832 ps |
| T1249 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.749761444 |
|
|
Feb 09 07:35:56 AM UTC 25 |
Feb 09 07:35:58 AM UTC 25 |
92971664 ps |
| T1250 |
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1795610031 |
|
|
Feb 09 07:35:56 AM UTC 25 |
Feb 09 07:35:58 AM UTC 25 |
17567038 ps |