USBDEV Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 0.640s 1.714us 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.760s 21.232us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.070s 67.646us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 10.830s 1.737ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 2.980s 127.227us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 3.710s 106.575us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.070s 67.646us 20 20 100.00
usbdev_csr_aliasing 2.980s 127.227us 5 5 100.00
V1 mem_walk usbdev_mem_walk 3.540s 167.934us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.380s 185.114us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 intr_test usbdev_intr_test 0.680s 43.225us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.130s 310.292us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.130s 310.292us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.760s 21.232us 5 5 100.00
usbdev_csr_rw 1.070s 67.646us 20 20 100.00
usbdev_csr_aliasing 2.980s 127.227us 5 5 100.00
usbdev_same_csr_outstanding 9.210s 10.056ms 19 20 95.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.760s 21.232us 5 5 100.00
usbdev_csr_rw 1.070s 67.646us 20 20 100.00
usbdev_csr_aliasing 2.980s 127.227us 5 5 100.00
usbdev_same_csr_outstanding 9.210s 10.056ms 19 20 95.00
V2 TOTAL 89 90 98.89
V2S tl_intg_err usbdev_sec_cm 9.530s 10.006ms 0 5 0.00
usbdev_tl_intg_err 10.510s 10.009ms 6 20 30.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 10.510s 10.009ms 6 20 30.00
V2S TOTAL 6 25 24.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 0.630s 3.360us 0 50 0.00
usbdev_stress_all 0.590s 0 50 0.00
TOTAL 160 330 48.48

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 7 87.50
V2 3 3 2 66.67
V2S 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
69.81 69.41 63.91 87.42 0.00 74.05 97.77 96.10

Failure Buckets

Past Results