Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T33,T36,T43 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T33,T36,T43 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1142739 |
1360 |
0 |
0 |
T5 |
3772 |
4 |
0 |
0 |
T6 |
2182 |
2 |
0 |
0 |
T7 |
4279 |
2 |
0 |
0 |
T9 |
3065 |
2 |
0 |
0 |
T12 |
3999 |
2 |
0 |
0 |
T14 |
2706 |
2 |
0 |
0 |
T18 |
14511 |
20 |
0 |
0 |
T22 |
11646 |
18 |
0 |
0 |
T26 |
16748 |
40 |
0 |
0 |
T27 |
2979 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1657737 |
1362 |
0 |
0 |
T5 |
3772 |
4 |
0 |
0 |
T6 |
2182 |
2 |
0 |
0 |
T7 |
4279 |
2 |
0 |
0 |
T9 |
3065 |
2 |
0 |
0 |
T12 |
3999 |
2 |
0 |
0 |
T14 |
2706 |
2 |
0 |
0 |
T18 |
14511 |
20 |
0 |
0 |
T22 |
11646 |
18 |
0 |
0 |
T26 |
16748 |
40 |
0 |
0 |
T27 |
2979 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 6 | 2 | 33.33 |
Logical | 6 | 2 | 33.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Not Covered | |
1 | 1 | Unreachable | |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209247 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
724245 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T33,T36,T43 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T33,T36,T43 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209247 |
680 |
0 |
0 |
T5 |
1185 |
2 |
0 |
0 |
T6 |
685 |
1 |
0 |
0 |
T7 |
911 |
1 |
0 |
0 |
T9 |
437 |
1 |
0 |
0 |
T12 |
1090 |
1 |
0 |
0 |
T14 |
255 |
1 |
0 |
0 |
T18 |
1367 |
10 |
0 |
0 |
T22 |
2328 |
9 |
0 |
0 |
T26 |
4379 |
20 |
0 |
0 |
T27 |
119 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
724245 |
681 |
0 |
0 |
T5 |
2587 |
2 |
0 |
0 |
T6 |
1497 |
1 |
0 |
0 |
T7 |
3368 |
1 |
0 |
0 |
T9 |
2628 |
1 |
0 |
0 |
T12 |
2909 |
1 |
0 |
0 |
T14 |
2451 |
1 |
0 |
0 |
T18 |
13144 |
10 |
0 |
0 |
T22 |
9318 |
9 |
0 |
0 |
T26 |
12369 |
20 |
0 |
0 |
T27 |
2860 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T33,T36,T43 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T33,T36,T43 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
724245 |
680 |
0 |
0 |
T5 |
2587 |
2 |
0 |
0 |
T6 |
1497 |
1 |
0 |
0 |
T7 |
3368 |
1 |
0 |
0 |
T9 |
2628 |
1 |
0 |
0 |
T12 |
2909 |
1 |
0 |
0 |
T14 |
2451 |
1 |
0 |
0 |
T18 |
13144 |
10 |
0 |
0 |
T22 |
9318 |
9 |
0 |
0 |
T26 |
12369 |
20 |
0 |
0 |
T27 |
2860 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209247 |
681 |
0 |
0 |
T5 |
1185 |
2 |
0 |
0 |
T6 |
685 |
1 |
0 |
0 |
T7 |
911 |
1 |
0 |
0 |
T9 |
437 |
1 |
0 |
0 |
T12 |
1090 |
1 |
0 |
0 |
T14 |
255 |
1 |
0 |
0 |
T18 |
1367 |
10 |
0 |
0 |
T22 |
2328 |
9 |
0 |
0 |
T26 |
4379 |
20 |
0 |
0 |
T27 |
119 |
1 |
0 |
0 |