Module Definition
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Module : prim_reg_cdc
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_wake_events_cdc 57.45 82.35 30.77 66.67 50.00
tb.dut.u_reg.u_wake_control_cdc 97.73 100.00 90.91 100.00 100.00



Module Instance : tb.dut.u_reg.u_wake_events_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
57.45 82.35 30.77 66.67 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.74 76.56 25.00 61.40 20.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.60 99.72 98.70 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 37.10 72.45 22.45 53.49 0.00
u_src_to_dst_req 58.33 100.00 33.33 100.00 0.00



Module Instance : tb.dut.u_reg.u_wake_control_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.13 96.08 96.43 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.60 99.72 98.70 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.88 87.50 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Module : prim_reg_cdc
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT5,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT5,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T6,T7
0 0 1 Covered T5,T6,T7
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T6,T7
0 0 1 Covered T5,T6,T7
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1448490 12792 0 0
DstReqKnown_A 418494 364098 0 0
SrcAckBusyChk_A 1448490 680 0 0
SrcBusyKnown_A 1448490 1394306 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1448490 12792 0 0
T5 2587 15 0 0
T6 1497 7 0 0
T7 3368 10 0 0
T9 2628 18 0 0
T12 2909 7 0 0
T14 2451 21 0 0
T18 13144 248 0 0
T22 9318 100 0 0
T26 12369 166 0 0
T27 2860 55 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 418494 364098 0 0
T1 3034 1346 0 0
T2 3720 2158 0 0
T3 11514 9830 0 0
T4 464 332 0 0
T5 2370 2228 0 0
T6 1370 1062 0 0
T7 1822 1648 0 0
T8 2968 2776 0 0
T9 874 680 0 0
T10 696 500 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1448490 680 0 0
T5 2587 2 0 0
T6 1497 1 0 0
T7 3368 1 0 0
T9 2628 1 0 0
T12 2909 1 0 0
T14 2451 1 0 0
T18 13144 10 0 0
T22 9318 9 0 0
T26 12369 20 0 0
T27 2860 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1448490 1394306 0 0
T1 14574 12990 0 0
T2 11172 9630 0 0
T3 23036 21386 0 0
T4 2808 2654 0 0
T5 5174 4976 0 0
T6 2994 2628 0 0
T7 6736 6580 0 0
T8 5940 5834 0 0
T9 5256 5038 0 0
T10 2090 1990 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Line No.TotalCoveredPercent
TOTAL171482.35
CONT_ASSIGN5400
ALWAYS605480.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS1047571.43
CONT_ASSIGN13900
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 unreachable
60 1 1
61 1 1
62 1 1
63 unreachable
64 1 1
65 0 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 unreachable
113 unreachable
114 1 1
123 0 1
124 0 1
MISSING_ELSE
139 unreachable
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
TotalCoveredPercent
Conditions13430.77
Logical13430.77
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Line No.TotalCoveredPercent
Branches 6 4 66.67
IF 60 3 2 66.67
IF 104 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 2 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 2 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 724245 0 0 0
DstReqKnown_A 209247 182049 0 0
SrcAckBusyChk_A 724245 0 0 0
SrcBusyKnown_A 724245 697153 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 724245 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 209247 182049 0 0
T1 1517 673 0 0
T2 1860 1079 0 0
T3 5757 4915 0 0
T4 232 166 0 0
T5 1185 1114 0 0
T6 685 531 0 0
T7 911 824 0 0
T8 1484 1388 0 0
T9 437 340 0 0
T10 348 250 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 724245 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 724245 697153 0 0
T1 7287 6495 0 0
T2 5586 4815 0 0
T3 11518 10693 0 0
T4 1404 1327 0 0
T5 2587 2488 0 0
T6 1497 1314 0 0
T7 3368 3290 0 0
T8 2970 2917 0 0
T9 2628 2519 0 0
T10 1045 995 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT5,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT5,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T6,T7
0 0 1 Covered T5,T6,T7
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T6,T7
0 0 1 Covered T5,T6,T7
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 724245 12792 0 0
DstReqKnown_A 209247 182049 0 0
SrcAckBusyChk_A 724245 680 0 0
SrcBusyKnown_A 724245 697153 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 724245 12792 0 0
T5 2587 15 0 0
T6 1497 7 0 0
T7 3368 10 0 0
T9 2628 18 0 0
T12 2909 7 0 0
T14 2451 21 0 0
T18 13144 248 0 0
T22 9318 100 0 0
T26 12369 166 0 0
T27 2860 55 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 209247 182049 0 0
T1 1517 673 0 0
T2 1860 1079 0 0
T3 5757 4915 0 0
T4 232 166 0 0
T5 1185 1114 0 0
T6 685 531 0 0
T7 911 824 0 0
T8 1484 1388 0 0
T9 437 340 0 0
T10 348 250 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 724245 680 0 0
T5 2587 2 0 0
T6 1497 1 0 0
T7 3368 1 0 0
T9 2628 1 0 0
T12 2909 1 0 0
T14 2451 1 0 0
T18 13144 10 0 0
T22 9318 9 0 0
T26 12369 20 0 0
T27 2860 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 724245 697153 0 0
T1 7287 6495 0 0
T2 5586 4815 0 0
T3 11518 10693 0 0
T4 1404 1327 0 0
T5 2587 2488 0 0
T6 1497 1314 0 0
T7 3368 3290 0 0
T8 2970 2917 0 0
T9 2628 2519 0 0
T10 1045 995 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%