USBDEV Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 15.140s 8.507ms 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.950s 71.059us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.060s 101.533us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 8.420s 1.023ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.710s 364.494us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.740s 87.691us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.060s 101.533us 20 20 100.00
usbdev_csr_aliasing 3.710s 364.494us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.010s 154.990us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.410s 153.811us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 14.520s 8.447ms 50 50 100.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 15.100s 8.399ms 50 50 100.00
V2 av_buffer usbdev_av_buffer 15.550s 8.421ms 50 50 100.00
V2 rx_fifo rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 14.940s 8.382ms 50 50 100.00
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 15.190s 8.373ms 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 15.000s 8.439ms 50 50 100.00
V2 max_length_in_transaction max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 15.180s 8.372ms 50 50 100.00
V2 min_length_in_transaction min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 15.340s 8.382ms 49 50 98.00
V2 random_length_in_trans random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 14.520s 8.395ms 50 50 100.00
V2 in_stall usbdev_in_stall 14.590s 8.368ms 49 50 98.00
V2 out_iso out_iso 0 0 --
V2 in_iso usbdev_in_iso 14.420s 8.376ms 49 50 98.00
V2 pkt_received usbdev_pkt_received 15.710s 8.398ms 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 15.340s 8.461ms 50 50 100.00
V2 disconnected usbdev_disconnected 14.550s 8.387ms 50 50 100.00
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend usbdev_link_suspend 19.030s 11.487ms 50 50 100.00
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err usbdev_link_in_err 14.650s 8.391ms 17 50 34.00
V2 rx_crc_err usbdev_rx_crc_err 14.390s 8.367ms 49 50 98.00
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_bitstuff_err 14.570s 8.354ms 18 50 36.00
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 15.700s 8.380ms 50 50 100.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 15.520s 8.386ms 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 16.400s 9.252ms 41 50 82.00
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 16.020s 8.391ms 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 15.040s 8.436ms 49 50 98.00
V2 nak_trans usbdev_nak_trans 14.850s 8.466ms 49 50 98.00
V2 stall_trans usbdev_stall_trans 14.850s 8.420ms 48 50 96.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 15.310s 8.399ms 49 50 98.00
V2 pending_in_trans usbdev_pending_in_trans 15.140s 8.386ms 50 50 100.00
V2 streaming_test streaming_test 0 0 --
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 1.201m 30.364ms 40 50 80.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume aon_wake_resume 0 0 --
V2 aon_wake_reset aon_wake_reset 0 0 --
V2 aon_wake_disconnect aon_wake_disconnect 0 0 --
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets rand_bus_resets 0 0 --
V2 rand_disconnects rand_disconnects 0 0 --
V2 max_usb_traffic max_usb_traffic 0 0 --
V2 stress_usb_traffic stress_usb_traffic 0 0 --
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 16.300s 9.620ms 47 50 94.00
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 15.870s 8.576ms 50 50 100.00
V2 intr_test usbdev_intr_test 0.760s 105.132us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.680s 274.395us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.680s 274.395us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.950s 71.059us 5 5 100.00
usbdev_csr_rw 1.060s 101.533us 20 20 100.00
usbdev_csr_aliasing 3.710s 364.494us 5 5 100.00
usbdev_same_csr_outstanding 1.780s 190.232us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.950s 71.059us 5 5 100.00
usbdev_csr_rw 1.060s 101.533us 20 20 100.00
usbdev_csr_aliasing 3.710s 364.494us 5 5 100.00
usbdev_same_csr_outstanding 1.780s 190.232us 20 20 100.00
V2 TOTAL 1494 1590 93.96
V2S tl_intg_err usbdev_sec_cm 1.510s 565.409us 5 5 100.00
usbdev_tl_intg_err 5.570s 991.050us 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.570s 991.050us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 32.960s 5.132ms 1 1 100.00
usbdev_out_iso 14.840s 8.427ms 49 50 98.00
random_length_in_trans 15.520s 8.435ms 50 50 100.00
min_length_in_transaction 13.820s 8.393ms 49 50 98.00
max_length_in_transaction 14.380s 8.479ms 49 50 98.00
usbdev_stress_all_with_rand_reset 0.740s 47.933us 0 50 0.00
usbdev_stress_all 0.640s 0 50 0.00
TOTAL 1684 1881 89.53

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 1 25.00
V1 8 8 8 100.00
V2 76 33 20 26.32
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
90.50 96.07 90.96 96.79 60.94 94.79 97.35 96.58

Failure Buckets

Past Results