Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usbdev
SCORELINECONDTOGGLEFSMBRANCHASSERT
23.17 0.00 0.00 92.66 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 23.17 0.00 0.00 92.66 0.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
23.17 0.00 0.00 92.66 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
63.50 66.21 59.64 87.37 0.00 69.99 97.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_event 0.00 0.00 0.00
gen_no_stubbed_memory.u_memory_1p 0.00 0.00 0.00
gen_no_stubbed_memory.u_tlul2sram 0.00 0.00 0.00 0.00
i_usbdev_iomux 0.00 0.00 0.00 0.00
intr_av_out_empty 0.00 0.00 0.00 0.00
intr_av_overflow 0.00 0.00 0.00 0.00
intr_av_setup_empty 0.00 0.00 0.00 0.00
intr_disconnected 0.00 0.00 0.00 0.00
intr_frame 0.00 0.00 0.00 0.00
intr_host_lost 0.00 0.00 0.00 0.00
intr_hw_pkt_received 0.00 0.00 0.00 0.00
intr_hw_pkt_sent 0.00 0.00 0.00 0.00
intr_link_in_err 0.00 0.00 0.00 0.00
intr_link_out_err 0.00 0.00 0.00 0.00
intr_link_reset 0.00 0.00 0.00 0.00
intr_link_resume 0.00 0.00 0.00 0.00
intr_link_suspend 0.00 0.00 0.00 0.00
intr_powered 0.00 0.00 0.00 0.00
intr_rx_bitstuff_err 0.00 0.00 0.00 0.00
intr_rx_crc_err 0.00 0.00 0.00 0.00
intr_rx_full 0.00 0.00 0.00 0.00
intr_rx_pid_err 0.00 0.00 0.00 0.00
tlul_assert_device 33.33 0.00 0.00 100.00
u_ctr_errors 0.00 0.00 0.00 0.00
u_ctr_in 0.00 0.00 0.00 0.00
u_ctr_nodata_in 0.00 0.00 0.00 0.00
u_ctr_out 0.00 0.00 0.00 0.00
u_reg 91.04 97.79 90.57 82.01 97.73 87.10
usbdev_avoutfifo 0.00 0.00 0.00 0.00
usbdev_avsetupfifo 0.00 0.00 0.00 0.00
usbdev_csr_assert 100.00 100.00
usbdev_impl 0.00 0.00 0.00 0.00 0.00
usbdev_rxfifo 0.00 0.00 0.00 0.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usbdev
Line No.TotalCoveredPercent
TOTAL16200.00
CONT_ASSIGN123100.00
CONT_ASSIGN167100.00
CONT_ASSIGN220100.00
ALWAYS222500.00
CONT_ASSIGN257100.00
CONT_ASSIGN258100.00
CONT_ASSIGN259100.00
CONT_ASSIGN263100.00
CONT_ASSIGN264100.00
CONT_ASSIGN266100.00
CONT_ASSIGN268100.00
CONT_ASSIGN316100.00
CONT_ASSIGN321100.00
CONT_ASSIGN324100.00
CONT_ASSIGN327100.00
CONT_ASSIGN352100.00
CONT_ASSIGN353100.00
CONT_ASSIGN354100.00
CONT_ASSIGN355100.00
CONT_ASSIGN356100.00
CONT_ASSIGN360100.00
ALWAYS38300
ALWAYS383300.00
ALWAYS39100
ALWAYS391400.00
ALWAYS40000
ALWAYS400300.00
ALWAYS40700
ALWAYS407300.00
ALWAYS41400
ALWAYS414300.00
ALWAYS42100
ALWAYS421200.00
ALWAYS434500.00
CONT_ASSIGN442100.00
CONT_ASSIGN443100.00
CONT_ASSIGN447100.00
CONT_ASSIGN448100.00
CONT_ASSIGN449100.00
CONT_ASSIGN451100.00
CONT_ASSIGN456100.00
CONT_ASSIGN457100.00
CONT_ASSIGN458100.00
CONT_ASSIGN460100.00
ALWAYS464300.00
ALWAYS47100
ALWAYS471300.00
ALWAYS480300.00
ALWAYS492300.00
ALWAYS49900
ALWAYS499300.00
ALWAYS5061000.00
ALWAYS525300.00
ALWAYS53200
ALWAYS532300.00
ALWAYS54000
ALWAYS540300.00
ALWAYS54900
ALWAYS549300.00
CONT_ASSIGN559100.00
CONT_ASSIGN560100.00
CONT_ASSIGN561100.00
CONT_ASSIGN684100.00
CONT_ASSIGN685100.00
CONT_ASSIGN687100.00
CONT_ASSIGN688100.00
CONT_ASSIGN706100.00
CONT_ASSIGN709100.00
ALWAYS71500
ALWAYS715800.00
CONT_ASSIGN800100.00
CONT_ASSIGN801100.00
CONT_ASSIGN802100.00
CONT_ASSIGN803100.00
CONT_ASSIGN811100.00
ALWAYS820800.00
CONT_ASSIGN834100.00
CONT_ASSIGN83500
CONT_ASSIGN838100.00
CONT_ASSIGN839100.00
CONT_ASSIGN897100.00
CONT_ASSIGN898100.00
CONT_ASSIGN902100.00
CONT_ASSIGN1165100.00
CONT_ASSIGN1166100.00
CONT_ASSIGN1167100.00
CONT_ASSIGN1168100.00
CONT_ASSIGN1208100.00
CONT_ASSIGN1211100.00
CONT_ASSIGN1220100.00
ALWAYS1223500.00
ALWAYS1232300.00
CONT_ASSIGN1245100.00
CONT_ASSIGN1248100.00
CONT_ASSIGN1255100.00
ALWAYS1259300.00
CONT_ASSIGN1266100.00
CONT_ASSIGN1271100.00
CONT_ASSIGN1273100.00
CONT_ASSIGN1281100.00
CONT_ASSIGN1283100.00
CONT_ASSIGN1285100.00
CONT_ASSIGN1287100.00
CONT_ASSIGN1297100.00
CONT_ASSIGN1301100.00
CONT_ASSIGN1304100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
123 0 1
167 0 1
220 0 1
222 0 1
223 0 1
225 0 1
226 0 1
228 0 1
257 0 1
258 0 1
259 0 1
263 0 1
264 0 1
266 0 1
268 0 1
316 0 1
321 0 1
324 0 1
327 0 1
352 0 1
353 0 1
354 0 1
355 0 1
356 0 1
360 0 1
383 0 1
384 0 1
385 0 1
391 0 1
392 0 1
393 0 1
394 0 1
400 0 1
401 0 1
402 0 1
407 0 1
408 0 1
409 0 1
414 0 1
415 0 1
416 0 1
421 0 1
422 0 1
434 0 1
435 0 1
436 0 1
438 0 1
439 0 1
442 0 1
443 0 1
447 0 1
448 0 1
449 0 1
451 0 1
456 0 1
457 0 1
458 0 1
460 0 1
464 0 1
465 0 1
466 0 1
==> MISSING_ELSE
471 0 1
472 0 1
473 0 1
480 0 1
481 0 1
482 0 1
492 0 1
493 0 1
494 0 1
==> MISSING_ELSE
499 0 1
500 0 1
501 0 1
506 0 1
507 0 1
508 0 1
509 0 1
510 0 1
512 0 1
514 0 1
515 0 1
516 0 1
518 0 1
==> MISSING_ELSE
525 0 1
526 0 2
==> MISSING_ELSE
532 0 1
533 0 1
534 0 1
540 0 1
541 0 1
542 0 1
549 0 1
550 0 1
551 0 1
559 0 1
560 0 1
561 0 1
684 0 1
685 0 1
687 0 1
688 0 1
706 0 1
709 0 1
715 0 1
716 0 1
717 0 1
718 0 1
719 0 1
720 0 1
722 0 1
723 0 1
800 0 1
801 0 1
802 0 1
803 0 1
811 0 1
820 0 1
821 0 1
822 0 1
823 0 1
825 0 1
826 0 1
828 0 1
829 0 1
==> MISSING_ELSE
834 0 1
835 unreachable
838 0 1
839 0 1
897 0 1
898 0 1
902 0 1
1165 0 1
1166 0 1
1167 0 1
1168 0 1
1208 0 1
1211 0 1
1220 0 1
1223 0 1
1224 0 1
1225 0 1
1226 0 1
1227 0 1
==> MISSING_ELSE
1232 0 1
1233 0 1
1235 0 1
1245 0 1
1248 0 1
1255 0 1
1259 0 1
1260 0 1
1262 0 1
1266 0 1
1271 0 1
1273 0 1
1281 0 1
1283 0 1
1285 0 1
1287 0 1
1297 0 1
1301 0 1
1304 0 1


Cond Coverage for Module : usbdev
TotalCoveredPercent
Conditions13400.00
Logical13400.00
Non-Logical00
Event00

 LINE       167
 EXPRESSION (event_rx_crc5_err | event_rx_crc16_err)
             --------1--------   ---------2--------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       220
 EXPRESSION (ns_cnt == 6'd47)
            --------1--------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       257
 EXPRESSION (reg2hw.fifo_ctrl.avsetup_rst.qe & reg2hw.fifo_ctrl.avsetup_rst.q)
             ---------------1---------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       258
 EXPRESSION (reg2hw.fifo_ctrl.avout_rst.qe & reg2hw.fifo_ctrl.avout_rst.q)
             --------------1--------------   --------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       259
 EXPRESSION (reg2hw.fifo_ctrl.rx_rst.qe & reg2hw.fifo_ctrl.rx_rst.q)
             -------------1------------   ------------2------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       263
 EXPRESSION (connect_en & ((~avsetup_rvalid)))
             -----1----   ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       264
 EXPRESSION (connect_en & ((~avout_rvalid)))
             -----1----   --------2--------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       266
 EXPRESSION ((reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready))) | (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready))))
             --------------------------1-------------------------   ------------------------2-----------------------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       266
 SUB-EXPRESSION (reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready)))
                 -----------1-----------   ------------2-----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       266
 SUB-EXPRESSION (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready)))
                 ----------1----------   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       268
 EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
             -----1----   ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       316
 EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
             ---------1---------   -----------2----------   ----------3----------   -----------4-----------
-1--2--3--4-StatusTests
0000Not Covered
0001Not Covered
0010Not Covered
0100Not Covered
1000Not Covered

 LINE       327
 EXPRESSION (rx_wready & (rx_depth < 4'((RXFifoDepth - 1))))
             ----1----   -----------------2----------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       442
 EXPRESSION (in_xact_starting ? in_buf[in_xact_start_ep] : in_buf_q)
             --------1-------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       443
 EXPRESSION (in_xact_starting ? in_size[in_xact_start_ep] : in_size_q)
             --------1-------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       447
 EXPRESSION (reg2hw.out_data_toggle.status.qe & reg2hw.out_data_toggle.mask.qe)
             ----------------1---------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       456
 EXPRESSION (reg2hw.in_data_toggle.status.qe & reg2hw.in_data_toggle.mask.qe)
             ---------------1---------------   --------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       465
 EXPRESSION (in_ep_xact_end && in_endpoint_val)
             -------1------    -------2-------
-1--2-StatusTests
01Not Covered
10Unreachable
11Not Covered

 LINE       493
 EXPRESSION (rx_wvalid && out_endpoint_val)
             ----1----    --------2-------
-1--2-StatusTests
01Not Covered
10Unreachable
11Not Covered

 LINE       512
 EXPRESSION (setup_received & out_endpoint_val)
             -------1------   --------2-------
-1--2-StatusTests
01Not Covered
10Unreachable
11Not Covered

 LINE       516
 EXPRESSION (in_ep_xact_end & in_endpoint_val)
             -------1------   -------2-------
-1--2-StatusTests
01Not Covered
10Unreachable
11Not Covered

 LINE       542
 EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
             ------------1-----------   ------------2------------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       550
 EXPRESSION (set_sending[i] | set_sentbit[i] | update_pend[i])
             -------1------   -------2------   -------3------
-1--2--3-StatusTests
000Not Covered
001Not Covered
010Not Covered
100Not Covered

 LINE       551
 EXPRESSION (((~set_sentbit[i])) & ((~update_pend[i])))
             ---------1---------   ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       560
 EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
             -----1-----
-1-StatusTests
0Not Covered
1Not Covered

 LINE       561
 EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
             --------1-------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       688
 EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
             ------------------1-----------------   -----------------2-----------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       800
 EXPRESSION (usb_mem_b_req | sw_mem_a_req)
             ------1------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       801
 EXPRESSION (usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write)
             ------1------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       802
 EXPRESSION (usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr)
             ------1------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       803
 EXPRESSION (usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata)
             ------1------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       826
 EXPRESSION (usb_mem_b_req & ((!usb_mem_b_write)))
             ------1------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       834
 EXPRESSION (gen_no_stubbed_memory.mem_rvalid & ((!gen_no_stubbed_memory.mem_rsteering)))
             ----------------1---------------   --------------------2-------------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       839
 EXPRESSION (gen_no_stubbed_memory.mem_b_read_q ? gen_no_stubbed_memory.mem_rdata : gen_no_stubbed_memory.mem_b_rdata_q)
             -----------------1----------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       902
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       1211
 EXPRESSION (use_diff_rcvr & ((~link_suspend)))
             ------1------   --------2--------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       1220
 EXPRESSION (usb_rcvr_ok_counter_q == '0)
            --------------1--------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       1224
 EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
             ------1------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       1226
 EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
             ---1---    --------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       1248
 EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
             -------1-------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       1255
 EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
             -------1-------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       1255
 SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
                 -------------------------1------------------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       1255
 SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
                 --------1-------    ----2----    -------3-------
-1--2--3-StatusTests
000Not Covered
001Not Covered
010Not Covered
100Not Covered

 LINE       1271
 EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
             -----------------1----------------   ----------------2----------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       1273
 EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
             ---------------1---------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       1310
 EXPRESSION (reg2hw.count_out.rst.qe & reg2hw.count_out.rst.q)
             -----------1-----------   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       1336
 EXPRESSION (reg2hw.count_in.rst.qe & reg2hw.count_in.rst.q)
             -----------1----------   ----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       1359
 EXPRESSION (reg2hw.count_nodata_in.rst.qe & reg2hw.count_nodata_in.rst.q)
             --------------1--------------   --------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       1376
 EXPRESSION (reg2hw.count_errors.rst.qe & reg2hw.count_errors.rst.q)
             -------------1------------   ------------2------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Toggle Coverage for Module : usbdev
TotalCoveredPercent
Totals 72 62 86.11
Total Bits 436 404 92.66
Total Bits 0->1 218 202 92.66
Total Bits 1->0 218 202 92.66

Ports 72 62 86.11
Port Bits 436 404 92.66
Port Bits 0->1 218 202 92.66
Port Bits 1->0 218 202 92.66

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T6 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T7 Yes T4,T5,T7 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T2,T3,T6 Yes T2,T3,T6 INPUT
tl_i.a_source[7:0] Yes Yes T2,T3,T6 Yes T2,T3,T6 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T2,T3,T6 Yes T2,T3,T6 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T2,T3,T6 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T2,T6,T8 Yes T2,T6,T8 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T2,T6,T8 Yes T2,T6,T8 OUTPUT
cio_usb_dp_i Yes Yes T2,T6,T8 Yes T2,T6,T8 INPUT
cio_usb_dn_i Yes Yes T2,T6,T8 Yes T2,T6,T8 INPUT
usb_rx_d_i Yes Yes T2,T6,T4 Yes T2,T6,T4 INPUT
cio_usb_dp_o Yes Yes T2,T6,T4 Yes T2,T6,T4 OUTPUT
cio_usb_dp_en_o Yes Yes T2,T6,T8 Yes T2,T6,T8 OUTPUT
cio_usb_dn_o Yes Yes T2,T6,T4 Yes T2,T6,T4 OUTPUT
cio_usb_dn_en_o Yes Yes T2,T6,T8 Yes T2,T6,T8 OUTPUT
usb_tx_se0_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT
usb_tx_d_o Yes Yes T2,T6,T4 Yes T2,T6,T4 OUTPUT
cio_sense_i No No No INPUT
usb_dp_pullup_o Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
usb_dn_pullup_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT
usb_rx_enable_o Yes Yes T2,T4,T8 Yes T2,T6,T4 OUTPUT
usb_tx_use_d_se0_o Yes Yes T2,T5,T8 Yes T2,T6,T5 OUTPUT
usb_aon_suspend_req_o Yes Yes T10,T13 Yes T10,T13 OUTPUT
usb_aon_wake_ack_o Yes Yes T2,T4,T8 Yes T2,T4,T8 OUTPUT
usb_aon_bus_reset_i No No No INPUT
usb_aon_sense_lost_i No No No INPUT
usb_aon_bus_not_idle_i No No No INPUT
usb_aon_wake_detect_active_i Yes Yes T13 Yes T13 INPUT
usb_ref_val_o No No No OUTPUT
usb_ref_pulse_o No No No OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
intr_pkt_received_o Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
intr_pkt_sent_o Yes Yes T3,T7,T9 Yes T3,T7,T9 OUTPUT
intr_powered_o Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
intr_disconnected_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_host_lost_o Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
intr_link_reset_o Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
intr_link_suspend_o Yes Yes T1,T7,T14 Yes T1,T7,T14 OUTPUT
intr_link_resume_o Yes Yes T3,T9,T14 Yes T3,T9,T14 OUTPUT
intr_av_out_empty_o Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
intr_rx_full_o Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
intr_av_overflow_o Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
intr_link_in_err_o Yes Yes T3,T7,T9 Yes T3,T7,T9 OUTPUT
intr_link_out_err_o Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
intr_rx_crc_err_o Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
intr_rx_pid_err_o Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
intr_rx_bitstuff_err_o Yes Yes T3,T7,T14 Yes T3,T7,T14 OUTPUT
intr_frame_o Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
intr_av_setup_empty_o Yes Yes T1,T7,T14 Yes T1,T7,T14 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : usbdev
Line No.TotalCoveredPercent
Branches 48 0 0.00
TERNARY 442 2 0 0.00
TERNARY 443 2 0 0.00
TERNARY 560 2 0 0.00
TERNARY 561 2 0 0.00
TERNARY 1248 2 0 0.00
TERNARY 1255 3 0 0.00
TERNARY 801 2 0 0.00
TERNARY 802 2 0 0.00
TERNARY 803 2 0 0.00
TERNARY 839 2 0 0.00
IF 222 3 0 0.00
IF 434 2 0 0.00
IF 465 2 0 0.00
IF 493 2 0 0.00
IF 508 4 0 0.00
IF 526 2 0 0.00
IF 718 2 0 0.00
IF 1224 3 0 0.00
IF 1232 2 0 0.00
IF 1259 2 0 0.00
IF 820 3 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 442 (in_xact_starting) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 443 (in_xact_starting) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 560 (cfg_pinflip) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 561 ((!cfg_pinflip)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 1248 (usb_ref_disable) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 1255 (usb_ref_pulse_o) ? -2-: 1255 ((((!link_active) || host_lost) || usb_ref_disable)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 801 (usb_mem_b_req) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 802 (usb_mem_b_req) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 803 (usb_mem_b_req) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 839 (gen_no_stubbed_memory.mem_b_read_q) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 222 if ((!rst_n)) -2-: 225 if (us_tick)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 434 if ((!rst_n))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 465 if ((in_ep_xact_end && in_endpoint_val))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 493 if ((rx_wvalid && out_endpoint_val))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 508 if (event_link_reset) -2-: 512 if ((setup_received & out_endpoint_val)) -3-: 516 if ((in_ep_xact_end & in_endpoint_val))

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Not Covered


LineNo. Expression -1-: 526 if (in_xact_starting)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 718 if (((setup_received && out_endpoint_val) && (out_endpoint == 4'((unsigned'(i))))))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 1224 if ((use_diff_rcvr & (!usb_rx_enable_o))) -2-: 1226 if ((us_tick && (usb_rcvr_ok_counter_q > '0)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 1232 if ((!rst_n))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 1259 if ((!rst_n))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 820 if ((!rst_ni)) -2-: 828 if (gen_no_stubbed_memory.mem_b_read_q)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%