Module Definition
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Module : tlul_adapter_sram
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_no_stubbed_memory.u_tlul2sram 0.00 0.00 0.00 0.00


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
23.17 0.00 0.00 92.66 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 0.00 0.00 0.00 0.00
u_reqfifo 0.00 0.00 0.00 0.00
u_rsp_gen 0.00 0.00
u_rspfifo 0.00 0.00 0.00 0.00
u_sram_byte 0.00 0.00
u_sramreqfifo 0.00 0.00 0.00 0.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
TOTAL7000.00
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS129300.00
CONT_ASSIGN138100.00
CONT_ASSIGN144100.00
CONT_ASSIGN151100.00
CONT_ASSIGN176100.00
CONT_ASSIGN188100.00
CONT_ASSIGN274100.00
CONT_ASSIGN275100.00
CONT_ASSIGN276100.00
ALWAYS281800.00
ALWAYS301600.00
CONT_ASSIGN315100.00
CONT_ASSIGN319100.00
CONT_ASSIGN338100.00
CONT_ASSIGN343100.00
CONT_ASSIGN349100.00
CONT_ASSIGN361100.00
ALWAYS364300.00
CONT_ASSIGN371100.00
CONT_ASSIGN392100.00
CONT_ASSIGN393100.00
CONT_ASSIGN394100.00
CONT_ASSIGN395100.00
ALWAYS425600.00
ALWAYS437500.00
CONT_ASSIGN452100.00
CONT_ASSIGN453100.00
CONT_ASSIGN454100.00
CONT_ASSIGN458100.00
CONT_ASSIGN459100.00
CONT_ASSIGN461100.00
CONT_ASSIGN462100.00
CONT_ASSIGN469100.00
CONT_ASSIGN472100.00
CONT_ASSIGN476100.00
CONT_ASSIGN477100.00
CONT_ASSIGN479100.00
CONT_ASSIGN481100.00
CONT_ASSIGN490100.00
ALWAYS521300.00
CONT_ASSIGN527100.00
CONT_ASSIGN530100.00
CONT_ASSIGN535100.00
CONT_ASSIGN54000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 0 1
130 0 1
131 0 1
132 unreachable
==> MISSING_ELSE
138 0 1
144 0 1
151 0 1
176 0 1
188 0 1
274 0 1
275 0 1
276 0 1
281 0 1
283 0 1
284 0 1
286 0 1
287 0 1
288 0 1
291 0 1
294 0 1
301 0 1
303 0 1
304 0 1
305 0 1
307 0 1
310 0 1
315 0 1
319 0 1
338 0 1
343 0 1
349 0 1
361 0 1
364 0 1
365 0 1
367 0 1
371 0 1
392 0 1
393 0 1
394 0 1
395 0 1
425 0 1
426 0 1
428 0 1
429 0 1
430 0 1
431 0 1
==> MISSING_ELSE
437 0 1
438 0 1
440 0 1
441 0 1
442 0 1
==> MISSING_ELSE
452 0 1
453 0 1
454 0 1
458 0 1
459 0 1
461 0 1
462 0 1
469 0 1
472 0 1
476 0 1
477 0 1
479 0 1
481 0 1
490 0 1
521 0 1
522 0 1
523 0 1
527 0 1
530 0 1
535 0 1
540 unreachable

Cond Coverage for Module : tlul_adapter_sram
TotalCoveredPercent
Conditions11800.00
Logical11800.00
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00Not Covered
01Unreachable
10Unreachable 

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000Not Covered
0001Unreachable
0010Unreachable
0100Unreachable
1000Unreachable 

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000Not Covered
00001Not Covered
00010Unreachable
00100Unreachable
01000Unreachable
10000Unreachable 

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000Not Covered
000001Unreachable
000010Not Covered
000100Not Covered
001000Unreachable
010000Unreachable
100000Not Covered 

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered 

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Unreachable
1111Not Covered 

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       454
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0Not Covered
1Not Covered
Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 26 0 0.00
TERNARY 144 2 0 0.00
TERNARY 343 2 0 0.00
TERNARY 349 3 0 0.00
TERNARY 395 2 0 0.00
TERNARY 535 2 0 0.00
IF 129 2 0 0.00
IF 283 4 0 0.00
IF 303 3 0 0.00
IF 364 2 0 0.00
IF 428 2 0 0.00
IF 440 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	144	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	343	((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	349	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	349	(vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	395	(tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	535	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	129	if ((!rst_ni))
-2-:	131	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Unreachable
0 0 Not Covered 



	LineNo.	Expression
-1-:	283	if (reqfifo_rvalid)
-2-:	284	if (reqfifo_rdata.error)
-3-:	287	if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Not Covered
1 0 1 Not Covered
1 0 0 Not Covered
0 - - Not Covered 



	LineNo.	Expression
-1-:	303	if (reqfifo_rvalid)
-2-:	304	if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Not Covered 



	LineNo.	Expression
-1-:	364	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	428	if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	440	if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%