USBDEV Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.050s 252.218us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.130s 281.040us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.020s 57.758us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.010s 1.794ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.850s 381.281us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.750s 157.771us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.020s 57.758us 20 20 100.00
usbdev_csr_aliasing 3.850s 381.281us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.830s 733.025us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 1.450s 186.395us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.030s 290.186us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 1.780s 522.719us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.770s 89.361us 50 50 100.00
V2 av_buffer usbdev_av_buffer 0.910s 183.727us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 50.890s 21.249ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.070s 327.025us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.940s 255.983us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.050s 321.817us 50 50 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.850s 140.701us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 0.980s 189.951us 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.040s 278.439us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.900s 148.508us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0.930s 162.608us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 0.950s 188.535us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 0.990s 292.677us 50 50 100.00
V2 out_stall usbdev_out_stall 0.970s 208.890us 50 50 100.00
V2 in_stall usbdev_in_stall 0.890s 163.264us 50 50 100.00
V2 out_iso usbdev_out_iso 0.930s 193.512us 50 50 100.00
V2 in_iso usbdev_in_iso 0.980s 200.520us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.010s 257.338us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.040s 257.422us 50 50 100.00
V2 disconnected usbdev_disconnected 0.940s 154.643us 50 50 100.00
V2 host_lost usbdev_host_lost 9.650s 4.157ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.800s 176.917us 1 1 100.00
V2 link_suspend usbdev_link_suspend 4.620s 3.285ms 50 50 100.00
V2 link_resume usbdev_link_resume 30.310s 23.333ms 50 50 100.00
V2 av_empty usbdev_av_empty 0.840s 161.100us 5 5 100.00
V2 rx_full usbdev_rx_full 0.970s 250.638us 1 1 100.00
V2 av_overflow usbdev_av_overflow 0.820s 134.807us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.040s 268.793us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 0.920s 170.603us 50 50 100.00
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_bitstuff_err 0.920s 187.619us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.330s 452.222us 1 1 100.00
V2 enable usbdev_enable 0.770s 80.232us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 17.700s 20.167ms 1 1 100.00
V2 device_address usbdev_device_address 47.750s 22.939ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.470s 521.252us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.870s 176.616us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 2.590s 992.369us 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 1.600s 456.013us 50 50 100.00
V2 out_trans_nak usbdev_out_trans_nak 0.940s 186.793us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.900s 182.656us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.020s 234.015us 50 50 100.00
V2 stall_trans usbdev_stall_trans 0.930s 176.330us 50 50 100.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 0.920s 246.700us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.880s 203.159us 50 50 100.00
V2 streaming_test usbdev_streaming_out 6.806m 14.008ms 50 50 100.00
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 6.267m 13.395ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 6.958m 14.624ms 50 50 100.00
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 50.890s 21.249ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.190s 402.996us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 29.540s 23.370ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 16.470s 13.336ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 5.910s 4.187ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 9.155m 19.128ms 17 50 34.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 6.436m 14.009ms 50 50 100.00
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets usbdev_rand_bus_resets 9.000m 19.712ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 9.665m 24.370ms 10 10 100.00
V2 max_usb_traffic usbdev_max_usb_traffic 6.011m 12.459ms 50 50 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 12.628m 30.459ms 5 5 100.00
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 3.310s 1.349ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.470s 420.413us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 2.680s 486.272us 50 50 100.00
V2 intr_test usbdev_intr_test 0.800s 64.068us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.220s 134.278us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.220s 134.278us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.130s 281.040us 5 5 100.00
usbdev_csr_rw 1.020s 57.758us 20 20 100.00
usbdev_csr_aliasing 3.850s 381.281us 5 5 100.00
usbdev_same_csr_outstanding 1.830s 171.782us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.130s 281.040us 5 5 100.00
usbdev_csr_rw 1.020s 57.758us 20 20 100.00
usbdev_csr_aliasing 3.850s 381.281us 5 5 100.00
usbdev_same_csr_outstanding 1.830s 171.782us 20 20 100.00
V2 TOTAL 2456 2489 98.67
V2S tl_intg_err usbdev_sec_cm 2.450s 1.834ms 5 5 100.00
usbdev_tl_intg_err 5.510s 1.121ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.510s 1.121ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 41.220s 5.109ms 1 1 100.00
usbdev_rand_suspends 15.431m 35.454ms 10 10 100.00
usbdev_stress_all_with_rand_reset 0.690s 92.902us 0 10 0.00
usbdev_stress_all 0.630s 0 50 0.00
TOTAL 2607 2700 96.56

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 2 50.00
V1 8 8 8 100.00
V2 75 65 64 85.33
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.81 97.86 93.79 97.44 76.56 96.29 98.17 96.58

Failure Buckets

Past Results