USBDEV Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.120s 263.589us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.030s 192.806us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.050s 90.955us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.080s 858.079us 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.350s 363.271us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.350s 129.244us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.050s 90.955us 20 20 100.00
usbdev_csr_aliasing 3.350s 363.271us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.550s 716.116us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.260s 74.459us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.050s 237.994us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 1.670s 502.879us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.740s 46.338us 50 50 100.00
V2 av_buffer usbdev_av_buffer 0.920s 163.416us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 53.750s 23.487ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.040s 316.407us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.850s 188.568us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.050s 221.348us 50 50 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.900s 197.926us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 0.980s 252.644us 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.040s 237.763us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.880s 205.790us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0.920s 184.340us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 0.940s 211.790us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.000s 229.565us 50 50 100.00
V2 out_stall usbdev_out_stall 0.930s 235.613us 50 50 100.00
V2 in_stall usbdev_in_stall 0.850s 153.284us 50 50 100.00
V2 out_iso usbdev_out_iso 0.980s 253.859us 50 50 100.00
V2 in_iso usbdev_in_iso 0.980s 239.462us 50 50 100.00
V2 pkt_received usbdev_pkt_received 0.950s 204.880us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 0.940s 250.814us 50 50 100.00
V2 disconnected usbdev_disconnected 0.920s 168.158us 50 50 100.00
V2 host_lost usbdev_host_lost 9.200s 4.161ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.860s 214.018us 1 1 100.00
V2 link_suspend usbdev_link_suspend 4.930s 3.320ms 50 50 100.00
V2 link_resume usbdev_link_resume 30.560s 23.283ms 50 50 100.00
V2 av_empty usbdev_av_empty 0.930s 204.665us 5 5 100.00
V2 rx_full usbdev_rx_full 1.000s 272.789us 1 1 100.00
V2 av_overflow usbdev_av_overflow 0.840s 141.846us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.020s 293.953us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 0.930s 188.353us 50 50 100.00
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_bitstuff_err 0.900s 236.515us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.340s 423.589us 1 1 100.00
V2 enable usbdev_enable 0.820s 138.559us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 18.530s 20.172ms 1 1 100.00
V2 device_address usbdev_device_address 48.440s 21.457ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.420s 560.379us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.940s 186.331us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 2.620s 1.019ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 1.540s 436.817us 50 50 100.00
V2 out_trans_nak usbdev_out_trans_nak 0.900s 180.775us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.890s 155.058us 50 50 100.00
V2 nak_trans usbdev_nak_trans 0.990s 203.872us 50 50 100.00
V2 stall_trans usbdev_stall_trans 0.880s 236.506us 50 50 100.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 0.960s 149.014us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.930s 222.319us 50 50 100.00
V2 streaming_test usbdev_streaming_out 6.735m 14.664ms 50 50 100.00
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 7.116m 14.779ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 5.829m 12.458ms 50 50 100.00
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 53.750s 23.487ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.460s 486.572us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 30.260s 23.460ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 16.610s 13.536ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 6.050s 4.294ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 9.000m 18.720ms 19 50 38.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 6.143m 13.021ms 50 50 100.00
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets usbdev_rand_bus_resets 11.306m 25.644ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 5.519m 15.388ms 10 10 100.00
V2 max_usb_traffic usbdev_max_usb_traffic 6.248m 13.071ms 50 50 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 10.808m 26.059ms 5 5 100.00
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 3.750s 1.657ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.320s 372.530us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 2.510s 448.222us 50 50 100.00
V2 intr_test usbdev_intr_test 0.750s 85.053us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.310s 261.796us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.310s 261.796us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.030s 192.806us 5 5 100.00
usbdev_csr_rw 1.050s 90.955us 20 20 100.00
usbdev_csr_aliasing 3.350s 363.271us 5 5 100.00
usbdev_same_csr_outstanding 2.920s 555.345us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.030s 192.806us 5 5 100.00
usbdev_csr_rw 1.050s 90.955us 20 20 100.00
usbdev_csr_aliasing 3.350s 363.271us 5 5 100.00
usbdev_same_csr_outstanding 2.920s 555.345us 20 20 100.00
V2 TOTAL 2458 2489 98.75
V2S tl_intg_err usbdev_sec_cm 1.880s 1.174ms 5 5 100.00
usbdev_tl_intg_err 6.690s 2.233ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 6.690s 2.233ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 2.173m 5.114ms 1 1 100.00
usbdev_rand_suspends 13.849m 33.228ms 10 10 100.00
usbdev_stress_all_with_rand_reset 0.660s 20.793us 0 10 0.00
usbdev_stress_all 0.630s 0 50 0.00
TOTAL 2609 2700 96.63

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 2 50.00
V1 8 8 8 100.00
V2 75 65 64 85.33
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.57 97.84 93.72 97.44 75.00 96.25 98.17 96.58

Failure Buckets

Past Results