USBDEV Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.970s 253.171us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.250s 93.568us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.260s 147.752us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 6.750s 328.418us 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.400s 298.045us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.400s 201.332us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.260s 147.752us 20 20 100.00
usbdev_csr_aliasing 3.400s 298.045us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.220s 622.019us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.350s 203.435us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.950s 281.855us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 2.920s 487.619us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 1.200s 54.853us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.700s 208.124us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.683m 20.598ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 2.090s 314.545us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 1.520s 169.281us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.890s 252.224us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.860s 250.241us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.560s 242.989us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.840s 236.622us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.580s 194.123us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.830s 232.208us 50 50 100.00
usbdev_stream_len_max 5.020s 1.188ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 2.040s 289.085us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 1.790s 225.077us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.610s 246.691us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.650s 210.365us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.820s 240.856us 50 50 100.00
V2 out_stall usbdev_out_stall 1.660s 191.943us 50 50 100.00
V2 in_stall usbdev_in_stall 1.750s 233.070us 50 50 100.00
V2 out_iso usbdev_out_iso 1.650s 220.136us 50 50 100.00
V2 in_iso usbdev_in_iso 2.200s 265.782us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.710s 256.016us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.820s 264.795us 50 50 100.00
V2 disconnected usbdev_disconnected 1.500s 145.674us 50 50 100.00
V2 host_lost usbdev_host_lost 20.500s 4.178ms 1 1 100.00
V2 link_reset usbdev_link_reset 1.580s 165.898us 1 1 100.00
V2 link_suspend usbdev_link_suspend 32.050s 10.881ms 50 50 100.00
V2 link_resume usbdev_link_resume 1.732m 33.567ms 50 50 100.00
V2 av_empty usbdev_av_empty 1.620s 195.484us 5 5 100.00
V2 rx_full usbdev_rx_full 2.470s 348.919us 50 50 100.00
V2 av_overflow usbdev_av_overflow 1.490s 140.661us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.750s 240.425us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.580s 202.918us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 1.790s 251.943us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 1.600s 202.865us 50 50 100.00
V2 link_out_err usbdev_link_out_err 2.560s 519.939us 1 1 100.00
V2 enable usbdev_enable 1.330s 94.420us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 52.320s 20.163ms 20 20 100.00
V2 device_address usbdev_device_address 2.185m 40.875ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 2.780s 514.807us 1 1 100.00
V2 setup_stage usbdev_setup_stage 1.540s 182.497us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 5.260s 994.042us 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 3.680s 795.294us 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 3.290s 677.813us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.690s 244.030us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.610s 195.598us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.790s 263.121us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.670s 216.441us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.750s 228.616us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.650s 192.326us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 1.550s 178.453us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.560m 3.975ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 4.168m 111.190ms 5 5 100.00
usbdev_freq_loclk 5.450m 118.102ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 4.248m 100.389ms 5 5 100.00
usbdev_freq_loclk_max 5.295m 117.923ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 3.921m 94.183ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 1.895m 3.966ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.669m 3.630ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 45.230s 1.815ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 53.590s 5.554ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.683m 20.598ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 2.730s 470.728us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 1.316m 28.664ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 43.880s 15.263ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 36.440s 10.389ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.601m 5.521ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.592m 3.793ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.254m 3.827ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 6.055m 15.630ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 3.461m 6.073ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 2.661m 9.144ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.698m 3.200ms 25 25 100.00
usbdev_max_usb_traffic 2.210m 3.394ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 4.796m 11.758ms 10 10 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.371m 13.347ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 5.620s 1.278ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 2.640s 404.200us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 4.520s 538.880us 50 50 100.00
V2 tx_rx_disruption usbdev_tx_rx_disruption 3.360s 637.361us 500 500 100.00
V2 fifo_levels usbdev_fifo_levels 2.060s 302.060us 160 160 100.00
V2 intr_test usbdev_intr_test 1.180s 50.701us 50 50 100.00
V2 alert_test usbdev_alert_test 1.200s 99.419us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.610s 258.104us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.610s 258.104us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.250s 93.568us 5 5 100.00
usbdev_csr_rw 1.260s 147.752us 20 20 100.00
usbdev_csr_aliasing 3.400s 298.045us 5 5 100.00
usbdev_same_csr_outstanding 2.300s 408.728us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.250s 93.568us 5 5 100.00
usbdev_csr_rw 1.260s 147.752us 20 20 100.00
usbdev_csr_aliasing 3.400s 298.045us 5 5 100.00
usbdev_same_csr_outstanding 2.300s 408.728us 20 20 100.00
V2 TOTAL 3764 3764 100.00
V2S tl_intg_err usbdev_sec_cm 3.610s 1.265ms 5 5 100.00
usbdev_tl_intg_err 5.440s 908.119us 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.440s 908.119us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 2.879m 5.151ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 1.120s 63.205us 0 10 0.00
usbdev_stress_all 0.870s 0 50 0.00
TOTAL 3905 3965 98.49

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 86 86 86 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.63 98.23 96.05 97.44 96.61 98.42 98.21 98.46

Failure Buckets

Past Results