USBDEV Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	usbdev_smoke	1.850s	260.816us	50	50	100.00
V1	csr_hw_reset	usbdev_csr_hw_reset	0.870s	97.236us	5	5	100.00
V1	csr_rw	usbdev_csr_rw	41.558s		15	20	75.00
V1	csr_bit_bash	usbdev_csr_bit_bash	4.920s	1.139ms	5	5	100.00
V1	csr_aliasing	usbdev_csr_aliasing	41.572s		4	5	80.00
V1	csr_mem_rw_with_rand_reset	usbdev_csr_mem_rw_with_rand_reset	41.640s		17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	usbdev_csr_rw	41.558s		15	20	75.00
		usbdev_csr_aliasing	41.572s		4	5	80.00
V1	mem_walk	usbdev_mem_walk	4.240s	482.945us	5	5	100.00
V1	mem_partial_access	usbdev_mem_partial_access	2.060s	168.549us	5	5	100.00
V1		TOTAL			106	115	92.17
V2	in_trans	usbdev_in_trans	1.890s	274.978us	50	50	100.00
V2	data_toggle_clear	usbdev_data_toggle_clear	2.990s	530.420us	50	50	100.00
V2	phy_pins_sense	usbdev_phy_pins_sense	1.310s	117.928us	50	50	100.00
V2	av_buffer	usbdev_av_buffer	1.720s	243.569us	50	50	100.00
V2	rx_fifo	usbdev_pkt_buffer	1.120m	21.402ms	50	50	100.00
V2	phy_config_tx_osc_test_mode	usbdev_phy_config_tx_osc_test_mode	1.260s	307.057us	1	1	100.00
V2	phy_config_eop_single_bit_handling	usbdev_phy_config_eop_single_bit_handling	0.990s	169.769us	1	1	100.00
V2	phy_config_pinflip	usbdev_phy_config_pinflip	1.950s	249.694us	50	50	100.00
V2	phy_config_rand_bus_type	usbdev_phy_config_rand_bus_type	1.820s	260.398us	5	5	100.00
V2	phy_config_rx_dp_dn	usbdev_phy_config_rx_dp_dn	1.100s	239.116us	1	1	100.00
V2	phy_config_tx_use_d_se0	usbdev_phy_config_tx_use_d_se0	1.190s	263.262us	1	1	100.00
V2	phy_config_usb_ref_disable	usbdev_phy_config_usb_ref_disable	1.560s	209.998us	50	50	100.00
V2	max_length_out_transaction	usbdev_max_length_out_transaction	1.820s	275.916us	50	50	100.00
		usbdev_stream_len_max	5.870s	1.267ms	50	50	100.00
V2	max_length_in_transaction	usbdev_max_length_in_transaction	1.930s	260.476us	50	50	100.00
V2	min_length_out_transaction	usbdev_min_length_out_transaction	1.660s	236.918us	50	50	100.00
V2	min_length_in_transaction	usbdev_min_length_in_transaction	1.640s	182.898us	50	50	100.00
V2	random_length_out_transaction	usbdev_random_length_out_transaction	1.880s	245.091us	50	50	100.00
V2	random_length_in_transaction	usbdev_random_length_in_transaction	1.870s	251.980us	50	50	100.00
V2	out_stall	usbdev_out_stall	1.710s	192.974us	50	50	100.00
V2	in_stall	usbdev_in_stall	1.550s	203.979us	50	50	100.00
V2	out_iso	usbdev_out_iso	1.820s	235.518us	50	50	100.00
V2	in_iso	usbdev_in_iso	2.250s	232.205us	50	50	100.00
V2	pkt_received	usbdev_pkt_received	1.890s	257.915us	50	50	100.00
V2	pkt_sent	usbdev_pkt_sent	1.730s	234.101us	50	50	100.00
V2	disconnected	usbdev_disconnected	1.580s	195.697us	50	50	100.00
V2	host_lost	usbdev_host_lost	9.870s	4.167ms	1	1	100.00
V2	link_reset	usbdev_link_reset	1.120s	200.941us	1	1	100.00
V2	link_suspend	usbdev_link_suspend	29.780s	9.840ms	50	50	100.00
V2	link_resume	usbdev_link_resume	1.109m	31.920ms	50	50	100.00
V2	av_empty	usbdev_av_empty	1.610s	200.292us	5	5	100.00
V2	rx_full	usbdev_rx_full	2.710s	396.573us	50	50	100.00
V2	av_overflow	usbdev_av_overflow	1.460s	167.069us	5	5	100.00
V2	link_in_err	usbdev_link_in_err	1.770s	225.513us	50	50	100.00
V2	rx_crc_err	usbdev_rx_crc_err	1.630s	185.418us	50	50	100.00
V2	rx_pid_err	usbdev_rx_pid_err	1.600s	212.552us	5	5	100.00
V2	rx_bitstuff_err	usbdev_bitstuff_err	1.700s	242.637us	50	50	100.00
V2	link_out_err	usbdev_link_out_err	1.760s	576.802us	1	1	100.00
V2	enable	usbdev_enable	1.370s	128.462us	50	50	100.00
V2	resume_link_active	usbdev_resume_link_active	58.950s	20.148ms	20	20	100.00
V2	device_address	usbdev_device_address	1.974m	31.122ms	50	50	100.00
V2	invalid_data1_data0_toggle_test	usbdev_invalid_data1_data0_toggle_test	1.710s	556.954us	1	1	100.00
V2	setup_stage	usbdev_setup_stage	1.580s	191.936us	50	50	100.00
V2	endpoint_access	usbdev_endpoint_access	5.280s	1.065ms	50	50	100.00
V2	disable_endpoint	usbdev_disable_endpoint	4.960s	1.254ms	50	50	100.00
V2	endpoint_types	usbdev_endpoint_types	1.083m		188	200	94.00
V2	out_trans_nak	usbdev_out_trans_nak	1.680s	193.454us	50	50	100.00
V2	setup_trans_ignored	usbdev_setup_trans_ignored	1.610s	201.641us	50	50	100.00
V2	nak_trans	usbdev_nak_trans	1.840s	231.160us	50	50	100.00
V2	stall_trans	usbdev_stall_trans	1.670s	224.760us	50	50	100.00
V2	setup_priority_over_stall_response	usbdev_setup_priority_over_stall_response	1.550s	215.827us	5	5	100.00
V2	stall_priority_over_nak	usbdev_stall_priority_over_nak	1.690s	227.006us	50	50	100.00
V2	pending_in_trans	usbdev_pending_in_trans	1.580s	196.769us	50	50	100.00
V2	streaming_test	usbdev_streaming_out	1.731m	3.978ms	50	50	100.00
V2	max_clock_error_untracked	usbdev_freq_hiclk	3.971m	121.183ms	5	5	100.00
		usbdev_freq_loclk	3.126m	87.113ms	5	5	100.00
V2	max_clock_error_tracking	usbdev_freq_hiclk_max	4.379m	112.365ms	5	5	100.00
		usbdev_freq_loclk_max	4.177m	115.042ms	5	5	100.00
V2	max_phase_error	usbdev_freq_phase	4.307m	121.244ms	5	5	100.00
V2	min_inter_pkt_delay	usbdev_min_inter_pkt_delay	1.919m	4.012ms	50	50	100.00
V2	max_inter_pkt_delay	usbdev_max_inter_pkt_delay	2.021m	3.838ms	50	50	100.00
V2	device_timeout_missing_host_handshake	usbdev_timeout_missing_host_handshake	56.200s	8.403ms	50	50	100.00
V2	device_timeout	usbdev_device_timeout	50.530s	5.645ms	50	50	100.00
V2	packet_buffer	usbdev_pkt_buffer	1.120m	21.402ms	50	50	100.00
V2	nak_to_out_trans_when_avbuffer_empty_rxfifo_full	usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full	2.200s	515.556us	1	1	100.00
V2	aon_wake_resume	usbdev_aon_wake_resume	54.360s	30.179ms	50	50	100.00
V2	aon_wake_reset	usbdev_aon_wake_reset	38.700s	20.001ms	50	50	100.00
V2	aon_wake_disconnect	usbdev_aon_wake_disconnect	30.330s	11.722ms	50	50	100.00
V2	invalid_sync	usbdev_invalid_sync	2.656m	5.362ms	50	50	100.00
V2	spurious_pids_ignored	usbdev_spurious_pids_ignored	1.646m	3.622ms	50	50	100.00
V2	low_speed_traffic	usbdev_low_speed_traffic	2.254m	4.424ms	50	50	100.00
V2	rand_bus_resets	usbdev_rand_bus_resets	3.292m	11.061ms	10	10	100.00
V2	rand_disconnects	usbdev_rand_bus_disconnects	1.394m	3.600ms	10	10	100.00
V2	rand_suspends	usbdev_rand_suspends	3.162m	10.078ms	10	10	100.00
V2	max_usb_traffic	usbdev_max_non_iso_usb_traffic	1.684m	3.413ms	25	25	100.00
		usbdev_max_usb_traffic	1.527m	3.349ms	15	15	100.00
V2	stress_usb_traffic	usbdev_stress_usb_traffic	4.068m	9.721ms	10	10	100.00
V2	in_packet_retraction	usbdev_iso_retraction	2.509m	11.792ms	50	50	100.00
V2	data_toggle_restore	usbdev_data_toggle_restore	5.850s	1.217ms	50	50	100.00
V2	setup_priority	usbdev_setup_priority	2.620s	488.864us	5	5	100.00
V2	fifo_resets	usbdev_fifo_rst	4.870s	531.071us	50	50	100.00
V2	tx_rx_disruption	usbdev_tx_rx_disruption	1.083m		483	500	96.60
V2	fifo_levels	usbdev_fifo_levels	1.083m		154	160	96.25
V2	intr_test	usbdev_intr_test	36.602s		46	50	92.00
V2	alert_test	usbdev_alert_test	1.230s	115.950us	50	50	100.00
V2	tl_d_oob_addr_access	usbdev_tl_errors	41.699s		17	20	85.00
V2	tl_d_illegal_access	usbdev_tl_errors	41.699s		17	20	85.00
V2	tl_d_outstanding_access	usbdev_csr_hw_reset	0.870s	97.236us	5	5	100.00
		usbdev_csr_rw	41.558s		15	20	75.00
		usbdev_csr_aliasing	41.572s		4	5	80.00
		usbdev_same_csr_outstanding	41.605s		17	20	85.00
V2	tl_d_partial_access	usbdev_csr_hw_reset	0.870s	97.236us	5	5	100.00
		usbdev_csr_rw	41.558s		15	20	75.00
		usbdev_csr_aliasing	41.572s		4	5	80.00
		usbdev_same_csr_outstanding	41.605s		17	20	85.00
V2		TOTAL			3719	3764	98.80
V2S	tl_intg_err	usbdev_sec_cm	2.550s	512.174us	5	5	100.00
		usbdev_tl_intg_err	41.749s		17	20	85.00
V2S	sec_cm_bus_integrity	usbdev_tl_intg_err	41.749s		17	20	85.00
V2S		TOTAL			22	25	88.00
V3	dpi_config_host	usbdev_dpi_config_host	2.322m	5.131ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	usbdev_stress_all_with_rand_reset	1.080s	65.325us	0	10	0.00
		usbdev_stress_all	0.890s		0	50	0.00
		TOTAL			3848	3965	97.05

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	0	0.00
V1	8	8	5	62.50
V2	86	86	80	93.02
V2S	2	2	1	50.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.38	98.21	96.03	97.44	94.92	98.38	98.21	98.46

Failure Buckets

UVM_WARNING [BDTYP] Cannot create an object of type 'usbdev_stress_all_vseq' because it is not registered with the factory.

has 60 failures:

Test usbdev_stress_all_with_rand_reset has 10 failures.

0.usbdev_stress_all_with_rand_reset.40108272268268594422673533855473192576990844385272406110456850055037063199966
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/0.usbdev_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @  28969421 ps: [BDTYP] Cannot create an object of type 'usbdev_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @  28969421 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.usbdev_stress_all_with_rand_reset.113146460067037704527961049221698276820140803657334252831947051732350741597450
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/1.usbdev_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @  37267894 ps: [BDTYP] Cannot create an object of type 'usbdev_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @  37267894 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 8 more failures.

Test usbdev_stress_all has 50 failures.

0.usbdev_stress_all.111046104410844737126622643467438900611553507482851643001931867371574465129923
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/0.usbdev_stress_all/latest/run.log

  UVM_WARNING @         0 ps: [BDTYP] Cannot create an object of type 'usbdev_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @         0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.usbdev_stress_all.87701496522495095881477388820347192178806842197485023611567113835940612701373
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/1.usbdev_stress_all/latest/run.log

  UVM_WARNING @         0 ps: [BDTYP] Cannot create an object of type 'usbdev_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @         0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 48 more failures.

Job returned non-zero exit code has 56 failures:

Test usbdev_csr_rw has 5 failures.

1.usbdev_csr_rw.106709293763381542519104796459058833143040278716444503453736337616754766591878
Log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/1.usbdev_csr_rw/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 13:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

5.usbdev_csr_rw.9371874313327835579842695703997477045983525528701545049935353191911267669599
Log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/5.usbdev_csr_rw/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 13:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 3 more failures.

Test usbdev_csr_aliasing has 1 failures.

1.usbdev_csr_aliasing.64575516807165307822709262232355180833575692855809931111243922310069628236666
Log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/1.usbdev_csr_aliasing/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 13:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test usbdev_same_csr_outstanding has 3 failures.

1.usbdev_same_csr_outstanding.107061677642661669276251005291364003328660157485852006035719942596916773007294
Log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/1.usbdev_same_csr_outstanding/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 13:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

4.usbdev_same_csr_outstanding.79816836462661378157754695963152591700731922297754937059010717207087321167532
Log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/4.usbdev_same_csr_outstanding/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 13:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 1 more failures.

Test usbdev_csr_mem_rw_with_rand_reset has 3 failures.

1.usbdev_csr_mem_rw_with_rand_reset.98097502057894294147401181038931123724522463015955949127558675453443467083516
Log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/1.usbdev_csr_mem_rw_with_rand_reset/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 13:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

4.usbdev_csr_mem_rw_with_rand_reset.110433063409369608903771775281661686891407084146774563200079313987496000676748
Log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/4.usbdev_csr_mem_rw_with_rand_reset/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 13:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 1 more failures.

Test usbdev_tl_errors has 3 failures.

2.usbdev_tl_errors.48891031583228424438226196149333610764016776159963518666838582965146397815758
Log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/2.usbdev_tl_errors/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 13:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

5.usbdev_tl_errors.100335802200765001942473741353560542856035284370748023750389486267721060689548
Log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/5.usbdev_tl_errors/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 13:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 1 more failures.

... and 5 more tests.

UVM_ERROR (usbdev_scoreboard.sv:261) [scoreboard] Check failed expected_rsp_q.size() > * (* [*] vs * [*]) Unexpected response from DUT; no expectation ready has 1 failures:
- Test usbdev_tx_rx_disruption has 1 failures.
  - 294.usbdev_tx_rx_disruption.82498899889010240718959476648166168351245869245198079388444530776752808413722
    Line 172, in log /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/294.usbdev_tx_rx_disruption/latest/run.log
```
  UVM_ERROR @ 181539812 ps: (usbdev_scoreboard.sv:261) [uvm_test_top.env.scoreboard] Check failed expected_rsp_q.size() > 0 (0 [0x0] vs 0 [0x0]) Unexpected response from DUT; no expectation ready
  UVM_INFO @ 181539812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```