USBDEV Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.980s 242.235us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.380s 308.793us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.280s 87.585us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 4.500s 1.337ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.360s 379.445us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.310s 122.247us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.280s 87.585us 20 20 100.00
usbdev_csr_aliasing 3.360s 379.445us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.520s 703.427us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 1.870s 77.689us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.850s 214.652us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 3.110s 478.213us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 1.280s 106.523us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.760s 251.891us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.218m 23.448ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.850s 336.353us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 1.450s 200.348us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.990s 311.399us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.860s 281.911us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.620s 216.113us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.500s 196.957us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.560s 197.560us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.710s 185.136us 50 50 100.00
usbdev_stream_len_max 5.750s 1.235ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.970s 241.551us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 1.590s 175.938us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.790s 236.687us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.760s 239.730us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.830s 262.997us 50 50 100.00
V2 out_stall usbdev_out_stall 1.680s 214.597us 50 50 100.00
V2 in_stall usbdev_in_stall 1.510s 160.725us 50 50 100.00
V2 out_iso usbdev_out_iso 1.680s 240.592us 50 50 100.00
V2 in_iso usbdev_in_iso 2.330s 259.242us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.840s 233.150us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.840s 314.027us 50 50 100.00
V2 disconnected usbdev_disconnected 1.600s 208.170us 50 50 100.00
V2 host_lost usbdev_host_lost 10.300s 4.171ms 1 1 100.00
V2 link_reset usbdev_link_reset 1.450s 165.577us 1 1 100.00
V2 link_suspend usbdev_link_suspend 26.790s 9.189ms 50 50 100.00
V2 link_resume usbdev_link_resume 1.234m 31.225ms 50 50 100.00
V2 av_empty usbdev_av_empty 1.460s 163.575us 5 5 100.00
V2 rx_full usbdev_rx_full 2.510s 393.009us 50 50 100.00
V2 av_overflow usbdev_av_overflow 1.430s 159.455us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.980s 309.814us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.650s 172.070us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 1.460s 184.489us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 1.550s 198.882us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.990s 547.420us 1 1 100.00
V2 enable usbdev_enable 1.200s 87.291us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 54.560s 20.217ms 20 20 100.00
V2 device_address usbdev_device_address 2.210m 47.161ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 2.140s 459.004us 1 1 100.00
V2 setup_stage usbdev_setup_stage 1.600s 210.141us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 5.340s 1.090ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 5.300s 1.453ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 3.090s 642.667us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.740s 225.302us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.570s 232.346us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.850s 262.331us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.610s 224.576us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 2.020s 324.190us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.660s 220.724us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 1.580s 178.657us 50 50 100.00
V2 streaming_test usbdev_streaming_out 2.190m 4.170ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 5.584m 117.200ms 5 5 100.00
usbdev_freq_loclk 3.108m 93.137ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 5.146m 118.331ms 5 5 100.00
usbdev_freq_loclk_max 3.576m 114.056ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 3.352m 114.154ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 1.873m 4.259ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 2.058m 3.958ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 42.960s 5.530ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 1.010m 8.358ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.218m 23.448ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 2.140s 502.218us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 1.228m 30.610ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 51.600s 18.408ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 30.160s 10.586ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.656m 5.530ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.716m 3.573ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.630m 6.125ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 3.204m 6.599ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 3.769m 11.691ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 6.737m 15.022ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.509m 3.352ms 25 25 100.00
usbdev_max_usb_traffic 1.449m 2.646ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 4.107m 9.012ms 10 10 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.598m 12.723ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 6.030s 1.179ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 2.670s 477.688us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 5.150s 556.412us 50 50 100.00
V2 tx_rx_disruption usbdev_tx_rx_disruption 3.250s 664.705us 500 500 100.00
V2 fifo_levels usbdev_fifo_levels 2.080s 284.885us 160 160 100.00
V2 intr_test usbdev_intr_test 0.920s 56.785us 50 50 100.00
V2 alert_test usbdev_alert_test 1.160s 107.789us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.260s 350.379us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.260s 350.379us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.380s 308.793us 5 5 100.00
usbdev_csr_rw 1.280s 87.585us 20 20 100.00
usbdev_csr_aliasing 3.360s 379.445us 5 5 100.00
usbdev_same_csr_outstanding 1.990s 331.209us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.380s 308.793us 5 5 100.00
usbdev_csr_rw 1.280s 87.585us 20 20 100.00
usbdev_csr_aliasing 3.360s 379.445us 5 5 100.00
usbdev_same_csr_outstanding 1.990s 331.209us 20 20 100.00
V2 TOTAL 3764 3764 100.00
V2S tl_intg_err usbdev_sec_cm 3.500s 980.694us 5 5 100.00
usbdev_tl_intg_err 5.270s 2.045ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.270s 2.045ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 40.360s 5.123ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 1.170s 100.061us 0 10 0.00
usbdev_stress_all 0.910s 0 50 0.00
TOTAL 3905 3965 98.49

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 86 86 86 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.17 98.22 96.03 97.44 93.22 98.38 98.17 98.73

Failure Buckets

Past Results