USBDEV Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 2.220s 249.979us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.360s 144.701us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.460s 89.989us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.470s 1.748ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 2.300s 208.688us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.440s 132.515us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.460s 89.989us 20 20 100.00
usbdev_csr_aliasing 2.300s 208.688us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.640s 733.749us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.680s 218.393us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 2.040s 282.922us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 3.550s 565.045us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 1.440s 75.967us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.780s 182.126us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.378m 22.257ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 2.250s 306.424us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 1.290s 188.036us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 2.130s 241.266us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 2.060s 247.981us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.880s 258.558us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.930s 259.185us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.760s 176.974us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.970s 208.622us 50 50 100.00
usbdev_stream_len_max 7.100s 1.422ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 2.110s 281.354us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 1.750s 156.733us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.710s 193.746us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.880s 164.711us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.930s 222.166us 50 50 100.00
V2 out_stall usbdev_out_stall 1.840s 207.512us 50 50 100.00
V2 in_stall usbdev_in_stall 1.740s 138.384us 50 50 100.00
V2 out_iso usbdev_out_iso 2.120s 228.015us 50 50 100.00
V2 in_iso usbdev_in_iso 2.220s 239.866us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.800s 196.397us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 2.010s 247.581us 50 50 100.00
V2 disconnected usbdev_disconnected 1.630s 164.485us 50 50 100.00
V2 host_lost usbdev_host_lost 12.440s 4.200ms 1 1 100.00
V2 link_reset usbdev_link_reset 1.490s 182.570us 1 1 100.00
V2 link_suspend usbdev_link_suspend 33.440s 9.795ms 50 50 100.00
V2 link_resume usbdev_link_resume 1.696m 26.138ms 50 50 100.00
V2 av_empty usbdev_av_empty 1.850s 220.044us 5 5 100.00
V2 rx_full usbdev_rx_full 2.920s 359.920us 50 50 100.00
V2 av_overflow usbdev_av_overflow 1.480s 167.435us 5 5 100.00
V2 link_in_err usbdev_link_in_err 2.050s 256.037us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.650s 141.567us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 1.900s 193.077us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 1.720s 170.674us 50 50 100.00
V2 link_out_err usbdev_link_out_err 2.520s 453.586us 1 1 100.00
V2 enable usbdev_enable 1.270s 85.439us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 1.224m 20.175ms 20 20 100.00
V2 device_address usbdev_device_address 1.961m 44.616ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.710s 496.034us 1 1 100.00
V2 setup_stage usbdev_setup_stage 1.710s 204.856us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 6.280s 1.074ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 4.900s 1.165ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 3.520s 641.520us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 2.040s 227.751us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.750s 151.315us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.930s 256.336us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.890s 176.047us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 2.150s 309.029us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.820s 220.862us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 1.690s 240.705us 50 50 100.00
V2 streaming_test usbdev_streaming_out 2.462m 4.299ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 4.892m 111.177ms 5 5 100.00
usbdev_freq_loclk 4.434m 109.110ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 4.544m 121.271ms 5 5 100.00
usbdev_freq_loclk_max 4.158m 103.998ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 4.191m 106.120ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 1.653m 3.951ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 2.023m 4.021ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 45.940s 3.882ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 57.450s 7.360ms 49 50 98.00
V2 packet_buffer usbdev_pkt_buffer 1.378m 22.257ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 2.600s 496.121us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 1.262m 30.992ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 1.056m 20.947ms 49 50 98.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 38.320s 11.873ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.494m 4.908ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.673m 2.866ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.375m 5.322ms 49 50 98.00
V2 rand_bus_resets usbdev_rand_bus_resets 3.715m 7.380ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 3.306m 10.510ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 3.561m 10.272ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.382m 3.016ms 25 25 100.00
usbdev_max_usb_traffic 1.762m 3.670ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 7.470m 14.993ms 10 10 100.00
V2 in_packet_retraction usbdev_iso_retraction 3.245m 11.713ms 49 50 98.00
V2 data_toggle_restore usbdev_data_toggle_restore 5.840s 993.388us 50 50 100.00
V2 setup_priority usbdev_setup_priority 3.100s 434.064us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 4.860s 480.363us 50 50 100.00
V2 tx_rx_disruption usbdev_tx_rx_disruption 3.810s 566.970us 500 500 100.00
V2 fifo_levels usbdev_fifo_levels 2.320s 265.858us 160 160 100.00
V2 intr_test usbdev_intr_test 1.040s 57.643us 50 50 100.00
V2 alert_test usbdev_alert_test 1.280s 50.667us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.480s 339.369us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.480s 339.369us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.360s 144.701us 5 5 100.00
usbdev_csr_rw 1.460s 89.989us 20 20 100.00
usbdev_csr_aliasing 2.300s 208.688us 5 5 100.00
usbdev_same_csr_outstanding 1.790s 252.154us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.360s 144.701us 5 5 100.00
usbdev_csr_rw 1.460s 89.989us 20 20 100.00
usbdev_csr_aliasing 2.300s 208.688us 5 5 100.00
usbdev_same_csr_outstanding 1.790s 252.154us 20 20 100.00
V2 TOTAL 3760 3764 99.89
V2S tl_intg_err usbdev_sec_cm 4.740s 1.826ms 5 5 100.00
usbdev_tl_intg_err 5.530s 1.184ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.530s 1.184ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 42.230s 5.158ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 1.160s 73.553us 0 10 0.00
usbdev_stress_all 1.010s 0 50 0.00
TOTAL 3901 3965 98.39

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 86 86 82 95.35
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.41 98.21 96.12 97.44 94.92 98.38 98.21 98.55

Failure Buckets

Past Results