e3fb01b5e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 15.246m | 5.426ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 15.246m | 5.426ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 16.122m | 5.929ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 18.440m | 5.606ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 15.223m | 5.063ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 1.015h | 23.402ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 1.095h | 23.584ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 30.140m | 13.964ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 7.051m | 3.574ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 7.051m | 3.574ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 7.051m | 3.574ms | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_flash | 3.885m | 2.576ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.269m | 2.402ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 3.705m | 2.516ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.296m | 3.013ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 33.051m | 9.090ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 5.937m | 6.089ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 9.259m | 5.272ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 57.788m | 36.882ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.990h | 70.523ms | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 6.680m | 7.277ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.990h | 70.523ms | 4 | 5 | 80.00 |
| chip_csr_rw | 9.259m | 5.272ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 9.530s | 216.198us | 100 | 100 | 100.00 |
| V1 | TOTAL | 222 | 223 | 99.55 | |||
| V2 | chip_sw_spi_device_tx_rx | chip_sw_spi_device_tx_rx | 8.232m | 3.845ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 3.133h | 71.731ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 11.975m | 7.430ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 10.149m | 4.868ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 6.502m | 3.797ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 5.179m | 3.237ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 10.924m | 3.985ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 14.009m | 4.447ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 10.014m | 4.338ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 9.858m | 4.262ms | 3 | 3 | 100.00 |
| V2 | chip_sw_usbdev_dpi | chip_sw_usbdev_dpi | 23.723m | 7.216ms | 1 | 1 | 100.00 |
| V2 | chip_pin_mux | chip_padctrl_attributes | 4.840m | 4.323ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 4.840m | 4.323ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 6.186m | 3.514ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 9.315m | 5.990ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 4.321m | 3.560ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 22.547m | 14.504ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 16.686m | 9.776ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 8.840m | 6.460ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 19.271m | 10.492ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.025m | 3.151ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 22.101m | 9.155ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 13.204m | 5.597ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 13.204m | 5.597ms | 6 | 6 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 29.398m | 16.871ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 25.945m | 13.440ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 7.794m | 4.517ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 7.604m | 3.989ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 9.395m | 5.231ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 8.840m | 6.460ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 7.221m | 15.460ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 4.385m | 3.468ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 7.239m | 3.702ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 6.416m | 5.000ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 7.239m | 3.702ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 12.289m | 4.791ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 12.228m | 8.163ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 12.228m | 8.163ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 7.057m | 7.598ms | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs | 21.068m | 8.607ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.055m | 3.338ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 9.640m | 5.538ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 5.391m | 2.364ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.978m | 2.440ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.433m | 2.970ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 7.412m | 4.733ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 8.554m | 5.238ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 6.270m | 4.054ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 7.521m | 4.808ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 25.014m | 11.214ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_lc | 9.089m | 6.285ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 9.278m | 3.605ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 9.341m | 4.436ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 8.715m | 4.043ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 9.447m | 4.852ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 9.528m | 4.510ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 10.125m | 4.366ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 9.089m | 6.285ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 9.278m | 3.605ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 9.341m | 4.436ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 8.715m | 4.043ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 9.447m | 4.852ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 9.528m | 4.510ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 10.125m | 4.366ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 16.639m | 5.013ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.171m | 6.290ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 52.859m | 21.574ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.279m | 3.224ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 19.408m | 5.541ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.507m | 2.813ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 9.956m | 4.440ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.535m | 2.533ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.652m | 3.882ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.302m | 2.453ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 3.364m | 3.128ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 18.829m | 6.074ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 20.733m | 7.431ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.024h | 29.053ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.492m | 3.417ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.770m | 3.372ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 8.053m | 3.947ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 4.653m | 3.334ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 8.082m | 5.852ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 31.672m | 19.850ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 47.001m | 18.670ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 16.275m | 7.392ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.429m | 4.844ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 7.018m | 3.081ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 13.790m | 5.138ms | 100 | 100 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 6.471m | 6.536ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 26.199m | 19.431ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 8.224m | 6.803ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 12.228m | 8.163ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 22.618m | 19.652ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 35.309m | 21.991ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 29.628m | 13.489ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 9.110m | 4.904ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 6.471m | 6.536ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 8.466m | 4.174ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 44.309m | 30.133ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 8.971m | 6.604ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 10.663m | 5.881ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 59.947m | 35.960ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 18.994m | 8.692ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 37.572m | 21.239ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 6.052m | 3.258ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 13.790m | 5.138ms | 100 | 100 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 6.416m | 5.000ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 7.794m | 4.517ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 12.883m | 5.645ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 7.391m | 3.520ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 29.438m | 11.270ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 5.411m | 2.763ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 13.790m | 5.138ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 7.373m | 3.564ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 9.827m | 5.377ms | 3 | 3 | 100.00 |
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 13.790m | 5.138ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 21.068m | 8.607ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 5.434m | 3.657ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 29.438m | 11.270ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 7.712m | 4.134ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.240m | 4.142ms | 90 | 90 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 27.092m | 12.658ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 26.830m | 7.728ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 26.092m | 7.993ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.161h | 254.777ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 9.827m | 5.377ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 22.547m | 14.504ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 8.840m | 6.460ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 19.271m | 10.492ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 5.499m | 3.132ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 16.723m | 13.252ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 16.723m | 13.252ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 16.723m | 13.252ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 10.507m | 5.695ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 9.624m | 5.488ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.288h | 43.121ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.316m | 4.949ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 20.988m | 7.879ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 20.694m | 9.371ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 20.362m | 8.464ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 16.723m | 13.252ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 7.598m | 3.911ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 11.832m | 8.570ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 16.068m | 10.069ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 5.677m | 8.840ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 9.089m | 6.285ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 9.278m | 3.605ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 9.341m | 4.436ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 8.715m | 4.043ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 9.447m | 4.852ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 9.528m | 4.510ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 10.125m | 4.366ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 22.547m | 14.504ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 8.840m | 6.460ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 19.271m | 10.492ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 7.221m | 15.460ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 5.337m | 2.907ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 5.459m | 3.084ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 10.978m | 4.376ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 29.540m | 22.384ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_sysrst_ctrl_reset | 29.540m | 22.384ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 29.540m | 22.384ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 47.055m | 19.826ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 47.055m | 19.826ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 9.550m | 6.409ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.888m | 18.682ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.888m | 18.682ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.888m | 18.682ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.117m | 3.468ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.279m | 3.224ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.066m | 2.639ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 5.391m | 2.364ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 10.283m | 5.752ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 6.521m | 3.158ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.507m | 2.813ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.978m | 2.440ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.127m | 2.229ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.377m | 3.148ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.535m | 2.533ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 7.598m | 3.911ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 16.723m | 13.252ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.637m | 2.305ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.059m | 2.548ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.433m | 2.970ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.628m | 3.202ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 24.146m | 7.191ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 11.349m | 4.700ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 3.233m | 2.006ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 24.146m | 7.191ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 10.344m | 4.928ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 11.613m | 5.842ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 4.628m | 2.823ms | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 45.559m | 12.071ms | 3 | 3 | 100.00 |
| chip_sw_edn_entropy_reqs | 14.836m | 4.702ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 7.598m | 3.911ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 9.956m | 4.440ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 9.696m | 5.279ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 10.283m | 5.752ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 40.070m | 9.547ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 55.845m | 20.027ms | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 52.859m | 21.574ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 9.640m | 5.538ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 9.640m | 5.538ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 9.640m | 5.538ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 8.000m | 2.921ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 11.832m | 8.570ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 11.832m | 8.570ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 10.935m | 5.533ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.652m | 3.882ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 25.584m | 12.867ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 16.068m | 10.069ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 13.790m | 5.138ms | 100 | 100 | 100.00 |
| chip_sw_data_integrity_escalation | 13.204m | 5.597ms | 6 | 6 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 16.723m | 13.252ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 34.351m | 22.622ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.000m | 2.921ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 7.598m | 3.911ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 10.935m | 5.533ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.905m | 2.415ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 34.351m | 22.622ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.000m | 2.921ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 7.598m | 3.911ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 10.935m | 5.533ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.905m | 2.415ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 16.723m | 13.252ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 8.482m | 4.914ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 5.499m | 3.132ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.316m | 4.949ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 20.988m | 7.879ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 20.694m | 9.371ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 20.362m | 8.464ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 16.723m | 13.252ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 5.677m | 8.840ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 5.677m | 8.840ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_init | chip_sw_flash_init | 34.351m | 22.622ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 18.931m | 5.366ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.171m | 6.290ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 15.639m | 5.088ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 16.639m | 5.013ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.288h | 43.121ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 34.351m | 22.622ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.739m | 3.948ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 7.598m | 3.911ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.624m | 5.488ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.288h | 43.121ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.624m | 5.488ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.624m | 5.488ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 9.624m | 5.488ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.624m | 5.488ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 13.790m | 5.138ms | 100 | 100 | 100.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 5.677m | 8.840ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 16.999m | 5.783ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 12.702m | 5.418ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 16.275m | 7.392ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 10.550m | 10.754ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 16.639m | 5.013ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.171m | 6.290ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 52.859m | 21.574ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.279m | 3.224ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 19.408m | 5.541ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.507m | 2.813ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 9.956m | 4.440ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.535m | 2.533ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.652m | 3.882ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.302m | 2.453ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 4.864m | 3.307ms | 1 | 1 | 100.00 |
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 28.324m | 14.352ms | 5 | 5 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 28.324m | 14.352ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.656m | 4.391ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.363m | 2.831ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.656m | 4.391ms | 3 | 3 | 100.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 15.296m | 5.195ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 15.667m | 4.807ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 4.842m | 2.576ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 4.905m | 2.415ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 12.883m | 5.645ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 12.883m | 5.645ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.079m | 2.808ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.622m | 3.023ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.586m | 2.817ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.275m | 2.905ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.146m | 2.915ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 7.474m | 3.521ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 4.969m | 3.010ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 7.434m | 3.158ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 4.819m | 2.559ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 33.019m | 11.183ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 4.270m | 3.013ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 6.416m | 5.000ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 8.308m | 4.494ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.242m | 2.708ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 5.496m | 3.615ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.186m | 2.792ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.211m | 3.513ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 5.885m | 3.555ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 9.787m | 5.157ms | 3 | 3 | 100.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 33.051m | 9.090ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.133h | 71.731ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 31.223m | 8.780ms | 3 | 3 | 100.00 |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 5.370m | 3.501ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 1.915m | 2.667ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 3.310m | 3.285ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 2.770m | 3.501ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 34.524m | 21.146ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 7.221m | 15.460ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.377h | 47.104ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.364h | 51.201ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 16.241m | 11.457ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.367h | 48.511ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 34.524m | 21.146ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 4.559m | 4.796ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 5.161m | 3.811ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_96mhz | 6.748m | 4.875ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 5.295h | 116.726ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 13.572m | 4.577ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 9.689m | 10.839ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.716h | 59.502ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.070h | 64.844ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 7.624m | 4.813ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 7.624m | 4.813ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.990h | 70.523ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 56.258m | 28.372ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 5.937m | 6.089ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 9.259m | 5.272ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.990h | 70.523ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 56.258m | 28.372ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 5.937m | 6.089ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 9.259m | 5.272ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.461m | 2.507ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 6.840s | 50.077us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 1.945m | 10.369ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 1.978m | 7.066ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 54.170s | 544.816us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 21.482m | 106.924ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 21.143m | 64.764ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.017m | 1.471ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 55.340s | 1.368ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.661m | 2.670ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 55.340s | 1.368ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.323m | 3.642ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 48.043m | 158.873ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.246m | 2.443ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 12.690m | 20.676ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 14.287m | 23.307ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 23.959m | 12.472ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 17.192m | 21.299ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 31.223m | 8.780ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 44.169m | 24.640ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 30.496m | 8.542ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 3.820h | 77.361ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 33.056m | 9.029ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 31.508m | 8.649ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 28.007m | 9.040ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 24.701m | 8.282ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 3.788h | 77.795ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 35.383m | 9.213ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 30.988m | 9.039ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 36.138m | 8.746ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 29.936m | 8.822ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 7.150h | 151.643ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 47.082m | 11.472ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 39.060m | 11.911ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 41.878m | 11.336ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 46.199m | 11.634ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 7.456h | 152.612ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 39.770m | 11.413ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 30.656m | 11.689ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 40.320m | 12.024ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 44.886m | 11.749ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 3.876h | 77.886ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 32.932m | 8.779ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 24.962m | 8.847ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 30.492m | 8.952ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 27.200m | 8.952ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 3.928h | 78.066ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 29.645m | 7.816ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 30.694m | 7.911ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 29.607m | 8.519ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 26.780m | 8.129ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_mod_exp | rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 3.872h | 76.801ms | 3 | 3 | 100.00 |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 3.809h | 76.318ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 34.935m | 8.867ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 30.670m | 8.757ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 31.506m | 8.263ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 34.702m | 8.453ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 35.923m | 8.965ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 29.293m | 8.807ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 31.887m | 8.071ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 31.455m | 8.428ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 3.793h | 77.305ms | 0 | 3 | 0.00 |
| rom_e2e_asm_init_dev | 30.688m | 8.700ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod | 29.714m | 8.463ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod_end | 29.447m | 8.938ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_rma | 33.026m | 8.681ms | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 30.623m | 8.307ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 32.533m | 9.078ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 33.613m | 8.198ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 35.991m | 10.343ms | 3 | 3 | 100.00 |
| V2 | TOTAL | 2636 | 2651 | 99.43 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 4.946m | 2.596ms | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 4.303m | 3.365ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 6 | 6 | 100.00 | |||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_usb_fs_tx_rx | chip_sw_usbdev_stream | 44.538m | 12.866ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usb_vbus | chip_sw_usb_vbus | 0 | 0 | -- | ||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_sof | chip_usb_sof | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_usb_enumeration | chip_usb_enumeration | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 21.360m | 10.703ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 30.836m | 11.247ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 31.266m | 10.410ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 9.182m | 4.867ms | 3 | 3 | 100.00 |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 13.790m | 5.138ms | 100 | 100 | 100.00 |
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 3.636m | 3.119ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 10.088m | 5.171ms | 1 | 1 | 100.00 |
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.470s | 0 | 1 | 0.00 | |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 33.543m | 8.625ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 21.360m | 10.703ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 30.836m | 11.247ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 31.266m | 10.410ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 49.928m | 44.865ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 50.051m | 32.226ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 46.132m | 44.902ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | TOTAL | 17 | 18 | 94.44 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 11.435m | 5.638ms | 3 | 3 | 100.00 | |
| TOTAL | 2884 | 2901 | 99.41 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 19 | 19 | 18 | 94.74 |
| V2 | 270 | 270 | 265 | 98.15 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 26 | 12 | 11 | 42.31 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.60 | 95.57 | 93.89 | 98.10 | -- | 94.50 | 97.93 | 99.62 |
UVM_ERROR @ * us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[*] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (* [*] vs * [*]) has 15 failures:
0.rom_e2e_asm_init_test_unlocked0.1903668947
Line 1099, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log
UVM_ERROR @ 77504.915112 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 77504.915112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_test_unlocked0.4056342336
Line 1096, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest/run.log
UVM_ERROR @ 77725.772840 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 77725.772840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_dev.3684831478
Line 1102, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log
UVM_ERROR @ 8700.293340 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8700.293340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_dev.2109168119
Line 1098, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log
UVM_ERROR @ 9300.911524 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 9300.911524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_prod.3552790485
Line 1098, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log
UVM_ERROR @ 8463.375584 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8463.375584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_prod.990182875
Line 1094, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest/run.log
UVM_ERROR @ 8988.966808 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8988.966808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_prod_end.1768683567
Line 1101, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log
UVM_ERROR @ 8937.592930 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8937.592930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_prod_end.3050583314
Line 1095, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest/run.log
UVM_ERROR @ 8601.858072 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8601.858072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_rma.1569310946
Line 1103, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log
UVM_ERROR @ 8681.499760 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8681.499760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_rma.734138729
Line 1098, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest/run.log
UVM_ERROR @ 8586.052180 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8586.052180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (uart_logger.sv:25) [m_logger] Check failed (!logs_output_fd) Failed to open log for writing has 1 failures:
0.chip_sw_coremark.4185099089
Line 1043, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
UVM_FATAL @ 0.000000 us: (uart_logger.sv:25) [uvm_test_top.env.m_uart_agent0.m_logger] Check failed (!logs_output_fd) Failed to open uvm_test_top.env.m_uart_agent0.m_logger.log for writing
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
4.chip_csr_aliasing.3460417905
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_csr_aliasing/latest/run.log
Job ID: smart:c7b45708-7a9e-42df-a454-b93f4422e666