| T352 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.3300954415 |
|
|
Mar 07 04:03:44 PM PST 24 |
Mar 07 04:17:08 PM PST 24 |
4614529122 ps |
| T21 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3863338886 |
|
|
Mar 07 03:54:25 PM PST 24 |
Mar 07 04:46:41 PM PST 24 |
20289172937 ps |
| T17 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2263387948 |
|
|
Mar 07 03:41:04 PM PST 24 |
Mar 07 05:32:40 PM PST 24 |
30923076232 ps |
| T897 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2634464582 |
|
|
Mar 07 03:55:45 PM PST 24 |
Mar 07 04:01:21 PM PST 24 |
3131540889 ps |
| T649 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.363840989 |
|
|
Mar 07 04:04:47 PM PST 24 |
Mar 07 04:11:42 PM PST 24 |
4111300448 ps |
| T898 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2844161313 |
|
|
Mar 07 03:57:47 PM PST 24 |
Mar 07 04:16:13 PM PST 24 |
7626730980 ps |
| T899 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2644599551 |
|
|
Mar 07 03:38:39 PM PST 24 |
Mar 07 03:41:56 PM PST 24 |
2455822736 ps |
| T900 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.1992305420 |
|
|
Mar 07 04:03:39 PM PST 24 |
Mar 07 04:38:49 PM PST 24 |
8574108302 ps |
| T224 |
/workspace/coverage/default/2.chip_sw_flash_init.424945189 |
|
|
Mar 07 03:53:02 PM PST 24 |
Mar 07 04:24:21 PM PST 24 |
24435771852 ps |
| T901 |
/workspace/coverage/default/0.chip_sw_aes_idle.2173278870 |
|
|
Mar 07 03:39:02 PM PST 24 |
Mar 07 03:43:29 PM PST 24 |
2426788792 ps |
| T375 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3680131253 |
|
|
Mar 07 03:45:08 PM PST 24 |
Mar 07 04:31:27 PM PST 24 |
10129082296 ps |
| T278 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2513790706 |
|
|
Mar 07 03:46:05 PM PST 24 |
Mar 07 03:58:59 PM PST 24 |
5490581220 ps |
| T186 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1026127147 |
|
|
Mar 07 03:38:51 PM PST 24 |
Mar 07 03:50:10 PM PST 24 |
4242185256 ps |
| T209 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2725512369 |
|
|
Mar 07 03:41:14 PM PST 24 |
Mar 07 03:49:49 PM PST 24 |
4817741440 ps |
| T675 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.83632071 |
|
|
Mar 07 03:57:23 PM PST 24 |
Mar 07 04:06:05 PM PST 24 |
3215234978 ps |
| T672 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2264906427 |
|
|
Mar 07 04:08:47 PM PST 24 |
Mar 07 04:14:58 PM PST 24 |
3409988726 ps |
| T165 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4251011563 |
|
|
Mar 07 03:37:16 PM PST 24 |
Mar 07 03:43:49 PM PST 24 |
4897289400 ps |
| T902 |
/workspace/coverage/default/2.chip_sw_example_rom.3065243452 |
|
|
Mar 07 03:50:42 PM PST 24 |
Mar 07 03:52:34 PM PST 24 |
2725667098 ps |
| T903 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.3340600 |
|
|
Mar 07 03:38:50 PM PST 24 |
Mar 07 03:42:58 PM PST 24 |
2415395880 ps |
| T142 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2903175416 |
|
|
Mar 07 03:43:32 PM PST 24 |
Mar 07 03:47:49 PM PST 24 |
3090967726 ps |
| T647 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3395909058 |
|
|
Mar 07 03:50:28 PM PST 24 |
Mar 07 04:24:06 PM PST 24 |
9658733162 ps |
| T904 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3736017288 |
|
|
Mar 07 03:43:06 PM PST 24 |
Mar 07 03:57:57 PM PST 24 |
10180392430 ps |
| T667 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2039538793 |
|
|
Mar 07 04:04:47 PM PST 24 |
Mar 07 04:12:16 PM PST 24 |
3948944670 ps |
| T654 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.2705195045 |
|
|
Mar 07 04:01:12 PM PST 24 |
Mar 07 04:02:57 PM PST 24 |
1952425519 ps |
| T161 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1948605988 |
|
|
Mar 07 04:03:40 PM PST 24 |
Mar 07 04:18:51 PM PST 24 |
6098808330 ps |
| T678 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.661344323 |
|
|
Mar 07 04:07:29 PM PST 24 |
Mar 07 04:19:30 PM PST 24 |
5657774050 ps |
| T343 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3375956312 |
|
|
Mar 07 03:58:08 PM PST 24 |
Mar 07 04:03:15 PM PST 24 |
3429037446 ps |
| T905 |
/workspace/coverage/default/2.rom_keymgr_functest.477971623 |
|
|
Mar 07 04:00:10 PM PST 24 |
Mar 07 04:09:16 PM PST 24 |
4752791464 ps |
| T906 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3694615569 |
|
|
Mar 07 03:39:30 PM PST 24 |
Mar 07 03:44:31 PM PST 24 |
3074426448 ps |
| T14 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1155580327 |
|
|
Mar 07 03:37:20 PM PST 24 |
Mar 07 03:43:58 PM PST 24 |
3836481184 ps |
| T354 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.742349268 |
|
|
Mar 07 03:41:00 PM PST 24 |
Mar 07 03:47:33 PM PST 24 |
3489646640 ps |
| T394 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2006836176 |
|
|
Mar 07 04:01:03 PM PST 24 |
Mar 07 04:12:10 PM PST 24 |
4766046436 ps |
| T365 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.136761288 |
|
|
Mar 07 04:02:31 PM PST 24 |
Mar 07 04:09:40 PM PST 24 |
3306316650 ps |
| T369 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.2229660284 |
|
|
Mar 07 03:38:39 PM PST 24 |
Mar 07 03:48:05 PM PST 24 |
4468540806 ps |
| T370 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.4087844828 |
|
|
Mar 07 03:49:19 PM PST 24 |
Mar 07 04:02:09 PM PST 24 |
5074047814 ps |
| T213 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.57220504 |
|
|
Mar 07 03:43:13 PM PST 24 |
Mar 07 03:50:56 PM PST 24 |
4330229859 ps |
| T371 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1673818624 |
|
|
Mar 07 04:05:13 PM PST 24 |
Mar 07 04:23:28 PM PST 24 |
5033928520 ps |
| T372 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1616778709 |
|
|
Mar 07 03:54:44 PM PST 24 |
Mar 07 04:49:55 PM PST 24 |
16566029404 ps |
| T373 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.4166126323 |
|
|
Mar 07 03:42:48 PM PST 24 |
Mar 07 04:24:03 PM PST 24 |
8436312100 ps |
| T113 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1347666263 |
|
|
Mar 07 04:08:14 PM PST 24 |
Mar 07 04:13:29 PM PST 24 |
3628008648 ps |
| T263 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2563316586 |
|
|
Mar 07 03:45:27 PM PST 24 |
Mar 07 03:54:42 PM PST 24 |
8880034011 ps |
| T374 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2074382302 |
|
|
Mar 07 03:49:07 PM PST 24 |
Mar 07 03:54:13 PM PST 24 |
3652388196 ps |
| T665 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1015094621 |
|
|
Mar 07 04:08:27 PM PST 24 |
Mar 07 04:14:45 PM PST 24 |
3863670604 ps |
| T202 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1425996734 |
|
|
Mar 07 03:54:24 PM PST 24 |
Mar 07 04:23:41 PM PST 24 |
8398080264 ps |
| T907 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2339781749 |
|
|
Mar 07 03:50:36 PM PST 24 |
Mar 07 03:55:15 PM PST 24 |
2908035580 ps |
| T908 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3515690224 |
|
|
Mar 07 03:38:17 PM PST 24 |
Mar 07 03:43:07 PM PST 24 |
2973346536 ps |
| T909 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3224166631 |
|
|
Mar 07 03:56:41 PM PST 24 |
Mar 07 04:01:36 PM PST 24 |
2197899256 ps |
| T223 |
/workspace/coverage/default/1.chip_sw_flash_init.259086031 |
|
|
Mar 07 03:40:15 PM PST 24 |
Mar 07 04:19:54 PM PST 24 |
22769182220 ps |
| T324 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3817394495 |
|
|
Mar 07 03:55:01 PM PST 24 |
Mar 07 04:10:30 PM PST 24 |
5048742178 ps |
| T655 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.616008747 |
|
|
Mar 07 03:44:41 PM PST 24 |
Mar 07 03:46:09 PM PST 24 |
2322803706 ps |
| T910 |
/workspace/coverage/default/2.rom_e2e_static_critical.736409773 |
|
|
Mar 07 04:02:48 PM PST 24 |
Mar 07 04:41:30 PM PST 24 |
11143144460 ps |
| T313 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1016452875 |
|
|
Mar 07 03:37:20 PM PST 24 |
Mar 07 03:50:44 PM PST 24 |
4108258577 ps |
| T742 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3971511184 |
|
|
Mar 07 04:09:17 PM PST 24 |
Mar 07 04:15:31 PM PST 24 |
3594201054 ps |
| T314 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.517735323 |
|
|
Mar 07 03:39:05 PM PST 24 |
Mar 07 03:49:22 PM PST 24 |
4461619300 ps |
| T668 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1476145862 |
|
|
Mar 07 04:03:23 PM PST 24 |
Mar 07 04:11:01 PM PST 24 |
3181252472 ps |
| T643 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2408534510 |
|
|
Mar 07 04:04:16 PM PST 24 |
Mar 07 04:13:34 PM PST 24 |
5057086430 ps |
| T237 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2914035525 |
|
|
Mar 07 03:42:28 PM PST 24 |
Mar 07 04:15:42 PM PST 24 |
12885964800 ps |
| T18 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.934543373 |
|
|
Mar 07 03:40:36 PM PST 24 |
Mar 07 03:46:43 PM PST 24 |
2964606818 ps |
| T23 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.214198757 |
|
|
Mar 07 04:00:01 PM PST 24 |
Mar 07 04:03:55 PM PST 24 |
2635084641 ps |
| T911 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2446297779 |
|
|
Mar 07 03:39:34 PM PST 24 |
Mar 07 03:46:09 PM PST 24 |
4972123246 ps |
| T912 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2865942387 |
|
|
Mar 07 03:51:53 PM PST 24 |
Mar 07 03:58:15 PM PST 24 |
2953644464 ps |
| T120 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1463502829 |
|
|
Mar 07 04:08:03 PM PST 24 |
Mar 07 04:19:36 PM PST 24 |
5671777800 ps |
| T644 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2052915192 |
|
|
Mar 07 03:55:17 PM PST 24 |
Mar 07 04:01:22 PM PST 24 |
3998535698 ps |
| T214 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3456465703 |
|
|
Mar 07 03:42:23 PM PST 24 |
Mar 07 03:52:49 PM PST 24 |
5164014358 ps |
| T716 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2446574996 |
|
|
Mar 07 04:04:00 PM PST 24 |
Mar 07 04:15:07 PM PST 24 |
4573956310 ps |
| T913 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2394259681 |
|
|
Mar 07 03:36:53 PM PST 24 |
Mar 07 03:41:51 PM PST 24 |
2513877436 ps |
| T914 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.3078271361 |
|
|
Mar 07 03:44:13 PM PST 24 |
Mar 07 03:49:51 PM PST 24 |
3046951792 ps |
| T915 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.4215394150 |
|
|
Mar 07 03:41:45 PM PST 24 |
Mar 07 03:53:55 PM PST 24 |
9628741288 ps |
| T916 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3730445991 |
|
|
Mar 07 03:40:52 PM PST 24 |
Mar 07 04:05:20 PM PST 24 |
11988901526 ps |
| T311 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.2702182375 |
|
|
Mar 07 04:00:27 PM PST 24 |
Mar 07 04:17:15 PM PST 24 |
4243622388 ps |
| T917 |
/workspace/coverage/default/1.rom_e2e_static_critical.3336750217 |
|
|
Mar 07 03:53:30 PM PST 24 |
Mar 07 04:37:07 PM PST 24 |
10460235650 ps |
| T167 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.691111778 |
|
|
Mar 07 03:36:37 PM PST 24 |
Mar 07 03:40:27 PM PST 24 |
2256544374 ps |
| T918 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3090739540 |
|
|
Mar 07 03:57:50 PM PST 24 |
Mar 07 04:16:37 PM PST 24 |
6226142108 ps |
| T919 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.4184830197 |
|
|
Mar 07 03:59:54 PM PST 24 |
Mar 07 04:06:31 PM PST 24 |
4668522732 ps |
| T764 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3391909463 |
|
|
Mar 07 04:06:27 PM PST 24 |
Mar 07 04:13:56 PM PST 24 |
3613586170 ps |
| T121 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2313696510 |
|
|
Mar 07 04:05:50 PM PST 24 |
Mar 07 04:11:50 PM PST 24 |
3715228592 ps |
| T920 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2287741563 |
|
|
Mar 07 03:40:47 PM PST 24 |
Mar 07 03:44:49 PM PST 24 |
2124315048 ps |
| T111 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.1056422208 |
|
|
Mar 07 03:46:01 PM PST 24 |
Mar 07 03:57:03 PM PST 24 |
4026619168 ps |
| T264 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3200401401 |
|
|
Mar 07 03:53:32 PM PST 24 |
Mar 07 04:19:30 PM PST 24 |
8842305566 ps |
| T122 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3820015491 |
|
|
Mar 07 04:05:34 PM PST 24 |
Mar 07 04:12:34 PM PST 24 |
3277030536 ps |
| T126 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1157683452 |
|
|
Mar 07 03:41:35 PM PST 24 |
Mar 07 03:45:47 PM PST 24 |
2604583716 ps |
| T44 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.423731773 |
|
|
Mar 07 03:51:55 PM PST 24 |
Mar 07 03:57:32 PM PST 24 |
3724362786 ps |
| T921 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2669062225 |
|
|
Mar 07 03:38:08 PM PST 24 |
Mar 07 04:20:53 PM PST 24 |
29234957940 ps |
| T679 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1373087135 |
|
|
Mar 07 04:05:45 PM PST 24 |
Mar 07 04:14:23 PM PST 24 |
4035898200 ps |
| T922 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.68159730 |
|
|
Mar 07 03:37:13 PM PST 24 |
Mar 07 03:39:56 PM PST 24 |
2727922850 ps |
| T923 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4205586772 |
|
|
Mar 07 03:57:56 PM PST 24 |
Mar 07 04:03:06 PM PST 24 |
3316080520 ps |
| T516 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4271438238 |
|
|
Mar 07 03:53:58 PM PST 24 |
Mar 07 04:10:28 PM PST 24 |
4383889080 ps |
| T924 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2221961777 |
|
|
Mar 07 03:37:35 PM PST 24 |
Mar 07 03:44:33 PM PST 24 |
4577417920 ps |
| T925 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.416555193 |
|
|
Mar 07 03:56:37 PM PST 24 |
Mar 07 04:09:22 PM PST 24 |
8390445716 ps |
| T212 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1614180908 |
|
|
Mar 07 03:56:37 PM PST 24 |
Mar 07 04:03:17 PM PST 24 |
4433173984 ps |
| T926 |
/workspace/coverage/default/2.rom_e2e_smoke.2500917861 |
|
|
Mar 07 04:00:57 PM PST 24 |
Mar 07 04:41:20 PM PST 24 |
9101547124 ps |
| T927 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3881265860 |
|
|
Mar 07 03:38:15 PM PST 24 |
Mar 07 03:56:54 PM PST 24 |
10443990748 ps |
| T328 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.829985574 |
|
|
Mar 07 03:42:36 PM PST 24 |
Mar 07 03:56:46 PM PST 24 |
5676524432 ps |
| T928 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2197580180 |
|
|
Mar 07 04:02:07 PM PST 24 |
Mar 07 04:09:59 PM PST 24 |
7671671900 ps |
| T711 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.980503080 |
|
|
Mar 07 03:37:22 PM PST 24 |
Mar 07 04:37:49 PM PST 24 |
20084642269 ps |
| T210 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1233122356 |
|
|
Mar 07 03:35:50 PM PST 24 |
Mar 07 03:45:13 PM PST 24 |
4994592788 ps |
| T929 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3206343418 |
|
|
Mar 07 03:51:35 PM PST 24 |
Mar 07 04:07:11 PM PST 24 |
5125852018 ps |
| T321 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.338424184 |
|
|
Mar 07 03:37:44 PM PST 24 |
Mar 07 04:05:52 PM PST 24 |
7983434196 ps |
| T24 |
/workspace/coverage/default/1.chip_sw_gpio.1702041744 |
|
|
Mar 07 03:39:50 PM PST 24 |
Mar 07 03:47:52 PM PST 24 |
4213516221 ps |
| T193 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.1396032528 |
|
|
Mar 07 03:40:45 PM PST 24 |
Mar 07 03:57:52 PM PST 24 |
5452446290 ps |
| T645 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.112743191 |
|
|
Mar 07 04:08:57 PM PST 24 |
Mar 07 04:18:51 PM PST 24 |
5804192180 ps |
| T930 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.125150516 |
|
|
Mar 07 03:50:46 PM PST 24 |
Mar 07 03:55:01 PM PST 24 |
2354206640 ps |
| T215 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4168651031 |
|
|
Mar 07 03:43:35 PM PST 24 |
Mar 07 03:51:27 PM PST 24 |
4568065683 ps |
| T931 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1290626479 |
|
|
Mar 07 03:56:09 PM PST 24 |
Mar 07 04:03:28 PM PST 24 |
3873865980 ps |
| T932 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.2583975315 |
|
|
Mar 07 04:04:37 PM PST 24 |
Mar 07 04:52:49 PM PST 24 |
24138666160 ps |
| T933 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1020245713 |
|
|
Mar 07 03:55:01 PM PST 24 |
Mar 07 04:05:33 PM PST 24 |
5619027472 ps |
| T642 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.2241591836 |
|
|
Mar 07 03:41:59 PM PST 24 |
Mar 07 03:46:30 PM PST 24 |
2571122376 ps |
| T216 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2113699818 |
|
|
Mar 07 03:55:10 PM PST 24 |
Mar 07 04:01:48 PM PST 24 |
4947999434 ps |
| T200 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.599394496 |
|
|
Mar 07 04:06:01 PM PST 24 |
Mar 07 04:20:47 PM PST 24 |
5056152392 ps |
| T33 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.114539253 |
|
|
Mar 07 03:38:50 PM PST 24 |
Mar 07 03:44:05 PM PST 24 |
3326997500 ps |
| T326 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2448000000 |
|
|
Mar 07 03:37:10 PM PST 24 |
Mar 07 03:49:54 PM PST 24 |
4500637596 ps |
| T650 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.3777838434 |
|
|
Mar 07 03:51:57 PM PST 24 |
Mar 07 04:06:09 PM PST 24 |
6168687384 ps |
| T934 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.765392372 |
|
|
Mar 07 03:53:02 PM PST 24 |
Mar 07 07:01:36 PM PST 24 |
64837600543 ps |
| T935 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.3982999247 |
|
|
Mar 07 03:55:41 PM PST 24 |
Mar 07 04:01:29 PM PST 24 |
2981909080 ps |
| T112 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.3911132299 |
|
|
Mar 07 03:35:54 PM PST 24 |
Mar 07 03:45:07 PM PST 24 |
4067924234 ps |
| T936 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.948516387 |
|
|
Mar 07 03:56:51 PM PST 24 |
Mar 07 04:07:21 PM PST 24 |
4619769698 ps |
| T937 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.1301387444 |
|
|
Mar 07 03:36:56 PM PST 24 |
Mar 07 06:46:28 PM PST 24 |
64790736152 ps |
| T938 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2108153033 |
|
|
Mar 07 03:54:25 PM PST 24 |
Mar 07 04:01:23 PM PST 24 |
4016273626 ps |
| T673 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1476185575 |
|
|
Mar 07 04:01:59 PM PST 24 |
Mar 07 04:09:16 PM PST 24 |
3962638110 ps |
| T159 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1419032750 |
|
|
Mar 07 03:46:35 PM PST 24 |
Mar 07 03:57:09 PM PST 24 |
5026315362 ps |
| T939 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.1499194448 |
|
|
Mar 07 03:39:00 PM PST 24 |
Mar 07 03:43:13 PM PST 24 |
3156106520 ps |
| T940 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3501531788 |
|
|
Mar 07 03:37:28 PM PST 24 |
Mar 07 03:47:27 PM PST 24 |
5531008465 ps |
| T195 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.609257859 |
|
|
Mar 07 03:57:49 PM PST 24 |
Mar 07 04:06:57 PM PST 24 |
5481388630 ps |
| T941 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1792445221 |
|
|
Mar 07 03:40:58 PM PST 24 |
Mar 07 03:45:45 PM PST 24 |
3250822070 ps |
| T942 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1491001540 |
|
|
Mar 07 04:00:32 PM PST 24 |
Mar 07 04:18:13 PM PST 24 |
5290734376 ps |
| T225 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.752348201 |
|
|
Mar 07 03:49:33 PM PST 24 |
Mar 07 04:24:17 PM PST 24 |
24788731763 ps |
| T114 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.635222185 |
|
|
Mar 07 03:55:43 PM PST 24 |
Mar 07 07:00:41 PM PST 24 |
256015209740 ps |
| T267 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2696029288 |
|
|
Mar 07 03:37:56 PM PST 24 |
Mar 07 03:52:31 PM PST 24 |
4540282470 ps |
| T22 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.2256210587 |
|
|
Mar 07 03:40:53 PM PST 24 |
Mar 07 04:15:56 PM PST 24 |
7586949000 ps |
| T943 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.4010647384 |
|
|
Mar 07 03:45:40 PM PST 24 |
Mar 07 04:01:28 PM PST 24 |
8431308416 ps |
| T204 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2196120621 |
|
|
Mar 07 03:40:59 PM PST 24 |
Mar 07 05:25:43 PM PST 24 |
49657958944 ps |
| T944 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.33259794 |
|
|
Mar 07 03:53:58 PM PST 24 |
Mar 07 04:05:11 PM PST 24 |
8015072768 ps |
| T724 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.423741044 |
|
|
Mar 07 04:09:23 PM PST 24 |
Mar 07 04:21:27 PM PST 24 |
5427008296 ps |
| T695 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1751267838 |
|
|
Mar 07 03:54:13 PM PST 24 |
Mar 07 03:59:42 PM PST 24 |
2738392930 ps |
| T146 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2532594497 |
|
|
Mar 07 03:37:22 PM PST 24 |
Mar 07 03:47:01 PM PST 24 |
19593557208 ps |
| T945 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.4267879646 |
|
|
Mar 07 03:59:51 PM PST 24 |
Mar 07 04:06:53 PM PST 24 |
2986160244 ps |
| T238 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3023240974 |
|
|
Mar 07 04:06:03 PM PST 24 |
Mar 07 04:15:24 PM PST 24 |
3914639776 ps |
| T284 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3943738763 |
|
|
Mar 07 04:02:19 PM PST 24 |
Mar 07 04:09:17 PM PST 24 |
3960945800 ps |
| T285 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1263943136 |
|
|
Mar 07 03:36:28 PM PST 24 |
Mar 07 03:49:28 PM PST 24 |
5683136316 ps |
| T286 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1781167482 |
|
|
Mar 07 03:58:56 PM PST 24 |
Mar 07 04:18:33 PM PST 24 |
6161777830 ps |
| T287 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1438132655 |
|
|
Mar 07 04:01:04 PM PST 24 |
Mar 07 04:09:39 PM PST 24 |
6693064623 ps |
| T143 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2389607763 |
|
|
Mar 07 03:38:12 PM PST 24 |
Mar 07 03:42:19 PM PST 24 |
2052565136 ps |
| T288 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3072886742 |
|
|
Mar 07 03:39:40 PM PST 24 |
Mar 07 03:55:34 PM PST 24 |
5833022114 ps |
| T289 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2200258912 |
|
|
Mar 07 04:00:26 PM PST 24 |
Mar 07 04:08:02 PM PST 24 |
3451642370 ps |
| T290 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1703857428 |
|
|
Mar 07 04:05:37 PM PST 24 |
Mar 07 04:11:23 PM PST 24 |
3368880450 ps |
| T291 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2046383551 |
|
|
Mar 07 04:03:16 PM PST 24 |
Mar 07 04:10:14 PM PST 24 |
3715041800 ps |
| T315 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2239854364 |
|
|
Mar 07 03:38:18 PM PST 24 |
Mar 07 03:48:53 PM PST 24 |
4406945352 ps |
| T381 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1938532382 |
|
|
Mar 07 03:46:44 PM PST 24 |
Mar 07 03:58:24 PM PST 24 |
4073464720 ps |
| T46 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.4222930579 |
|
|
Mar 07 03:47:47 PM PST 24 |
Mar 07 03:55:27 PM PST 24 |
5144075766 ps |
| T382 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1252274740 |
|
|
Mar 07 03:55:58 PM PST 24 |
Mar 07 05:19:49 PM PST 24 |
20886494520 ps |
| T383 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1642784876 |
|
|
Mar 07 04:05:24 PM PST 24 |
Mar 07 04:11:56 PM PST 24 |
3362365516 ps |
| T9 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1821756619 |
|
|
Mar 07 03:53:08 PM PST 24 |
Mar 07 04:09:56 PM PST 24 |
7765734510 ps |
| T697 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1130556084 |
|
|
Mar 07 03:44:33 PM PST 24 |
Mar 07 03:59:06 PM PST 24 |
5569498972 ps |
| T639 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.1547034629 |
|
|
Mar 07 03:55:40 PM PST 24 |
Mar 07 04:16:51 PM PST 24 |
4553563520 ps |
| T47 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.643027104 |
|
|
Mar 07 04:02:28 PM PST 24 |
Mar 07 04:07:42 PM PST 24 |
4799525340 ps |
| T681 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4150202905 |
|
|
Mar 07 03:40:35 PM PST 24 |
Mar 07 03:43:44 PM PST 24 |
2530649580 ps |
| T698 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.602661162 |
|
|
Mar 07 03:39:00 PM PST 24 |
Mar 07 03:41:50 PM PST 24 |
2706342134 ps |
| T646 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.1503463956 |
|
|
Mar 07 04:06:37 PM PST 24 |
Mar 07 04:16:24 PM PST 24 |
5024881974 ps |
| T946 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.107225284 |
|
|
Mar 07 03:37:58 PM PST 24 |
Mar 07 03:43:17 PM PST 24 |
2720193294 ps |
| T670 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.549797704 |
|
|
Mar 07 04:06:45 PM PST 24 |
Mar 07 04:14:42 PM PST 24 |
4000082590 ps |
| T947 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3371502954 |
|
|
Mar 07 04:10:08 PM PST 24 |
Mar 07 04:21:24 PM PST 24 |
6066108476 ps |
| T10 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2429583567 |
|
|
Mar 07 03:42:14 PM PST 24 |
Mar 07 03:53:26 PM PST 24 |
5065007778 ps |
| T82 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1983368309 |
|
|
Mar 07 03:54:49 PM PST 24 |
Mar 07 04:20:19 PM PST 24 |
13189162000 ps |
| T948 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3893759043 |
|
|
Mar 07 03:45:33 PM PST 24 |
Mar 07 04:31:12 PM PST 24 |
10025566030 ps |
| T949 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3722207931 |
|
|
Mar 07 04:00:38 PM PST 24 |
Mar 07 04:17:37 PM PST 24 |
5344522092 ps |
| T753 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.4195900904 |
|
|
Mar 07 04:11:29 PM PST 24 |
Mar 07 04:16:15 PM PST 24 |
3945053210 ps |
| T950 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.146033278 |
|
|
Mar 07 03:51:38 PM PST 24 |
Mar 07 03:55:53 PM PST 24 |
3010400262 ps |
| T705 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1173678270 |
|
|
Mar 07 03:44:01 PM PST 24 |
Mar 07 03:50:59 PM PST 24 |
5658770592 ps |
| T11 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1835705746 |
|
|
Mar 07 03:37:02 PM PST 24 |
Mar 07 03:49:48 PM PST 24 |
7738471328 ps |
| T422 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.2220220631 |
|
|
Mar 07 03:36:37 PM PST 24 |
Mar 07 03:41:24 PM PST 24 |
3489422040 ps |
| T239 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2573279090 |
|
|
Mar 07 04:02:45 PM PST 24 |
Mar 07 04:09:34 PM PST 24 |
3313314568 ps |
| T235 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1084579764 |
|
|
Mar 07 04:09:40 PM PST 24 |
Mar 07 04:22:08 PM PST 24 |
5997202802 ps |
| T951 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3824510094 |
|
|
Mar 07 03:56:40 PM PST 24 |
Mar 07 04:18:48 PM PST 24 |
10650187880 ps |
| T952 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.952455730 |
|
|
Mar 07 03:42:52 PM PST 24 |
Mar 07 03:47:00 PM PST 24 |
2755713872 ps |
| T953 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.108579121 |
|
|
Mar 07 03:51:11 PM PST 24 |
Mar 07 03:55:36 PM PST 24 |
3425681308 ps |
| T163 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.894491461 |
|
|
Mar 07 03:56:00 PM PST 24 |
Mar 07 04:06:46 PM PST 24 |
4211161816 ps |
| T954 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1113669712 |
|
|
Mar 07 04:01:34 PM PST 24 |
Mar 07 04:19:38 PM PST 24 |
8474875207 ps |
| T955 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.4205438104 |
|
|
Mar 07 03:47:14 PM PST 24 |
Mar 07 04:05:17 PM PST 24 |
9426444787 ps |
| T759 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3739710021 |
|
|
Mar 07 04:05:30 PM PST 24 |
Mar 07 04:13:10 PM PST 24 |
3514132180 ps |
| T696 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2809729746 |
|
|
Mar 07 03:41:30 PM PST 24 |
Mar 07 03:45:50 PM PST 24 |
3028333448 ps |
| T956 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3917664771 |
|
|
Mar 07 03:45:43 PM PST 24 |
Mar 07 04:20:30 PM PST 24 |
20493482985 ps |
| T732 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3690957461 |
|
|
Mar 07 04:08:46 PM PST 24 |
Mar 07 04:16:15 PM PST 24 |
3802483030 ps |
| T651 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2756266793 |
|
|
Mar 07 03:51:06 PM PST 24 |
Mar 07 03:59:23 PM PST 24 |
5319261539 ps |
| T196 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.108149950 |
|
|
Mar 07 03:48:46 PM PST 24 |
Mar 07 03:57:48 PM PST 24 |
3965800536 ps |
| T174 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.1610294488 |
|
|
Mar 07 03:37:18 PM PST 24 |
Mar 07 04:26:05 PM PST 24 |
11962851720 ps |
| T243 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.2379621178 |
|
|
Mar 07 03:45:55 PM PST 24 |
Mar 07 03:50:53 PM PST 24 |
2997016940 ps |
| T957 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3240076601 |
|
|
Mar 07 04:03:08 PM PST 24 |
Mar 07 04:44:42 PM PST 24 |
14392967252 ps |
| T518 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.867139908 |
|
|
Mar 07 03:41:05 PM PST 24 |
Mar 07 04:12:52 PM PST 24 |
13076386572 ps |
| T958 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.264908168 |
|
|
Mar 07 03:45:33 PM PST 24 |
Mar 07 04:12:23 PM PST 24 |
7184224976 ps |
| T713 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3589289872 |
|
|
Mar 07 04:05:21 PM PST 24 |
Mar 07 04:14:56 PM PST 24 |
5189098836 ps |
| T656 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3845428113 |
|
|
Mar 07 03:42:34 PM PST 24 |
Mar 07 03:44:27 PM PST 24 |
2715359481 ps |
| T118 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1218976970 |
|
|
Mar 07 03:37:30 PM PST 24 |
Mar 07 07:13:53 PM PST 24 |
255102197356 ps |
| T959 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2581281623 |
|
|
Mar 07 03:59:15 PM PST 24 |
Mar 07 04:03:20 PM PST 24 |
3005665006 ps |
| T227 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.4017698557 |
|
|
Mar 07 03:39:54 PM PST 24 |
Mar 07 05:24:52 PM PST 24 |
49816284120 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.3705034842 |
|
|
Mar 07 03:50:52 PM PST 24 |
Mar 07 03:56:59 PM PST 24 |
2995659700 ps |
| T961 |
/workspace/coverage/default/1.rom_keymgr_functest.1319252724 |
|
|
Mar 07 03:50:56 PM PST 24 |
Mar 07 04:01:42 PM PST 24 |
4633179308 ps |
| T962 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.218553808 |
|
|
Mar 07 03:42:52 PM PST 24 |
Mar 07 04:07:02 PM PST 24 |
6799703041 ps |
| T963 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.627135307 |
|
|
Mar 07 03:55:37 PM PST 24 |
Mar 07 04:00:32 PM PST 24 |
2842049912 ps |
| T964 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.916178955 |
|
|
Mar 07 03:55:06 PM PST 24 |
Mar 07 04:31:01 PM PST 24 |
9072362409 ps |
| T965 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2161261992 |
|
|
Mar 07 03:44:33 PM PST 24 |
Mar 07 04:24:28 PM PST 24 |
8183265725 ps |
| T966 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.896325420 |
|
|
Mar 07 03:41:54 PM PST 24 |
Mar 07 04:38:46 PM PST 24 |
22996298949 ps |
| T967 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3536637897 |
|
|
Mar 07 03:43:34 PM PST 24 |
Mar 07 04:18:26 PM PST 24 |
7711884409 ps |
| T968 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1902197275 |
|
|
Mar 07 03:41:50 PM PST 24 |
Mar 07 03:49:51 PM PST 24 |
7004127348 ps |
| T740 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4130770243 |
|
|
Mar 07 04:07:45 PM PST 24 |
Mar 07 04:14:06 PM PST 24 |
3558566044 ps |
| T969 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2460429864 |
|
|
Mar 07 03:40:12 PM PST 24 |
Mar 07 03:46:12 PM PST 24 |
3065994813 ps |
| T325 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3838533523 |
|
|
Mar 07 03:38:41 PM PST 24 |
Mar 07 03:55:27 PM PST 24 |
5677702228 ps |
| T970 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.163089744 |
|
|
Mar 07 03:42:37 PM PST 24 |
Mar 07 04:07:47 PM PST 24 |
7210472519 ps |
| T971 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.3272805776 |
|
|
Mar 07 03:41:33 PM PST 24 |
Mar 07 03:46:47 PM PST 24 |
3170969830 ps |
| T972 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.3948798036 |
|
|
Mar 07 03:38:29 PM PST 24 |
Mar 07 03:43:24 PM PST 24 |
2695864761 ps |
| T973 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.973395845 |
|
|
Mar 07 04:03:36 PM PST 24 |
Mar 07 04:18:22 PM PST 24 |
10451761616 ps |
| T974 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.285411969 |
|
|
Mar 07 03:57:41 PM PST 24 |
Mar 07 04:05:49 PM PST 24 |
5115490112 ps |
| T310 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4102994503 |
|
|
Mar 07 03:44:50 PM PST 24 |
Mar 07 04:20:39 PM PST 24 |
11840365016 ps |
| T975 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2477203365 |
|
|
Mar 07 03:53:46 PM PST 24 |
Mar 07 03:58:11 PM PST 24 |
2789105106 ps |
| T976 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1406991856 |
|
|
Mar 07 03:47:34 PM PST 24 |
Mar 07 03:57:57 PM PST 24 |
5033496918 ps |
| T702 |
/workspace/coverage/default/0.rom_raw_unlock.739597708 |
|
|
Mar 07 03:40:45 PM PST 24 |
Mar 07 04:22:40 PM PST 24 |
15427705855 ps |
| T977 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2251977366 |
|
|
Mar 07 04:04:04 PM PST 24 |
Mar 07 04:12:47 PM PST 24 |
3544906112 ps |
| T127 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2876572712 |
|
|
Mar 07 03:52:50 PM PST 24 |
Mar 07 03:56:50 PM PST 24 |
2756870097 ps |
| T978 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2961420320 |
|
|
Mar 07 03:54:29 PM PST 24 |
Mar 07 04:37:23 PM PST 24 |
12491541322 ps |
| T717 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2644083175 |
|
|
Mar 07 04:05:56 PM PST 24 |
Mar 07 04:17:34 PM PST 24 |
4827193216 ps |
| T979 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1494445701 |
|
|
Mar 07 03:37:44 PM PST 24 |
Mar 07 03:54:07 PM PST 24 |
5644015208 ps |
| T640 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.3074654508 |
|
|
Mar 07 03:44:03 PM PST 24 |
Mar 07 04:05:35 PM PST 24 |
5200253900 ps |
| T771 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1729049133 |
|
|
Mar 07 04:07:44 PM PST 24 |
Mar 07 04:16:59 PM PST 24 |
4993790520 ps |
| T980 |
/workspace/coverage/default/1.chip_sw_example_rom.722833990 |
|
|
Mar 07 03:39:46 PM PST 24 |
Mar 07 03:41:41 PM PST 24 |
2764743720 ps |
| T358 |
/workspace/coverage/default/2.chip_sw_hmac_enc.3179851234 |
|
|
Mar 07 03:56:33 PM PST 24 |
Mar 07 04:02:19 PM PST 24 |
2862402790 ps |
| T981 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2554083076 |
|
|
Mar 07 03:54:00 PM PST 24 |
Mar 07 04:02:01 PM PST 24 |
5079405082 ps |
| T755 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3201255092 |
|
|
Mar 07 04:08:18 PM PST 24 |
Mar 07 04:17:44 PM PST 24 |
5132735546 ps |
| T982 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.2785794424 |
|
|
Mar 07 03:54:05 PM PST 24 |
Mar 07 04:30:29 PM PST 24 |
8739696661 ps |
| T983 |
/workspace/coverage/default/0.rom_e2e_smoke.2770365521 |
|
|
Mar 07 03:39:21 PM PST 24 |
Mar 07 04:16:33 PM PST 24 |
9084391180 ps |
| T984 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.862694449 |
|
|
Mar 07 03:37:32 PM PST 24 |
Mar 07 03:42:41 PM PST 24 |
3303715704 ps |
| T985 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2393386791 |
|
|
Mar 07 03:40:55 PM PST 24 |
Mar 07 03:49:42 PM PST 24 |
5541226610 ps |
| T671 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2921128912 |
|
|
Mar 07 04:06:27 PM PST 24 |
Mar 07 04:13:50 PM PST 24 |
4217315040 ps |
| T986 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3585030475 |
|
|
Mar 07 04:06:05 PM PST 24 |
Mar 07 04:12:47 PM PST 24 |
4202679402 ps |
| T340 |
/workspace/coverage/default/0.chip_sival_flash_info_access.3786236149 |
|
|
Mar 07 03:37:28 PM PST 24 |
Mar 07 03:43:10 PM PST 24 |
2904304102 ps |
| T987 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2147225470 |
|
|
Mar 07 03:53:15 PM PST 24 |
Mar 07 04:09:17 PM PST 24 |
5116387928 ps |
| T988 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.833120056 |
|
|
Mar 07 03:46:33 PM PST 24 |
Mar 07 03:54:36 PM PST 24 |
4993921368 ps |
| T989 |
/workspace/coverage/default/0.chip_sw_aes_entropy.3245219005 |
|
|
Mar 07 03:39:05 PM PST 24 |
Mar 07 03:41:54 PM PST 24 |
3103772888 ps |
| T990 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.571510830 |
|
|
Mar 07 03:39:20 PM PST 24 |
Mar 07 03:59:33 PM PST 24 |
5380160952 ps |
| T991 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.1437877266 |
|
|
Mar 07 03:53:00 PM PST 24 |
Mar 07 04:11:17 PM PST 24 |
5699995544 ps |
| T992 |
/workspace/coverage/default/0.chip_tap_straps_rma.4021673900 |
|
|
Mar 07 03:40:53 PM PST 24 |
Mar 07 03:57:05 PM PST 24 |
9554815443 ps |
| T993 |
/workspace/coverage/default/3.chip_tap_straps_prod.201502382 |
|
|
Mar 07 04:00:48 PM PST 24 |
Mar 07 04:33:09 PM PST 24 |
17768236101 ps |
| T994 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2492455845 |
|
|
Mar 07 03:51:33 PM PST 24 |
Mar 07 03:56:36 PM PST 24 |
3052293744 ps |
| T995 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3866688511 |
|
|
Mar 07 03:43:08 PM PST 24 |
Mar 07 03:56:25 PM PST 24 |
7284461000 ps |
| T996 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2316440171 |
|
|
Mar 07 03:58:40 PM PST 24 |
Mar 07 04:17:14 PM PST 24 |
6869745541 ps |
| T279 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.5960619 |
|
|
Mar 07 03:38:14 PM PST 24 |
Mar 07 03:49:17 PM PST 24 |
4537143832 ps |
| T997 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3304507033 |
|
|
Mar 07 03:37:56 PM PST 24 |
Mar 07 03:46:09 PM PST 24 |
4762208584 ps |
| T998 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1266847323 |
|
|
Mar 07 03:53:52 PM PST 24 |
Mar 07 04:01:05 PM PST 24 |
4196126275 ps |
| T999 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3794466862 |
|
|
Mar 07 03:46:56 PM PST 24 |
Mar 07 03:57:03 PM PST 24 |
4252412914 ps |
| T1000 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3393021794 |
|
|
Mar 07 03:54:56 PM PST 24 |
Mar 07 07:33:39 PM PST 24 |
79561555768 ps |
| T1001 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.652606709 |
|
|
Mar 07 04:03:23 PM PST 24 |
Mar 07 04:16:00 PM PST 24 |
11341887481 ps |
| T1002 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2223860594 |
|
|
Mar 07 03:45:02 PM PST 24 |
Mar 07 03:55:39 PM PST 24 |
6593824474 ps |