| T1140 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2497751029 |
|
|
Mar 07 03:38:29 PM PST 24 |
Mar 07 03:47:16 PM PST 24 |
5346789936 ps |
| T1141 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.878609583 |
|
|
Mar 07 04:07:14 PM PST 24 |
Mar 07 04:14:20 PM PST 24 |
3377562968 ps |
| T1142 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.3856534844 |
|
|
Mar 07 03:39:03 PM PST 24 |
Mar 07 03:41:54 PM PST 24 |
2508760484 ps |
| T683 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2253585506 |
|
|
Mar 07 03:37:00 PM PST 24 |
Mar 07 03:41:40 PM PST 24 |
3536836998 ps |
| T638 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1086628166 |
|
|
Mar 07 03:38:16 PM PST 24 |
Mar 07 04:50:55 PM PST 24 |
25319348073 ps |
| T218 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3334104723 |
|
|
Mar 07 03:36:25 PM PST 24 |
Mar 07 03:46:07 PM PST 24 |
5587892440 ps |
| T1143 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1305347872 |
|
|
Mar 07 03:42:25 PM PST 24 |
Mar 07 04:21:24 PM PST 24 |
8320170412 ps |
| T1144 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2145595990 |
|
|
Mar 07 04:06:34 PM PST 24 |
Mar 07 04:18:11 PM PST 24 |
5071804312 ps |
| T1145 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2297928546 |
|
|
Mar 07 04:01:11 PM PST 24 |
Mar 07 04:06:18 PM PST 24 |
2438176500 ps |
| T1146 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4109380049 |
|
|
Mar 07 03:43:14 PM PST 24 |
Mar 07 03:46:39 PM PST 24 |
2888680302 ps |
| T1147 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.607056798 |
|
|
Mar 07 03:39:21 PM PST 24 |
Mar 07 04:04:50 PM PST 24 |
8672959398 ps |
| T1148 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1339870372 |
|
|
Mar 07 03:51:46 PM PST 24 |
Mar 07 04:05:57 PM PST 24 |
5470150012 ps |
| T1149 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3867625926 |
|
|
Mar 07 04:05:48 PM PST 24 |
Mar 07 04:13:23 PM PST 24 |
3174855640 ps |
| T747 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4158465941 |
|
|
Mar 07 04:08:45 PM PST 24 |
Mar 07 04:15:57 PM PST 24 |
4049923948 ps |
| T1150 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2010981284 |
|
|
Mar 07 03:42:24 PM PST 24 |
Mar 07 03:48:31 PM PST 24 |
3514523410 ps |
| T1151 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3705301386 |
|
|
Mar 07 03:42:31 PM PST 24 |
Mar 07 04:17:55 PM PST 24 |
8096359800 ps |
| T429 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3071671193 |
|
|
Mar 07 03:53:21 PM PST 24 |
Mar 07 04:02:26 PM PST 24 |
3307581708 ps |
| T197 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3525038286 |
|
|
Mar 07 03:38:04 PM PST 24 |
Mar 07 03:46:01 PM PST 24 |
5540497256 ps |
| T1152 |
/workspace/coverage/default/0.chip_sw_kmac_idle.3081564129 |
|
|
Mar 07 03:38:48 PM PST 24 |
Mar 07 03:45:10 PM PST 24 |
3263857676 ps |
| T1153 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2969688162 |
|
|
Mar 07 03:42:15 PM PST 24 |
Mar 07 04:41:24 PM PST 24 |
12670775416 ps |
| T1154 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1473097518 |
|
|
Mar 07 03:46:45 PM PST 24 |
Mar 07 04:06:05 PM PST 24 |
8411709064 ps |
| T1155 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2860815616 |
|
|
Mar 07 03:44:09 PM PST 24 |
Mar 07 04:24:08 PM PST 24 |
8840336646 ps |
| T739 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2738795192 |
|
|
Mar 07 04:08:53 PM PST 24 |
Mar 07 04:15:41 PM PST 24 |
3852607492 ps |
| T25 |
/workspace/coverage/default/0.chip_sw_gpio.730981513 |
|
|
Mar 07 03:37:26 PM PST 24 |
Mar 07 03:46:32 PM PST 24 |
4272859332 ps |
| T1156 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1621097223 |
|
|
Mar 07 04:04:16 PM PST 24 |
Mar 07 04:15:35 PM PST 24 |
6430470320 ps |
| T769 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.3770072673 |
|
|
Mar 07 04:04:38 PM PST 24 |
Mar 07 04:16:16 PM PST 24 |
4421613452 ps |
| T1157 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2986571486 |
|
|
Mar 07 04:00:58 PM PST 24 |
Mar 07 04:17:15 PM PST 24 |
6234282304 ps |
| T1158 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4195741236 |
|
|
Mar 07 03:43:10 PM PST 24 |
Mar 07 04:12:25 PM PST 24 |
16764804602 ps |
| T1159 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.2474112305 |
|
|
Mar 07 04:00:30 PM PST 24 |
Mar 07 04:09:09 PM PST 24 |
5516955419 ps |
| T1160 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.1322673586 |
|
|
Mar 07 03:54:29 PM PST 24 |
Mar 07 03:58:08 PM PST 24 |
2211401630 ps |
| T412 |
/workspace/coverage/default/2.chip_jtag_mem_access.2733766674 |
|
|
Mar 07 03:49:54 PM PST 24 |
Mar 07 04:13:36 PM PST 24 |
13213132865 ps |
| T1161 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.754093482 |
|
|
Mar 07 03:36:52 PM PST 24 |
Mar 07 03:46:03 PM PST 24 |
9139203324 ps |
| T148 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2407751529 |
|
|
Mar 07 03:55:38 PM PST 24 |
Mar 07 04:08:42 PM PST 24 |
19278283648 ps |
| T704 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.1224458762 |
|
|
Mar 07 03:51:49 PM PST 24 |
Mar 07 03:56:20 PM PST 24 |
2689769924 ps |
| T244 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.1350985867 |
|
|
Mar 07 03:50:54 PM PST 24 |
Mar 07 03:58:43 PM PST 24 |
3985510072 ps |
| T1162 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.2571349266 |
|
|
Mar 07 03:42:40 PM PST 24 |
Mar 07 04:20:20 PM PST 24 |
9050910348 ps |
| T1163 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1523103058 |
|
|
Mar 07 04:04:34 PM PST 24 |
Mar 07 04:13:05 PM PST 24 |
3944933256 ps |
| T684 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.2228289651 |
|
|
Mar 07 03:56:57 PM PST 24 |
Mar 07 04:01:25 PM PST 24 |
2049021832 ps |
| T1164 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1073081470 |
|
|
Mar 07 04:01:35 PM PST 24 |
Mar 07 04:07:48 PM PST 24 |
3783111408 ps |
| T1165 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.948397378 |
|
|
Mar 07 04:03:07 PM PST 24 |
Mar 07 04:21:03 PM PST 24 |
6190017280 ps |
| T268 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.363390976 |
|
|
Mar 07 03:38:54 PM PST 24 |
Mar 07 03:53:06 PM PST 24 |
4822993558 ps |
| T1166 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.305570345 |
|
|
Mar 07 03:37:48 PM PST 24 |
Mar 07 03:44:50 PM PST 24 |
4095817416 ps |
| T1167 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2384734729 |
|
|
Mar 07 04:04:35 PM PST 24 |
Mar 07 04:21:36 PM PST 24 |
6205609940 ps |
| T772 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.581237554 |
|
|
Mar 07 04:08:21 PM PST 24 |
Mar 07 04:17:07 PM PST 24 |
4561029000 ps |
| T327 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.4077575318 |
|
|
Mar 07 03:39:22 PM PST 24 |
Mar 07 03:53:55 PM PST 24 |
5418952204 ps |
| T1168 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3275039744 |
|
|
Mar 07 03:48:04 PM PST 24 |
Mar 07 04:00:21 PM PST 24 |
4596186636 ps |
| T653 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.661517290 |
|
|
Mar 07 03:58:31 PM PST 24 |
Mar 07 04:07:34 PM PST 24 |
4863592974 ps |
| T1169 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1267588178 |
|
|
Mar 07 04:04:30 PM PST 24 |
Mar 07 04:46:23 PM PST 24 |
13137920696 ps |
| T50 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2182327771 |
|
|
Mar 07 03:42:19 PM PST 24 |
Mar 07 03:48:11 PM PST 24 |
4218857840 ps |
| T88 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3478701049 |
|
|
Mar 07 04:09:10 PM PST 24 |
Mar 07 04:22:18 PM PST 24 |
5061589902 ps |
| T712 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3185023840 |
|
|
Mar 07 04:09:53 PM PST 24 |
Mar 07 04:21:21 PM PST 24 |
5302688852 ps |
| T1170 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3316139190 |
|
|
Mar 07 03:42:19 PM PST 24 |
Mar 07 06:50:22 PM PST 24 |
255002245080 ps |
| T1171 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.976506613 |
|
|
Mar 07 03:52:49 PM PST 24 |
Mar 07 04:16:18 PM PST 24 |
9565280166 ps |
| T1172 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1357320326 |
|
|
Mar 07 04:02:37 PM PST 24 |
Mar 07 04:11:10 PM PST 24 |
5759045754 ps |
| T1173 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2819368267 |
|
|
Mar 07 03:46:37 PM PST 24 |
Mar 07 03:55:32 PM PST 24 |
4635915268 ps |
| T1174 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.595765161 |
|
|
Mar 07 03:39:09 PM PST 24 |
Mar 07 03:47:14 PM PST 24 |
5924482468 ps |
| T1175 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.4167445793 |
|
|
Mar 07 03:37:28 PM PST 24 |
Mar 07 03:41:56 PM PST 24 |
3252414125 ps |
| T768 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3625264328 |
|
|
Mar 07 04:09:27 PM PST 24 |
Mar 07 04:16:09 PM PST 24 |
3587096186 ps |
| T1176 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3715270479 |
|
|
Mar 07 04:04:05 PM PST 24 |
Mar 07 04:20:53 PM PST 24 |
5788807272 ps |
| T1177 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2826971640 |
|
|
Mar 07 03:55:44 PM PST 24 |
Mar 07 04:01:07 PM PST 24 |
2986670338 ps |
| T723 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3760846565 |
|
|
Mar 07 03:39:10 PM PST 24 |
Mar 07 03:49:44 PM PST 24 |
5635435560 ps |
| T1178 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2522812297 |
|
|
Mar 07 03:38:08 PM PST 24 |
Mar 07 03:44:26 PM PST 24 |
3501260482 ps |
| T1179 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3222125206 |
|
|
Mar 07 03:42:40 PM PST 24 |
Mar 07 04:20:04 PM PST 24 |
8297976565 ps |
| T1180 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2042423706 |
|
|
Mar 07 03:51:54 PM PST 24 |
Mar 07 04:12:26 PM PST 24 |
5092222896 ps |
| T1181 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2709780824 |
|
|
Mar 07 03:40:42 PM PST 24 |
Mar 07 03:51:02 PM PST 24 |
6160165508 ps |
| T1182 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.292644074 |
|
|
Mar 07 03:39:19 PM PST 24 |
Mar 07 03:43:39 PM PST 24 |
3021136623 ps |
| T207 |
/workspace/coverage/default/2.chip_jtag_csr_rw.2116822591 |
|
|
Mar 07 03:49:50 PM PST 24 |
Mar 07 04:26:42 PM PST 24 |
18933675470 ps |
| T1183 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.706147861 |
|
|
Mar 07 03:39:58 PM PST 24 |
Mar 07 03:48:06 PM PST 24 |
6611467180 ps |
| T1184 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1432542907 |
|
|
Mar 07 03:54:43 PM PST 24 |
Mar 07 04:29:25 PM PST 24 |
13455152498 ps |
| T1185 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.2171087852 |
|
|
Mar 07 03:51:25 PM PST 24 |
Mar 07 03:57:34 PM PST 24 |
2981938440 ps |
| T269 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2102769159 |
|
|
Mar 07 03:51:37 PM PST 24 |
Mar 07 04:06:50 PM PST 24 |
5553240960 ps |
| T1186 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.472654232 |
|
|
Mar 07 03:40:20 PM PST 24 |
Mar 07 04:04:25 PM PST 24 |
9462394000 ps |
| T1187 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.1837992334 |
|
|
Mar 07 04:00:14 PM PST 24 |
Mar 07 04:04:57 PM PST 24 |
2939301148 ps |
| T1188 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1628860763 |
|
|
Mar 07 03:40:32 PM PST 24 |
Mar 07 05:14:55 PM PST 24 |
49781956672 ps |
| T1189 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.1737410809 |
|
|
Mar 07 03:40:16 PM PST 24 |
Mar 07 03:44:24 PM PST 24 |
2664067640 ps |
| T1190 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1440510313 |
|
|
Mar 07 03:43:01 PM PST 24 |
Mar 07 04:09:01 PM PST 24 |
6939161528 ps |
| T1191 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.761665535 |
|
|
Mar 07 03:54:40 PM PST 24 |
Mar 07 04:07:19 PM PST 24 |
6638153768 ps |
| T1192 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.2826865376 |
|
|
Mar 07 03:54:42 PM PST 24 |
Mar 07 04:00:16 PM PST 24 |
3126961968 ps |
| T734 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.1250269826 |
|
|
Mar 07 04:04:07 PM PST 24 |
Mar 07 04:14:45 PM PST 24 |
4170412632 ps |
| T1193 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.470700726 |
|
|
Mar 07 03:42:55 PM PST 24 |
Mar 07 04:20:58 PM PST 24 |
9026792023 ps |
| T1194 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.496346609 |
|
|
Mar 07 03:51:10 PM PST 24 |
Mar 07 03:56:02 PM PST 24 |
3461439270 ps |
| T699 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3017737290 |
|
|
Mar 07 03:43:46 PM PST 24 |
Mar 07 03:58:02 PM PST 24 |
4509281208 ps |
| T1195 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2651370501 |
|
|
Mar 07 04:02:10 PM PST 24 |
Mar 07 04:18:23 PM PST 24 |
5795253456 ps |
| T1196 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.673500998 |
|
|
Mar 07 03:44:55 PM PST 24 |
Mar 07 03:54:34 PM PST 24 |
3479641790 ps |
| T1197 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1650489926 |
|
|
Mar 07 03:54:17 PM PST 24 |
Mar 07 05:21:45 PM PST 24 |
44981687309 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.1639656736 |
|
|
Mar 07 03:38:52 PM PST 24 |
Mar 07 03:53:10 PM PST 24 |
5549261610 ps |
| T1199 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.2894508028 |
|
|
Mar 07 03:42:25 PM PST 24 |
Mar 07 03:45:19 PM PST 24 |
1955715608 ps |
| T1200 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.1912280102 |
|
|
Mar 07 04:04:24 PM PST 24 |
Mar 07 04:14:38 PM PST 24 |
6297620434 ps |
| T1201 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.2973846480 |
|
|
Mar 07 04:01:19 PM PST 24 |
Mar 07 04:29:08 PM PST 24 |
7958893160 ps |
| T1202 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3188990604 |
|
|
Mar 07 03:54:11 PM PST 24 |
Mar 07 04:09:54 PM PST 24 |
6765085319 ps |
| T1203 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.3098741051 |
|
|
Mar 07 04:06:30 PM PST 24 |
Mar 07 04:17:29 PM PST 24 |
4156162052 ps |
| T1204 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1439403087 |
|
|
Mar 07 03:43:10 PM PST 24 |
Mar 07 03:44:43 PM PST 24 |
2357183341 ps |
| T219 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.475315284 |
|
|
Mar 07 03:45:04 PM PST 24 |
Mar 07 03:53:13 PM PST 24 |
3599662162 ps |
| T1205 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.3252117000 |
|
|
Mar 07 03:37:53 PM PST 24 |
Mar 07 03:42:09 PM PST 24 |
2388956600 ps |
| T1206 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.932696648 |
|
|
Mar 07 03:57:23 PM PST 24 |
Mar 07 04:01:41 PM PST 24 |
2993015407 ps |
| T1207 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3749571981 |
|
|
Mar 07 03:52:46 PM PST 24 |
Mar 07 04:05:38 PM PST 24 |
4050406664 ps |
| T1208 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1692264763 |
|
|
Mar 07 03:54:39 PM PST 24 |
Mar 07 04:03:09 PM PST 24 |
6716114151 ps |
| T1209 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.928264589 |
|
|
Mar 07 03:49:57 PM PST 24 |
Mar 07 03:59:41 PM PST 24 |
5831335890 ps |
| T1210 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3846363186 |
|
|
Mar 07 04:00:04 PM PST 24 |
Mar 07 04:17:02 PM PST 24 |
4913755609 ps |
| T773 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.205009710 |
|
|
Mar 07 04:03:01 PM PST 24 |
Mar 07 04:09:54 PM PST 24 |
3933161632 ps |
| T1211 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.267913187 |
|
|
Mar 07 03:53:08 PM PST 24 |
Mar 07 04:33:20 PM PST 24 |
27529044200 ps |
| T1212 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.536569735 |
|
|
Mar 07 03:48:28 PM PST 24 |
Mar 07 03:57:23 PM PST 24 |
5942622448 ps |
| T1213 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.972328425 |
|
|
Mar 07 03:54:00 PM PST 24 |
Mar 07 03:59:29 PM PST 24 |
2846982972 ps |
| T356 |
/workspace/coverage/default/1.chip_sival_flash_info_access.3584707732 |
|
|
Mar 07 03:40:34 PM PST 24 |
Mar 07 03:46:01 PM PST 24 |
3028976080 ps |
| T763 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1727677120 |
|
|
Mar 07 04:04:19 PM PST 24 |
Mar 07 04:15:58 PM PST 24 |
4518800188 ps |
| T765 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3577614943 |
|
|
Mar 07 04:07:37 PM PST 24 |
Mar 07 04:16:45 PM PST 24 |
4365363688 ps |
| T89 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.974088735 |
|
|
Mar 07 04:06:58 PM PST 24 |
Mar 07 04:19:49 PM PST 24 |
5116663464 ps |
| T1214 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3478927250 |
|
|
Mar 07 03:57:01 PM PST 24 |
Mar 07 04:00:54 PM PST 24 |
2621838658 ps |
| T749 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.479651771 |
|
|
Mar 07 04:08:02 PM PST 24 |
Mar 07 04:18:13 PM PST 24 |
6090396042 ps |
| T379 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3261919638 |
|
|
Mar 07 03:50:15 PM PST 24 |
Mar 07 03:55:23 PM PST 24 |
2790293504 ps |
| T1215 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1834858180 |
|
|
Mar 07 04:07:18 PM PST 24 |
Mar 07 04:15:51 PM PST 24 |
4583708306 ps |
| T1216 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.521356669 |
|
|
Mar 07 03:47:30 PM PST 24 |
Mar 07 04:03:58 PM PST 24 |
5962304836 ps |
| T744 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2009885052 |
|
|
Mar 07 04:08:37 PM PST 24 |
Mar 07 04:19:48 PM PST 24 |
4990016872 ps |
| T770 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.182508589 |
|
|
Mar 07 04:04:42 PM PST 24 |
Mar 07 04:16:39 PM PST 24 |
5469868720 ps |
| T1217 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.636730555 |
|
|
Mar 07 03:54:26 PM PST 24 |
Mar 07 04:33:19 PM PST 24 |
8428784568 ps |
| T56 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1717796010 |
|
|
Mar 07 03:41:07 PM PST 24 |
Mar 07 03:50:41 PM PST 24 |
3176365488 ps |
| T760 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3023626184 |
|
|
Mar 07 04:06:52 PM PST 24 |
Mar 07 04:17:49 PM PST 24 |
4740298598 ps |
| T1218 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2611743307 |
|
|
Mar 07 03:42:08 PM PST 24 |
Mar 07 04:31:17 PM PST 24 |
13357274490 ps |
| T1219 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1672030377 |
|
|
Mar 07 03:53:04 PM PST 24 |
Mar 07 04:10:33 PM PST 24 |
5595773950 ps |
| T1220 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.1963022578 |
|
|
Mar 07 03:37:30 PM PST 24 |
Mar 07 03:49:48 PM PST 24 |
4607507760 ps |
| T1221 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2361206737 |
|
|
Mar 07 03:41:26 PM PST 24 |
Mar 07 03:48:45 PM PST 24 |
6366046072 ps |
| T1222 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.926660369 |
|
|
Mar 07 03:53:01 PM PST 24 |
Mar 07 03:54:44 PM PST 24 |
2624574282 ps |
| T54 |
/workspace/coverage/default/2.chip_sw_alert_test.3619934594 |
|
|
Mar 07 03:54:28 PM PST 24 |
Mar 07 04:00:51 PM PST 24 |
3059026840 ps |
| T1223 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.4065823074 |
|
|
Mar 07 03:37:05 PM PST 24 |
Mar 07 03:42:10 PM PST 24 |
2798166556 ps |
| T1224 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.422972862 |
|
|
Mar 07 03:46:01 PM PST 24 |
Mar 07 03:51:22 PM PST 24 |
3413261130 ps |
| T1225 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.11912426 |
|
|
Mar 07 03:38:44 PM PST 24 |
Mar 07 03:46:27 PM PST 24 |
3396712358 ps |
| T1226 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1522048593 |
|
|
Mar 07 03:44:52 PM PST 24 |
Mar 07 04:02:02 PM PST 24 |
4666616753 ps |
| T1227 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3130433284 |
|
|
Mar 07 04:04:47 PM PST 24 |
Mar 07 04:14:44 PM PST 24 |
5948801876 ps |
| T1228 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3618778699 |
|
|
Mar 07 03:38:11 PM PST 24 |
Mar 07 03:40:58 PM PST 24 |
2878510303 ps |
| T1229 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2480832297 |
|
|
Mar 07 04:01:50 PM PST 24 |
Mar 07 04:10:14 PM PST 24 |
6720880440 ps |
| T1230 |
/workspace/coverage/default/2.chip_sw_example_flash.946705346 |
|
|
Mar 07 03:51:03 PM PST 24 |
Mar 07 03:55:42 PM PST 24 |
2635813960 ps |
| T1231 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.3271319438 |
|
|
Mar 07 03:54:10 PM PST 24 |
Mar 07 04:43:12 PM PST 24 |
23241336992 ps |
| T1232 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2763161336 |
|
|
Mar 07 03:56:43 PM PST 24 |
Mar 07 04:03:16 PM PST 24 |
4874932794 ps |
| T754 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.3074053022 |
|
|
Mar 07 04:02:38 PM PST 24 |
Mar 07 04:14:30 PM PST 24 |
6591896170 ps |
| T1233 |
/workspace/coverage/default/1.chip_sw_power_idle_load.2986197717 |
|
|
Mar 07 03:49:26 PM PST 24 |
Mar 07 04:03:05 PM PST 24 |
4131236024 ps |
| T757 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1302309697 |
|
|
Mar 07 04:06:06 PM PST 24 |
Mar 07 04:13:33 PM PST 24 |
3249009646 ps |
| T1234 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2818205720 |
|
|
Mar 07 04:07:08 PM PST 24 |
Mar 07 04:20:20 PM PST 24 |
6037465364 ps |
| T748 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2064092206 |
|
|
Mar 07 04:04:25 PM PST 24 |
Mar 07 04:11:43 PM PST 24 |
3817755240 ps |
| T767 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1791495445 |
|
|
Mar 07 04:04:04 PM PST 24 |
Mar 07 04:10:19 PM PST 24 |
3627592008 ps |
| T1235 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1154412380 |
|
|
Mar 07 03:42:49 PM PST 24 |
Mar 07 03:48:53 PM PST 24 |
4133963936 ps |
| T357 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3776108594 |
|
|
Mar 07 03:49:23 PM PST 24 |
Mar 07 04:02:50 PM PST 24 |
4926084048 ps |
| T1236 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.559084013 |
|
|
Mar 07 03:43:10 PM PST 24 |
Mar 07 04:12:31 PM PST 24 |
12168156822 ps |
| T1237 |
/workspace/coverage/default/0.chip_sw_aes_enc.1230672527 |
|
|
Mar 07 03:39:31 PM PST 24 |
Mar 07 03:44:55 PM PST 24 |
2880369312 ps |
| T1238 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1147371934 |
|
|
Mar 07 03:57:31 PM PST 24 |
Mar 07 04:05:28 PM PST 24 |
3947386992 ps |
| T8 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.843034364 |
|
|
Mar 07 03:40:04 PM PST 24 |
Mar 07 03:44:35 PM PST 24 |
2742910074 ps |
| T1239 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3461288869 |
|
|
Mar 07 04:02:53 PM PST 24 |
Mar 07 04:09:31 PM PST 24 |
3725199080 ps |
| T1240 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2856617640 |
|
|
Mar 07 03:52:44 PM PST 24 |
Mar 07 04:02:35 PM PST 24 |
4974395163 ps |
| T1241 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2940373096 |
|
|
Mar 07 03:54:51 PM PST 24 |
Mar 07 04:01:50 PM PST 24 |
3523138851 ps |
| T1242 |
/workspace/coverage/default/2.chip_sw_kmac_idle.213175646 |
|
|
Mar 07 03:55:54 PM PST 24 |
Mar 07 04:00:02 PM PST 24 |
2131588148 ps |
| T32 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1608606009 |
|
|
Mar 07 03:39:11 PM PST 24 |
Mar 07 03:43:56 PM PST 24 |
2485929788 ps |
| T692 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.831441702 |
|
|
Mar 07 03:58:18 PM PST 24 |
Mar 07 04:04:20 PM PST 24 |
4146883290 ps |
| T1243 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.667149754 |
|
|
Mar 07 04:08:01 PM PST 24 |
Mar 07 04:13:18 PM PST 24 |
3479464886 ps |
| T1244 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4032864407 |
|
|
Mar 07 03:54:04 PM PST 24 |
Mar 07 04:15:55 PM PST 24 |
8719973035 ps |
| T1245 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3161060251 |
|
|
Mar 07 03:36:58 PM PST 24 |
Mar 07 05:10:55 PM PST 24 |
49751356700 ps |
| T304 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.576973227 |
|
|
Mar 07 04:06:35 PM PST 24 |
Mar 07 04:15:17 PM PST 24 |
3924229352 ps |
| T55 |
/workspace/coverage/default/1.chip_sw_alert_test.667469855 |
|
|
Mar 07 03:45:35 PM PST 24 |
Mar 07 03:50:11 PM PST 24 |
2932678960 ps |
| T1246 |
/workspace/coverage/default/0.rom_e2e_static_critical.1825373181 |
|
|
Mar 07 03:43:02 PM PST 24 |
Mar 07 04:28:44 PM PST 24 |
10601381096 ps |
| T1247 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2769581012 |
|
|
Mar 07 03:44:53 PM PST 24 |
Mar 07 04:07:30 PM PST 24 |
11233777392 ps |
| T1248 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.3020875354 |
|
|
Mar 07 03:43:10 PM PST 24 |
Mar 07 03:48:02 PM PST 24 |
2377636510 ps |
| T1249 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3065571562 |
|
|
Mar 07 03:40:30 PM PST 24 |
Mar 07 03:50:46 PM PST 24 |
5302004082 ps |
| T1250 |
/workspace/coverage/default/2.chip_tap_straps_dev.3040358609 |
|
|
Mar 07 04:02:01 PM PST 24 |
Mar 07 04:04:13 PM PST 24 |
2728937059 ps |
| T255 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.436573908 |
|
|
Mar 07 04:03:59 PM PST 24 |
Mar 07 04:13:43 PM PST 24 |
5523440000 ps |
| T1251 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4287284655 |
|
|
Mar 07 03:44:09 PM PST 24 |
Mar 07 04:23:11 PM PST 24 |
7883042296 ps |
| T1252 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3262789258 |
|
|
Mar 07 04:00:54 PM PST 24 |
Mar 07 04:17:21 PM PST 24 |
5571925840 ps |
| T1253 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2453856187 |
|
|
Mar 07 03:50:19 PM PST 24 |
Mar 07 03:55:08 PM PST 24 |
2493062628 ps |
| T1254 |
/workspace/coverage/default/2.chip_tap_straps_rma.2902627019 |
|
|
Mar 07 03:56:08 PM PST 24 |
Mar 07 04:00:06 PM PST 24 |
2815154524 ps |
| T222 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.842232270 |
|
|
Mar 07 03:44:31 PM PST 24 |
Mar 07 05:01:12 PM PST 24 |
18084636950 ps |
| T1255 |
/workspace/coverage/default/1.rom_e2e_smoke.4023153358 |
|
|
Mar 07 03:50:08 PM PST 24 |
Mar 07 04:31:02 PM PST 24 |
9352785408 ps |
| T331 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2688080045 |
|
|
Mar 07 03:42:46 PM PST 24 |
Mar 07 04:00:07 PM PST 24 |
6005329300 ps |
| T1256 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2507286388 |
|
|
Mar 07 03:40:00 PM PST 24 |
Mar 07 03:55:23 PM PST 24 |
5605048260 ps |
| T1257 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2342012004 |
|
|
Mar 07 04:05:40 PM PST 24 |
Mar 07 04:12:02 PM PST 24 |
3758059560 ps |
| T1258 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.584349660 |
|
|
Mar 07 03:38:15 PM PST 24 |
Mar 07 03:44:07 PM PST 24 |
2840486340 ps |
| T1259 |
/workspace/coverage/default/4.chip_tap_straps_prod.470678301 |
|
|
Mar 07 04:00:43 PM PST 24 |
Mar 07 04:33:27 PM PST 24 |
18770452231 ps |
| T1260 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.491657832 |
|
|
Mar 07 03:40:40 PM PST 24 |
Mar 07 03:51:50 PM PST 24 |
3329109518 ps |
| T344 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2369500747 |
|
|
Mar 07 04:00:43 PM PST 24 |
Mar 07 04:13:04 PM PST 24 |
4324912856 ps |
| T1261 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2824894904 |
|
|
Mar 07 03:42:39 PM PST 24 |
Mar 07 03:46:45 PM PST 24 |
2701513094 ps |
| T1262 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.2128356325 |
|
|
Mar 07 03:39:11 PM PST 24 |
Mar 07 03:49:51 PM PST 24 |
4934940880 ps |
| T1263 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3488591846 |
|
|
Mar 07 03:44:48 PM PST 24 |
Mar 07 04:20:22 PM PST 24 |
9016124784 ps |
| T1264 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.1363446661 |
|
|
Mar 07 04:04:38 PM PST 24 |
Mar 07 04:15:10 PM PST 24 |
4835842204 ps |
| T1265 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.857569272 |
|
|
Mar 07 04:05:31 PM PST 24 |
Mar 07 04:16:09 PM PST 24 |
5053931120 ps |
| T1266 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.3004304465 |
|
|
Mar 07 03:52:22 PM PST 24 |
Mar 07 04:15:51 PM PST 24 |
7247903116 ps |
| T1267 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3210030010 |
|
|
Mar 07 03:57:41 PM PST 24 |
Mar 07 04:08:13 PM PST 24 |
4202987920 ps |
| T1268 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2250019351 |
|
|
Mar 07 03:48:03 PM PST 24 |
Mar 07 03:54:54 PM PST 24 |
3011583368 ps |
| T1269 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.37904474 |
|
|
Mar 07 04:01:17 PM PST 24 |
Mar 07 04:08:19 PM PST 24 |
6508865604 ps |
| T1270 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2527928146 |
|
|
Mar 07 03:54:45 PM PST 24 |
Mar 07 04:31:19 PM PST 24 |
8920054110 ps |
| T1271 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2964059178 |
|
|
Mar 07 03:59:43 PM PST 24 |
Mar 07 04:13:47 PM PST 24 |
5241645168 ps |
| T346 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.586178120 |
|
|
Mar 07 04:03:17 PM PST 24 |
Mar 07 04:15:22 PM PST 24 |
5383945300 ps |
| T1272 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1827321917 |
|
|
Mar 07 03:40:19 PM PST 24 |
Mar 07 03:50:32 PM PST 24 |
5605316807 ps |
| T1273 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.641736968 |
|
|
Mar 07 03:42:47 PM PST 24 |
Mar 07 04:09:40 PM PST 24 |
6624320488 ps |
| T1274 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.4204699140 |
|
|
Mar 07 03:42:44 PM PST 24 |
Mar 07 04:30:45 PM PST 24 |
12086842520 ps |
| T1275 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1154898382 |
|
|
Mar 07 04:03:28 PM PST 24 |
Mar 07 04:17:31 PM PST 24 |
12835471621 ps |
| T1276 |
/workspace/coverage/default/0.chip_sw_hmac_enc.3625686759 |
|
|
Mar 07 03:39:11 PM PST 24 |
Mar 07 03:44:20 PM PST 24 |
2768781070 ps |
| T320 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.2916567441 |
|
|
Mar 07 03:46:17 PM PST 24 |
Mar 07 04:09:25 PM PST 24 |
6733823360 ps |
| T75 |
/workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.785857670 |
|
|
Mar 07 04:20:33 PM PST 24 |
Mar 07 04:21:09 PM PST 24 |
393240590 ps |
| T57 |
/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.433156082 |
|
|
Mar 07 04:06:25 PM PST 24 |
Mar 07 04:10:26 PM PST 24 |
5157054368 ps |
| T76 |
/workspace/coverage/cover_reg_top/43.xbar_access_same_device.2520274112 |
|
|
Mar 07 04:16:49 PM PST 24 |
Mar 07 04:18:00 PM PST 24 |
1679344431 ps |
| T79 |
/workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.3902407181 |
|
|
Mar 07 04:19:31 PM PST 24 |
Mar 07 04:19:37 PM PST 24 |
43818112 ps |
| T107 |
/workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.3865401345 |
|
|
Mar 07 04:14:02 PM PST 24 |
Mar 07 04:16:14 PM PST 24 |
7101631858 ps |
| T80 |
/workspace/coverage/cover_reg_top/28.xbar_error_random.1923735217 |
|
|
Mar 07 04:14:19 PM PST 24 |
Mar 07 04:14:53 PM PST 24 |
314039945 ps |
| T241 |
/workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2600912266 |
|
|
Mar 07 04:15:56 PM PST 24 |
Mar 07 04:16:03 PM PST 24 |
37314553 ps |
| T157 |
/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3580636765 |
|
|
Mar 07 04:14:10 PM PST 24 |
Mar 07 04:16:20 PM PST 24 |
355291404 ps |
| T428 |
/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.3351238535 |
|
|
Mar 07 04:11:18 PM PST 24 |
Mar 07 04:12:20 PM PST 24 |
3604237994 ps |
| T532 |
/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.23272803 |
|
|
Mar 07 04:23:17 PM PST 24 |
Mar 07 04:24:23 PM PST 24 |
163288211 ps |
| T427 |
/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.3370349004 |
|
|
Mar 07 04:18:58 PM PST 24 |
Mar 07 04:20:19 PM PST 24 |
1928112009 ps |
| T522 |
/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.778866754 |
|
|
Mar 07 04:19:09 PM PST 24 |
Mar 07 04:23:07 PM PST 24 |
7445955828 ps |
| T430 |
/workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3968155922 |
|
|
Mar 07 04:19:52 PM PST 24 |
Mar 07 04:47:13 PM PST 24 |
94496211118 ps |
| T433 |
/workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.3391786138 |
|
|
Mar 07 04:18:07 PM PST 24 |
Mar 07 04:38:00 PM PST 24 |
64439432364 ps |
| T520 |
/workspace/coverage/cover_reg_top/25.xbar_access_same_device.414975771 |
|
|
Mar 07 04:13:51 PM PST 24 |
Mar 07 04:15:05 PM PST 24 |
918881356 ps |
| T501 |
/workspace/coverage/cover_reg_top/25.xbar_same_source.488777744 |
|
|
Mar 07 04:13:47 PM PST 24 |
Mar 07 04:14:14 PM PST 24 |
307726856 ps |
| T171 |
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.2322730932 |
|
|
Mar 07 04:02:32 PM PST 24 |
Mar 07 05:29:52 PM PST 24 |
34004755250 ps |
| T431 |
/workspace/coverage/cover_reg_top/87.xbar_same_source.2912019151 |
|
|
Mar 07 04:22:51 PM PST 24 |
Mar 07 04:23:45 PM PST 24 |
1563174744 ps |
| T523 |
/workspace/coverage/cover_reg_top/32.xbar_random_large_delays.4249910906 |
|
|
Mar 07 04:15:07 PM PST 24 |
Mar 07 04:25:35 PM PST 24 |
49448705736 ps |
| T521 |
/workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1538783274 |
|
|
Mar 07 04:17:50 PM PST 24 |
Mar 07 04:35:47 PM PST 24 |
60019600108 ps |
| T854 |
/workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.3991602708 |
|
|
Mar 07 04:23:53 PM PST 24 |
Mar 07 04:25:32 PM PST 24 |
8514375635 ps |
| T525 |
/workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2531410245 |
|
|
Mar 07 04:21:42 PM PST 24 |
Mar 07 04:23:19 PM PST 24 |
8491716956 ps |
| T526 |
/workspace/coverage/cover_reg_top/64.xbar_random.1266752975 |
|
|
Mar 07 04:19:39 PM PST 24 |
Mar 07 04:20:05 PM PST 24 |
225247448 ps |
| T819 |
/workspace/coverage/cover_reg_top/51.xbar_access_same_device.3591370929 |
|
|
Mar 07 04:17:59 PM PST 24 |
Mar 07 04:18:21 PM PST 24 |
220001191 ps |
| T533 |
/workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.313212028 |
|
|
Mar 07 04:20:07 PM PST 24 |
Mar 07 04:21:47 PM PST 24 |
5686585436 ps |
| T531 |
/workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.1289780542 |
|
|
Mar 07 04:24:07 PM PST 24 |
Mar 07 04:24:19 PM PST 24 |
209587176 ps |
| T519 |
/workspace/coverage/cover_reg_top/31.xbar_access_same_device.2560636790 |
|
|
Mar 07 04:14:57 PM PST 24 |
Mar 07 04:15:52 PM PST 24 |
1166531253 ps |
| T359 |
/workspace/coverage/cover_reg_top/2.chip_csr_aliasing.4036581742 |
|
|
Mar 07 04:04:19 PM PST 24 |
Mar 07 05:17:09 PM PST 24 |
33762017836 ps |
| T633 |
/workspace/coverage/cover_reg_top/18.xbar_smoke.109610670 |
|
|
Mar 07 04:11:47 PM PST 24 |
Mar 07 04:11:57 PM PST 24 |
211404011 ps |
| T534 |
/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.564289066 |
|
|
Mar 07 04:18:25 PM PST 24 |
Mar 07 04:23:11 PM PST 24 |
809145259 ps |
| T524 |
/workspace/coverage/cover_reg_top/92.xbar_same_source.887153882 |
|
|
Mar 07 04:23:26 PM PST 24 |
Mar 07 04:24:05 PM PST 24 |
1113374085 ps |
| T478 |
/workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.102309689 |
|
|
Mar 07 04:06:03 PM PST 24 |
Mar 07 04:06:20 PM PST 24 |
117392196 ps |
| T776 |
/workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.3732714997 |
|
|
Mar 07 04:22:42 PM PST 24 |
Mar 07 04:40:12 PM PST 24 |
62218177570 ps |
| T454 |
/workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1008259308 |
|
|
Mar 07 04:19:11 PM PST 24 |
Mar 07 04:37:02 PM PST 24 |
58201250521 ps |
| T777 |
/workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2200427776 |
|
|
Mar 07 04:19:12 PM PST 24 |
Mar 07 04:39:31 PM PST 24 |
70829457220 ps |
| T528 |
/workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2410836186 |
|
|
Mar 07 04:23:13 PM PST 24 |
Mar 07 04:23:57 PM PST 24 |
1220707861 ps |
| T172 |
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3532060388 |
|
|
Mar 07 04:03:36 PM PST 24 |
Mar 07 04:32:58 PM PST 24 |
17968363648 ps |
| T535 |
/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.2608277612 |
|
|
Mar 07 04:17:26 PM PST 24 |
Mar 07 04:17:58 PM PST 24 |
315843255 ps |
| T1277 |
/workspace/coverage/cover_reg_top/12.xbar_smoke.2633274893 |
|
|
Mar 07 04:09:53 PM PST 24 |
Mar 07 04:10:01 PM PST 24 |
177614648 ps |
| T529 |
/workspace/coverage/cover_reg_top/10.xbar_same_source.724163133 |
|
|
Mar 07 04:09:16 PM PST 24 |
Mar 07 04:09:31 PM PST 24 |
351657528 ps |
| T530 |
/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1691034333 |
|
|
Mar 07 04:04:57 PM PST 24 |
Mar 07 04:06:42 PM PST 24 |
2737648501 ps |
| T453 |
/workspace/coverage/cover_reg_top/95.xbar_random.1472342727 |
|
|
Mar 07 04:23:54 PM PST 24 |
Mar 07 04:24:23 PM PST 24 |
258218414 ps |
| T527 |
/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.145716289 |
|
|
Mar 07 04:19:19 PM PST 24 |
Mar 07 04:27:17 PM PST 24 |
4754211849 ps |
| T1278 |
/workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.3279614631 |
|
|
Mar 07 04:16:25 PM PST 24 |
Mar 07 04:17:55 PM PST 24 |
7645024875 ps |
| T441 |
/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.549011176 |
|
|
Mar 07 04:13:15 PM PST 24 |
Mar 07 04:27:44 PM PST 24 |
16900293741 ps |
| T1279 |
/workspace/coverage/cover_reg_top/26.xbar_same_source.3061669959 |
|
|
Mar 07 04:14:01 PM PST 24 |
Mar 07 04:14:11 PM PST 24 |
80813875 ps |
| T432 |
/workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.2063975870 |
|
|
Mar 07 04:21:07 PM PST 24 |
Mar 07 04:39:21 PM PST 24 |
62922091896 ps |
| T173 |
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3136505809 |
|
|
Mar 07 04:10:08 PM PST 24 |
Mar 07 05:00:56 PM PST 24 |
27057367962 ps |
| T624 |
/workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.4225596588 |
|
|
Mar 07 04:16:49 PM PST 24 |
Mar 07 04:17:02 PM PST 24 |
94382690 ps |
| T1280 |
/workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.4029817475 |
|
|
Mar 07 04:16:05 PM PST 24 |
Mar 07 04:16:42 PM PST 24 |
820725779 ps |
| T552 |
/workspace/coverage/cover_reg_top/40.xbar_random.2751530895 |
|
|
Mar 07 04:16:19 PM PST 24 |
Mar 07 04:17:19 PM PST 24 |
1354891606 ps |
| T503 |
/workspace/coverage/cover_reg_top/72.xbar_random_large_delays.1038235136 |
|
|
Mar 07 04:20:50 PM PST 24 |
Mar 07 04:38:24 PM PST 24 |
99050867751 ps |
| T555 |
/workspace/coverage/cover_reg_top/78.xbar_same_source.141370398 |
|
|
Mar 07 04:21:37 PM PST 24 |
Mar 07 04:22:38 PM PST 24 |
1875520944 ps |
| T1281 |
/workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.1700330732 |
|
|
Mar 07 04:05:15 PM PST 24 |
Mar 07 04:06:25 PM PST 24 |
4071780064 ps |
| T1282 |
/workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.3438727472 |
|
|
Mar 07 04:14:01 PM PST 24 |
Mar 07 04:14:10 PM PST 24 |
65415257 ps |
| T629 |
/workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2027771088 |
|
|
Mar 07 04:19:22 PM PST 24 |
Mar 07 04:19:29 PM PST 24 |
50029200 ps |
| T578 |
/workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.3642811595 |
|
|
Mar 07 04:12:00 PM PST 24 |
Mar 07 04:12:17 PM PST 24 |
109338077 ps |