| T1003 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.506872361 |
|
|
Mar 07 03:43:33 PM PST 24 |
Mar 07 04:14:34 PM PST 24 |
8311294729 ps |
| T1004 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3242423687 |
|
|
Mar 07 04:03:59 PM PST 24 |
Mar 07 04:44:23 PM PST 24 |
13886154480 ps |
| T1005 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.922060577 |
|
|
Mar 07 03:46:53 PM PST 24 |
Mar 07 03:57:40 PM PST 24 |
4153544200 ps |
| T1006 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.2790301932 |
|
|
Mar 07 03:56:16 PM PST 24 |
Mar 07 04:05:21 PM PST 24 |
4715610400 ps |
| T226 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1989643484 |
|
|
Mar 07 03:40:34 PM PST 24 |
Mar 07 05:12:27 PM PST 24 |
49794708832 ps |
| T1007 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.891846933 |
|
|
Mar 07 04:01:50 PM PST 24 |
Mar 07 04:10:25 PM PST 24 |
4356565100 ps |
| T1008 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.66477636 |
|
|
Mar 07 03:45:38 PM PST 24 |
Mar 07 03:55:18 PM PST 24 |
5288446672 ps |
| T1009 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3632101793 |
|
|
Mar 07 03:39:55 PM PST 24 |
Mar 07 03:50:33 PM PST 24 |
4966127430 ps |
| T727 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.479997453 |
|
|
Mar 07 04:06:55 PM PST 24 |
Mar 07 04:16:06 PM PST 24 |
4399719400 ps |
| T1010 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.2840417646 |
|
|
Mar 07 03:52:02 PM PST 24 |
Mar 07 04:10:21 PM PST 24 |
5777909218 ps |
| T292 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1711663079 |
|
|
Mar 07 03:48:41 PM PST 24 |
Mar 07 03:52:41 PM PST 24 |
2138297888 ps |
| T280 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2187991512 |
|
|
Mar 07 03:38:26 PM PST 24 |
Mar 07 03:49:32 PM PST 24 |
5556798728 ps |
| T1011 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2620787377 |
|
|
Mar 07 03:52:29 PM PST 24 |
Mar 07 03:57:16 PM PST 24 |
3386722650 ps |
| T230 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2509325179 |
|
|
Mar 07 03:39:47 PM PST 24 |
Mar 07 04:09:45 PM PST 24 |
21408952133 ps |
| T301 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3938493689 |
|
|
Mar 07 04:08:52 PM PST 24 |
Mar 07 04:19:10 PM PST 24 |
5488320872 ps |
| T1012 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.1413920422 |
|
|
Mar 07 03:45:10 PM PST 24 |
Mar 07 03:49:25 PM PST 24 |
2509664430 ps |
| T421 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1998018393 |
|
|
Mar 07 03:54:52 PM PST 24 |
Mar 07 04:30:55 PM PST 24 |
9174691400 ps |
| T751 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3244449086 |
|
|
Mar 07 04:07:21 PM PST 24 |
Mar 07 04:15:39 PM PST 24 |
5045238552 ps |
| T138 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1799382311 |
|
|
Mar 07 03:39:24 PM PST 24 |
Mar 07 03:42:16 PM PST 24 |
3160743936 ps |
| T657 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3029880868 |
|
|
Mar 07 03:36:20 PM PST 24 |
Mar 07 03:38:54 PM PST 24 |
3521247687 ps |
| T1013 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.42156607 |
|
|
Mar 07 03:57:24 PM PST 24 |
Mar 07 04:09:49 PM PST 24 |
4631043944 ps |
| T316 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3640537736 |
|
|
Mar 07 03:42:31 PM PST 24 |
Mar 07 03:52:30 PM PST 24 |
3587796838 ps |
| T680 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2118799901 |
|
|
Mar 07 03:37:54 PM PST 24 |
Mar 07 03:45:54 PM PST 24 |
4684788954 ps |
| T725 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3114990951 |
|
|
Mar 07 04:07:35 PM PST 24 |
Mar 07 04:19:29 PM PST 24 |
4431632192 ps |
| T750 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3914287759 |
|
|
Mar 07 04:09:16 PM PST 24 |
Mar 07 04:21:22 PM PST 24 |
6346190848 ps |
| T1014 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1313485613 |
|
|
Mar 07 03:53:42 PM PST 24 |
Mar 07 04:08:47 PM PST 24 |
11677960380 ps |
| T1015 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.624731208 |
|
|
Mar 07 03:37:16 PM PST 24 |
Mar 07 03:53:20 PM PST 24 |
6414127620 ps |
| T1016 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.241290542 |
|
|
Mar 07 04:04:16 PM PST 24 |
Mar 07 04:19:58 PM PST 24 |
5691182116 ps |
| T737 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.3020713589 |
|
|
Mar 07 04:06:08 PM PST 24 |
Mar 07 04:16:51 PM PST 24 |
5312125450 ps |
| T1017 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.795961414 |
|
|
Mar 07 03:55:54 PM PST 24 |
Mar 07 03:59:21 PM PST 24 |
2604328200 ps |
| T1018 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.2035384374 |
|
|
Mar 07 03:42:36 PM PST 24 |
Mar 07 04:13:12 PM PST 24 |
8398782600 ps |
| T1019 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1073871667 |
|
|
Mar 07 04:03:06 PM PST 24 |
Mar 07 04:09:35 PM PST 24 |
4355553084 ps |
| T1020 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3889501974 |
|
|
Mar 07 03:40:07 PM PST 24 |
Mar 07 03:44:28 PM PST 24 |
3038673864 ps |
| T348 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.931044933 |
|
|
Mar 07 04:05:55 PM PST 24 |
Mar 07 04:18:00 PM PST 24 |
4252195070 ps |
| T409 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.797114073 |
|
|
Mar 07 04:07:24 PM PST 24 |
Mar 07 04:17:31 PM PST 24 |
5250871240 ps |
| T78 |
/workspace/coverage/default/1.chip_jtag_mem_access.2411152244 |
|
|
Mar 07 03:41:00 PM PST 24 |
Mar 07 04:08:20 PM PST 24 |
13176101976 ps |
| T337 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1835997202 |
|
|
Mar 07 03:39:20 PM PST 24 |
Mar 07 03:52:26 PM PST 24 |
4162015427 ps |
| T376 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.419321206 |
|
|
Mar 07 03:44:32 PM PST 24 |
Mar 07 04:36:38 PM PST 24 |
12099335432 ps |
| T355 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2965192828 |
|
|
Mar 07 03:38:06 PM PST 24 |
Mar 07 04:32:34 PM PST 24 |
38883380413 ps |
| T1021 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1608043186 |
|
|
Mar 07 03:48:44 PM PST 24 |
Mar 07 03:53:32 PM PST 24 |
3441619301 ps |
| T1022 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1671937661 |
|
|
Mar 07 03:38:05 PM PST 24 |
Mar 07 03:41:32 PM PST 24 |
2717377320 ps |
| T752 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3096884717 |
|
|
Mar 07 04:07:35 PM PST 24 |
Mar 07 04:14:39 PM PST 24 |
3781787320 ps |
| T221 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2750413775 |
|
|
Mar 07 03:37:19 PM PST 24 |
Mar 07 04:44:16 PM PST 24 |
14343216600 ps |
| T648 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.2892987992 |
|
|
Mar 07 03:39:14 PM PST 24 |
Mar 07 03:44:51 PM PST 24 |
3554705057 ps |
| T766 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1891149374 |
|
|
Mar 07 04:03:08 PM PST 24 |
Mar 07 04:11:19 PM PST 24 |
4226604170 ps |
| T251 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.3328985357 |
|
|
Mar 07 04:03:42 PM PST 24 |
Mar 07 04:12:55 PM PST 24 |
4499255458 ps |
| T182 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2471160227 |
|
|
Mar 07 03:38:15 PM PST 24 |
Mar 07 03:46:39 PM PST 24 |
4763951890 ps |
| T228 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1448341145 |
|
|
Mar 07 03:41:33 PM PST 24 |
Mar 07 03:52:58 PM PST 24 |
5414988250 ps |
| T1023 |
/workspace/coverage/default/2.chip_sw_example_concurrency.3965944489 |
|
|
Mar 07 03:52:33 PM PST 24 |
Mar 07 03:57:09 PM PST 24 |
2379727910 ps |
| T1024 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.284695120 |
|
|
Mar 07 03:37:32 PM PST 24 |
Mar 07 04:23:43 PM PST 24 |
28123091876 ps |
| T1025 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3569244000 |
|
|
Mar 07 03:37:07 PM PST 24 |
Mar 07 04:02:43 PM PST 24 |
9446329980 ps |
| T1026 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2166376082 |
|
|
Mar 07 03:37:58 PM PST 24 |
Mar 07 03:47:39 PM PST 24 |
4247741768 ps |
| T1027 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3592830306 |
|
|
Mar 07 03:39:35 PM PST 24 |
Mar 07 03:59:27 PM PST 24 |
9638637405 ps |
| T658 |
/workspace/coverage/default/2.chip_sw_power_idle_load.3390823665 |
|
|
Mar 07 03:59:23 PM PST 24 |
Mar 07 04:12:11 PM PST 24 |
4416945500 ps |
| T147 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.1948317335 |
|
|
Mar 07 03:39:21 PM PST 24 |
Mar 07 03:48:19 PM PST 24 |
11182930952 ps |
| T1028 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3573046127 |
|
|
Mar 07 03:46:35 PM PST 24 |
Mar 07 04:47:28 PM PST 24 |
16814268000 ps |
| T1029 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.4151678665 |
|
|
Mar 07 03:41:36 PM PST 24 |
Mar 07 04:04:37 PM PST 24 |
7537256894 ps |
| T1030 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2503489133 |
|
|
Mar 07 04:01:39 PM PST 24 |
Mar 07 04:11:17 PM PST 24 |
5579763805 ps |
| T715 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2692473906 |
|
|
Mar 07 04:05:31 PM PST 24 |
Mar 07 04:12:47 PM PST 24 |
3563880816 ps |
| T1031 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.71370269 |
|
|
Mar 07 04:03:22 PM PST 24 |
Mar 07 04:50:32 PM PST 24 |
14187670380 ps |
| T168 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3599888697 |
|
|
Mar 07 03:56:33 PM PST 24 |
Mar 07 04:00:48 PM PST 24 |
2794692418 ps |
| T1032 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.702440629 |
|
|
Mar 07 04:05:43 PM PST 24 |
Mar 07 04:15:11 PM PST 24 |
6350971426 ps |
| T1033 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1889102597 |
|
|
Mar 07 03:54:46 PM PST 24 |
Mar 07 04:02:24 PM PST 24 |
6858423192 ps |
| T83 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1293891819 |
|
|
Mar 07 03:43:32 PM PST 24 |
Mar 07 03:50:32 PM PST 24 |
3158794393 ps |
| T252 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1104923752 |
|
|
Mar 07 03:42:11 PM PST 24 |
Mar 07 03:52:08 PM PST 24 |
7071013592 ps |
| T349 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1880077492 |
|
|
Mar 07 04:08:50 PM PST 24 |
Mar 07 04:20:35 PM PST 24 |
5498521240 ps |
| T253 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3834213228 |
|
|
Mar 07 03:37:26 PM PST 24 |
Mar 07 03:50:04 PM PST 24 |
6124634996 ps |
| T1034 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.3150242091 |
|
|
Mar 07 03:56:51 PM PST 24 |
Mar 07 04:00:53 PM PST 24 |
3372468284 ps |
| T1035 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3645881012 |
|
|
Mar 07 03:47:50 PM PST 24 |
Mar 07 03:59:51 PM PST 24 |
4445501180 ps |
| T1036 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3579231887 |
|
|
Mar 07 04:00:37 PM PST 24 |
Mar 07 04:05:19 PM PST 24 |
2315972608 ps |
| T281 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.235714402 |
|
|
Mar 07 03:56:19 PM PST 24 |
Mar 07 04:05:06 PM PST 24 |
3742210312 ps |
| T1037 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.869347021 |
|
|
Mar 07 04:02:46 PM PST 24 |
Mar 07 04:31:20 PM PST 24 |
14260287665 ps |
| T1038 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1337634144 |
|
|
Mar 07 03:52:55 PM PST 24 |
Mar 07 03:54:49 PM PST 24 |
2447760444 ps |
| T1039 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.209065320 |
|
|
Mar 07 03:41:16 PM PST 24 |
Mar 07 04:04:53 PM PST 24 |
7923097016 ps |
| T1040 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3899222306 |
|
|
Mar 07 03:42:26 PM PST 24 |
Mar 07 04:23:56 PM PST 24 |
8481681692 ps |
| T733 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3821333250 |
|
|
Mar 07 04:02:10 PM PST 24 |
Mar 07 04:09:38 PM PST 24 |
3665888942 ps |
| T1041 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1460067750 |
|
|
Mar 07 03:48:33 PM PST 24 |
Mar 07 04:07:40 PM PST 24 |
7297733823 ps |
| T1042 |
/workspace/coverage/default/1.chip_sw_example_flash.2512927491 |
|
|
Mar 07 03:40:47 PM PST 24 |
Mar 07 03:43:44 PM PST 24 |
2950552500 ps |
| T719 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3888418785 |
|
|
Mar 07 04:11:08 PM PST 24 |
Mar 07 04:22:04 PM PST 24 |
5955007904 ps |
| T59 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2196722070 |
|
|
Mar 07 04:01:39 PM PST 24 |
Mar 07 04:07:51 PM PST 24 |
4434306060 ps |
| T1043 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1174721737 |
|
|
Mar 07 04:02:00 PM PST 24 |
Mar 07 04:09:04 PM PST 24 |
3706644440 ps |
| T423 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.591289820 |
|
|
Mar 07 03:43:28 PM PST 24 |
Mar 07 04:03:07 PM PST 24 |
5564816170 ps |
| T1044 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2909148041 |
|
|
Mar 07 04:03:54 PM PST 24 |
Mar 07 04:41:25 PM PST 24 |
9228110808 ps |
| T1045 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.1369095675 |
|
|
Mar 07 04:03:34 PM PST 24 |
Mar 07 04:13:18 PM PST 24 |
5443437002 ps |
| T1046 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1601136552 |
|
|
Mar 07 04:02:49 PM PST 24 |
Mar 07 04:27:21 PM PST 24 |
7521140951 ps |
| T302 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.533316856 |
|
|
Mar 07 04:08:08 PM PST 24 |
Mar 07 04:19:38 PM PST 24 |
4709375600 ps |
| T1047 |
/workspace/coverage/default/2.chip_tap_straps_prod.3140214686 |
|
|
Mar 07 03:57:11 PM PST 24 |
Mar 07 04:00:27 PM PST 24 |
3112678152 ps |
| T350 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.230027304 |
|
|
Mar 07 04:01:20 PM PST 24 |
Mar 07 04:11:11 PM PST 24 |
4585436592 ps |
| T338 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2104187940 |
|
|
Mar 07 03:40:05 PM PST 24 |
Mar 07 03:53:22 PM PST 24 |
5087505695 ps |
| T1048 |
/workspace/coverage/default/3.chip_tap_straps_dev.1945454475 |
|
|
Mar 07 04:00:13 PM PST 24 |
Mar 07 04:02:47 PM PST 24 |
2459108311 ps |
| T1049 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1385924121 |
|
|
Mar 07 03:53:49 PM PST 24 |
Mar 07 04:43:56 PM PST 24 |
26519047770 ps |
| T1050 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.236508205 |
|
|
Mar 07 03:39:38 PM PST 24 |
Mar 07 03:51:56 PM PST 24 |
4812124236 ps |
| T60 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1906391243 |
|
|
Mar 07 03:51:00 PM PST 24 |
Mar 07 03:55:45 PM PST 24 |
5483263128 ps |
| T34 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.2012386511 |
|
|
Mar 07 03:37:11 PM PST 24 |
Mar 07 03:43:51 PM PST 24 |
3594089973 ps |
| T1051 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2732911835 |
|
|
Mar 07 03:59:21 PM PST 24 |
Mar 07 04:29:10 PM PST 24 |
10415694235 ps |
| T1052 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3156264972 |
|
|
Mar 07 03:52:08 PM PST 24 |
Mar 07 03:59:13 PM PST 24 |
5714084452 ps |
| T1053 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.4107574800 |
|
|
Mar 07 03:38:06 PM PST 24 |
Mar 07 03:47:25 PM PST 24 |
5035916872 ps |
| T217 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2426885261 |
|
|
Mar 07 03:57:47 PM PST 24 |
Mar 07 04:08:51 PM PST 24 |
5073707726 ps |
| T1054 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1781535648 |
|
|
Mar 07 03:47:19 PM PST 24 |
Mar 07 03:57:54 PM PST 24 |
5628272520 ps |
| T1055 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1081917622 |
|
|
Mar 07 03:54:46 PM PST 24 |
Mar 07 04:05:21 PM PST 24 |
4510807445 ps |
| T1056 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2438382195 |
|
|
Mar 07 03:39:39 PM PST 24 |
Mar 07 03:54:01 PM PST 24 |
5824394300 ps |
| T1057 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.1752864840 |
|
|
Mar 07 03:38:36 PM PST 24 |
Mar 07 03:51:33 PM PST 24 |
7140734584 ps |
| T1058 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.507739638 |
|
|
Mar 07 03:58:33 PM PST 24 |
Mar 07 04:09:03 PM PST 24 |
5198323710 ps |
| T160 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3905028824 |
|
|
Mar 07 03:37:59 PM PST 24 |
Mar 07 03:45:06 PM PST 24 |
5355510178 ps |
| T1059 |
/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.3076690181 |
|
|
Mar 07 04:04:43 PM PST 24 |
Mar 07 04:38:44 PM PST 24 |
8668581740 ps |
| T377 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.353927325 |
|
|
Mar 07 03:47:17 PM PST 24 |
Mar 07 04:46:41 PM PST 24 |
12003393970 ps |
| T329 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.151057551 |
|
|
Mar 07 03:37:54 PM PST 24 |
Mar 07 03:41:55 PM PST 24 |
2956457560 ps |
| T1060 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2200289943 |
|
|
Mar 07 03:42:27 PM PST 24 |
Mar 07 04:35:39 PM PST 24 |
11476833587 ps |
| T726 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1825442872 |
|
|
Mar 07 03:38:21 PM PST 24 |
Mar 07 03:49:24 PM PST 24 |
4963600262 ps |
| T1061 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.4177851921 |
|
|
Mar 07 03:51:30 PM PST 24 |
Mar 07 03:56:30 PM PST 24 |
2542119168 ps |
| T1062 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3330532722 |
|
|
Mar 07 04:04:15 PM PST 24 |
Mar 07 04:15:59 PM PST 24 |
5277799280 ps |
| T345 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3456717150 |
|
|
Mar 07 04:03:28 PM PST 24 |
Mar 07 04:17:43 PM PST 24 |
4640124874 ps |
| T1063 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.308247970 |
|
|
Mar 07 03:57:11 PM PST 24 |
Mar 07 04:17:29 PM PST 24 |
5560996229 ps |
| T6 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3502218667 |
|
|
Mar 07 03:38:18 PM PST 24 |
Mar 07 03:42:22 PM PST 24 |
2964612393 ps |
| T1064 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.3537833334 |
|
|
Mar 07 04:02:42 PM PST 24 |
Mar 07 04:38:33 PM PST 24 |
8900356472 ps |
| T1065 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.711247828 |
|
|
Mar 07 03:57:58 PM PST 24 |
Mar 07 04:05:49 PM PST 24 |
6240056056 ps |
| T1066 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3252293234 |
|
|
Mar 07 03:38:53 PM PST 24 |
Mar 07 03:52:15 PM PST 24 |
6982296570 ps |
| T1067 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3019065807 |
|
|
Mar 07 03:52:55 PM PST 24 |
Mar 07 04:39:17 PM PST 24 |
25972073420 ps |
| T1068 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3520437296 |
|
|
Mar 07 03:57:16 PM PST 24 |
Mar 07 04:07:04 PM PST 24 |
5118200024 ps |
| T1069 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.490830577 |
|
|
Mar 07 03:36:50 PM PST 24 |
Mar 07 03:53:35 PM PST 24 |
5959095682 ps |
| T1070 |
/workspace/coverage/default/1.chip_tap_straps_prod.2110513480 |
|
|
Mar 07 03:50:10 PM PST 24 |
Mar 07 04:07:49 PM PST 24 |
10690899376 ps |
| T1071 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.142563326 |
|
|
Mar 07 03:55:41 PM PST 24 |
Mar 07 04:01:17 PM PST 24 |
2997227507 ps |
| T1072 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.535332036 |
|
|
Mar 07 03:41:49 PM PST 24 |
Mar 07 03:49:59 PM PST 24 |
4697456120 ps |
| T183 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2534366368 |
|
|
Mar 07 03:53:17 PM PST 24 |
Mar 07 04:01:12 PM PST 24 |
4403932202 ps |
| T1073 |
/workspace/coverage/default/1.chip_sw_edn_kat.353188944 |
|
|
Mar 07 03:42:44 PM PST 24 |
Mar 07 03:53:12 PM PST 24 |
3377459902 ps |
| T1074 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3443754793 |
|
|
Mar 07 04:03:07 PM PST 24 |
Mar 07 04:10:47 PM PST 24 |
3727344360 ps |
| T746 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.503085907 |
|
|
Mar 07 04:05:42 PM PST 24 |
Mar 07 04:20:39 PM PST 24 |
5053910000 ps |
| T1075 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3933163156 |
|
|
Mar 07 03:40:54 PM PST 24 |
Mar 07 03:50:43 PM PST 24 |
5051871432 ps |
| T303 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3856579802 |
|
|
Mar 07 04:04:35 PM PST 24 |
Mar 07 04:16:21 PM PST 24 |
5664565320 ps |
| T53 |
/workspace/coverage/default/0.chip_sw_alert_test.1394944814 |
|
|
Mar 07 03:37:26 PM PST 24 |
Mar 07 03:42:46 PM PST 24 |
3235675748 ps |
| T1076 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3843693763 |
|
|
Mar 07 04:01:06 PM PST 24 |
Mar 07 04:11:51 PM PST 24 |
8981073787 ps |
| T1077 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3055335883 |
|
|
Mar 07 03:38:13 PM PST 24 |
Mar 07 03:54:22 PM PST 24 |
5539430172 ps |
| T1078 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3925142274 |
|
|
Mar 07 03:52:30 PM PST 24 |
Mar 07 04:09:05 PM PST 24 |
6248806399 ps |
| T87 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3171061622 |
|
|
Mar 07 04:07:46 PM PST 24 |
Mar 07 04:23:09 PM PST 24 |
6543106050 ps |
| T367 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.581164669 |
|
|
Mar 07 03:57:36 PM PST 24 |
Mar 07 04:07:22 PM PST 24 |
4667545400 ps |
| T728 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.1851804223 |
|
|
Mar 07 03:57:01 PM PST 24 |
Mar 07 04:14:14 PM PST 24 |
7125206580 ps |
| T756 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.2449504003 |
|
|
Mar 07 03:40:24 PM PST 24 |
Mar 07 03:54:03 PM PST 24 |
4548183220 ps |
| T1079 |
/workspace/coverage/default/0.chip_sw_flash_init.4246539257 |
|
|
Mar 07 03:37:28 PM PST 24 |
Mar 07 04:14:10 PM PST 24 |
23462637732 ps |
| T745 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.1202847756 |
|
|
Mar 07 04:01:48 PM PST 24 |
Mar 07 04:11:38 PM PST 24 |
4341955260 ps |
| T1080 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.2085928538 |
|
|
Mar 07 04:01:58 PM PST 24 |
Mar 07 04:13:28 PM PST 24 |
4709544616 ps |
| T1081 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2894549945 |
|
|
Mar 07 03:56:15 PM PST 24 |
Mar 07 04:18:57 PM PST 24 |
7692485900 ps |
| T240 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1665825550 |
|
|
Mar 07 04:06:04 PM PST 24 |
Mar 07 04:11:09 PM PST 24 |
3936972186 ps |
| T1082 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.389501529 |
|
|
Mar 07 03:43:08 PM PST 24 |
Mar 07 03:49:28 PM PST 24 |
8921808786 ps |
| T293 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3544315603 |
|
|
Mar 07 03:57:44 PM PST 24 |
Mar 07 04:02:25 PM PST 24 |
2582484284 ps |
| T1083 |
/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.3215720853 |
|
|
Mar 07 03:42:26 PM PST 24 |
Mar 07 04:21:18 PM PST 24 |
8928197880 ps |
| T1084 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.626860607 |
|
|
Mar 07 03:39:16 PM PST 24 |
Mar 07 03:50:24 PM PST 24 |
4001486046 ps |
| T1085 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3758096092 |
|
|
Mar 07 03:50:24 PM PST 24 |
Mar 07 03:54:04 PM PST 24 |
3185682571 ps |
| T49 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1366710570 |
|
|
Mar 07 03:38:05 PM PST 24 |
Mar 07 03:43:57 PM PST 24 |
4413495024 ps |
| T424 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.4024454693 |
|
|
Mar 07 03:56:15 PM PST 24 |
Mar 07 04:17:09 PM PST 24 |
5922105692 ps |
| T294 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3013745181 |
|
|
Mar 07 03:59:19 PM PST 24 |
Mar 07 04:03:55 PM PST 24 |
2581843482 ps |
| T517 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1458021150 |
|
|
Mar 07 03:38:13 PM PST 24 |
Mar 07 03:53:12 PM PST 24 |
4731625160 ps |
| T1086 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1067136431 |
|
|
Mar 07 03:58:48 PM PST 24 |
Mar 07 04:07:36 PM PST 24 |
4533167657 ps |
| T84 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3179828109 |
|
|
Mar 07 03:37:50 PM PST 24 |
Mar 07 03:43:19 PM PST 24 |
3123437109 ps |
| T775 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1856591733 |
|
|
Mar 07 03:41:24 PM PST 24 |
Mar 07 03:47:36 PM PST 24 |
3310993416 ps |
| T1087 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3398014082 |
|
|
Mar 07 03:41:43 PM PST 24 |
Mar 07 03:46:27 PM PST 24 |
2745967625 ps |
| T1088 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1940018639 |
|
|
Mar 07 03:38:24 PM PST 24 |
Mar 07 03:46:44 PM PST 24 |
7085364950 ps |
| T1089 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2046199199 |
|
|
Mar 07 04:08:53 PM PST 24 |
Mar 07 04:16:18 PM PST 24 |
3954002980 ps |
| T1090 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3934349454 |
|
|
Mar 07 03:53:48 PM PST 24 |
Mar 07 03:56:14 PM PST 24 |
2537951732 ps |
| T413 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3375281820 |
|
|
Mar 07 03:42:53 PM PST 24 |
Mar 07 04:12:09 PM PST 24 |
12749752968 ps |
| T1091 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2688071965 |
|
|
Mar 07 03:37:05 PM PST 24 |
Mar 07 03:43:53 PM PST 24 |
3517138152 ps |
| T682 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.409537782 |
|
|
Mar 07 03:54:06 PM PST 24 |
Mar 07 03:57:43 PM PST 24 |
3186079048 ps |
| T1092 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3827673062 |
|
|
Mar 07 04:06:14 PM PST 24 |
Mar 07 04:12:37 PM PST 24 |
3780216184 ps |
| T1093 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.3711915817 |
|
|
Mar 07 03:37:48 PM PST 24 |
Mar 07 03:42:01 PM PST 24 |
2870354072 ps |
| T1094 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.3064464539 |
|
|
Mar 07 03:37:00 PM PST 24 |
Mar 07 03:41:45 PM PST 24 |
3225252846 ps |
| T721 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.127052178 |
|
|
Mar 07 04:04:33 PM PST 24 |
Mar 07 04:15:14 PM PST 24 |
5690628140 ps |
| T736 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3633987551 |
|
|
Mar 07 04:04:36 PM PST 24 |
Mar 07 04:12:52 PM PST 24 |
3576115770 ps |
| T128 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2496984540 |
|
|
Mar 07 03:39:54 PM PST 24 |
Mar 07 03:44:17 PM PST 24 |
3095987360 ps |
| T722 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2506396418 |
|
|
Mar 07 04:08:12 PM PST 24 |
Mar 07 04:18:54 PM PST 24 |
5913349384 ps |
| T774 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.774080843 |
|
|
Mar 07 04:08:09 PM PST 24 |
Mar 07 04:18:22 PM PST 24 |
5862347600 ps |
| T738 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1938088992 |
|
|
Mar 07 04:08:22 PM PST 24 |
Mar 07 04:14:08 PM PST 24 |
3173879848 ps |
| T312 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.1288761913 |
|
|
Mar 07 03:38:08 PM PST 24 |
Mar 07 04:00:36 PM PST 24 |
5488046090 ps |
| T1095 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3780735163 |
|
|
Mar 07 03:38:51 PM PST 24 |
Mar 07 03:59:45 PM PST 24 |
5619742768 ps |
| T361 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.944426841 |
|
|
Mar 07 03:37:56 PM PST 24 |
Mar 07 03:46:22 PM PST 24 |
2947622628 ps |
| T1096 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1546706479 |
|
|
Mar 07 03:58:36 PM PST 24 |
Mar 07 04:07:55 PM PST 24 |
5917073960 ps |
| T323 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.2880761077 |
|
|
Mar 07 03:56:43 PM PST 24 |
Mar 07 04:16:11 PM PST 24 |
5901879600 ps |
| T1097 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3802182975 |
|
|
Mar 07 03:40:50 PM PST 24 |
Mar 07 03:58:15 PM PST 24 |
7332815804 ps |
| T706 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1377243826 |
|
|
Mar 07 03:53:54 PM PST 24 |
Mar 07 04:21:56 PM PST 24 |
21981576376 ps |
| T1098 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.1207859537 |
|
|
Mar 07 04:03:28 PM PST 24 |
Mar 07 04:38:24 PM PST 24 |
8987405470 ps |
| T283 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.2657494106 |
|
|
Mar 07 04:04:13 PM PST 24 |
Mar 07 04:13:03 PM PST 24 |
4799109416 ps |
| T1099 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3908464882 |
|
|
Mar 07 03:40:29 PM PST 24 |
Mar 07 03:44:09 PM PST 24 |
2877907992 ps |
| T1100 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1156980460 |
|
|
Mar 07 04:09:00 PM PST 24 |
Mar 07 04:16:16 PM PST 24 |
3731241564 ps |
| T1101 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1802536963 |
|
|
Mar 07 03:40:00 PM PST 24 |
Mar 07 03:47:48 PM PST 24 |
4093755572 ps |
| T35 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.1551328004 |
|
|
Mar 07 03:52:17 PM PST 24 |
Mar 07 03:58:12 PM PST 24 |
3184464099 ps |
| T1102 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2974577248 |
|
|
Mar 07 03:43:21 PM PST 24 |
Mar 07 03:47:34 PM PST 24 |
2552726220 ps |
| T1103 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2868070439 |
|
|
Mar 07 03:55:57 PM PST 24 |
Mar 07 04:47:15 PM PST 24 |
23401167877 ps |
| T322 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3162138921 |
|
|
Mar 07 03:45:32 PM PST 24 |
Mar 07 04:18:07 PM PST 24 |
7698827244 ps |
| T1104 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3410784456 |
|
|
Mar 07 04:04:46 PM PST 24 |
Mar 07 04:14:26 PM PST 24 |
5841459300 ps |
| T1105 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.912921868 |
|
|
Mar 07 03:52:34 PM PST 24 |
Mar 07 04:08:02 PM PST 24 |
5945767700 ps |
| T1106 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4266283081 |
|
|
Mar 07 03:44:11 PM PST 24 |
Mar 07 04:35:12 PM PST 24 |
12108080732 ps |
| T1107 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.4015028738 |
|
|
Mar 07 03:57:49 PM PST 24 |
Mar 07 04:10:56 PM PST 24 |
7113920260 ps |
| T1108 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1899566894 |
|
|
Mar 07 03:54:56 PM PST 24 |
Mar 07 04:16:41 PM PST 24 |
12968754946 ps |
| T707 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2264294194 |
|
|
Mar 07 03:39:37 PM PST 24 |
Mar 07 04:11:19 PM PST 24 |
21873422064 ps |
| T1109 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3832843882 |
|
|
Mar 07 03:38:30 PM PST 24 |
Mar 07 03:47:05 PM PST 24 |
7225033548 ps |
| T1110 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.1778369073 |
|
|
Mar 07 03:51:06 PM PST 24 |
Mar 07 03:55:47 PM PST 24 |
2755416272 ps |
| T1111 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1343027499 |
|
|
Mar 07 03:39:30 PM PST 24 |
Mar 07 03:44:51 PM PST 24 |
4018276240 ps |
| T735 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2747995497 |
|
|
Mar 07 04:04:04 PM PST 24 |
Mar 07 04:10:29 PM PST 24 |
3707820936 ps |
| T1112 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2250345693 |
|
|
Mar 07 03:58:13 PM PST 24 |
Mar 07 04:07:32 PM PST 24 |
6077756335 ps |
| T378 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.146977520 |
|
|
Mar 07 03:58:26 PM PST 24 |
Mar 07 04:03:48 PM PST 24 |
2861901160 ps |
| T1113 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3230282576 |
|
|
Mar 07 03:39:52 PM PST 24 |
Mar 07 06:33:16 PM PST 24 |
59378371976 ps |
| T1114 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.4267352251 |
|
|
Mar 07 03:37:16 PM PST 24 |
Mar 07 03:45:46 PM PST 24 |
4316130156 ps |
| T1115 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.393814821 |
|
|
Mar 07 03:43:09 PM PST 24 |
Mar 07 03:58:47 PM PST 24 |
4911820480 ps |
| T1116 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4248829059 |
|
|
Mar 07 04:03:26 PM PST 24 |
Mar 07 04:20:45 PM PST 24 |
12396616974 ps |
| T1117 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1129464029 |
|
|
Mar 07 03:42:18 PM PST 24 |
Mar 07 04:02:08 PM PST 24 |
16268318770 ps |
| T1118 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1086406720 |
|
|
Mar 07 03:39:14 PM PST 24 |
Mar 07 04:14:01 PM PST 24 |
7961174110 ps |
| T1119 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2788219984 |
|
|
Mar 07 03:44:28 PM PST 24 |
Mar 07 04:07:30 PM PST 24 |
6043758456 ps |
| T1120 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2255978387 |
|
|
Mar 07 03:55:38 PM PST 24 |
Mar 07 04:09:55 PM PST 24 |
4994775011 ps |
| T1121 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4125747066 |
|
|
Mar 07 03:57:55 PM PST 24 |
Mar 07 04:12:06 PM PST 24 |
4623144404 ps |
| T1122 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3870266927 |
|
|
Mar 07 03:43:29 PM PST 24 |
Mar 07 04:33:03 PM PST 24 |
11844270550 ps |
| T1123 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.283044301 |
|
|
Mar 07 03:52:54 PM PST 24 |
Mar 07 04:00:20 PM PST 24 |
5647244368 ps |
| T720 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2832069622 |
|
|
Mar 07 04:05:37 PM PST 24 |
Mar 07 04:14:07 PM PST 24 |
4327094998 ps |
| T1124 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1075633464 |
|
|
Mar 07 03:40:26 PM PST 24 |
Mar 07 04:29:39 PM PST 24 |
12832410488 ps |
| T162 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2604335279 |
|
|
Mar 07 04:04:18 PM PST 24 |
Mar 07 04:11:08 PM PST 24 |
4313253128 ps |
| T1125 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2168552433 |
|
|
Mar 07 03:48:09 PM PST 24 |
Mar 07 03:56:13 PM PST 24 |
4389304670 ps |
| T368 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4015408970 |
|
|
Mar 07 03:41:06 PM PST 24 |
Mar 07 03:49:19 PM PST 24 |
4931671788 ps |
| T7 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3543258139 |
|
|
Mar 07 03:51:55 PM PST 24 |
Mar 07 03:56:25 PM PST 24 |
2953720208 ps |
| T1126 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1712252496 |
|
|
Mar 07 03:37:56 PM PST 24 |
Mar 07 03:57:54 PM PST 24 |
7473152040 ps |
| T45 |
/workspace/coverage/default/0.chip_jtag_csr_rw.2083314954 |
|
|
Mar 07 03:29:30 PM PST 24 |
Mar 07 04:21:38 PM PST 24 |
20279866793 ps |
| T395 |
/workspace/coverage/default/0.chip_sw_edn_kat.1358110359 |
|
|
Mar 07 03:38:26 PM PST 24 |
Mar 07 03:48:02 PM PST 24 |
3276592960 ps |
| T396 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4268355632 |
|
|
Mar 07 04:03:12 PM PST 24 |
Mar 07 04:10:45 PM PST 24 |
3613512178 ps |
| T397 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1866807916 |
|
|
Mar 07 03:49:11 PM PST 24 |
Mar 07 04:56:12 PM PST 24 |
24816541182 ps |
| T398 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.839699286 |
|
|
Mar 07 04:06:57 PM PST 24 |
Mar 07 04:15:31 PM PST 24 |
5561384094 ps |
| T399 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4098964412 |
|
|
Mar 07 03:40:56 PM PST 24 |
Mar 07 03:58:01 PM PST 24 |
4910832984 ps |
| T400 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1958263693 |
|
|
Mar 07 03:41:27 PM PST 24 |
Mar 07 04:06:54 PM PST 24 |
7617253490 ps |
| T61 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1679028834 |
|
|
Mar 07 03:40:14 PM PST 24 |
Mar 07 03:48:17 PM PST 24 |
5620248672 ps |
| T401 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3620633250 |
|
|
Mar 07 03:45:40 PM PST 24 |
Mar 07 03:53:57 PM PST 24 |
3516028754 ps |
| T402 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1621929465 |
|
|
Mar 07 04:07:44 PM PST 24 |
Mar 07 04:14:08 PM PST 24 |
4057304900 ps |
| T1127 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.2681884676 |
|
|
Mar 07 04:03:49 PM PST 24 |
Mar 07 04:15:16 PM PST 24 |
4615126272 ps |
| T1128 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1479831125 |
|
|
Mar 07 03:43:25 PM PST 24 |
Mar 07 04:13:52 PM PST 24 |
8381883096 ps |
| T652 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3396672400 |
|
|
Mar 07 03:40:00 PM PST 24 |
Mar 07 03:49:25 PM PST 24 |
4581624002 ps |
| T332 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.1902904267 |
|
|
Mar 07 03:40:19 PM PST 24 |
Mar 07 03:44:29 PM PST 24 |
3058523476 ps |
| T362 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.4294229623 |
|
|
Mar 07 03:43:33 PM PST 24 |
Mar 07 03:52:00 PM PST 24 |
3115629480 ps |
| T229 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1693149378 |
|
|
Mar 07 03:40:50 PM PST 24 |
Mar 07 05:07:44 PM PST 24 |
48358678132 ps |
| T1129 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.903122590 |
|
|
Mar 07 03:40:04 PM PST 24 |
Mar 07 03:46:05 PM PST 24 |
5717726869 ps |
| T1130 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1800851328 |
|
|
Mar 07 03:44:26 PM PST 24 |
Mar 07 04:23:09 PM PST 24 |
8399315300 ps |
| T1131 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3876096030 |
|
|
Mar 07 04:07:50 PM PST 24 |
Mar 07 04:15:35 PM PST 24 |
3743077728 ps |
| T339 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.882383337 |
|
|
Mar 07 03:57:22 PM PST 24 |
Mar 07 04:08:10 PM PST 24 |
4200013754 ps |
| T1132 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2262575125 |
|
|
Mar 07 03:53:24 PM PST 24 |
Mar 07 04:05:50 PM PST 24 |
5988291760 ps |
| T48 |
/workspace/coverage/default/1.chip_jtag_csr_rw.3767355365 |
|
|
Mar 07 03:40:55 PM PST 24 |
Mar 07 04:21:30 PM PST 24 |
19804466340 ps |
| T1133 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.220423515 |
|
|
Mar 07 03:57:32 PM PST 24 |
Mar 07 04:01:10 PM PST 24 |
3178760252 ps |
| T1134 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.4166309560 |
|
|
Mar 07 03:55:20 PM PST 24 |
Mar 07 04:13:01 PM PST 24 |
5803798332 ps |
| T741 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3563302821 |
|
|
Mar 07 04:09:30 PM PST 24 |
Mar 07 04:21:31 PM PST 24 |
5049224098 ps |
| T1135 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1248760273 |
|
|
Mar 07 03:46:49 PM PST 24 |
Mar 07 03:55:49 PM PST 24 |
4215002640 ps |
| T254 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.2024884606 |
|
|
Mar 07 04:04:30 PM PST 24 |
Mar 07 04:14:10 PM PST 24 |
4663452336 ps |
| T1136 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2552639821 |
|
|
Mar 07 04:08:28 PM PST 24 |
Mar 07 04:14:33 PM PST 24 |
2973803854 ps |
| T718 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3112553308 |
|
|
Mar 07 04:07:12 PM PST 24 |
Mar 07 04:16:27 PM PST 24 |
4853087472 ps |
| T1137 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.1385078430 |
|
|
Mar 07 03:54:47 PM PST 24 |
Mar 07 04:18:57 PM PST 24 |
5827754740 ps |
| T743 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.829533870 |
|
|
Mar 07 04:06:01 PM PST 24 |
Mar 07 04:18:52 PM PST 24 |
5223519040 ps |
| T164 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3450486641 |
|
|
Mar 07 03:45:27 PM PST 24 |
Mar 07 03:52:03 PM PST 24 |
5754385516 ps |
| T1138 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3033063288 |
|
|
Mar 07 03:38:32 PM PST 24 |
Mar 07 03:48:55 PM PST 24 |
4254922492 ps |
| T1139 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.1158733983 |
|
|
Mar 07 03:36:59 PM PST 24 |
Mar 07 03:39:55 PM PST 24 |
1941108071 ps |