CHIP Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: 8d1fda3660

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	5.989m	3.222ms	3	3	100.00
		chip_sw_example_rom	2.134m	2.403ms	3	3	100.00
		chip_sw_example_manufacturer	4.081m	2.911ms	3	3	100.00
		chip_sw_example_concurrency	4.995m	3.619ms	3	3	100.00
		chip_sw_uart_smoketest_signed	40.167m	8.999ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset			0	5	0.00
V1	csr_rw	chip_csr_rw			0	20	0.00
V1	csr_bit_bash	chip_csr_bit_bash			0	5	0.00
V1	csr_aliasing	chip_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	5	0.00
		chip_csr_rw			0	20	0.00
V1	xbar_smoke	xbar_smoke			0	100	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	10.488m	4.371ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	10.488m	4.371ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	10.488m	4.371ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	18.860m	5.878ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	18.860m	5.878ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	19.830m	5.376ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	16.921m	6.180ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	17.662m	5.042ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.266h	22.946ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.124h	23.764ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	45.885m	23.108ms	4	5	80.00
V1		TOTAL			67	223	30.04
V2	chip_pin_mux	chip_padctrl_attributes	5.176m	6.139ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.176m	6.139ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.571m	3.223ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.740m	5.545ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.833m	4.406ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	28.203m	14.844ms	5	5	100.00
		chip_tap_straps_testunlock0	11.872m	7.404ms	5	5	100.00
		chip_tap_straps_rma	9.231m	5.850ms	5	5	100.00
		chip_tap_straps_prod	21.773m	11.580ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.142m	3.138ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	25.110m	8.710ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	15.108m	5.308ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	15.108m	5.308ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	17.925m	6.607ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.288m	4.142ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.029m	6.030ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	59.652m	18.594ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.578m	2.858ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	15.635m	5.358ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.506m	3.127ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.155m	5.070ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.239m	2.411ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.747m	4.142ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.163m	2.816ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.753m	3.515ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	14.831m	5.837ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	14.831m	5.837ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.025m	4.883ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.776m	2.963ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.025m	4.883ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.211m	2.740ms	3	3	100.00
		chip_sw_aes_smoketest	6.737m	3.469ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.439m	3.188ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.729m	2.830ms	3	3	100.00
		chip_sw_csrng_smoketest	4.557m	3.211ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.023m	3.315ms	3	3	100.00
		chip_sw_gpio_smoketest	5.047m	3.026ms	3	3	100.00
		chip_sw_hmac_smoketest	5.715m	2.826ms	3	3	100.00
		chip_sw_kmac_smoketest	6.149m	2.571ms	3	3	100.00
		chip_sw_otbn_smoketest	32.451m	8.740ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.680m	2.714ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.335m	4.569ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	9.550m	5.795ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.012m	2.599ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.957m	3.192ms	3	3	100.00
		chip_sw_rstmgr_smoketest	3.604m	2.199ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.699m	3.095ms	3	3	100.00
		chip_sw_uart_smoketest	5.510m	2.814ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.356m	3.753ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	40.167m	8.999ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.775h	79.417ms	1	3	33.33
V2	chip_sw_secure_boot	rom_e2e_smoke	35.639m	8.744ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	35.014m	14.681ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	13.431m	4.555ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	10.128m	9.673ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.075h	58.709ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.532h	65.753ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors			0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors			0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	tl_d_partial_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	xbar_base_random_sequence	xbar_random			0	100	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays			0	100	0.00
		xbar_smoke_large_delays			0	100	0.00
		xbar_smoke_slow_rsp			0	100	0.00
		xbar_random_zero_delays			0	100	0.00
		xbar_random_large_delays			0	100	0.00
		xbar_random_slow_rsp			0	100	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_error_cases	xbar_error_random			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_all_access_same_device	xbar_access_same_device			0	100	0.00
		xbar_access_same_device_slow_rsp			0	100	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source			0	100	0.00
V2	xbar_stress_all	xbar_stress_all			0	100	0.00
		xbar_stress_all_with_error			0	100	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset			0	100	0.00
		xbar_stress_all_with_reset_error			0	100	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	35.639m	8.744ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	54.665m	23.556ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	35.460m	8.524ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	28.996m	6.545ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	34.268m	8.469ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.544m	8.448ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	37.853m	9.433ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	37.373m	8.303ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.776m	6.729ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	31.398m	8.946ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	38.256m	8.847ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	38.154m	8.394ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	36.697m	8.786ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	44.359m	9.391ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	53.610m	12.312ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	54.234m	12.453ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	55.164m	11.901ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	55.184m	11.829ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	45.929m	10.459ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	50.732m	11.484ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	51.561m	12.200ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	47.453m	11.609ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	49.560m	12.044ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	29.487m	6.998ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	31.497m	8.859ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	28.034m	9.033ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	35.329m	8.780ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	37.507m	8.461ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.849m	7.301ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	32.884m	8.517ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	36.552m	8.813ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	33.223m	8.197ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	33.562m	9.067ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	30.215m	6.456ms	3	3	100.00
		rom_e2e_asm_init_dev	43.081m	8.823ms	3	3	100.00
		rom_e2e_asm_init_prod	37.746m	8.324ms	3	3	100.00
		rom_e2e_asm_init_prod_end	37.922m	8.665ms	3	3	100.00
		rom_e2e_asm_init_rma	41.857m	9.124ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	44.300m	10.305ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.233m	3.224ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.578m	2.858ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	6.034m	2.708ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.143m	2.663ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	10.774m	5.061ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.877m	18.842ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.877m	18.842ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	6.843m	3.144ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	9.335m	4.569ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	6.843m	3.144ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.275m	7.145ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.275m	7.145ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.831m	6.303ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	14.267m	5.063ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.712m	5.963ms	3	3	100.00
		chip_sw_aes_idle	4.143m	2.663ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.283m	2.993ms	3	3	100.00
		chip_sw_kmac_idle	4.338m	3.413ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	9.527m	4.621ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	10.181m	3.944ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.996m	4.929ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	10.523m	4.133ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	19.514m	10.566ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.288m	4.000ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.667m	5.359ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.437m	4.843ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.280m	4.978ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.506m	4.060ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.332m	5.033ms	3	3	100.00
		chip_sw_ast_clk_outputs	17.925m	6.607ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	18.238m	10.822ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.437m	4.843ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.280m	4.978ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.288m	4.142ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.029m	6.030ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	59.652m	18.594ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.578m	2.858ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	15.635m	5.358ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.506m	3.127ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.155m	5.070ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.239m	2.411ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.747m	4.142ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.163m	2.816ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.470m	2.458ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	13.728m	4.123ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	18.909m	7.280ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.112h	24.608ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.140m	3.289ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.300m	2.811ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.856m	3.982ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.748m	3.470ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.474m	4.742ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	39.129m	19.807ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.039h	17.886ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	17.925m	6.607ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.042m	4.678ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.347m	3.395ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.817m	6.016ms	100	100	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	30.580m	9.155ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	31.863m	7.083ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	9.951m	10.010ms	0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	20.114m	20.010ms	0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.628m	2.539ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.988m	8.128ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	36.398m	24.796ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.053m	2.577ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	43.740s	10.360us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	10.752m	5.284ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	36.398m	24.796ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	36.398m	24.796ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.097h	21.020ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.097h	21.020ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.154m	5.624ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.877m	18.842ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	55.326m	12.811ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.766m	3.072ms	3	3	100.00
		chip_sw_edn_entropy_reqs	20.052m	5.351ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.766m	3.072ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	31.863m	7.083ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.858m	2.698ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	41.553m	17.356ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	19.992m	5.874ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.029m	6.030ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	13.973m	4.128ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	13.288m	4.142ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	10.430m	10.010ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	41.553m	17.356ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.370m	3.270ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	11.065m	4.961ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.542m	4.558ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	10.430m	10.010ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.542m	4.558ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.542m	4.558ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	8.542m	4.558ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.542m	4.558ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.817m	6.016ms	100	100	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	17.470m	5.967ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.524m	5.017ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.524m	5.017ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.958m	3.637ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.506m	3.127ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.283m	2.993ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	17.488m	5.179ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	17.169m	5.985ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	17.450m	6.141ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	8.839m	4.158ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	11.065m	4.961ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.155m	5.070ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	10.050m	4.684ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	10.774m	5.061ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.180h	17.833ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.701m	3.076ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.018m	3.228ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.239m	2.411ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	11.065m	4.961ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	19.828m	10.068ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.304m	2.719ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.672m	2.585ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.338m	3.413ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.224m	5.610ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	28.203m	14.844ms	5	5	100.00
		chip_tap_straps_rma	9.231m	5.850ms	5	5	100.00
		chip_tap_straps_prod	21.773m	11.580ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.451m	2.565ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	19.828m	10.068ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	19.828m	10.068ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	19.828m	10.068ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	8.859m	4.273ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	8.542m	4.558ms	3	3	100.00
		chip_sw_flash_rma_unlocked	10.430m	10.010ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.509m	4.431ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	27.333m	9.305ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.998m	7.256ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.624m	7.283ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.828m	10.068ms	15	15	100.00
		chip_sw_keymgr_key_derivation	11.065m	4.961ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	9.724m	9.210ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	11.287m	10.021ms	0	3	0.00
		chip_prim_tl_access			0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	18.238m	10.822ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.288m	4.000ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.667m	5.359ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.437m	4.843ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.280m	4.978ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.506m	4.060ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.332m	5.033ms	3	3	100.00
		chip_tap_straps_dev	28.203m	14.844ms	5	5	100.00
		chip_tap_straps_rma	9.231m	5.850ms	5	5	100.00
		chip_tap_straps_prod	21.773m	11.580ms	5	5	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.441m	3.270ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.256m	3.207ms	0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.543m	3.551ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.529m	2.843ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	39.614m	27.735ms	3	3	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.594h	52.633ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.626h	49.153ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	18.659m	11.025ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.517h	46.784ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	39.614m	27.735ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.043m	2.652ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.028m	3.036ms	3	3	100.00
		rom_volatile_raw_unlock	1.978m	2.332ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	19.828m	10.068ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	41.553m	17.356ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.982m	2.750ms	3	3	100.00
		chip_sw_keymgr_key_derivation	11.065m	4.961ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	9.434m	4.456ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.958m	2.463ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	41.553m	17.356ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.982m	2.750ms	3	3	100.00
		chip_sw_keymgr_key_derivation	11.065m	4.961ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	9.434m	4.456ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.958m	2.463ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	19.828m	10.068ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	15.757m	14.422ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.451m	2.565ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.509m	4.431ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	27.333m	9.305ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.998m	7.256ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.624m	7.283ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.828m	10.068ms	15	15	100.00
		chip_prim_tl_access			0	3	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.842m	6.773ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	9.520m	8.410ms	0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	6.978m	6.285ms	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	14.606m	8.575ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	13.456m	16.858ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	12.142m	11.912ms	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	26.296m	15.957ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.275m	7.145ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	26.955m	10.384ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	8.898m	5.348ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.842m	6.773ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	9.195m	4.655ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	55.794m	37.427ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.935m	7.126ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	7.884m	4.223ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.048m	21.519ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.988m	8.128ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	28.948m	11.993ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	46.788m	26.644ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.507m	3.144ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.817m	6.016ms	100	100	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.724m	9.210ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.724m	9.210ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	28.948m	11.993ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.048m	21.519ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	8.898m	5.348ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.335m	4.569ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.775m	4.708ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	13.889m	5.933ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.834m	3.718ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	29.658m	14.308ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.334m	2.823ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.817m	6.016ms	100	100	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	26.735m	6.429ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	21.112m	5.509ms	3	3	100.00
		chip_plic_all_irqs_10	10.393m	3.974ms	3	3	100.00
		chip_plic_all_irqs_20	12.200m	4.361ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.932m	3.256ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.643m	2.988ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	35.639m	8.744ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	18.716m	7.331ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	9.657m	4.253ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.356m	3.481ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.093m	3.157ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	9.434m	4.456ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.747m	4.142ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	11.101m	6.335ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	12.644m	6.290ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.287m	10.021ms	0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.817m	6.016ms	100	100	100.00
		chip_sw_data_integrity_escalation	15.108m	5.308ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.416m	2.792ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.240m	3.180ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	9.009m	3.282ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	7.993m	3.389ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	30.123m	7.814ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.893h	31.638ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	49.005m	11.777ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.105m	3.044ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.224m	5.610ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.817m	6.016ms	100	100	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	7.114m	3.237ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	29.658m	14.308ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	7.126m	4.072ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.182m	3.955ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	23.974m	11.315ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	30.580m	9.155ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	26.735m	6.429ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.536h	255.962ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	37.400m	18.270ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	25.502m	13.394ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.775m	4.708ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.146m	5.239ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.386m	5.893ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	9.231m	5.850ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			826	2657	31.09
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.864m	3.135ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	14.746m	5.285ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.043m	2.593ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.555m	2.181ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.545m	1.970ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.193h	40.616ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.024h	40.953ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.049h	53.681ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	36.418m	9.451ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.060m	3.575ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.921m	3.432ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	26.660m	5.985ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	36.684m	9.037ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.840m	3.191ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	23.108m	5.458ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.888m	2.515ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	15.043m	4.969ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	7.925m	4.285ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	11.062m	5.726ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	28.948m	11.993ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.817m	6.016ms	100	100	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	18.860m	5.878ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.245h	18.772ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.043m	2.593ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.555m	2.181ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.545m	1.970ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.000m	5.299ms	3	3	100.00
V3		TOTAL			32	48	66.67
	Unmapped tests	chip_sival_flash_info_access	5.731m	2.922ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	10.970m	4.251ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.159h	16.967ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	21.542m	5.393ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.921m	4.973ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.487m	5.632ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.773m	2.907ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	2.325m	2.371ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			952	2958	32.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	12	63.16
V2	290	276	228	78.62
V2S	1	1	1	100.00
V3	91	22	12	13.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.41	93.42	83.69	89.79	--	94.62	97.20	83.74

Failure Buckets

• launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:

  • Test chip_csr_bit_bash has 3 failures.

    • 0.chip_csr_bit_bash.115532176603559894160419084880486763135068300329727483788049092781748803021638
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

    • 2.chip_csr_bit_bash.43783447585662205719181555425326642860655460946876684539345242827076900336394
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log

    • ... and 1 more failures.

  • Test chip_same_csr_outstanding has 3 failures.

    • 0.chip_same_csr_outstanding.75387829840559263311948455016367226902059217802350842952501650485398920391198
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

    • 2.chip_same_csr_outstanding.80991825399335603094545213954981310289431369636443029859030540705837343439143
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log

    • ... and 1 more failures.

  • Test chip_prim_tl_access has 2 failures.

    • 0.chip_prim_tl_access.55848588329253851069433815374463000799564367122522374162717277421421785429089
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log

    • 2.chip_prim_tl_access.9773341609943552754031821083214485714911597917311474518590820712969865614831
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log

  • Test xbar_smoke has 8 failures.

    • 0.xbar_smoke.77772456850916808079079372515034339829532150257915186453697572047563891510180
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log

    • 2.xbar_smoke.7963741624304042250147363273644606633864040207584594434452295843641600298512
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log

    • ... and 6 more failures.

  • Test xbar_smoke_large_delays has 8 failures.

    • 0.xbar_smoke_large_delays.52653030102914474576213956899441960331286669090313296163626589374805305885472
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log

    • 2.xbar_smoke_large_delays.53803428975058398026823093033352100929004430989319626654097324794606949478713
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log

    • ... and 6 more failures.

  • ... and 22 more tests.

• Job killed most likely because its dependent job failed. has 955 failures:

  • Test chip_csr_aliasing has 3 failures.

    • 0.chip_csr_aliasing.25409420638794415071845753939003689448639105487961745178836601391001257718672
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

    • 2.chip_csr_aliasing.75554985801015018058553725999038359539374560064497147769731155189131849259497
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log

    • ... and 1 more failures.

  • Test chip_tl_errors has 8 failures.

    • 0.chip_tl_errors.30022461495482568578049977555139689414729009115751218421768242438428425586055
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

    • 2.chip_tl_errors.109735709562950959150085202851402624569897534722147322890816596264617949645210
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log

    • ... and 6 more failures.

  • Test chip_rv_dm_lc_disabled has 2 failures.

    • 0.chip_rv_dm_lc_disabled.53595444895304446557590433257585052816902854684008359786481266999246957865117
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

    • 2.chip_rv_dm_lc_disabled.34500956771619194811704693556705502298223637244992743202177678931801825156278
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log

  • Test xbar_smoke_zero_delays has 8 failures.

    • 0.xbar_smoke_zero_delays.49063957759708992625862069681464703676430520746212862880117780980380257854906
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log

    • 2.xbar_smoke_zero_delays.71589873888574004717946013663969396579526693799006246082948698125849977783958
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log

    • ... and 6 more failures.

  • Test xbar_smoke_slow_rsp has 8 failures.

    • 0.xbar_smoke_slow_rsp.3095441099804370682501584754175599895992077548081639528431153234962135290809
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log

    • 2.xbar_smoke_slow_rsp.66523483936942110494488367933145753597161606485424329004082933261520350010809
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log

    • ... and 6 more failures.

  • ... and 22 more tests.

• Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

  • Test chip_sw_flash_ctrl_write_clear has 3 failures.

    • 0.chip_sw_flash_ctrl_write_clear.96807409544373721528026015281794148730320519637332057906240692388516810983034
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

        (14:50:46) Loading:
        (14:50:46) Loading:
        (14:50:46) Loading: 4 packages loaded
        (14:50:46) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (14:50:46) WARNING: Target pattern parsing failed.
        (14:50:46) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (14:50:46) INFO: Elapsed time: 18.196s
        (14:50:46) INFO: 0 processes.
        (14:50:46) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_flash_ctrl_write_clear.90706227217124623095004551152646528900177741894424671233015160455952752964888
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

        (15:02:57) Loading:
        (15:02:58) Loading:
        (15:02:58) Loading: 4 packages loaded
        (15:02:58) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (15:02:58) WARNING: Target pattern parsing failed.
        (15:02:58) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (15:02:58) INFO: Elapsed time: 26.246s
        (15:02:58) INFO: 0 processes.
        (15:02:58) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_meas.113305203672214588141498449420803297680811817760766999037280968937592860828975
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

        (14:51:43) Loading:
        (14:51:43) Loading:
        (14:51:43) Loading: 4 packages loaded
        (14:51:43) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (14:51:43) WARNING: Target pattern parsing failed.
        (14:51:43) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (14:51:43) INFO: Elapsed time: 22.553s
        (14:51:43) INFO: 0 processes.
        (14:51:43) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_meas.64566222293242224432365360273978834410454588474909974214574713955105657597156
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

        (15:04:09) Loading:
        (15:04:09) Loading:
        (15:04:09) Loading: 4 packages loaded
        (15:04:10) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:04:10) WARNING: Target pattern parsing failed.
        (15:04:10) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:04:10) INFO: Elapsed time: 23.136s
        (15:04:10) INFO: 0 processes.
        (15:04:10) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_no_meas.39287022791608347981245426117359413943543365927652325099549815644299522936781
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

        (14:51:46) Loading:
        (14:51:46) Loading:
        (14:51:46) Loading: 4 packages loaded
        (14:51:46) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (14:51:46) WARNING: Target pattern parsing failed.
        (14:51:46) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (14:51:46) INFO: Elapsed time: 18.247s
        (14:51:46) INFO: 0 processes.
        (14:51:46) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_no_meas.76684225346744018195270464990841007499433632330348735188316393062334869482784
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

        (15:04:16) Loading:
        (15:04:17) Loading:
        (15:04:17) Loading: 4 packages loaded
        (15:04:17) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:04:17) WARNING: Target pattern parsing failed.
        (15:04:17) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:04:17) INFO: Elapsed time: 34.320s
        (15:04:17) INFO: 0 processes.
        (15:04:17) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_invalid_meas.111364024896040557866093670219921758449255463954562180149899745472884269567656
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

        (14:51:28) Loading:
        (14:51:29) Loading:
        (14:51:29) Loading: 4 packages loaded
        (14:51:29) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (14:51:29) WARNING: Target pattern parsing failed.
        (14:51:29) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (14:51:29) INFO: Elapsed time: 17.844s
        (14:51:29) INFO: 0 processes.
        (14:51:29) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_invalid_meas.105943254099106610226586216680414822175317558182502982513310729156214304708238
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

        (15:04:06) Loading:
        (15:04:07) Loading:
        (15:04:07) Loading: 4 packages loaded
        (15:04:07) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:04:07) WARNING: Target pattern parsing failed.
        (15:04:07) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:04:07) INFO: Elapsed time: 18.421s
        (15:04:07) INFO: 0 processes.
        (15:04:07) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

    • 0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.83028164792941477224161235879283892803897799625632731502049404195722864652320
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

        (14:51:33) Loading:
        (14:51:34) Loading:
        (14:51:34) Loading: 4 packages loaded
        (14:51:34) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (14:51:34) WARNING: Target pattern parsing failed.
        (14:51:34) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (14:51:34) INFO: Elapsed time: 17.454s
        (14:51:34) INFO: 0 processes.
        (14:51:34) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.105921141305838657057241859535733396231078700631465375721579026520038684816182
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

        (15:04:06) Loading:
        (15:04:07) Loading:
        (15:04:07) Loading: 4 packages loaded
        (15:04:07) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:04:07) WARNING: Target pattern parsing failed.
        (15:04:07) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:04:07) INFO: Elapsed time: 18.575s
        (15:04:07) INFO: 0 processes.
        (15:04:07) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • ... and 9 more tests.

• Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:

  • Test chip_sw_rv_timer_systick_test has 3 failures.

    • 0.chip_sw_rv_timer_systick_test.18053074653478450337551209210707430104616050598427790322795060367814826638321
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:290387d0-1d1d-4b3d-bcce-77adda6388cc
      

    • 1.chip_sw_rv_timer_systick_test.111878681387668628843904419255395736933968953735017745657211208126559232775818
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:c7878e33-de15-4485-9fce-3c1323b107a0
      

    • ... and 1 more failures.

  • Test chip_sw_coremark has 1 failures.

    • 0.chip_sw_coremark.8153153477096651665479773985969384375279115785274132668021520983610010705035
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log

        Job ID: smart:2e198362-1613-45e3-abf5-dbb098f8c49d
      

  • Test chip_sw_ast_clk_rst_inputs has 3 failures.

    • 0.chip_sw_ast_clk_rst_inputs.106074669555636004820972854689887900157196531180980774929575362468588196589499
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log

        Job ID: smart:f9d9fac9-edc7-4d5c-a2cb-29c6e2c524d2
      

    • 1.chip_sw_ast_clk_rst_inputs.43468160042704557602825720151172376465147127811247350617620817222004896604293
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log

        Job ID: smart:305d69f6-f396-42a2-a134-604d2bfba9f1
      

    • ... and 1 more failures.

  • Test chip_sw_power_virus has 2 failures.

    • 0.chip_sw_power_virus.25906067851939167002772031471551286789364868166860188218321828569227837701999
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log

        Job ID: smart:801614e8-b4ef-40bf-8e34-4965cd6f2e92
      

    • 1.chip_sw_power_virus.66941276825181281155919022202147225663762538361691645774019497698795837997186
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log

        Job ID: smart:a034047d-cfa7-4f2f-a914-d382822401b2
      

  • Test chip_sw_uart_tx_rx_bootstrap has 2 failures.

    • 1.chip_sw_uart_tx_rx_bootstrap.80419413818236208891396777952827540877836850938298791159686892689675510360683
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log

        Job ID: smart:ca05e994-038f-4756-b7ce-53c5bbbe2379
      

    • 2.chip_sw_uart_tx_rx_bootstrap.32970983741556613091598605267676100402774812733557527190616410701105131269827
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log

        Job ID: smart:401dd5d3-2530-437d-b525-e5976e88ff7f
      

  • ... and 1 more tests.

• UVM_FATAL @ * us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [chip_sw_flash_rma_unlocked_vseq] wait timeout occurred! has 3 failures:

  • Test chip_sw_flash_rma_unlocked has 3 failures.

    • 0.chip_sw_flash_rma_unlocked.6136407567062776733260257331460532743364178486772001816001901903114569068901
      Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log

        UVM_FATAL @ 10010.100001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
        UVM_INFO @ 10010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_flash_rma_unlocked.29813654957236466955806758835333928180387848782019577203354643406752711064533
      Line 701, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log

        UVM_FATAL @ 10010.280001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
        UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:

  • Test chip_sw_sysrst_ctrl_outputs has 3 failures.

    • 0.chip_sw_sysrst_ctrl_outputs.29297471279881930275382110484237552306629405059617353047792573979078443278421
      Line 820, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_sysrst_ctrl_outputs.43830367511359470093477608673801401468844924487864960790741973908303858549754
      Line 749, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress has 3 failures:

  • Test chip_sw_csrng_lc_hw_debug_en_test has 3 failures.

    • 0.chip_sw_csrng_lc_hw_debug_en_test.56419660960885640958964265327897672166930383280359008530569727397480566801192
      Line 766, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log

        UVM_FATAL @ 20010.300001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
        UVM_INFO @ 20010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_csrng_lc_hw_debug_en_test.53348193800487284156407283779619471160554508703960265857375561567209152909460
      Line 744, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log

        UVM_FATAL @ 20010.300001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
        UVM_INFO @ 20010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_entropy_src_fuse_vseq.sv:33) [chip_sw_entropy_src_fuse_vseq] *- has 3 failures:

  • Test chip_sw_csrng_fuse_en_sw_app_read_test has 3 failures.

    • 0.chip_sw_csrng_fuse_en_sw_app_read_test.88771428642907169090486132522699717256452297876487011779290257767930798688812
      Line 732, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log

        UVM_FATAL @ 10010.400001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
        UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_csrng_fuse_en_sw_app_read_test.91999413130679069146755189451150104260630175463511661224164383736543637398140
      Line 726, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log

        UVM_FATAL @ 10010.320001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
        UVM_INFO @ 10010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred! has 3 failures:

  • Test chip_sw_sram_ctrl_execution_main has 3 failures.

    • 0.chip_sw_sram_ctrl_execution_main.63698654791533399144444195930105389380201010257707373207884564665971159928244
      Line 823, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log

        UVM_FATAL @ 10020.400001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
        UVM_INFO @ 10020.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_sram_ctrl_execution_main.40363039064339647026718723580787844343881076387817746076601880352395078791856
      Line 725, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/run.log

        UVM_FATAL @ 10020.460001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
        UVM_INFO @ 10020.460001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

  • Test chip_sw_lc_ctrl_program_error has 3 failures.

    • 0.chip_sw_lc_ctrl_program_error.98049501699119109787989616897890377610924467970117640104329194214507055918975
      Line 744, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 14362.652784 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 14362.652784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.chip_sw_lc_ctrl_program_error.42521925953483539041376339581853667780827382384569544092585835460629318385006
      Line 724, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 15220.583490 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 15220.583490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit * set in irq causes has 3 failures:

  • Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 3 failures.

    • 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.51308673201518079074592020492571700295402656402296649343776397449016082529581
      Line 796, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 5844.440552 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit 5 set in irq causes
        UVM_INFO @ 5844.440552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.868393288690700275731752311895917458159431917182408870998285653097354623519
      Line 747, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 5965.847630 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit 5 set in irq causes
        UVM_INFO @ 5965.847630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit * set in irq causes has 3 failures:

  • Test chip_sw_pwrmgr_deep_sleep_all_wake_ups has 3 failures.

    • 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.96395234812389548388698515746168839335392214054150961372147548959764306546039
      Line 849, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 11911.525560 us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit 5 set in irq causes
        UVM_INFO @ 11911.525560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.20680016724155601322145501553168548986199169056741071189149657567862577486028
      Line 740, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 9477.292960 us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit 5 set in irq causes
        UVM_INFO @ 9477.292960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit * set in irq causes has 3 failures:

  • Test chip_sw_pwrmgr_random_sleep_all_wake_ups has 3 failures.

    • 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.70976003658765422441466013047966635262276057619180773917357675588427091020021
      Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 8170.703370 us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit 5 set in irq causes
        UVM_INFO @ 8170.703370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.103624275132290797962059068692769219284685437914847756465138796976491262254820
      Line 749, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 8247.030442 us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit 5 set in irq causes
        UVM_INFO @ 8247.030442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:

  • Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_debug_test_unlocked0.92516618077807053836746505214761885224874394318505341032258445166072823417427
      Line 732, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log

        UVM_FATAL @ 2593.267500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2593.267500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_dev has 1 failures.

    • 0.rom_e2e_jtag_debug_dev.60074385780070780682617697744858000597209382604044818521758146472541173049860
      Line 692, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log

        UVM_FATAL @ 2180.918000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2180.918000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_rma has 1 failures.

    • 0.rom_e2e_jtag_debug_rma.79137640698363079973250594748117506536167402040221144772194333049868740885739
      Line 696, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log

        UVM_FATAL @ 1970.177500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 1970.177500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:

  • Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_inject_test_unlocked0.95800088461735061654020348275203680505883381432249025735942589494239291083201
      Line 748, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log

        UVM_FATAL @ 40616.368010 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 40616.368010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_inject_dev has 1 failures.

    • 0.rom_e2e_jtag_inject_dev.45044211265605577620391831495509711031294885334338731971718510637100062167320
      Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log

        UVM_FATAL @ 40953.388010 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 40953.388010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_inject_rma has 1 failures.

    • 0.rom_e2e_jtag_inject_rma.43236935370460912318183239941036838605009326160608886803196297650715538890008
      Line 767, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log

        UVM_FATAL @ 53681.340777 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 53681.340777 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns * has 3 failures:

  • Test rom_e2e_self_hash has 3 failures.

    • 0.rom_e2e_self_hash.113236824970743148168582006465344849263466555761497101300001565045773921677440
      Line 726, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

        UVM_ERROR @ 9046.362650 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
        UVM_INFO @ 9046.362650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_e2e_self_hash.97576408737231765268932032450053030943407960319802097525163994313713963555284
      Line 844, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

        UVM_ERROR @ 9450.905828 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
        UVM_INFO @ 9450.905828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.

    • 8.chip_sw_alert_handler_lpg_sleep_mode_alerts.30619505268212015434506587500114042830970920252643782590348970543658272680204
      Line 749, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 3431.546072 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a36 MTVAL=40600800
        UVM_INFO @ 3431.546072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 32.chip_sw_alert_handler_lpg_sleep_mode_alerts.43333494366114007070498159190365179870893733067526969407887570820553058462241
      Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 4184.747912 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a36 MTVAL=40600800
        UVM_INFO @ 4184.747912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:767) [chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == * (* [*] vs * [*]) Unexpected status error *f* has 1 failures:

  • Test chip_sw_lc_ctrl_raw_to_scrap has 1 failures.

    • 0.chip_sw_lc_ctrl_raw_to_scrap.59839961984235250369584292300542809423050442432459252250948556235991211293128
      Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log

        UVM_ERROR @ 3207.219075 us: (chip_sw_base_vseq.sv:767) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == 0 (524310 [0x80016] vs 0 [0x0]) Unexpected status error 800166f8
        UVM_INFO @ 3207.219075 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:

  • Test chip_sw_pwrmgr_normal_sleep_por_reset has 1 failures.

    • 2.chip_sw_pwrmgr_normal_sleep_por_reset.39532831873728249827407630314031876760222058618198304780958131988295786664220
      Line 753, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

        UVM_ERROR @ 16857.638317 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 16857.638317 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 1 failures:

  • Test chip_sw_power_virus has 1 failures.

    • 2.chip_sw_power_virus.56964233779187827872424561398159161750044614542442939828900911662672446169035
      Line 920, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log

        UVM_ERROR @ 5285.002891 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 5285.002891 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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