Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67	33.33					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a	50.00	0.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b	50.00	0.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en	50.00	0.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en	66.67	33.33					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en	75.00	50.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en	75.00	50.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	0.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	0.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
47.62	0.00	42.86				100.00	u_prim_lc_or_hardened

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[3].u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	0.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	0.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
47.62	0.00	42.86				100.00	u_prim_lc_or_hardened

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[3].u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	0.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	0.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
67.66	92.41	50.91			50.85	76.47	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[3].u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67	33.33					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.00	28.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
67.66	92.41	50.91			50.85	76.47	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.25	43.75				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
67.66	92.41	50.91			50.85	76.47	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.25	43.75				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
67.66	92.41	50.91			50.85	76.47	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.25	43.75				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
67.66	92.41	50.91			50.85	76.47	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.94	28.24	14.29	17.96		58.33	40.91	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.94	28.24	14.29	17.96		58.33	40.91	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
75.00	50.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

SCORE	LINE
75.00	50.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

SCORE	LINE
75.00	50.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
50.00	0.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	0	1
106	0	3

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
50.00	0.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

SCORE	LINE
50.00	0.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	0	1
106	0	4

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
66.67	33.33

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		3	1	33.33
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	0	2

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	90	90	0	0
OutputsKnown_A	3937925	3868282	0	0
gen_flops.OutputDelay_A	3630626	3588824	0	180
gen_no_flops.OutputDelay_A	307299	278898	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90	90	0	0
T1	9	9	0	0
T2	9	9	0	0
T3	9	9	0	0
T4	9	9	0	0
T5	9	9	0	0
T6	9	9	0	0
T7	9	9	0	0
T8	9	9	0	0
T9	9	9	0	0
T10	9	9	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3937925	3868282	0	0
T1	384061	377377	0	0
T2	389929	383169	0	0
T3	473798	468592	0	0
T4	403010	393022	0	0
T5	310957	300800	0	0
T6	506938	501135	0	0
T7	313911	306526	0	0
T8	415327	407943	0	0
T9	320863	315592	0	0
T10	419131	414126	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3630626	3588824	0	180
T1	353524	349502	0	18
T2	358918	354862	0	18
T3	443786	440618	0	18
T4	370928	365018	0	18
T5	278800	272796	0	18
T6	476656	473128	0	18
T7	283314	278888	0	18
T8	384124	379708	0	18
T9	291586	288380	0	18
T10	388990	385924	0	18

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307299	278898	0	0
T1	30537	27819	0	0
T2	31011	28251	0	0
T3	30012	27918	0	0
T4	32082	27948	0	0
T5	32157	27948	0	0
T6	30282	27951	0	0
T7	30597	27582	0	0
T8	31203	28179	0	0
T9	29277	27156	0	0
T10	30141	28146	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	0	1
106	0	4

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	10	10	0	0
OutputsKnown_A	102433	92966	0	0
gen_no_flops.OutputDelay_A	102433	92966	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	0	1
106	0	4

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	10	10	0	0
OutputsKnown_A	102433	92966	0	0
gen_no_flops.OutputDelay_A	102433	92966	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	0	1
106	0	3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	10	10	0	0
OutputsKnown_A	102433	92966	0	0
gen_no_flops.OutputDelay_A	102433	92966	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		3	1	33.33
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	0	2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	10	10	0	0
OutputsKnown_A	102433	92966	0	0
gen_flops.OutputDelay_A	102433	92886	0	30

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92886	0	30
T1	10179	9265	0	3
T2	10337	9409	0	3
T3	10004	9298	0	3
T4	10694	9308	0	3
T5	10719	9308	0	3
T6	10094	9309	0	3
T7	10199	9186	0	3
T8	10401	9385	0	3
T9	9759	9044	0	3
T10	10047	9374	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	1	50.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	0	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	10	10	0	0
OutputsKnown_A	102433	92966	0	0
gen_flops.OutputDelay_A	102433	92886	0	30

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92886	0	30
T1	10179	9265	0	3
T2	10337	9409	0	3
T3	10004	9298	0	3
T4	10694	9308	0	3
T5	10719	9308	0	3
T6	10094	9309	0	3
T7	10199	9186	0	3
T8	10401	9385	0	3
T9	9759	9044	0	3
T10	10047	9374	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

	Line No.	Total	Covered	Percent
TOTAL		2	1	50.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	0	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	10	10	0	0
OutputsKnown_A	102433	92966	0	0
gen_flops.OutputDelay_A	102433	92886	0	30

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92886	0	30
T1	10179	9265	0	3
T2	10337	9409	0	3
T3	10004	9298	0	3
T4	10694	9308	0	3
T5	10719	9308	0	3
T6	10094	9309	0	3
T7	10199	9186	0	3
T8	10401	9385	0	3
T9	9759	9044	0	3
T10	10047	9374	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

	Line No.	Total	Covered	Percent
TOTAL		2	1	50.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	0	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	10	10	0	0
OutputsKnown_A	102433	92966	0	0
gen_flops.OutputDelay_A	102433	92886	0	30

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92886	0	30
T1	10179	9265	0	3
T2	10337	9409	0	3
T3	10004	9298	0	3
T4	10694	9308	0	3
T5	10719	9308	0	3
T6	10094	9309	0	3
T7	10199	9186	0	3
T8	10401	9385	0	3
T9	9759	9044	0	3
T10	10047	9374	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	10	10	0	0
OutputsKnown_A	1610447	1608760	0	0
gen_flops.OutputDelay_A	1610447	1608640	0	30

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608640	0	30
T1	156404	156221	0	3
T2	158785	158613	0	3
T3	201885	201713	0	3
T4	164076	163893	0	3
T5	117962	117782	0	3
T6	218140	217946	0	3
T7	121259	121072	0	3
T8	171260	171084	0	3
T9	126275	126102	0	3
T10	174401	174214	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	10	10	0	0
OutputsKnown_A	1610447	1608760	0	0
gen_flops.OutputDelay_A	1610447	1608640	0	30

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608640	0	30
T1	156404	156221	0	3
T2	158785	158613	0	3
T3	201885	201713	0	3
T4	164076	163893	0	3
T5	117962	117782	0	3
T6	218140	217946	0	3
T7	121259	121072	0	3
T8	171260	171084	0	3
T9	126275	126102	0	3
T10	174401	174214	0	3