CHIP Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.059m	2.732ms	3	3	100.00
		chip_sw_example_rom	2.381m	2.867ms	3	3	100.00
		chip_sw_example_manufacturer	3.426m	2.270ms	3	3	100.00
		chip_sw_example_concurrency	4.442m	3.093ms	3	3	100.00
		chip_sw_uart_smoketest_signed	33.486m	9.017ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	5.700m	6.146ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.651m	5.366ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	22.968m	10.140ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.599h	51.535ms	3	5	60.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.213m	3.172ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.599h	51.535ms	3	5	60.00
		chip_csr_rw	11.651m	5.366ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.990s	265.232us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.342m	3.949ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.342m	3.949ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.342m	3.949ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	15.294m	5.326ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	15.294m	5.326ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	17.051m	5.725ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	15.608m	5.218ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	13.768m	5.581ms	1	5	20.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	54.470m	22.805ms	12	20	60.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	54.360m	23.204ms	4	5	80.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	31.974m	14.574ms	4	5	80.00
V1		TOTAL			187	223	83.86
V2	chip_pin_mux	chip_padctrl_attributes	5.624m	4.768ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.624m	4.768ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.711m	3.264ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	9.074m	4.436ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	7.652m	4.972ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	32.857m	20.118ms	5	5	100.00
		chip_tap_straps_testunlock0	17.898m	7.942ms	5	5	100.00
		chip_tap_straps_rma	17.233m	10.090ms	5	5	100.00
		chip_tap_straps_prod	21.630m	11.959ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.427m	2.425ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.527m	7.937ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	12.638m	5.202ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	12.638m	5.202ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.185m	7.618ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.040m	4.462ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	16.730m	5.461ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.002h	18.854ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.898m	2.428ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	17.916m	5.675ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.501m	3.516ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.862m	3.527ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.579m	3.214ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.903m	5.444ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.717m	3.160ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.762m	2.817ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	12.835m	4.772ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	12.835m	4.772ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.403m	5.244ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.449m	2.770ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.403m	5.244ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.944m	3.400ms	3	3	100.00
		chip_sw_aes_smoketest	6.230m	2.704ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.774m	3.044ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.038m	2.681ms	3	3	100.00
		chip_sw_csrng_smoketest	4.417m	2.898ms	3	3	100.00
		chip_sw_entropy_src_smoketest	8.731m	3.043ms	3	3	100.00
		chip_sw_gpio_smoketest	4.959m	2.816ms	3	3	100.00
		chip_sw_hmac_smoketest	7.012m	2.843ms	3	3	100.00
		chip_sw_kmac_smoketest	5.541m	3.471ms	3	3	100.00
		chip_sw_otbn_smoketest	33.598m	9.003ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.147m	2.935ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.264m	5.707ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.383m	5.314ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.544m	2.852ms	3	3	100.00
		chip_sw_rv_timer_smoketest	6.207m	2.370ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.700m	3.065ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.275m	2.500ms	3	3	100.00
		chip_sw_uart_smoketest	4.442m	2.619ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.906m	5.067ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	33.486m	9.017ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.621h	78.826ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	35.415m	8.991ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	38.584m	15.211ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.142m	4.290ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	11.159m	10.646ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.890h	57.845ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.147h	63.619ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	7.376m	4.511ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	7.376m	4.511ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.599h	51.535ms	3	5	60.00
		chip_same_csr_outstanding	1.304h	31.634ms	20	20	100.00
		chip_csr_hw_reset	5.700m	6.146ms	5	5	100.00
		chip_csr_rw	11.651m	5.366ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.599h	51.535ms	3	5	60.00
		chip_same_csr_outstanding	1.304h	31.634ms	20	20	100.00
		chip_csr_hw_reset	5.700m	6.146ms	5	5	100.00
		chip_csr_rw	11.651m	5.366ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.594m	2.632ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.470s	58.539us	100	100	100.00
		xbar_smoke_large_delays	1.999m	10.092ms	100	100	100.00
		xbar_smoke_slow_rsp	2.046m	6.804ms	100	100	100.00
		xbar_random_zero_delays	57.580s	580.885us	100	100	100.00
		xbar_random_large_delays	22.327m	104.762ms	100	100	100.00
		xbar_random_slow_rsp	23.510m	66.498ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.079m	1.550ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.071m	1.378ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.526m	2.285ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.071m	1.378ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.685m	3.722ms	100	100	100.00
		xbar_access_same_device_slow_rsp	51.627m	162.707ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.455m	2.597ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	14.062m	18.624ms	100	100	100.00
		xbar_stress_all_with_error	13.987m	21.591ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	19.026m	7.734ms	100	100	100.00
		xbar_stress_all_with_reset_error	21.891m	29.314ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	35.415m	8.991ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	49.516m	24.247ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	34.380m	7.921ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	28.046m	6.922ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	33.806m	8.811ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	37.873m	8.613ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	33.827m	8.532ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	32.524m	8.700ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.359m	6.473ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	33.695m	8.766ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	30.519m	8.670ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	35.577m	8.354ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	33.010m	8.111ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	45.383m	9.398ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	49.047m	12.646ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	44.503m	12.283ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	49.823m	12.321ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	53.989m	12.335ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	44.774m	9.901ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	51.162m	11.469ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	43.960m	11.642ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	54.078m	12.004ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	47.902m	11.977ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.208m	6.836ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	31.139m	8.633ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	33.193m	9.364ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	34.029m	8.975ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	33.180m	8.164ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	31.565m	7.266ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	33.224m	8.744ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	32.310m	8.813ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	29.069m	9.323ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	30.853m	8.824ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	25.325m	7.673ms	3	3	100.00
		rom_e2e_asm_init_dev	34.174m	8.772ms	3	3	100.00
		rom_e2e_asm_init_prod	32.503m	9.438ms	3	3	100.00
		rom_e2e_asm_init_prod_end	30.921m	8.394ms	3	3	100.00
		rom_e2e_asm_init_rma	36.536m	8.461ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	48.159m	10.515ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.485m	3.175ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.898m	2.428ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.093m	2.698ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.195m	3.155ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	8.000m	4.353ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.131m	19.632ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.131m	19.632ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.467m	3.646ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.264m	5.707ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.467m	3.646ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	18.884m	8.247ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	18.884m	8.247ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.823m	7.467ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.131m	5.792ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.688m	6.104ms	3	3	100.00
		chip_sw_aes_idle	5.195m	3.155ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.995m	2.718ms	3	3	100.00
		chip_sw_kmac_idle	4.376m	2.325ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.439m	4.325ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.914m	5.431ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	9.296m	4.801ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	11.192m	5.028ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	22.305m	9.713ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.848m	4.232ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.718m	4.869ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.104m	3.966ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.279m	4.551ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.287m	3.818ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.082m	4.433ms	3	3	100.00
		chip_sw_ast_clk_outputs	16.185m	7.618ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	18.034m	13.877ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.104m	3.966ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.279m	4.551ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.040m	4.462ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	16.730m	5.461ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.002h	18.854ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.898m	2.428ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	17.916m	5.675ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.501m	3.516ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.862m	3.527ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.579m	3.214ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.903m	5.444ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.717m	3.160ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.998m	3.328ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	13.416m	5.255ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	21.169m	7.685ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.104h	24.364ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.131m	2.673ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.802m	2.477ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.333m	4.025ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	4.972m	3.121ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.501m	5.555ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	38.054m	25.078ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	38.153m	12.197ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.185m	7.618ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.612m	4.406ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.552m	3.447ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.220m	6.220ms	98	100	98.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	29.392m	8.733ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	30.081m	7.846ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	9.069m	10.010ms	0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	24.013m	20.010ms	0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.023m	3.434ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	17.508m	7.474ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	36.863m	21.938ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.138m	3.464ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	42.740s	10.360us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.744m	4.968ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	36.863m	21.938ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	36.863m	21.938ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.036h	20.706ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.036h	20.706ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.191m	6.419ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.131m	19.632ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	45.886m	10.974ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.216m	3.136ms	3	3	100.00
		chip_sw_edn_entropy_reqs	21.119m	6.399ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.216m	3.136ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	30.081m	7.846ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.834m	2.896ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	35.634m	15.899ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	23.064m	5.351ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	16.730m	5.461ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.603m	4.124ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	13.040m	4.462ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	9.547m	10.010ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	35.634m	15.899ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	8.338m	3.490ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	8.598m	4.115ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.018m	5.103ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	9.547m	10.010ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.018m	5.103ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.018m	5.103ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	10.018m	5.103ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.018m	5.103ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.220m	6.220ms	98	100	98.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.469m	8.019ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	19.191m	5.254ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	12.755m	5.788ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	12.755m	5.788ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	7.229m	3.205ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.501m	3.516ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.995m	2.718ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	16.609m	5.355ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	16.996m	5.275ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	16.811m	5.809ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.536m	3.756ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	8.598m	4.115ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.862m	3.527ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	9.826m	5.022ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	8.000m	4.353ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	58.704m	17.984ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.185m	2.572ms	3	3	100.00
		chip_sw_kmac_mode_kmac	7.075m	2.710ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.579m	3.214ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	8.598m	4.115ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	17.991m	8.518ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.277m	2.239ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.231m	3.131ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.376m	2.325ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.546m	6.058ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	32.857m	20.118ms	5	5	100.00
		chip_tap_straps_rma	17.233m	10.090ms	5	5	100.00
		chip_tap_straps_prod	21.630m	11.959ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.828m	2.496ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	17.991m	8.518ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	17.991m	8.518ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	17.991m	8.518ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.597m	4.668ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	10.018m	5.103ms	3	3	100.00
		chip_sw_flash_rma_unlocked	9.547m	10.010ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.975m	4.936ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	23.168m	8.928ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	24.853m	7.483ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.502m	9.295ms	3	3	100.00
		chip_sw_lc_ctrl_transition	17.991m	8.518ms	15	15	100.00
		chip_sw_keymgr_key_derivation	8.598m	4.115ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	11.236m	8.188ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	8.933m	10.020ms	0	3	0.00
		chip_prim_tl_access	4.469m	8.019ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	18.034m	13.877ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.848m	4.232ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.718m	4.869ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.104m	3.966ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.279m	4.551ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.287m	3.818ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.082m	4.433ms	3	3	100.00
		chip_tap_straps_dev	32.857m	20.118ms	5	5	100.00
		chip_tap_straps_rma	17.233m	10.090ms	5	5	100.00
		chip_tap_straps_prod	21.630m	11.959ms	5	5	100.00
		chip_rv_dm_lc_disabled	7.427m	15.953ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.052m	2.709ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.753m	3.310ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.195m	3.363ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.574m	4.026ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	43.297m	24.251ms	3	3	100.00
		chip_rv_dm_lc_disabled	7.427m	15.953ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.508h	49.924ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.418h	49.518ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	21.372m	10.179ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.407h	46.008ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	43.297m	24.251ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.009m	2.739ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.154m	2.482ms	3	3	100.00
		rom_volatile_raw_unlock	1.818m	2.528ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	17.991m	8.518ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	35.634m	15.899ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.247m	4.027ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.598m	4.115ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.871m	5.126ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.245m	2.553ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	35.634m	15.899ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.247m	4.027ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.598m	4.115ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.871m	5.126ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.245m	2.553ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	17.991m	8.518ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.245m	14.524ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.828m	2.496ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.975m	4.936ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	23.168m	8.928ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	24.853m	7.483ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.502m	9.295ms	3	3	100.00
		chip_sw_lc_ctrl_transition	17.991m	8.518ms	15	15	100.00
		chip_prim_tl_access	4.469m	8.019ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.469m	8.019ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.015m	8.864ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	39.573m	22.023ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.735m	7.228ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.797m	8.629ms	2	3	66.67
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	10.469m	16.324ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	28.313m	22.435ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	30.678m	17.916ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	18.884m	8.247ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	21.758m	10.344ms	2	3	66.67
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	9.416m	3.912ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.015m	8.864ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	8.157m	4.979ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.007h	35.253ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	10.287m	6.134ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	8.033m	4.970ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	39.314m	20.436ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	17.508m	7.474ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	29.690m	9.935ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	44.771m	21.643ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.925m	3.210ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.220m	6.220ms	98	100	98.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.236m	8.188ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.236m	8.188ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	29.690m	9.935ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	39.314m	20.436ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	9.416m	3.912ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.264m	5.707ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.978m	4.204ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	11.286m	5.331ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.054m	3.911ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	31.183m	11.567ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.080m	2.947ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.220m	6.220ms	98	100	98.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	31.494m	8.899ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	20.435m	5.778ms	3	3	100.00
		chip_plic_all_irqs_10	10.694m	3.630ms	3	3	100.00
		chip_plic_all_irqs_20	14.557m	4.680ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	6.246m	2.665ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.053m	2.977ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	35.415m	8.991ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.015m	8.142ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	9.381m	4.571ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.000m	3.122ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.482m	3.541ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.871m	5.126ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.903m	5.444ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	13.443m	6.225ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	16.378m	8.624ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.933m	10.020ms	0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.220m	6.220ms	98	100	98.00
		chip_sw_data_integrity_escalation	12.638m	5.202ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.117m	2.843ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.606m	2.900ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.444m	3.217ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	11.862m	3.563ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	35.597m	8.163ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.814h	31.586ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	49.768m	12.068ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.792m	3.070ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.546m	6.058ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.220m	6.220ms	98	100	98.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.464m	3.401ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	31.183m	11.567ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.096m	5.523ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.816m	3.507ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	23.434m	12.791ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	29.392m	8.733ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	31.494m	8.899ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.493h	255.540ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	41.184m	18.541ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	26.838m	13.703ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.978m	4.204ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	8.900m	4.419ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.684m	3.348ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	17.233m	10.090ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	7.427m	15.953ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2587	2657	97.37
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.606m	2.688ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.834h	50.732ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.516m	4.134ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.981m	2.661ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.158m	2.697ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.735m	2.146ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.061h	50.770ms	0	1	0.00
		rom_e2e_jtag_inject_dev	41.907m	40.712ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.183h	51.732ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	38.903m	9.630ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.872m	3.588ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.966m	2.914ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	27.580m	5.780ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	34.273m	11.265ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.913m	3.731ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	19.568m	5.237ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.215m	2.593ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.271m	5.336ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	6.162m	23.019ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	8.720m	4.560ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	29.690m	9.935ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.220m	6.220ms	98	100	98.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	15.294m	5.326ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.195h	18.401ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.981m	2.661ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.158m	2.697ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.735m	2.146ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.331m	4.594ms	3	3	100.00
V3		TOTAL			30	48	62.50
	Unmapped tests	chip_sival_flash_info_access	5.335m	2.940ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	11.627m	5.655ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.026h	17.304ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	17.006m	5.577ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	16.685m	4.847ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.325m	6.109ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.743m	2.832ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.534m	2.216ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2831	2958	95.71

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	13	68.42
V2	290	276	250	86.21
V2S	1	1	1	100.00
V3	91	22	12	13.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.89	95.27	93.76	95.04	--	94.38	97.38	99.53

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.62975004719122976135194001971331449210828937269934349029255103547382207997010
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:41:02) Loading:
  (15:41:03) Loading:
  (15:41:03) Loading: 4 packages loaded
  (15:41:03) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:41:03) WARNING: Target pattern parsing failed.
  (15:41:03) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:41:03) INFO: Elapsed time: 18.634s
  (15:41:03) INFO: 0 processes.
  (15:41:03) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.46861548575756603028667389378794834104631150336346809562666762266534667275061
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:51:16) Loading:
  (15:51:17) Loading:
  (15:51:17) Loading: 4 packages loaded
  (15:51:17) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:51:17) WARNING: Target pattern parsing failed.
  (15:51:17) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:51:17) INFO: Elapsed time: 25.362s
  (15:51:17) INFO: 0 processes.
  (15:51:17) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.46535056602539485065153152998323832149552459972455465677862251902706726922107
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:42:30) Loading:
  (15:42:31) Loading:
  (15:42:31) Loading: 4 packages loaded
  (15:42:31) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:42:31) WARNING: Target pattern parsing failed.
  (15:42:31) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:42:31) INFO: Elapsed time: 18.429s
  (15:42:31) INFO: 0 processes.
  (15:42:31) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.1202467619601360804722354671983532719170064585992599563318282038661341800305
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:52:46) Loading:
  (15:52:47) Loading:
  (15:52:47) Loading: 4 packages loaded
  (15:52:47) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:52:47) WARNING: Target pattern parsing failed.
  (15:52:47) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:52:47) INFO: Elapsed time: 20.920s
  (15:52:47) INFO: 0 processes.
  (15:52:47) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.96284536026299043724859653258249377794942481804593487583342416502737962525385
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:42:41) Loading:
  (15:42:42) Loading:
  (15:42:42) Loading: 4 packages loaded
  (15:42:42) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:42:42) WARNING: Target pattern parsing failed.
  (15:42:42) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:42:42) INFO: Elapsed time: 20.755s
  (15:42:42) INFO: 0 processes.
  (15:42:42) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.69703831793037062024205012139734846290762938438381468388945037904288701730575
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:52:48) Loading:
  (15:52:49) Loading:
  (15:52:49) Loading: 4 packages loaded
  (15:52:49) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:52:49) WARNING: Target pattern parsing failed.
  (15:52:49) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:52:49) INFO: Elapsed time: 18.446s
  (15:52:49) INFO: 0 processes.
  (15:52:49) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.80152528923090859929237528306651013133864373938854153244516187678923629637560
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:42:33) Loading:
  (15:42:34) Loading:
  (15:42:34) Loading: 4 packages loaded
  (15:42:34) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:42:34) WARNING: Target pattern parsing failed.
  (15:42:34) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:42:34) INFO: Elapsed time: 24.095s
  (15:42:34) INFO: 0 processes.
  (15:42:34) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.23350657052299913143109598469319569807747133865038796278100030425380511456250
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:52:40) Loading:
  (15:52:41) Loading:
  (15:52:41) Loading: 4 packages loaded
  (15:52:41) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:52:41) WARNING: Target pattern parsing failed.
  (15:52:41) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:52:41) INFO: Elapsed time: 17.534s
  (15:52:41) INFO: 0 processes.
  (15:52:41) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.91980659385657940021077188909571045560134761048159746446694440221892932392590
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:42:32) Loading:
  (15:42:33) Loading:
  (15:42:33) Loading: 4 packages loaded
  (15:42:33) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:42:33) WARNING: Target pattern parsing failed.
  (15:42:33) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:42:33) INFO: Elapsed time: 18.944s
  (15:42:33) INFO: 0 processes.
  (15:42:33) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.25971577787301586847159222807556521374567197204712472571078114817590851839045
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:52:55) Loading:
  (15:52:56) Loading:
  (15:52:56) Loading: 4 packages loaded
  (15:52:56) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:52:56) WARNING: Target pattern parsing failed.
  (15:52:56) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:52:56) INFO: Elapsed time: 23.934s
  (15:52:56) INFO: 0 processes.
  (15:52:56) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 9 more tests.

UVM_ERROR @ * us: (cip_base_vseq.sv:827) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.52571894141880148634197309722888796412737134662531992506863739030997254549808
    Line 374, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1945.505503 us: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1945.505503 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.21350262504346054439299904810562375111857911789260652111355226429243060464553
    Line 397, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2777.212135 us: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2777.212135 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt has 14 failures:
- Test chip_sw_uart_tx_rx_idx3 has 4 failures.
  - 0.chip_sw_uart_tx_rx_idx3.12466817007786837323084346425521515861800849776983008510490390696030657185673
    Line 784, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx3/latest/run.log
```
  UVM_ERROR @ 5159.540692 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 5159.540692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_uart_tx_rx_idx3.92621423811946522830522280906034442546838003697499639682971000194528613679012
    Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx3/latest/run.log
```
  UVM_ERROR @ 4476.287688 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 4476.287688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test chip_sw_uart_tx_rx_alt_clk_freq has 1 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq.17869284906069798036548081432816803801344179309436350127871814026935983569765
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log
```
  UVM_ERROR @ 4535.643958 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 4535.643958 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_alt_clk_freq_low_speed has 1 failures.
  - 2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.25147023742888226516849464605888888926100893297896176440064349849199587562561
    Line 801, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest/run.log
```
  UVM_ERROR @ 10900.749948 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 10900.749948 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_rand_baudrate has 8 failures.
  - 3.chip_sw_uart_rand_baudrate.39595531677235407970131608883662642138384347974894452879834002913578836614272
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest/run.log
```
  UVM_ERROR @ 5048.927860 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 5048.927860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.chip_sw_uart_rand_baudrate.108021973799907892273682460844029341608957254931987426360632128049386305536002
    Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/7.chip_sw_uart_rand_baudrate/latest/run.log
```
  UVM_ERROR @ 5144.071612 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 5144.071612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.28228274449182886157263685553925920694585678896519592217899439975083719859608
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:9183d88c-bca6-45f9-a6c2-747e1392dcbc
```
  - 1.chip_sw_rv_timer_systick_test.17897639887245866409781227268453022917354969601444656308193042821234424568832
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:55913e58-0e5d-4f2f-9583-d0c64480bebd
```
  - ... and 1 more failures.
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.72264738030697590502815643393248220148366585552224615136953527359306776685135
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:191972b5-f1f3-4039-a8bd-d7f0fe9df783
```
  - 1.chip_sw_ast_clk_rst_inputs.37602464974209791161725380013979022920548183678204095838194867253726466720775
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:8bc83fbf-1452-4c8e-b737-88368b280e88
```
  - ... and 1 more failures.
- Test chip_sw_power_virus has 2 failures.
  - 0.chip_sw_power_virus.59744098844554062907885540313735352802689918374644617832814173555343688948621
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:9ac74c5f-4f37-4dbf-9363-6b50451c505b
```
  - 2.chip_sw_power_virus.83627608440898034829815595817548110822873181745024846541681305868728251640805
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:cbf1ba2e-6c96-4de5-b823-2542dbcdcd46
```
UVM_FATAL @ * us: (chip_sw_flash_rma_unlocked_vseq.sv:159) [chip_sw_flash_rma_unlocked_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.33174389961775061063339621224075324939943864995102403878848676019627836373388
    Line 728, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.140001 us: (chip_sw_flash_rma_unlocked_vseq.sv:159) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_rma_unlocked.29755251241457869532869242734705286331526301592561717330046084496171485387761
    Line 711, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.160001 us: (chip_sw_flash_rma_unlocked_vseq.sv:159) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.37813746997333079652202595504554285944627937518581966192963142427506149881421
    Line 771, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.76562262522697825138201602440073560672592515075046277303624446542917032671512
    Line 750, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:57) [chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress has 3 failures:
- Test chip_sw_csrng_lc_hw_debug_en_test has 3 failures.
  - 0.chip_sw_csrng_lc_hw_debug_en_test.77204272832504236015886982412508790618077283196153051008374213812175419221149
    Line 815, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.260001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_lc_hw_debug_en_test.39034753423415041036829058531128617146602806014331130924930966345673043768580
    Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.300001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_entropy_src_fuse_vseq.sv:34) [chip_sw_entropy_src_fuse_vseq] *- has 3 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 3 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.84670199354840246592733750620616949198414008401172707133869427546303033188572
    Line 742, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.220001 us: (chip_sw_entropy_src_fuse_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_fuse_en_sw_app_read_test.96282961691988196088076457562967733220435905255987758167548297992307502714305
    Line 755, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.360001 us: (chip_sw_entropy_src_fuse_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_sram_ctrl_execution_main_vseq.sv:33) [chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_sram_ctrl_execution_main has 3 failures.
  - 0.chip_sw_sram_ctrl_execution_main.112210879889682777637422736831952155143599937786499483041771499918899640407400
    Line 784, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.360001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sram_ctrl_execution_main.33002900233319894919744851418976141355311092410150461285101489536393560287683
    Line 737, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.260001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.52734231438510586050481354504364328158113590858262145054354484653501739418164
    Line 766, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14524.378512 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14524.378512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.114461842273675333212002985539150341144757061005481229015513556672006164303156
    Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15362.237312 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15362.237312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.25893451827922222471560531835620433114398794565356487969691516694166052446259
    Line 785, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23423.202556 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23423.202556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2446804179447314155366977262934730047264733984150390198221142070771312202111
    Line 753, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23138.926892 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23138.926892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.94535727516774584402005373420578151440271479948756030192175275822047895418310
    Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3517.037697 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3517.037697 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.66914366092379277109717417454656249906335933364209471774727524430288417520469
    Line 732, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3348.042054 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3348.042054 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.509384006236823347683200297778158280644928833728410018448450011465971159441
    Line 748, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2661.465000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2661.465000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.21074839079315008977222486456118188453272547167363842268583187868350075971793
    Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2696.637000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2696.637000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.26515726999683226249225099193918522430638296173714646056594106503992686560742
    Line 717, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2145.800500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2145.800500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.98636150098801592716829883542389147613054094355711537810503625058668747645183
    Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 50769.694176 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 50769.694176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.63867199264116096327460369069197542921785373657047374768868305116604856540068
    Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 40712.081860 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 40712.081860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.12343051233908753191010755968614694527139827804355889206094915206530855017508
    Line 801, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 51732.048939 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 51732.048939 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns * has 3 failures:
- Test rom_e2e_self_hash has 3 failures.
  - 0.rom_e2e_self_hash.99574477838095828341915999813693299049134362917764591226539627370994217777433
    Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log
```
  UVM_ERROR @ 9115.156552 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
  UVM_INFO @ 9115.156552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_e2e_self_hash.90644958243029567402651393177373507460895891311927383211824880556917495187579
    Line 796, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log
```
  UVM_ERROR @ 9629.773290 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
  UVM_INFO @ 9629.773290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test chip_csr_aliasing has 2 failures.
  - 0.chip_csr_aliasing.76769914389194007200490308648436773038060720224154963465722585759835647775716
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:866db0c1-791d-4ef5-a6ed-8701ce44805e
```
  - 4.chip_csr_aliasing.45953254613316621613381767666596366615327732052656209306443171421416019961154
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:cbaed846-5f08-4314-b894-0b51ff7dd6d6
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 2 failures:
- Test chip_sw_pwrmgr_normal_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_por_reset.103882149068926895174728301311481092124167023066416844063032202189464515141424
    Line 771, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 16323.738315 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 16323.738315 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 1 failures.
  - 1.chip_sw_pwrmgr_deep_sleep_por_reset.41442693102332800480408763646257630150496452992353604555978113060553916310242
    Line 792, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 15719.955427 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15719.955427 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
- Test chip_sw_all_escalation_resets has 2 failures.
  - 13.chip_sw_all_escalation_resets.13189038418487375686456073560287724677473718457486918089340068664458316404274
    Line 818, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2640.818590 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2640.818590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 71.chip_sw_all_escalation_resets.83428200074772607659061232711698769492248324797905027275519394551874362310177
    Line 758, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3112.768920 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3112.768920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 33.chip_sw_alert_handler_lpg_sleep_mode_alerts.49414235160460235790160667313926946590954098528309150432153197663908428286445
    Line 796, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3902.455240 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3902.455240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.chip_sw_alert_handler_lpg_sleep_mode_alerts.55780896437290970919308043774740628570414760939758183565218223874439054760164
    Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3380.831600 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3380.831600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.52358642114947844345535438458510039363846122179657227992747763329279238560302
    Line 827, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 6312.107718 us: (tlul_assert.sv:263) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 6312.107718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 1.chip_sw_power_virus.28821690818122184848717089275171796671447179254337611892443652515199352685288
    Line 982, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4134.316218 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 4134.316218 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```