CHIP Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	3.674m	3.038ms	3	3	100.00
		chip_sw_example_rom	2.687m	2.936ms	3	3	100.00
		chip_sw_example_manufacturer	4.439m	3.084ms	3	3	100.00
		chip_sw_example_concurrency	4.478m	3.012ms	3	3	100.00
		chip_sw_uart_smoketest_signed	37.657m	8.867ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	7.235m	7.290ms	5	5	100.00
V1	csr_rw	chip_csr_rw	13.303m	5.715ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.389h	96.540ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.854h	56.161ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.976m	2.595ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.854h	56.161ms	5	5	100.00
		chip_csr_rw	13.303m	5.715ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.250s	268.956us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.079m	4.295ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.079m	4.295ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.079m	4.295ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	18.424m	5.251ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	18.424m	5.251ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	18.778m	4.979ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	20.250m	6.137ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	16.697m	5.288ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.252h	22.923ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.192h	23.482ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	42.301m	23.766ms	5	5	100.00
V1		TOTAL			203	223	91.03
V2	chip_pin_mux	chip_padctrl_attributes	5.210m	5.821ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.210m	5.821ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.919m	2.621ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.387m	3.915ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.330m	4.522ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	24.759m	13.226ms	5	5	100.00
		chip_tap_straps_testunlock0	9.800m	6.161ms	5	5	100.00
		chip_tap_straps_rma	15.317m	8.304ms	5	5	100.00
		chip_tap_straps_prod	24.691m	13.532ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.880m	2.808ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.009m	9.036ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.969m	5.368ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.969m	5.368ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	19.445m	7.815ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.089m	4.107ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.501m	5.423ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.072h	19.134ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.785m	2.773ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.235m	5.989ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.580m	2.678ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.921m	4.836ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.959m	2.943ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.455m	4.500ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.710m	2.398ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.527m	3.168ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	21.052m	7.566ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	21.052m	7.566ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.013m	5.069ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.541m	3.019ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.013m	5.069ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.045m	2.995ms	3	3	100.00
		chip_sw_aes_smoketest	6.293m	3.293ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.255m	3.160ms	3	3	100.00
		chip_sw_clkmgr_smoketest	6.061m	2.953ms	3	3	100.00
		chip_sw_csrng_smoketest	4.276m	3.068ms	3	3	100.00
		chip_sw_entropy_src_smoketest	11.784m	3.916ms	3	3	100.00
		chip_sw_gpio_smoketest	5.763m	2.574ms	3	3	100.00
		chip_sw_hmac_smoketest	7.371m	3.630ms	3	3	100.00
		chip_sw_kmac_smoketest	4.728m	3.152ms	3	3	100.00
		chip_sw_otbn_smoketest	41.019m	8.993ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.469m	2.381ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.550m	4.838ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.750m	4.678ms	3	3	100.00
		chip_sw_rv_plic_smoketest	3.397m	2.394ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.310m	3.383ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.757m	3.294ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.443m	2.775ms	3	3	100.00
		chip_sw_uart_smoketest	5.722m	2.795ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.425m	3.956ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	37.657m	8.867ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.743h	79.174ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.003m	8.499ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	33.549m	15.575ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	13.167m	4.412ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	6.646m	4.558ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.055h	59.867ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.523h	64.688ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	6.780m	5.131ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	6.780m	5.131ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.854h	56.161ms	5	5	100.00
		chip_same_csr_outstanding	1.219h	26.580ms	20	20	100.00
		chip_csr_hw_reset	7.235m	7.290ms	5	5	100.00
		chip_csr_rw	13.303m	5.715ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.854h	56.161ms	5	5	100.00
		chip_same_csr_outstanding	1.219h	26.580ms	20	20	100.00
		chip_csr_hw_reset	7.235m	7.290ms	5	5	100.00
		chip_csr_rw	13.303m	5.715ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.613m	2.266ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.600s	53.509us	100	100	100.00
		xbar_smoke_large_delays	2.095m	10.502ms	100	100	100.00
		xbar_smoke_slow_rsp	1.992m	6.533ms	100	100	100.00
		xbar_random_zero_delays	59.470s	615.402us	100	100	100.00
		xbar_random_large_delays	21.612m	116.910ms	100	100	100.00
		xbar_random_slow_rsp	23.591m	70.848ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	54.750s	1.254ms	100	100	100.00
		xbar_error_and_unmapped_addr	57.960s	1.342ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.528m	2.540ms	100	100	100.00
		xbar_error_and_unmapped_addr	57.960s	1.342ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.440m	4.159ms	100	100	100.00
		xbar_access_same_device_slow_rsp	52.228m	183.629ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.358m	2.535ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	12.107m	17.224ms	100	100	100.00
		xbar_stress_all_with_error	15.237m	23.330ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	15.268m	8.052ms	100	100	100.00
		xbar_stress_all_with_reset_error	20.041m	10.833ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.003m	8.499ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	50.071m	27.807ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	36.857m	9.176ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.501m	6.894ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	32.072m	9.184ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	33.896m	8.976ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	32.056m	8.524ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.557m	8.396ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.226m	6.947ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	37.763m	8.705ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	34.312m	8.607ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	41.818m	8.481ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	32.818m	8.829ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	43.866m	10.024ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	48.507m	12.496ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	43.451m	11.435ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	43.979m	12.159ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	44.722m	12.531ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	44.955m	9.870ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	46.193m	11.568ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	44.110m	11.027ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	51.128m	11.101ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	52.742m	12.124ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	27.026m	6.776ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	36.227m	9.069ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	34.066m	8.857ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	30.126m	8.061ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	32.746m	8.756ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	27.359m	6.751ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	33.135m	8.348ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	33.754m	8.769ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	33.692m	8.749ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	28.890m	8.488ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	26.512m	6.275ms	3	3	100.00
		rom_e2e_asm_init_dev	34.411m	9.235ms	3	3	100.00
		rom_e2e_asm_init_prod	41.751m	8.629ms	3	3	100.00
		rom_e2e_asm_init_prod_end	29.668m	9.044ms	3	3	100.00
		rom_e2e_asm_init_rma	34.215m	9.265ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.049m	10.980ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.527m	2.654ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.785m	2.773ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.799m	2.988ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.138m	3.584ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	10.683m	4.632ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.025m	19.116ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.025m	19.116ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	9.130m	4.320ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	7.550m	4.838ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	9.130m	4.320ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.311m	7.428ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.311m	7.428ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.755m	7.613ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.898m	5.437ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.125m	5.397ms	3	3	100.00
		chip_sw_aes_idle	5.138m	3.584ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.921m	2.771ms	3	3	100.00
		chip_sw_kmac_idle	5.579m	3.133ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	9.975m	4.910ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.603m	4.725ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.858m	4.842ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	8.298m	5.804ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	25.348m	10.218ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.160m	4.034ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.151m	5.032ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.577m	3.683ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.101m	4.693ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.386m	3.443ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.080m	4.274ms	3	3	100.00
		chip_sw_ast_clk_outputs	19.445m	7.815ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	23.562m	11.716ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.577m	3.683ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.101m	4.693ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.089m	4.107ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.501m	5.423ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.072h	19.134ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.785m	2.773ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.235m	5.989ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.580m	2.678ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.921m	4.836ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.959m	2.943ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.455m	4.500ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.710m	2.398ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.677m	3.215ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	13.008m	5.284ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	19.402m	7.329ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.168h	24.613ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.332m	2.665ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.477m	3.301ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.844m	5.164ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.373m	3.241ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	12.355m	5.239ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	32.337m	25.072ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	58.011m	21.255ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	19.445m	7.815ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.542m	4.913ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.186m	3.660ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.550m	6.523ms	98	100	98.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	34.579m	8.375ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	25.370m	6.871ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	9.711m	10.010ms	0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	19.033m	20.010ms	0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.277m	2.820ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	25.016m	7.592ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	33.397m	22.602ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	4.635m	2.887ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	45.640s	10.340us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	13.437m	4.470ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	33.397m	22.602ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	33.397m	22.602ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.035h	20.650ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.035h	20.650ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	7.732m	5.528ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.025m	19.116ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	54.274m	14.039ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.674m	2.306ms	3	3	100.00
		chip_sw_edn_entropy_reqs	15.957m	5.081ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.674m	2.306ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	25.370m	6.871ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.841m	2.731ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	35.582m	23.195ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.159m	5.815ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.501m	5.423ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	11.691m	4.453ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.089m	4.107ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	7.701m	10.010ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	35.582m	23.195ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.690m	3.629ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	8.810m	5.382ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	11.482m	4.680ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	7.701m	10.010ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	11.482m	4.680ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	11.482m	4.680ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	11.482m	4.680ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	11.482m	4.680ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.550m	6.523ms	98	100	98.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	6.416m	11.817ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	18.889m	5.524ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	12.651m	4.495ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	12.651m	4.495ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.380m	3.141ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.580m	2.678ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.921m	2.771ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	15.560m	5.152ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	16.872m	5.961ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	16.343m	5.384ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.324m	3.810ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	8.810m	5.382ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.921m	4.836ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	9.203m	5.456ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	10.683m	4.632ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.097h	12.984ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.717m	3.186ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.769m	2.965ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.959m	2.943ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	8.810m	5.382ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	18.239m	11.107ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	5.717m	2.955ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.969m	2.918ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.579m	3.133ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	8.244m	5.432ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	24.759m	13.226ms	5	5	100.00
		chip_tap_straps_rma	15.317m	8.304ms	5	5	100.00
		chip_tap_straps_prod	24.691m	13.532ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.923m	3.523ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	18.239m	11.107ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	18.239m	11.107ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	18.239m	11.107ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	8.861m	5.060ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	11.482m	4.680ms	3	3	100.00
		chip_sw_flash_rma_unlocked	7.701m	10.010ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.475m	4.351ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.128m	8.077ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.015m	7.982ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.677m	8.971ms	3	3	100.00
		chip_sw_lc_ctrl_transition	18.239m	11.107ms	15	15	100.00
		chip_sw_keymgr_key_derivation	8.810m	5.382ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	10.315m	9.817ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	12.107m	10.021ms	0	3	0.00
		chip_prim_tl_access	6.416m	11.817ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	23.562m	11.716ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.160m	4.034ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.151m	5.032ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.577m	3.683ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.101m	4.693ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.386m	3.443ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.080m	4.274ms	3	3	100.00
		chip_tap_straps_dev	24.759m	13.226ms	5	5	100.00
		chip_tap_straps_rma	15.317m	8.304ms	5	5	100.00
		chip_tap_straps_prod	24.691m	13.532ms	5	5	100.00
		chip_rv_dm_lc_disabled	6.827m	10.250ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.504m	3.432ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.178m	2.587ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.580m	3.292ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.228m	3.365ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	38.957m	24.416ms	3	3	100.00
		chip_rv_dm_lc_disabled	6.827m	10.250ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.517h	46.727ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.543h	46.471ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	15.727m	8.069ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.469h	45.370ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	38.957m	24.416ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.023m	2.656ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.956m	3.005ms	3	3	100.00
		rom_volatile_raw_unlock	1.790m	2.323ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	18.239m	11.107ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	35.582m	23.195ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.829m	3.268ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.810m	5.382ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.161m	4.952ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.284m	2.537ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	35.582m	23.195ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.829m	3.268ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.810m	5.382ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.161m	4.952ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.284m	2.537ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	18.239m	11.107ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	18.071m	14.415ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.923m	3.523ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.475m	4.351ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.128m	8.077ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.015m	7.982ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.677m	8.971ms	3	3	100.00
		chip_sw_lc_ctrl_transition	18.239m	11.107ms	15	15	100.00
		chip_prim_tl_access	6.416m	11.817ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	6.416m	11.817ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.766m	7.560ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	35.774m	19.109ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.460m	7.654ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	9.909m	16.976ms	1	3	33.33
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	13.677m	6.845ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	36.411m	24.123ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	28.157m	12.871ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	15.311m	7.428ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	28.390m	11.099ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.525m	4.010ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.766m	7.560ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	9.870m	4.904ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.088h	47.865ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.517m	7.478ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.910m	4.830ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	42.966m	25.615ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	25.016m	7.592ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	35.940m	13.254ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	51.415m	24.997ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.556m	3.136ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.550m	6.523ms	98	100	98.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.315m	9.817ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.315m	9.817ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	35.940m	13.254ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	42.966m	25.615ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	13.525m	4.010ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.550m	4.838ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.392m	3.529ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	12.422m	4.991ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.359m	4.481ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	31.271m	14.828ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	6.079m	2.684ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.550m	6.523ms	98	100	98.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	27.085m	9.060ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	20.807m	6.439ms	3	3	100.00
		chip_plic_all_irqs_10	12.467m	3.396ms	3	3	100.00
		chip_plic_all_irqs_20	16.036m	5.140ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.928m	3.435ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.969m	2.935ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.003m	8.499ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.911m	6.870ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	10.965m	4.221ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.245m	3.606ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.958m	3.443ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	13.161m	4.952ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.455m	4.500ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	11.186m	7.271ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	13.174m	8.446ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.107m	10.021ms	0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.550m	6.523ms	98	100	98.00
		chip_sw_data_integrity_escalation	14.969m	5.368ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.685m	2.484ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.217m	2.895ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	10.677m	3.546ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	8.044m	4.224ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	30.998m	7.573ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.841h	31.424ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	48.567m	12.019ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.777m	3.623ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	8.244m	5.432ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.550m	6.523ms	98	100	98.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	7.351m	3.326ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	31.271m	14.828ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	8.159m	5.356ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.967m	4.494ms	89	90	98.89
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	25.034m	10.196ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	34.579m	8.375ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	27.085m	9.060ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.471h	254.698ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	38.170m	18.264ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	25.106m	13.833ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.392m	3.529ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.545m	4.027ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.875m	3.802ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	15.317m	8.304ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.827m	10.250ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2587	2657	97.37
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.453m	2.663ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.769h	49.615ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	17.316m	5.652ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.746m	2.272ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.763m	2.475ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.807m	2.234ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	56.891m	40.537ms	0	1	0.00
		rom_e2e_jtag_inject_dev	51.554m	40.551ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.043h	48.895ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	40.582m	8.913ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	6.895m	3.222ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	12.493m	2.659ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	26.353m	5.746ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	34.398m	9.093ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.625m	3.392ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	18.101m	5.895ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.609m	3.248ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	7.847m	4.431ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	9.921m	23.442ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	10.788m	4.535ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	35.940m	13.254ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.550m	6.523ms	98	100	98.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	18.424m	5.251ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.310h	19.187ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.746m	2.272ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.763m	2.475ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.807m	2.234ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.261m	4.654ms	3	3	100.00
V3		TOTAL			30	48	62.50
	Unmapped tests	chip_sival_flash_info_access	6.902m	3.206ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	13.843m	5.591ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.065h	17.110ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	20.337m	5.280ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	14.431m	4.565ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.447m	5.444ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.673m	2.931ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.015m	2.873ms	2	3	66.67
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2846	2958	96.21

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	7	77.78
V1	19	19	18	94.74
V2	290	276	251	86.55
V2S	1	1	1	100.00
V3	91	22	12	13.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	95.43	94.14	95.01	--	94.90	97.38	99.49

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.25160596513956611764361157386064598953902850308831148214806781997925890757068
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:37:49) Loading:
  (15:37:49) Loading:
  (15:37:49) Loading: 4 packages loaded
  (15:37:49) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:37:49) WARNING: Target pattern parsing failed.
  (15:37:49) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:37:49) INFO: Elapsed time: 16.888s
  (15:37:49) INFO: 0 processes.
  (15:37:49) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.105629408939238663881574015780018769919150050376729321799888838992455152016440
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:46:53) Loading:
  (15:46:54) Loading:
  (15:46:54) Loading: 4 packages loaded
  (15:46:54) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:46:54) WARNING: Target pattern parsing failed.
  (15:46:54) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:46:54) INFO: Elapsed time: 29.163s
  (15:46:54) INFO: 0 processes.
  (15:46:54) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.17351986389877500829082667970381792774889684885765695273722164621261287793411
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:40:03) Loading:
  (15:40:04) Loading:
  (15:40:04) Loading: 4 packages loaded
  (15:40:04) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:40:04) WARNING: Target pattern parsing failed.
  (15:40:04) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:40:04) INFO: Elapsed time: 63.111s
  (15:40:04) INFO: 0 processes.
  (15:40:04) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.70799904570525030251371767876598958684333016052465817021718711707043520826932
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:47:33) Loading:
  (15:47:34) Loading:
  (15:47:34) Loading: 4 packages loaded
  (15:47:34) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:47:34) WARNING: Target pattern parsing failed.
  (15:47:34) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:47:34) INFO: Elapsed time: 19.170s
  (15:47:34) INFO: 0 processes.
  (15:47:34) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.19257182199346245440724629741822507985641933712610263371394124992532120474944
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:39:57) Loading:
  (15:39:58) Loading:
  (15:39:58) Loading: 4 packages loaded
  (15:39:58) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:39:58) WARNING: Target pattern parsing failed.
  (15:39:58) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:39:59) INFO: Elapsed time: 84.539s
  (15:39:59) INFO: 0 processes.
  (15:39:59) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.29077279809362785599413814263974777376361940780718478048538598642683450317313
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:47:25) Loading:
  (15:47:25) Loading:
  (15:47:25) Loading: 4 packages loaded
  (15:47:25) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:47:25) WARNING: Target pattern parsing failed.
  (15:47:25) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:47:26) INFO: Elapsed time: 16.938s
  (15:47:26) INFO: 0 processes.
  (15:47:26) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.61370133774947347333652723402402491521295932407357339763094527352982241760472
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:38:59) Loading:
  (15:39:00) Loading:
  (15:39:00) Loading: 4 packages loaded
  (15:39:00) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:39:00) WARNING: Target pattern parsing failed.
  (15:39:00) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:39:00) INFO: Elapsed time: 27.506s
  (15:39:00) INFO: 0 processes.
  (15:39:00) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.46331857834479704228675262476711780304796796320355011996673409462197060116933
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:47:31) Loading:
  (15:47:32) Loading:
  (15:47:32) Loading: 4 packages loaded
  (15:47:32) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:47:32) WARNING: Target pattern parsing failed.
  (15:47:32) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:47:32) INFO: Elapsed time: 19.203s
  (15:47:32) INFO: 0 processes.
  (15:47:32) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.63050904421722911562360071253496736760685908833885463583639930547683184646630
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:39:05) Loading:
  (15:39:06) Loading:
  (15:39:06) Loading: 4 packages loaded
  (15:39:06) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:39:06) WARNING: Target pattern parsing failed.
  (15:39:06) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:39:06) INFO: Elapsed time: 28.045s
  (15:39:06) INFO: 0 processes.
  (15:39:06) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.61213037855175937638396740412889278166125653284254188732673821539448113386581
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:48:06) Loading:
  (15:48:08) Loading:
  (15:48:08) Loading: 4 packages loaded
  (15:48:08) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:48:08) WARNING: Target pattern parsing failed.
  (15:48:08) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:48:08) INFO: Elapsed time: 39.997s
  (15:48:08) INFO: 0 processes.
  (15:48:08) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 9 more tests.

UVM_ERROR @ * us: (cip_base_vseq.sv:827) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.2203728615241250735055251188169054550839659125206415538553133114300484540158
    Line 394, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2477.738498 us: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2477.738498 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.14897396462015968603076062303806876430814163988332618551125696278399414985592
    Line 362, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2982.589114 us: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2982.589114 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.115430476405536902988353678574149917965653555621698359601304605020913169531698
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:b643dc39-d819-4c1e-83e3-4ccbd0bc567d
```
  - 1.chip_sw_rv_timer_systick_test.8699930061644020339458539184993303339744960267485111707384098970670719031187
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:b980eb27-4d63-40d7-a5df-54023a4b5287
```
  - ... and 1 more failures.
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.42153753575545812925249677187034686503169939339928887772400422827156635050989
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:df9d291d-5490-4eed-901a-f248673abd34
```
  - 1.chip_sw_ast_clk_rst_inputs.19641165473535824400260802378261254795003407731336822767414628666197488605876
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:c1126457-0f07-4ec8-b2aa-6c3f1bd838cf
```
  - ... and 1 more failures.
- Test chip_sw_power_virus has 1 failures.
  - 1.chip_sw_power_virus.83883324652584815565904341530258934864842465660636888274218058329905559380463
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:aee5f8a8-4951-42e4-a870-189e5572a319
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_pwrmgr_normal_sleep_por_reset has 2 failures.

0.chip_sw_pwrmgr_normal_sleep_por_reset.112343557111484186443351546561011692651678963350598222045405548734914381384879
Line 825, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

  UVM_ERROR @ 17237.679373 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17237.679373 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_pwrmgr_normal_sleep_por_reset.16355565620051013541327464077330760979213298533346820038595506630415403211364
Line 828, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

  UVM_ERROR @ 17050.470897 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17050.470897 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_pwrmgr_deep_sleep_por_reset has 2 failures.

1.chip_sw_pwrmgr_deep_sleep_por_reset.24876943223584383516319580771520114281286870745872435612851580141173726606428
Line 850, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

  UVM_ERROR @ 16976.096288 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 16976.096288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_pwrmgr_deep_sleep_por_reset.99713572106535688048416084640417768758395405071412784502478672911832163933124
Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

  UVM_ERROR @ 16089.023066 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 16089.023066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [chip_sw_flash_rma_unlocked_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.95935558266808793546156165266149029608633831595387613772435076825423616208675
    Line 722, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.140001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_rma_unlocked.77677990077604298095486930573355647576961166380083721695946683400877592526629
    Line 850, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.400001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.74446846339075515658978472268665811061046740879079805537390964740002482535853
    Line 771, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.7007362242289460840894097563633818663999326825402042234372876965551399510716
    Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress has 3 failures:
- Test chip_sw_csrng_lc_hw_debug_en_test has 3 failures.
  - 0.chip_sw_csrng_lc_hw_debug_en_test.102687924274902714836580655015090212443470849906023877936499603829997541429751
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.280001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_lc_hw_debug_en_test.26696101803877234198808845171979098054116962964506616483485437422250323039934
    Line 799, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.240001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_entropy_src_fuse_vseq.sv:33) [chip_sw_entropy_src_fuse_vseq] *- has 3 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 3 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.37443921053571350234554411744468777259300898819147315442299980070897958072288
    Line 815, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.360001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_fuse_en_sw_app_read_test.1924356363258868552939037853522736709673732756655603253239737381875751127620
    Line 782, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.240001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_sram_ctrl_execution_main has 3 failures.
  - 0.chip_sw_sram_ctrl_execution_main.12063982504710697259070908394681696684705698563082316857736546893368176184958
    Line 809, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.620001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.620001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sram_ctrl_execution_main.64645915671875618295886671158366842153911588486363561499302770225331072825040
    Line 745, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.680001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.680001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.98766931175350246532953491274850836995429589870980955293961228299020280299559
    Line 895, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15099.678908 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15099.678908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.90843751967616577632664620002670132106738660180074981505179707243111818478863
    Line 783, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14415.193244 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14415.193244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.47098926528389569393640850368019182975091720487534138034019289331095761459507
    Line 838, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 22975.874194 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 22975.874194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.64006497888377752702774504609624310669920998950454136786266757988851283827552
    Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23442.189080 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23442.189080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.56350166420157398239958320261320558700914206661127005836995401727595757208286
    Line 767, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3787.359703 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3787.359703 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.13558131164608912219290854525853828830971812730258915276285756014375367483387
    Line 771, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3801.908074 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3801.908074 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.72907230066725793284178251658674140431267950552151796092501135273182106460073
    Line 783, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2271.988000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2271.988000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.52952263675736848524828615048261474687312061011219363405592394832146755833081
    Line 824, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2475.303000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2475.303000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.115688557628160916337067855210098731261436042504682035203007800770804536019366
    Line 725, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2233.907000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2233.907000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.48279978508094646753183274691477092729869956691468798827218694648063064831891
    Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 40536.746888 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 40536.746888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.94086544849937285165265822780602094285729083517389317259028333777125586093345
    Line 832, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 40550.581788 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 40550.581788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.85102457685355072583235726112014633050953602763916969175025615577014031302494
    Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 48894.942266 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 48894.942266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns * has 3 failures:
- Test rom_e2e_self_hash has 3 failures.
  - 0.rom_e2e_self_hash.96536248380817774260772092116465126908421421172184872235205796834198473520008
    Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log
```
  UVM_ERROR @ 8912.982680 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
  UVM_INFO @ 8912.982680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_e2e_self_hash.6226632588835904227619965247679623934592484321238409557897927656849513263905
    Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log
```
  UVM_ERROR @ 8915.500010 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
  UVM_INFO @ 8915.500010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 2 failures:
- Test chip_sw_power_virus has 2 failures.
  - 0.chip_sw_power_virus.103284443962367462964838346128517057538721482909678458245434660543729182423357
    Line 1074, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5651.557616 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 5651.557616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_power_virus.10171967235512905273111763453182320653960260575881222472265597238428237104727
    Line 977, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4945.014820 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 4945.014820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
- Test chip_sw_all_escalation_resets has 2 failures.
  - 56.chip_sw_all_escalation_resets.94299623833680206065094517730813048377754339755458320580578330796773596846765
    Line 751, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3241.730616 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3241.730616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 65.chip_sw_all_escalation_resets.44437598192872483770050925725408573756597375466850875665001695264283478309398
    Line 850, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3341.604688 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3341.604688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:695) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.112664815510971472928687085791171496469895678591532611651269860845985150935702
    Line 886, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2222.613638 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:695) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2222.613638 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 55.chip_sw_alert_handler_lpg_sleep_mode_alerts.21060742059182129412101812800433753849935531066281997638150147310862411197815
    Line 810, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3474.922120 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a36 MTVAL=40600800
  UVM_INFO @ 3474.922120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```