CHIP Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.281m	3.020ms	3	3	100.00
		chip_sw_example_rom	2.371m	2.088ms	3	3	100.00
		chip_sw_example_manufacturer	4.130m	2.501ms	3	3	100.00
		chip_sw_example_concurrency	4.979m	2.578ms	3	3	100.00
		chip_sw_uart_smoketest_signed	35.809m	8.909ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	8.252m	5.969ms	5	5	100.00
V1	csr_rw	chip_csr_rw	12.153m	5.741ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.444h	57.224ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.751h	55.494ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.570m	3.077ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.751h	55.494ms	4	5	80.00
		chip_csr_rw	12.153m	5.741ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.350s	250.880us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.440m	4.313ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.440m	4.313ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.440m	4.313ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	16.235m	5.198ms	3	5	60.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	16.235m	5.198ms	3	5	60.00
		chip_sw_uart_tx_rx_idx1	17.138m	5.566ms	4	5	80.00
		chip_sw_uart_tx_rx_idx2	16.437m	5.668ms	4	5	80.00
		chip_sw_uart_tx_rx_idx3	13.787m	5.322ms	2	5	40.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.032h	22.697ms	11	20	55.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	32.414m	10.221ms	2	5	40.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	37.806m	23.475ms	4	5	80.00
V1		TOTAL			182	223	81.61
V2	chip_pin_mux	chip_padctrl_attributes	5.197m	4.784ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.197m	4.784ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.051m	3.489ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	10.215m	5.313ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.811m	3.768ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	32.302m	15.494ms	5	5	100.00
		chip_tap_straps_testunlock0	5.687m	4.404ms	5	5	100.00
		chip_tap_straps_rma	18.732m	10.280ms	5	5	100.00
		chip_tap_straps_prod	25.459m	13.057ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.684m	2.623ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	26.706m	8.630ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.932m	5.618ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.932m	5.618ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	17.757m	6.934ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	10.048m	4.601ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.848m	5.733ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.003h	18.575ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.863m	3.242ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.513m	5.152ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.891m	3.564ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.872m	5.356ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.771m	3.087ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.675m	4.798ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.722m	2.566ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.923m	2.788ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	18.120m	7.198ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	18.120m	7.198ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.240m	5.845ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.298m	2.012ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.240m	5.845ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.725m	2.624ms	3	3	100.00
		chip_sw_aes_smoketest	5.911m	3.200ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.993m	3.140ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.337m	2.411ms	3	3	100.00
		chip_sw_csrng_smoketest	4.305m	2.771ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.527m	4.136ms	3	3	100.00
		chip_sw_gpio_smoketest	4.920m	2.811ms	3	3	100.00
		chip_sw_hmac_smoketest	5.528m	3.620ms	3	3	100.00
		chip_sw_kmac_smoketest	4.185m	2.841ms	3	3	100.00
		chip_sw_otbn_smoketest	30.558m	8.443ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.568m	3.404ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.194m	5.383ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	9.134m	5.756ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.661m	2.863ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.443m	2.938ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.743m	2.752ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.579m	2.891ms	3	3	100.00
		chip_sw_uart_smoketest	4.542m	2.921ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.685m	5.586ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	35.809m	8.909ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.627h	78.152ms	0	3	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke	38.040m	8.952ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	36.415m	16.793ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.453m	4.314ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	7.194m	10.120ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.261h	58.322ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.285h	65.061ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	13.108m	6.109ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	13.108m	6.109ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.751h	55.494ms	4	5	80.00
		chip_same_csr_outstanding	1.075h	31.800ms	20	20	100.00
		chip_csr_hw_reset	8.252m	5.969ms	5	5	100.00
		chip_csr_rw	12.153m	5.741ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.751h	55.494ms	4	5	80.00
		chip_same_csr_outstanding	1.075h	31.800ms	20	20	100.00
		chip_csr_hw_reset	8.252m	5.969ms	5	5	100.00
		chip_csr_rw	12.153m	5.741ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.757m	2.402ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.780s	54.547us	100	100	100.00
		xbar_smoke_large_delays	2.078m	10.805ms	100	100	100.00
		xbar_smoke_slow_rsp	2.217m	7.162ms	100	100	100.00
		xbar_random_zero_delays	1.083m	611.595us	100	100	100.00
		xbar_random_large_delays	21.911m	118.153ms	100	100	100.00
		xbar_random_slow_rsp	20.731m	67.487ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.119m	1.348ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.174m	1.560ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.666m	2.531ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.174m	1.560ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.174m	4.002ms	100	100	100.00
		xbar_access_same_device_slow_rsp	45.687m	154.075ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.577m	2.655ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	14.461m	21.086ms	100	100	100.00
		xbar_stress_all_with_error	13.297m	18.696ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	17.034m	23.065ms	100	100	100.00
		xbar_stress_all_with_reset_error	15.544m	20.599ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	38.040m	8.952ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	52.270m	26.173ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	37.956m	8.972ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.292m	6.956ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	33.374m	8.151ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.847m	8.804ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	36.249m	8.358ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.677m	8.607ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	26.795m	7.414ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	33.771m	8.565ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	38.963m	9.226ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	38.270m	9.194ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	39.160m	7.828ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	46.502m	9.363ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	50.164m	12.569ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	56.527m	11.489ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	58.206m	12.229ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	55.770m	12.870ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	41.949m	10.318ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	46.378m	11.824ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	53.112m	11.925ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	50.517m	11.828ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	49.534m	12.523ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	32.155m	7.699ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	32.303m	9.335ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	33.048m	8.073ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	35.339m	8.517ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	32.362m	8.989ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	28.449m	6.894ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	29.274m	8.073ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	36.593m	8.805ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	35.865m	8.227ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	34.955m	8.412ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	35.709m	7.067ms	3	3	100.00
		rom_e2e_asm_init_dev	36.297m	8.213ms	3	3	100.00
		rom_e2e_asm_init_prod	40.134m	9.272ms	3	3	100.00
		rom_e2e_asm_init_prod_end	36.558m	8.235ms	3	3	100.00
		rom_e2e_asm_init_rma	37.438m	8.792ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	44.972m	10.947ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.750m	3.025ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.863m	3.242ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.471m	2.540ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.903m	2.950ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	11.359m	5.232ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.754m	19.098ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.754m	19.098ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.484m	3.528ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.194m	5.383ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.484m	3.528ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.825m	7.808ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.825m	7.808ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.755m	8.053ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.087m	4.804ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	18.162m	5.375ms	3	3	100.00
		chip_sw_aes_idle	4.903m	2.950ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.266m	3.430ms	3	3	100.00
		chip_sw_kmac_idle	4.618m	2.813ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	7.019m	5.475ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	10.495m	5.386ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.478m	4.203ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	8.032m	4.904ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	24.924m	11.747ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.329m	4.202ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.252m	5.063ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.072m	3.898ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	15.060m	4.972ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.829m	4.217ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.277m	4.468ms	3	3	100.00
		chip_sw_ast_clk_outputs	17.757m	6.934ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.946m	10.983ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.072m	3.898ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	15.060m	4.972ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	10.048m	4.601ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.848m	5.733ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.003h	18.575ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.863m	3.242ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.513m	5.152ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.891m	3.564ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.872m	5.356ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.771m	3.087ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.675m	4.798ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.722m	2.566ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.107m	2.986ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.062m	5.156ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	19.702m	7.359ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.286h	24.339ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.825m	3.503ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.514m	3.024ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.392m	5.648ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	7.089m	3.462ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.750m	5.522ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	37.616m	21.681ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.313h	29.266ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	17.757m	6.934ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.400m	4.852ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.829m	3.387ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.191m	5.380ms	99	100	99.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	39.933m	9.322ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	27.990m	7.854ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.681m	10.010ms	0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	24.610m	20.010ms	0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.562m	2.803ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.928m	8.158ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	29.754m	21.870ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.112m	3.588ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	45.090s	10.140us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.120m	4.713ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	29.754m	21.870ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	29.754m	21.870ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.013h	20.185ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.013h	20.185ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.747m	6.546ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.754m	19.098ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	59.029m	15.864ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.832m	2.594ms	3	3	100.00
		chip_sw_edn_entropy_reqs	25.680m	5.702ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.832m	2.594ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	27.990m	7.854ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.499m	3.008ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	36.681m	22.058ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.316m	5.025ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.848m	5.733ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	13.412m	3.943ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	10.048m	4.601ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	8.681m	10.010ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	36.681m	22.058ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.486m	3.457ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	8.167m	3.745ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.079m	4.924ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	8.681m	10.010ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.079m	4.924ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.079m	4.924ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	10.079m	4.924ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.079m	4.924ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.191m	5.380ms	99	100	99.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	7.879m	9.297ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	20.550m	6.220ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.282m	5.615ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.282m	5.615ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.065m	2.951ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.891m	3.564ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.266m	3.430ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	15.758m	5.853ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	17.515m	5.152ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	20.287m	5.731ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.883m	4.717ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	8.167m	3.745ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.872m	5.356ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	8.630m	3.829ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	11.359m	5.232ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.440h	19.251ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.526m	3.145ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.946m	3.518ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.771m	3.087ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	8.167m	3.745ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	20.725m	13.244ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.348m	3.073ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.085m	3.115ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.618m	2.813ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	9.431m	5.268ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	32.302m	15.494ms	5	5	100.00
		chip_tap_straps_rma	18.732m	10.280ms	5	5	100.00
		chip_tap_straps_prod	25.459m	13.057ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.580m	2.262ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	20.725m	13.244ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	20.725m	13.244ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	20.725m	13.244ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	10.434m	4.772ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	10.079m	4.924ms	3	3	100.00
		chip_sw_flash_rma_unlocked	8.681m	10.010ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.410m	4.458ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	25.623m	7.656ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	27.135m	8.390ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.705m	7.898ms	3	3	100.00
		chip_sw_lc_ctrl_transition	20.725m	13.244ms	15	15	100.00
		chip_sw_keymgr_key_derivation	8.167m	3.745ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	9.796m	8.387ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	8.321m	10.021ms	0	3	0.00
		chip_prim_tl_access	7.879m	9.297ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.946m	10.983ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.329m	4.202ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.252m	5.063ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.072m	3.898ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	15.060m	4.972ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.829m	4.217ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.277m	4.468ms	3	3	100.00
		chip_tap_straps_dev	32.302m	15.494ms	5	5	100.00
		chip_tap_straps_rma	18.732m	10.280ms	5	5	100.00
		chip_tap_straps_prod	25.459m	13.057ms	5	5	100.00
		chip_rv_dm_lc_disabled	6.194m	9.351ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.632m	2.891ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.809m	3.562ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.902m	2.899ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.091m	3.414ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	32.956m	22.620ms	3	3	100.00
		chip_rv_dm_lc_disabled	6.194m	9.351ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.574h	45.552ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.625h	47.957ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	21.270m	9.206ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.653h	48.031ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	32.956m	22.620ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.157m	2.075ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.817m	2.109ms	3	3	100.00
		rom_volatile_raw_unlock	2.163m	2.685ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	20.725m	13.244ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	36.681m	22.058ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.304m	3.706ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.167m	3.745ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.997m	5.379ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.353m	2.989ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	36.681m	22.058ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.304m	3.706ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.167m	3.745ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.997m	5.379ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.353m	2.989ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	20.725m	13.244ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	17.801m	14.839ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.580m	2.262ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.410m	4.458ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	25.623m	7.656ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	27.135m	8.390ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.705m	7.898ms	3	3	100.00
		chip_sw_lc_ctrl_transition	20.725m	13.244ms	15	15	100.00
		chip_prim_tl_access	7.879m	9.297ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.879m	9.297ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.056m	9.029ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	29.932m	19.896ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	8.492m	6.854ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	9.627m	6.617ms	1	3	33.33
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	8.310m	5.386ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	32.593m	22.611ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	26.411m	14.261ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	15.825m	7.808ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	26.902m	12.632ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.268m	5.514ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.056m	9.029ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	8.842m	3.901ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.100h	36.863ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.463m	5.704ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.983m	5.113ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	48.393m	26.076ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.928m	8.158ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	28.585m	11.412ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	47.142m	22.557ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.495m	2.767ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.191m	5.380ms	99	100	99.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.796m	8.387ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.796m	8.387ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	28.585m	11.412ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	48.393m	26.076ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	11.268m	5.514ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.194m	5.383ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.527m	5.027ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	9.347m	4.645ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.025m	3.956ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	31.256m	11.853ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.125m	2.401ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.191m	5.380ms	99	100	99.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	30.803m	7.062ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	21.213m	6.652ms	3	3	100.00
		chip_plic_all_irqs_10	10.353m	3.950ms	3	3	100.00
		chip_plic_all_irqs_20	15.529m	4.750ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.079m	2.429ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.797m	2.965ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	38.040m	8.952ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.311m	7.038ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	11.580m	4.339ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	9.024m	3.694ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.797m	2.881ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.997m	5.379ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.675m	4.798ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	14.382m	6.565ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	13.779m	8.361ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.321m	10.021ms	0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.191m	5.380ms	99	100	99.00
		chip_sw_data_integrity_escalation	14.932m	5.618ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.123m	2.513ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.787m	2.518ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.911m	4.032ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	11.534m	3.912ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	36.226m	8.393ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.952h	31.128ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	50.848m	11.775ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.294m	3.203ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	9.431m	5.268ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.191m	5.380ms	99	100	99.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.073m	3.782ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	31.256m	11.853ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.614m	5.817ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.097m	3.984ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	23.275m	12.033ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	39.933m	9.322ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	30.803m	7.062ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.690h	255.796ms	2	3	66.67
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	39.556m	18.759ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	27.107m	13.960ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.527m	5.027ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.517m	5.043ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.952m	3.537ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	18.732m	10.280ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.194m	9.351ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2585	2657	97.29
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.345m	3.338ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	18.158m	5.934ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.948m	2.314ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.424m	2.726ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.817m	2.029ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	44.348m	40.863ms	0	1	0.00
		rom_e2e_jtag_inject_dev	48.837m	40.394ms	0	1	0.00
		rom_e2e_jtag_inject_rma	47.573m	40.465ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	41.020m	9.169ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.509m	3.582ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.977m	3.017ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	27.546m	5.876ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	36.670m	9.945ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.786m	3.710ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	20.608m	5.892ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.982m	2.231ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.977m	5.738ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.386m	22.985ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.250m	4.338ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	28.585m	11.412ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.191m	5.380ms	99	100	99.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	16.235m	5.198ms	3	5	60.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.223h	18.453ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.948m	2.314ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.424m	2.726ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.817m	2.029ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	7.757m	4.871ms	3	3	100.00
V3		TOTAL			29	48	60.42
	Unmapped tests	chip_sival_flash_info_access	6.493m	3.715ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	11.427m	4.339ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.009h	16.791ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	18.506m	4.890ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.732m	4.940ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	8.454m	5.582ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	6.063m	2.785ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.984m	2.120ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2823	2958	95.44

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	10	52.63
V2	290	276	250	86.21
V2S	1	1	1	100.00
V3	91	22	11	12.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.89	95.29	93.76	94.97	--	94.48	97.20	99.64

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.95916384575894284045277747187424132353436011497405516753397548167789304763189
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:36:47) Loading:
  (15:36:48) Loading:
  (15:36:48) Loading: 4 packages loaded
  (15:36:48) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:36:48) WARNING: Target pattern parsing failed.
  (15:36:48) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:36:48) INFO: Elapsed time: 18.871s
  (15:36:48) INFO: 0 processes.
  (15:36:48) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.9169759627633979302138154331040274880380140783307666419436086868830936262664
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:39:48) Loading:
  (15:39:49) Loading:
  (15:39:49) Loading: 4 packages loaded
  (15:39:49) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:39:49) WARNING: Target pattern parsing failed.
  (15:39:49) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:39:49) INFO: Elapsed time: 21.017s
  (15:39:49) INFO: 0 processes.
  (15:39:49) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.28122044298705742426308538499603798168986802561922780794589716114276222014295
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:37:03) Loading:
  (15:37:04) Loading:
  (15:37:04) Loading: 4 packages loaded
  (15:37:04) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:37:04) WARNING: Target pattern parsing failed.
  (15:37:04) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:37:04) INFO: Elapsed time: 20.562s
  (15:37:04) INFO: 0 processes.
  (15:37:04) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.43006678575153566921336205542228944165515430558488550302248872147885755540099
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:42:53) Loading:
  (15:42:53) Loading:
  (15:42:53) Loading: 4 packages loaded
  (15:42:54) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:42:54) WARNING: Target pattern parsing failed.
  (15:42:54) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:42:54) INFO: Elapsed time: 60.635s
  (15:42:54) INFO: 0 processes.
  (15:42:54) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.9866540403602016910584270417966896857853698959288894151564967344069694154243
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:37:09) Loading:
  (15:37:10) Loading:
  (15:37:10) Loading: 4 packages loaded
  (15:37:10) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:37:10) WARNING: Target pattern parsing failed.
  (15:37:10) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:37:10) INFO: Elapsed time: 22.707s
  (15:37:10) INFO: 0 processes.
  (15:37:10) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.13254706990072614139255289437988064006271592992946498736081788561122973089614
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:42:49) Loading:
  (15:42:49) Loading:
  (15:42:49) Loading: 4 packages loaded
  (15:42:50) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:42:50) WARNING: Target pattern parsing failed.
  (15:42:50) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:42:50) INFO: Elapsed time: 87.362s
  (15:42:50) INFO: 0 processes.
  (15:42:50) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.45433472566321994304933856486638208066539929143553857114326454268738255934636
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:37:04) Loading:
  (15:37:05) Loading:
  (15:37:05) Loading: 4 packages loaded
  (15:37:05) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:37:05) WARNING: Target pattern parsing failed.
  (15:37:05) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:37:05) INFO: Elapsed time: 23.915s
  (15:37:05) INFO: 0 processes.
  (15:37:05) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.18032067758903389374922927454372551963605155761397751639246242788089254987521
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:44:21) Loading:
  (15:44:22) Loading:
  (15:44:22) Loading: 4 packages loaded
  (15:44:22) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:44:22) WARNING: Target pattern parsing failed.
  (15:44:22) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:44:23) INFO: Elapsed time: 116.451s
  (15:44:23) INFO: 0 processes.
  (15:44:23) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.36363002892025165336375889288647514297917056819361741556809932660155581940617
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:37:01) Loading:
  (15:37:02) Loading:
  (15:37:02) Loading: 4 packages loaded
  (15:37:02) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:37:02) WARNING: Target pattern parsing failed.
  (15:37:02) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:37:02) INFO: Elapsed time: 19.651s
  (15:37:02) INFO: 0 processes.
  (15:37:02) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.24294403652674432529638662444711759671781340238758553093419493895476155779050
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:43:40) Loading:
  (15:43:41) Loading:
  (15:43:41) Loading: 4 packages loaded
  (15:43:41) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:43:41) WARNING: Target pattern parsing failed.
  (15:43:41) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:43:41) INFO: Elapsed time: 76.350s
  (15:43:41) INFO: 0 processes.
  (15:43:41) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 9 more tests.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt has 22 failures:
- Test chip_sw_uart_rand_baudrate has 9 failures.
  - 0.chip_sw_uart_rand_baudrate.94996696802782012126182982012153304319591136869546199738795455217077450946948
    Line 850, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest/run.log
```
  UVM_ERROR @ 17466.413714 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 17466.413714 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.chip_sw_uart_rand_baudrate.110152963576065342034872173903121374660439069114920812098451250083078884128161
    Line 835, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest/run.log
```
  UVM_ERROR @ 4884.528260 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 4884.528260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
- Test chip_sw_uart_tx_rx has 2 failures.
  - 1.chip_sw_uart_tx_rx.91530248422313584091787112600192677575626100019381578905067689551106235961555
    Line 993, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log
```
  UVM_ERROR @ 4925.503308 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 4925.503308 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.chip_sw_uart_tx_rx.67874575662390791748226428380296790944717200346492673844789115823008073675608
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx/latest/run.log
```
  UVM_ERROR @ 4577.280416 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 4577.280416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_idx3 has 3 failures.
  - 1.chip_sw_uart_tx_rx_idx3.1555756421310910862073582563234168179799456050552151402120963180734256018970
    Line 982, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx3/latest/run.log
```
  UVM_ERROR @ 5208.833934 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 5208.833934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.chip_sw_uart_tx_rx_idx3.23368182328256683493572367943954488897388605394565155312485749353750731427934
    Line 794, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx3/latest/run.log
```
  UVM_ERROR @ 5286.348686 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 5286.348686 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_sw_uart_tx_rx_bootstrap has 2 failures.
  - 1.chip_sw_uart_tx_rx_bootstrap.91008758916710043264177738583650016057531273833773972775229717949188440802026
    Line 975, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  UVM_ERROR @ 78151.591535 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 78151.591535 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_uart_tx_rx_bootstrap.100241518446360628511253448615917340027045520883659866192530043368619849678400
    Line 825, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  UVM_ERROR @ 76606.076190 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 76606.076190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_alt_clk_freq_low_speed has 1 failures.
  - 1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.16271789170899945465287264167298656797302947223730219265559023551346282558734
    Line 976, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest/run.log
```
  UVM_ERROR @ 4546.226832 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 4546.226832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 3 more tests.
UVM_ERROR @ * us: (cip_base_vseq.sv:827) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.61616608777597177259879421757984636766719062786365409170943780835651324035363
    Line 419, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2407.027802 us: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2407.027802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.77018611134937536564270880364175576824767499385458600800676046833105692389739
    Line 374, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3008.781161 us: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3008.781161 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test chip_sw_uart_tx_rx_bootstrap has 1 failures.
  - 0.chip_sw_uart_tx_rx_bootstrap.31111220423568105484721924597221146479954514727686112417427446702289874673749
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:7a74eb81-b341-49b2-9e71-7319e277bdff
```
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.62558499628779186909487971601597854667156749367942965079566131230352825135592
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:f19bae19-7349-41e1-ba3c-2db3bfb3b4b3
```
  - 1.chip_sw_rv_timer_systick_test.53420254957476928262889272442537789232813489906944713661538656955154969910982
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:9c53f361-fbcd-4bae-af36-5a57c0174d01
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.8699494797381888545280502681790731851021807879585549104059053478126628068407
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:42d739cb-69d3-4ddc-9bac-8abe8b45135c
```
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.79841136065990226649638945796740427603823440151194528577595776858038761501967
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:e4a1c542-71cb-4768-a357-61b14e2e62e2
```
  - 1.chip_sw_ast_clk_rst_inputs.46641251287711402481126300296317349909243057821623565156566696634299495824441
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:d87d6527-bc42-4772-9d49-7ffc6ef4f597
```
  - ... and 1 more failures.
- Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 1 failures.
  - 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.75927647154844681649640196091834629703171314117356728140577861151286241427356
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
```
  Job ID: smart:021d6c3e-ea9e-4c1a-92ff-648e72c2fc4e
```
UVM_FATAL @ * us: (chip_sw_flash_rma_unlocked_vseq.sv:159) [chip_sw_flash_rma_unlocked_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.2765634697791885245916426384414921098400648588376144095863974284238929986299
    Line 710, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.180001 us: (chip_sw_flash_rma_unlocked_vseq.sv:159) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_rma_unlocked.69719996289770736883978449718990065769035476067090903977660323651071896294575
    Line 836, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.160001 us: (chip_sw_flash_rma_unlocked_vseq.sv:159) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.25707750737648752834028782120907326800107999290071084562752596214548030059497
    Line 865, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.70875730551848224532658822586108897702283584471234210559526882326461029414632
    Line 816, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:57) [chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress has 3 failures:
- Test chip_sw_csrng_lc_hw_debug_en_test has 3 failures.
  - 0.chip_sw_csrng_lc_hw_debug_en_test.29824927754951105206230951665072806234963147454464083111956287511377390167059
    Line 935, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.140001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_lc_hw_debug_en_test.8322697081189581670931400197242714583075402888267919432715784720730630675545
    Line 838, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.320001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_entropy_src_fuse_vseq.sv:34) [chip_sw_entropy_src_fuse_vseq] *- has 3 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 3 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.61911173605219367464832765991057064655098122228235689242490200667904294657613
    Line 833, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.340001 us: (chip_sw_entropy_src_fuse_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_fuse_en_sw_app_read_test.96738611714769282774158509557458770889733531707124089750903339545593674098497
    Line 766, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.200001 us: (chip_sw_entropy_src_fuse_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_sram_ctrl_execution_main_vseq.sv:33) [chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_sram_ctrl_execution_main has 3 failures.
  - 0.chip_sw_sram_ctrl_execution_main.54960677736683926297637123920926506811161868040162534292447326917646279036256
    Line 862, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.640001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.640001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sram_ctrl_execution_main.5481685477612541056758692845273685163313405077372770616989506693594829569205
    Line 1046, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.420001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.420001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.20807724836525157552024614471703643100244739511136779363366898731285797170469
    Line 868, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15185.914020 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15185.914020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.10804724600210139454651010042726351339580306285417749155894244493656516086963
    Line 834, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14839.446426 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14839.446426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.107009635896068698629751521450581266505401433147568569047429172242105954260611
    Line 978, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 22985.150952 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 22985.150952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.58676144963999724188537550103736192092968326332134092187482651478793507864715
    Line 1042, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23218.374892 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23218.374892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.49622266488760393694699195380304279342249089287280435307066506368298348720647
    Line 840, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3725.905468 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3725.905468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.90675013362914844130528336511545798512463026811831914526101631844883422700223
    Line 824, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3827.733049 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3827.733049 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 3 failures:
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.15990560957867287777448746384292707704987290029339723827236462493596849834440
    Line 1068, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5933.820776 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 5933.820776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_power_virus.9406997973338591044302152808016714759049917992007919906148529416801132189157
    Line 1064, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4683.356222 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 4683.356222 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.46849907893764597963345309777280452666256417008451973958328907017025781332008
    Line 824, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2313.858000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2313.858000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.115469951968859645483939706522769210554635916324505467666038234803797973257421
    Line 760, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2725.890000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2725.890000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.7430730811702628060065830338312713508540198560992812193188920100774566851041
    Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2029.340000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2029.340000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.49331011813925616704559383512295059898136738136468268757107089407616701905153
    Line 898, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 40863.463879 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 40863.463879 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.10087752370672450571194668648483015634554808559129646436373432347110012635451
    Line 915, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 40394.074786 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 40394.074786 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.9415398621585551590034797742648920148126075657677073887526417840632727693460
    Line 928, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 40464.799929 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 40464.799929 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns * has 3 failures:
- Test rom_e2e_self_hash has 3 failures.
  - 0.rom_e2e_self_hash.108470690440923971368311450225187046705605747322168281252512527430275133415586
    Line 818, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log
```
  UVM_ERROR @ 9169.449784 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
  UVM_INFO @ 9169.449784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_e2e_self_hash.30001637094055880108291306563745202788834750371593351762559212145156319793363
    Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log
```
  UVM_ERROR @ 8859.365754 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
  UVM_INFO @ 8859.365754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 2 failures:
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 2 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.28452761041999586973689321031340300586024788670154838632350207190637134783406
    Line 982, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 16245.335974 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 16245.335974 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 2.chip_sw_pwrmgr_deep_sleep_por_reset.322683649796176773565624286532304608875124724737161005308737872000507633028
    Line 752, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 16553.396055 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 16553.396055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 4.chip_sw_alert_handler_lpg_sleep_mode_alerts.50035491620678075043483765979726399886077428073361189004258398819060050539761
    Line 797, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3894.720940 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3894.720940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.chip_sw_alert_handler_lpg_sleep_mode_alerts.92552690462198346600967971729007483326967997054769711611402876547534909440651
    Line 786, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3921.100312 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3921.100312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 3.chip_csr_aliasing.33333851080779399699256133770775358162285375787329806575860149197170013709347
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:83d42a46-d249-4973-9bae-1e432a9d4c47
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 88.chip_sw_all_escalation_resets.88616903681817071200095311488178322310561903881060352537426828254560414579020
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/88.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2821.336902 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2821.336902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```