| T833 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3853438867 |
|
|
Mar 21 03:58:20 PM PDT 24 |
Mar 21 04:13:12 PM PDT 24 |
8506637702 ps |
| T315 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3608429005 |
|
|
Mar 21 04:07:28 PM PDT 24 |
Mar 21 04:11:14 PM PDT 24 |
2318739230 ps |
| T623 |
/workspace/coverage/default/0.chip_sw_power_idle_load.4262480835 |
|
|
Mar 21 04:02:45 PM PDT 24 |
Mar 21 04:14:40 PM PDT 24 |
4640088590 ps |
| T834 |
/workspace/coverage/default/0.chip_tap_straps_dev.3811494778 |
|
|
Mar 21 04:00:51 PM PDT 24 |
Mar 21 04:05:54 PM PDT 24 |
3912792407 ps |
| T835 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.3884544538 |
|
|
Mar 21 04:16:01 PM PDT 24 |
Mar 21 04:51:59 PM PDT 24 |
9724788008 ps |
| T359 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3376748063 |
|
|
Mar 21 03:57:28 PM PDT 24 |
Mar 21 04:02:16 PM PDT 24 |
3343978094 ps |
| T836 |
/workspace/coverage/default/0.chip_tap_straps_prod.50000376 |
|
|
Mar 21 03:59:20 PM PDT 24 |
Mar 21 04:01:42 PM PDT 24 |
2246799159 ps |
| T837 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2323504132 |
|
|
Mar 21 04:01:25 PM PDT 24 |
Mar 21 04:05:40 PM PDT 24 |
2996766436 ps |
| T838 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.411010786 |
|
|
Mar 21 04:02:28 PM PDT 24 |
Mar 21 04:20:03 PM PDT 24 |
6284173303 ps |
| T839 |
/workspace/coverage/default/2.rom_keymgr_functest.906072671 |
|
|
Mar 21 04:21:10 PM PDT 24 |
Mar 21 04:28:43 PM PDT 24 |
4872193520 ps |
| T840 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2910374643 |
|
|
Mar 21 04:00:46 PM PDT 24 |
Mar 21 04:07:48 PM PDT 24 |
4203033356 ps |
| T841 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1157539088 |
|
|
Mar 21 03:58:44 PM PDT 24 |
Mar 21 04:21:31 PM PDT 24 |
8658672164 ps |
| T842 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3109238413 |
|
|
Mar 21 04:00:51 PM PDT 24 |
Mar 21 04:05:09 PM PDT 24 |
3071489636 ps |
| T843 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.4160625986 |
|
|
Mar 21 04:18:26 PM PDT 24 |
Mar 21 04:25:58 PM PDT 24 |
3772131900 ps |
| T844 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2316948176 |
|
|
Mar 21 03:56:56 PM PDT 24 |
Mar 21 04:10:22 PM PDT 24 |
8143805923 ps |
| T391 |
/workspace/coverage/default/1.chip_jtag_mem_access.2159538995 |
|
|
Mar 21 04:02:02 PM PDT 24 |
Mar 21 04:29:14 PM PDT 24 |
13212927536 ps |
| T845 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.202489980 |
|
|
Mar 21 04:17:04 PM PDT 24 |
Mar 21 04:21:14 PM PDT 24 |
2856019304 ps |
| T846 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1899517878 |
|
|
Mar 21 04:18:57 PM PDT 24 |
Mar 21 04:29:53 PM PDT 24 |
4255071772 ps |
| T367 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3982205821 |
|
|
Mar 21 04:00:17 PM PDT 24 |
Mar 21 04:05:37 PM PDT 24 |
3779601192 ps |
| T338 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3065975437 |
|
|
Mar 21 03:59:14 PM PDT 24 |
Mar 21 04:09:58 PM PDT 24 |
5716855716 ps |
| T171 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.410631255 |
|
|
Mar 21 04:00:46 PM PDT 24 |
Mar 21 04:12:17 PM PDT 24 |
5837438464 ps |
| T847 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.4281456381 |
|
|
Mar 21 04:23:02 PM PDT 24 |
Mar 21 04:32:05 PM PDT 24 |
4958056500 ps |
| T480 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1903603634 |
|
|
Mar 21 04:20:28 PM PDT 24 |
Mar 21 04:33:36 PM PDT 24 |
4644808200 ps |
| T848 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2817086537 |
|
|
Mar 21 04:06:02 PM PDT 24 |
Mar 21 04:19:49 PM PDT 24 |
4939270998 ps |
| T680 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1692625927 |
|
|
Mar 21 04:28:48 PM PDT 24 |
Mar 21 04:35:55 PM PDT 24 |
3971568984 ps |
| T15 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2549544153 |
|
|
Mar 21 03:58:07 PM PDT 24 |
Mar 21 04:08:57 PM PDT 24 |
4430386036 ps |
| T849 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.3813723153 |
|
|
Mar 21 04:16:29 PM PDT 24 |
Mar 21 05:01:20 PM PDT 24 |
20950710648 ps |
| T713 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.942174376 |
|
|
Mar 21 04:29:58 PM PDT 24 |
Mar 21 04:34:35 PM PDT 24 |
3100248290 ps |
| T850 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1762830389 |
|
|
Mar 21 04:16:42 PM PDT 24 |
Mar 21 04:23:13 PM PDT 24 |
2805957519 ps |
| T851 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1217927204 |
|
|
Mar 21 04:00:06 PM PDT 24 |
Mar 21 04:15:42 PM PDT 24 |
6867161392 ps |
| T852 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3966867037 |
|
|
Mar 21 04:17:21 PM PDT 24 |
Mar 21 05:02:41 PM PDT 24 |
27528175763 ps |
| T136 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.606378608 |
|
|
Mar 21 03:56:28 PM PDT 24 |
Mar 21 04:03:43 PM PDT 24 |
4867760200 ps |
| T853 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.2202491030 |
|
|
Mar 21 04:25:07 PM PDT 24 |
Mar 21 04:53:41 PM PDT 24 |
8805875122 ps |
| T854 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.1834510713 |
|
|
Mar 21 04:02:05 PM PDT 24 |
Mar 21 04:05:27 PM PDT 24 |
2364335728 ps |
| T855 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1023666972 |
|
|
Mar 21 03:59:31 PM PDT 24 |
Mar 21 04:04:06 PM PDT 24 |
2283879050 ps |
| T397 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.245575196 |
|
|
Mar 21 04:19:41 PM PDT 24 |
Mar 21 05:32:19 PM PDT 24 |
24791265264 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1746226276 |
|
|
Mar 21 04:17:01 PM PDT 24 |
Mar 21 04:29:48 PM PDT 24 |
4698547816 ps |
| T856 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.3133149550 |
|
|
Mar 21 04:14:40 PM PDT 24 |
Mar 21 04:22:58 PM PDT 24 |
3931127740 ps |
| T34 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2971795346 |
|
|
Mar 21 04:14:07 PM PDT 24 |
Mar 21 04:18:41 PM PDT 24 |
3184895320 ps |
| T152 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3502979446 |
|
|
Mar 21 04:11:24 PM PDT 24 |
Mar 21 04:53:03 PM PDT 24 |
14933025664 ps |
| T112 |
/workspace/coverage/default/1.rom_raw_unlock.1841022918 |
|
|
Mar 21 04:12:59 PM PDT 24 |
Mar 21 04:39:30 PM PDT 24 |
17022999014 ps |
| T482 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1169031977 |
|
|
Mar 21 04:13:47 PM PDT 24 |
Mar 21 04:41:42 PM PDT 24 |
13661742065 ps |
| T703 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1045926724 |
|
|
Mar 21 04:29:16 PM PDT 24 |
Mar 21 04:37:39 PM PDT 24 |
5115756760 ps |
| T857 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.162975971 |
|
|
Mar 21 04:05:35 PM PDT 24 |
Mar 21 04:35:36 PM PDT 24 |
8571431800 ps |
| T674 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3615710568 |
|
|
Mar 21 04:24:30 PM PDT 24 |
Mar 21 04:37:26 PM PDT 24 |
5825622040 ps |
| T858 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2342279216 |
|
|
Mar 21 04:08:48 PM PDT 24 |
Mar 21 04:45:34 PM PDT 24 |
24756227302 ps |
| T198 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2452885501 |
|
|
Mar 21 03:59:03 PM PDT 24 |
Mar 21 04:05:49 PM PDT 24 |
3897530034 ps |
| T859 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1002134857 |
|
|
Mar 21 04:07:47 PM PDT 24 |
Mar 21 04:31:40 PM PDT 24 |
7470942036 ps |
| T860 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.581880633 |
|
|
Mar 21 04:19:04 PM PDT 24 |
Mar 21 04:30:14 PM PDT 24 |
3467927828 ps |
| T139 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.369204135 |
|
|
Mar 21 03:58:24 PM PDT 24 |
Mar 21 05:34:11 PM PDT 24 |
47845110852 ps |
| T117 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3913270226 |
|
|
Mar 21 04:17:03 PM PDT 24 |
Mar 21 07:37:47 PM PDT 24 |
255107930550 ps |
| T861 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.583340572 |
|
|
Mar 21 03:58:33 PM PDT 24 |
Mar 21 07:03:40 PM PDT 24 |
65333743465 ps |
| T862 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2821343577 |
|
|
Mar 21 04:03:30 PM PDT 24 |
Mar 21 05:00:50 PM PDT 24 |
16354787581 ps |
| T613 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.769606849 |
|
|
Mar 21 04:27:34 PM PDT 24 |
Mar 21 04:34:57 PM PDT 24 |
4198536312 ps |
| T863 |
/workspace/coverage/default/1.rom_e2e_smoke.1026472987 |
|
|
Mar 21 04:11:55 PM PDT 24 |
Mar 21 04:42:38 PM PDT 24 |
8876650296 ps |
| T234 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.793860829 |
|
|
Mar 21 04:20:34 PM PDT 24 |
Mar 21 04:25:38 PM PDT 24 |
2948322588 ps |
| T864 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.807811064 |
|
|
Mar 21 04:15:10 PM PDT 24 |
Mar 21 04:34:47 PM PDT 24 |
9230959976 ps |
| T865 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1256706120 |
|
|
Mar 21 03:57:22 PM PDT 24 |
Mar 21 04:01:05 PM PDT 24 |
2640446952 ps |
| T650 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.908130683 |
|
|
Mar 21 04:26:25 PM PDT 24 |
Mar 21 04:35:04 PM PDT 24 |
4365779576 ps |
| T866 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2568995348 |
|
|
Mar 21 03:59:29 PM PDT 24 |
Mar 21 04:49:46 PM PDT 24 |
28393955600 ps |
| T172 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3787826792 |
|
|
Mar 21 04:17:26 PM PDT 24 |
Mar 21 04:28:54 PM PDT 24 |
6167853380 ps |
| T151 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2412412454 |
|
|
Mar 21 04:06:42 PM PDT 24 |
Mar 21 04:17:17 PM PDT 24 |
19120310648 ps |
| T867 |
/workspace/coverage/default/0.chip_sw_coremark.1994999334 |
|
|
Mar 21 03:58:50 PM PDT 24 |
Mar 21 06:36:12 PM PDT 24 |
50373624462 ps |
| T868 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2611023060 |
|
|
Mar 21 04:08:20 PM PDT 24 |
Mar 21 04:18:26 PM PDT 24 |
4269249296 ps |
| T644 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2126601365 |
|
|
Mar 21 04:27:01 PM PDT 24 |
Mar 21 04:32:47 PM PDT 24 |
3827701580 ps |
| T869 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2433853168 |
|
|
Mar 21 04:18:40 PM PDT 24 |
Mar 21 04:29:24 PM PDT 24 |
4723852248 ps |
| T870 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1973005296 |
|
|
Mar 21 03:58:07 PM PDT 24 |
Mar 21 04:04:07 PM PDT 24 |
3959615825 ps |
| T21 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3656475558 |
|
|
Mar 21 04:05:14 PM PDT 24 |
Mar 21 04:57:56 PM PDT 24 |
20556054737 ps |
| T871 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.105581835 |
|
|
Mar 21 03:58:37 PM PDT 24 |
Mar 21 04:13:16 PM PDT 24 |
9268054848 ps |
| T872 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2341494281 |
|
|
Mar 21 04:02:15 PM PDT 24 |
Mar 21 04:06:01 PM PDT 24 |
3291126510 ps |
| T303 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2201535078 |
|
|
Mar 21 03:56:41 PM PDT 24 |
Mar 21 04:12:37 PM PDT 24 |
5551133436 ps |
| T356 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.47344072 |
|
|
Mar 21 04:08:16 PM PDT 24 |
Mar 21 04:30:41 PM PDT 24 |
6772722880 ps |
| T873 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3334871486 |
|
|
Mar 21 04:08:01 PM PDT 24 |
Mar 21 04:17:49 PM PDT 24 |
4401769432 ps |
| T874 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.3580109927 |
|
|
Mar 21 03:57:25 PM PDT 24 |
Mar 21 04:12:45 PM PDT 24 |
5010997992 ps |
| T875 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.4258638246 |
|
|
Mar 21 04:18:07 PM PDT 24 |
Mar 21 04:25:55 PM PDT 24 |
4476995028 ps |
| T876 |
/workspace/coverage/default/0.rom_raw_unlock.1737188562 |
|
|
Mar 21 04:03:07 PM PDT 24 |
Mar 21 04:38:50 PM PDT 24 |
15459687988 ps |
| T295 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.78035915 |
|
|
Mar 21 04:02:40 PM PDT 24 |
Mar 21 04:20:24 PM PDT 24 |
6012625238 ps |
| T877 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.92004913 |
|
|
Mar 21 03:58:23 PM PDT 24 |
Mar 21 04:11:44 PM PDT 24 |
3989734626 ps |
| T299 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.198326970 |
|
|
Mar 21 04:23:32 PM PDT 24 |
Mar 21 04:54:38 PM PDT 24 |
13487949982 ps |
| T296 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1227272377 |
|
|
Mar 21 03:57:13 PM PDT 24 |
Mar 21 04:12:27 PM PDT 24 |
5291938660 ps |
| T878 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3514587381 |
|
|
Mar 21 03:59:21 PM PDT 24 |
Mar 21 04:11:20 PM PDT 24 |
5517160548 ps |
| T879 |
/workspace/coverage/default/2.chip_sw_aes_entropy.2160625035 |
|
|
Mar 21 04:23:08 PM PDT 24 |
Mar 21 04:28:28 PM PDT 24 |
2889445012 ps |
| T336 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1070207362 |
|
|
Mar 21 04:27:43 PM PDT 24 |
Mar 21 04:35:38 PM PDT 24 |
5681558832 ps |
| T283 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3256343838 |
|
|
Mar 21 04:02:42 PM PDT 24 |
Mar 21 04:30:39 PM PDT 24 |
14660911200 ps |
| T225 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2228460352 |
|
|
Mar 21 04:29:57 PM PDT 24 |
Mar 21 04:39:14 PM PDT 24 |
5646973400 ps |
| T238 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3260084132 |
|
|
Mar 21 04:31:02 PM PDT 24 |
Mar 21 04:40:28 PM PDT 24 |
4328055792 ps |
| T239 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.780039810 |
|
|
Mar 21 04:24:52 PM PDT 24 |
Mar 21 04:51:12 PM PDT 24 |
8612871004 ps |
| T240 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.731399466 |
|
|
Mar 21 04:03:10 PM PDT 24 |
Mar 21 04:13:27 PM PDT 24 |
8217918430 ps |
| T241 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2923249371 |
|
|
Mar 21 04:02:58 PM PDT 24 |
Mar 21 04:39:54 PM PDT 24 |
8160988990 ps |
| T242 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1766593451 |
|
|
Mar 21 04:01:22 PM PDT 24 |
Mar 21 04:06:05 PM PDT 24 |
2799223448 ps |
| T243 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1047563295 |
|
|
Mar 21 04:28:54 PM PDT 24 |
Mar 21 04:36:06 PM PDT 24 |
4793926056 ps |
| T244 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3076371045 |
|
|
Mar 21 04:01:37 PM PDT 24 |
Mar 21 04:19:02 PM PDT 24 |
8027319786 ps |
| T245 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2239969090 |
|
|
Mar 21 04:26:38 PM PDT 24 |
Mar 21 04:32:01 PM PDT 24 |
3947575800 ps |
| T168 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1166208117 |
|
|
Mar 21 03:58:48 PM PDT 24 |
Mar 21 04:06:56 PM PDT 24 |
5961559400 ps |
| T344 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2511262968 |
|
|
Mar 21 04:08:45 PM PDT 24 |
Mar 21 05:01:53 PM PDT 24 |
11167992500 ps |
| T880 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.694880691 |
|
|
Mar 21 04:14:38 PM PDT 24 |
Mar 21 04:20:37 PM PDT 24 |
3150656872 ps |
| T202 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1753921917 |
|
|
Mar 21 04:04:14 PM PDT 24 |
Mar 21 05:33:04 PM PDT 24 |
49385646485 ps |
| T681 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2861549124 |
|
|
Mar 21 04:23:06 PM PDT 24 |
Mar 21 04:31:33 PM PDT 24 |
3935630216 ps |
| T881 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.738748146 |
|
|
Mar 21 04:06:58 PM PDT 24 |
Mar 21 04:39:25 PM PDT 24 |
9474660756 ps |
| T882 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1142681845 |
|
|
Mar 21 04:04:39 PM PDT 24 |
Mar 21 04:27:12 PM PDT 24 |
8371025596 ps |
| T883 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3273850793 |
|
|
Mar 21 04:12:43 PM PDT 24 |
Mar 21 04:19:35 PM PDT 24 |
4024412388 ps |
| T66 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.1533327273 |
|
|
Mar 21 03:57:08 PM PDT 24 |
Mar 21 04:04:17 PM PDT 24 |
4921896524 ps |
| T884 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.385016170 |
|
|
Mar 21 04:09:44 PM PDT 24 |
Mar 21 04:19:57 PM PDT 24 |
4783981908 ps |
| T885 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1292003908 |
|
|
Mar 21 03:59:40 PM PDT 24 |
Mar 21 05:10:20 PM PDT 24 |
17409267300 ps |
| T26 |
/workspace/coverage/default/0.chip_sw_gpio.2630072694 |
|
|
Mar 21 03:56:59 PM PDT 24 |
Mar 21 04:05:34 PM PDT 24 |
4334466652 ps |
| T143 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.219230098 |
|
|
Mar 21 04:03:42 PM PDT 24 |
Mar 21 04:41:30 PM PDT 24 |
25572653200 ps |
| T203 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1079508126 |
|
|
Mar 21 04:06:41 PM PDT 24 |
Mar 21 05:24:37 PM PDT 24 |
49925711750 ps |
| T25 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.1632349537 |
|
|
Mar 21 03:57:27 PM PDT 24 |
Mar 21 04:32:47 PM PDT 24 |
8259193750 ps |
| T261 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3729778358 |
|
|
Mar 21 04:24:17 PM PDT 24 |
Mar 21 04:34:39 PM PDT 24 |
6021635388 ps |
| T886 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.553754980 |
|
|
Mar 21 03:56:47 PM PDT 24 |
Mar 21 04:02:56 PM PDT 24 |
3241715736 ps |
| T382 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.2958696931 |
|
|
Mar 21 03:59:07 PM PDT 24 |
Mar 21 04:03:46 PM PDT 24 |
2638557840 ps |
| T887 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4183639771 |
|
|
Mar 21 04:10:18 PM PDT 24 |
Mar 21 04:13:47 PM PDT 24 |
3130031860 ps |
| T597 |
/workspace/coverage/default/2.chip_tap_straps_dev.3244642252 |
|
|
Mar 21 04:19:41 PM PDT 24 |
Mar 21 04:42:34 PM PDT 24 |
14221638252 ps |
| T658 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3183641372 |
|
|
Mar 21 04:27:43 PM PDT 24 |
Mar 21 04:35:48 PM PDT 24 |
4910603624 ps |
| T685 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1075594615 |
|
|
Mar 21 04:29:46 PM PDT 24 |
Mar 21 04:40:38 PM PDT 24 |
5484905672 ps |
| T888 |
/workspace/coverage/default/0.chip_sw_example_concurrency.720188942 |
|
|
Mar 21 03:56:04 PM PDT 24 |
Mar 21 04:01:00 PM PDT 24 |
3081365726 ps |
| T889 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2772323377 |
|
|
Mar 21 04:10:34 PM PDT 24 |
Mar 21 04:21:48 PM PDT 24 |
5061617896 ps |
| T890 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.1555606021 |
|
|
Mar 21 04:06:21 PM PDT 24 |
Mar 21 04:32:20 PM PDT 24 |
6827950340 ps |
| T891 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3808371901 |
|
|
Mar 21 04:12:56 PM PDT 24 |
Mar 21 04:17:45 PM PDT 24 |
2107495376 ps |
| T892 |
/workspace/coverage/default/1.chip_sw_aes_enc.120309160 |
|
|
Mar 21 04:06:02 PM PDT 24 |
Mar 21 04:10:53 PM PDT 24 |
2539273052 ps |
| T893 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.4277887858 |
|
|
Mar 21 04:06:50 PM PDT 24 |
Mar 21 04:16:58 PM PDT 24 |
5019752464 ps |
| T894 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4129541292 |
|
|
Mar 21 04:05:55 PM PDT 24 |
Mar 21 04:40:50 PM PDT 24 |
8598402936 ps |
| T646 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.493439998 |
|
|
Mar 21 04:30:02 PM PDT 24 |
Mar 21 04:35:33 PM PDT 24 |
3882484296 ps |
| T657 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2513541899 |
|
|
Mar 21 03:57:13 PM PDT 24 |
Mar 21 04:07:01 PM PDT 24 |
5249359040 ps |
| T642 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2985424129 |
|
|
Mar 21 04:18:08 PM PDT 24 |
Mar 21 04:25:41 PM PDT 24 |
3802434794 ps |
| T895 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.3942684466 |
|
|
Mar 21 04:09:43 PM PDT 24 |
Mar 21 04:26:33 PM PDT 24 |
7170597896 ps |
| T896 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.1963489691 |
|
|
Mar 21 03:57:57 PM PDT 24 |
Mar 21 04:03:27 PM PDT 24 |
2949673424 ps |
| T285 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.1036587746 |
|
|
Mar 21 04:17:47 PM PDT 24 |
Mar 21 04:41:48 PM PDT 24 |
6301369080 ps |
| T897 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.3589110501 |
|
|
Mar 21 03:56:57 PM PDT 24 |
Mar 21 03:59:27 PM PDT 24 |
2206890634 ps |
| T627 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1955596316 |
|
|
Mar 21 04:00:20 PM PDT 24 |
Mar 21 04:04:49 PM PDT 24 |
3048455560 ps |
| T898 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.754714417 |
|
|
Mar 21 03:57:17 PM PDT 24 |
Mar 21 04:25:01 PM PDT 24 |
12378883193 ps |
| T144 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.740561412 |
|
|
Mar 21 04:15:50 PM PDT 24 |
Mar 21 04:18:16 PM PDT 24 |
3707631601 ps |
| T899 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.501772030 |
|
|
Mar 21 03:57:28 PM PDT 24 |
Mar 21 04:15:21 PM PDT 24 |
7030810044 ps |
| T683 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.722084223 |
|
|
Mar 21 04:23:38 PM PDT 24 |
Mar 21 04:29:13 PM PDT 24 |
3470845080 ps |
| T262 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3525821555 |
|
|
Mar 21 04:12:48 PM PDT 24 |
Mar 21 04:27:46 PM PDT 24 |
5069607116 ps |
| T692 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2612743394 |
|
|
Mar 21 04:26:06 PM PDT 24 |
Mar 21 04:36:05 PM PDT 24 |
5222446896 ps |
| T617 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.883789008 |
|
|
Mar 21 04:32:07 PM PDT 24 |
Mar 21 04:38:22 PM PDT 24 |
3463251332 ps |
| T199 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3995747312 |
|
|
Mar 21 04:09:36 PM PDT 24 |
Mar 21 04:17:30 PM PDT 24 |
5011696232 ps |
| T900 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2288544327 |
|
|
Mar 21 04:03:34 PM PDT 24 |
Mar 21 04:13:17 PM PDT 24 |
4604346930 ps |
| T653 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.1000495091 |
|
|
Mar 21 04:12:43 PM PDT 24 |
Mar 21 04:22:48 PM PDT 24 |
4250697720 ps |
| T342 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.510613770 |
|
|
Mar 21 04:26:38 PM PDT 24 |
Mar 21 04:32:23 PM PDT 24 |
3383591626 ps |
| T215 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3082211839 |
|
|
Mar 21 04:09:35 PM PDT 24 |
Mar 21 04:41:13 PM PDT 24 |
25402563698 ps |
| T730 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1851629659 |
|
|
Mar 21 04:28:36 PM PDT 24 |
Mar 21 04:39:37 PM PDT 24 |
6198060240 ps |
| T901 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4176593171 |
|
|
Mar 21 04:03:58 PM PDT 24 |
Mar 21 04:10:48 PM PDT 24 |
6159665724 ps |
| T902 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1319997126 |
|
|
Mar 21 04:03:44 PM PDT 24 |
Mar 21 04:24:50 PM PDT 24 |
7909643196 ps |
| T903 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1733680029 |
|
|
Mar 21 04:00:12 PM PDT 24 |
Mar 21 04:07:44 PM PDT 24 |
5104668790 ps |
| T592 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.4035951735 |
|
|
Mar 21 04:29:15 PM PDT 24 |
Mar 21 04:34:24 PM PDT 24 |
3920858000 ps |
| T904 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2838706933 |
|
|
Mar 21 03:58:54 PM PDT 24 |
Mar 21 04:04:50 PM PDT 24 |
3010507620 ps |
| T905 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1219410202 |
|
|
Mar 21 04:01:38 PM PDT 24 |
Mar 21 04:05:37 PM PDT 24 |
3258043286 ps |
| T906 |
/workspace/coverage/default/2.chip_sw_example_concurrency.2609997426 |
|
|
Mar 21 04:13:24 PM PDT 24 |
Mar 21 04:16:43 PM PDT 24 |
2509867622 ps |
| T907 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3852363113 |
|
|
Mar 21 04:08:51 PM PDT 24 |
Mar 21 04:40:29 PM PDT 24 |
8774392173 ps |
| T9 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3539884012 |
|
|
Mar 21 04:14:10 PM PDT 24 |
Mar 21 04:19:01 PM PDT 24 |
2827611903 ps |
| T48 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1065677246 |
|
|
Mar 21 03:59:06 PM PDT 24 |
Mar 21 04:21:51 PM PDT 24 |
18024237240 ps |
| T717 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.411437755 |
|
|
Mar 21 04:29:31 PM PDT 24 |
Mar 21 04:35:15 PM PDT 24 |
3383527748 ps |
| T27 |
/workspace/coverage/default/1.chip_sw_gpio.4213148255 |
|
|
Mar 21 04:02:36 PM PDT 24 |
Mar 21 04:09:18 PM PDT 24 |
3754608550 ps |
| T908 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.685713119 |
|
|
Mar 21 04:24:02 PM PDT 24 |
Mar 21 04:35:49 PM PDT 24 |
5158660472 ps |
| T214 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.685571710 |
|
|
Mar 21 04:07:05 PM PDT 24 |
Mar 21 04:53:11 PM PDT 24 |
12337204550 ps |
| T909 |
/workspace/coverage/default/1.chip_tap_straps_prod.3502374470 |
|
|
Mar 21 04:09:15 PM PDT 24 |
Mar 21 04:12:01 PM PDT 24 |
2987669822 ps |
| T216 |
/workspace/coverage/default/0.chip_sw_flash_init.1841074580 |
|
|
Mar 21 03:58:23 PM PDT 24 |
Mar 21 04:28:55 PM PDT 24 |
20212077890 ps |
| T689 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.3558874270 |
|
|
Mar 21 04:26:49 PM PDT 24 |
Mar 21 04:35:51 PM PDT 24 |
5591126622 ps |
| T910 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1593408598 |
|
|
Mar 21 04:19:19 PM PDT 24 |
Mar 21 04:37:35 PM PDT 24 |
7931452917 ps |
| T911 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.3203083376 |
|
|
Mar 21 04:25:26 PM PDT 24 |
Mar 21 04:54:52 PM PDT 24 |
9139469100 ps |
| T22 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.984288806 |
|
|
Mar 21 04:03:39 PM PDT 24 |
Mar 21 04:35:28 PM PDT 24 |
21056115696 ps |
| T912 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3626380970 |
|
|
Mar 21 04:20:36 PM PDT 24 |
Mar 21 04:25:35 PM PDT 24 |
3555997169 ps |
| T226 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1337641184 |
|
|
Mar 21 04:28:16 PM PDT 24 |
Mar 21 04:36:49 PM PDT 24 |
4352657196 ps |
| T913 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3157356078 |
|
|
Mar 21 04:09:33 PM PDT 24 |
Mar 21 04:22:42 PM PDT 24 |
7649504248 ps |
| T669 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3815148626 |
|
|
Mar 21 04:25:20 PM PDT 24 |
Mar 21 04:31:08 PM PDT 24 |
3181017660 ps |
| T656 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.747357570 |
|
|
Mar 21 04:29:40 PM PDT 24 |
Mar 21 04:36:36 PM PDT 24 |
3789767302 ps |
| T310 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3669737212 |
|
|
Mar 21 04:30:33 PM PDT 24 |
Mar 21 04:39:05 PM PDT 24 |
4654601050 ps |
| T289 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3581563921 |
|
|
Mar 21 04:20:13 PM PDT 24 |
Mar 21 04:30:49 PM PDT 24 |
4796250521 ps |
| T914 |
/workspace/coverage/default/1.chip_sw_edn_kat.3564007545 |
|
|
Mar 21 04:07:03 PM PDT 24 |
Mar 21 04:17:48 PM PDT 24 |
3709648880 ps |
| T915 |
/workspace/coverage/default/2.chip_sw_example_rom.2656603991 |
|
|
Mar 21 04:12:31 PM PDT 24 |
Mar 21 04:14:51 PM PDT 24 |
2789210006 ps |
| T208 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2600628317 |
|
|
Mar 21 04:08:26 PM PDT 24 |
Mar 21 04:17:14 PM PDT 24 |
3849493046 ps |
| T666 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3894090083 |
|
|
Mar 21 04:23:18 PM PDT 24 |
Mar 21 04:33:16 PM PDT 24 |
5556251794 ps |
| T360 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2820556480 |
|
|
Mar 21 04:13:30 PM PDT 24 |
Mar 21 04:18:36 PM PDT 24 |
3365755960 ps |
| T916 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.2540648358 |
|
|
Mar 21 04:21:31 PM PDT 24 |
Mar 21 04:26:19 PM PDT 24 |
2651509800 ps |
| T180 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.2338489946 |
|
|
Mar 21 03:57:59 PM PDT 24 |
Mar 21 04:59:55 PM PDT 24 |
19439418392 ps |
| T917 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1653622442 |
|
|
Mar 21 03:59:54 PM PDT 24 |
Mar 21 04:10:31 PM PDT 24 |
4872585000 ps |
| T67 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.1202059786 |
|
|
Mar 21 04:09:58 PM PDT 24 |
Mar 21 04:18:25 PM PDT 24 |
6711335538 ps |
| T305 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.92703500 |
|
|
Mar 21 04:13:39 PM PDT 24 |
Mar 21 04:30:09 PM PDT 24 |
5224839431 ps |
| T321 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2847986815 |
|
|
Mar 21 04:15:21 PM PDT 24 |
Mar 21 04:24:48 PM PDT 24 |
18986098568 ps |
| T918 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2043740480 |
|
|
Mar 21 03:58:23 PM PDT 24 |
Mar 21 04:08:52 PM PDT 24 |
3987186152 ps |
| T616 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2946091202 |
|
|
Mar 21 04:27:11 PM PDT 24 |
Mar 21 04:33:52 PM PDT 24 |
3487880016 ps |
| T919 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1763926109 |
|
|
Mar 21 04:02:51 PM PDT 24 |
Mar 21 04:08:53 PM PDT 24 |
3649891312 ps |
| T920 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2119026183 |
|
|
Mar 21 04:22:04 PM PDT 24 |
Mar 21 04:25:44 PM PDT 24 |
2855014115 ps |
| T921 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2083678492 |
|
|
Mar 21 04:25:32 PM PDT 24 |
Mar 21 04:41:58 PM PDT 24 |
11474921175 ps |
| T727 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2491952300 |
|
|
Mar 21 04:28:34 PM PDT 24 |
Mar 21 04:33:29 PM PDT 24 |
3281346776 ps |
| T595 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1355072834 |
|
|
Mar 21 04:09:44 PM PDT 24 |
Mar 21 04:21:11 PM PDT 24 |
5444630239 ps |
| T922 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.3666805931 |
|
|
Mar 21 04:15:11 PM PDT 24 |
Mar 21 04:21:37 PM PDT 24 |
2767078194 ps |
| T923 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.119548921 |
|
|
Mar 21 04:24:56 PM PDT 24 |
Mar 21 04:36:46 PM PDT 24 |
7175342314 ps |
| T924 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.593021141 |
|
|
Mar 21 04:20:00 PM PDT 24 |
Mar 21 04:26:05 PM PDT 24 |
3360721548 ps |
| T676 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1503601002 |
|
|
Mar 21 04:27:06 PM PDT 24 |
Mar 21 04:33:38 PM PDT 24 |
3650024402 ps |
| T925 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.344410758 |
|
|
Mar 21 03:55:47 PM PDT 24 |
Mar 21 06:59:04 PM PDT 24 |
57183635650 ps |
| T926 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.583911592 |
|
|
Mar 21 04:08:23 PM PDT 24 |
Mar 21 04:44:46 PM PDT 24 |
8802742228 ps |
| T80 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1727807565 |
|
|
Mar 21 04:06:58 PM PDT 24 |
Mar 21 04:10:51 PM PDT 24 |
2938864351 ps |
| T383 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2019103712 |
|
|
Mar 21 04:12:39 PM PDT 24 |
Mar 21 04:26:12 PM PDT 24 |
8796590481 ps |
| T87 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3951608946 |
|
|
Mar 21 04:30:53 PM PDT 24 |
Mar 21 04:39:04 PM PDT 24 |
3943772056 ps |
| T306 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2314952590 |
|
|
Mar 21 04:12:58 PM PDT 24 |
Mar 21 04:46:43 PM PDT 24 |
13454838079 ps |
| T927 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.1587364265 |
|
|
Mar 21 04:16:28 PM PDT 24 |
Mar 21 04:26:42 PM PDT 24 |
5113930482 ps |
| T687 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3646114559 |
|
|
Mar 21 04:28:06 PM PDT 24 |
Mar 21 04:38:03 PM PDT 24 |
5703552528 ps |
| T928 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2790226942 |
|
|
Mar 21 03:58:01 PM PDT 24 |
Mar 21 04:12:10 PM PDT 24 |
4866441000 ps |
| T929 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1995365585 |
|
|
Mar 21 04:13:07 PM PDT 24 |
Mar 21 04:45:16 PM PDT 24 |
34413397692 ps |
| T930 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3834497121 |
|
|
Mar 21 04:17:36 PM PDT 24 |
Mar 21 04:27:54 PM PDT 24 |
4634803592 ps |
| T177 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1476465223 |
|
|
Mar 21 04:20:07 PM PDT 24 |
Mar 21 04:25:14 PM PDT 24 |
3538372799 ps |
| T931 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3446214809 |
|
|
Mar 21 04:09:18 PM PDT 24 |
Mar 21 04:13:18 PM PDT 24 |
2394431566 ps |
| T932 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2873718630 |
|
|
Mar 21 04:29:35 PM PDT 24 |
Mar 21 04:38:51 PM PDT 24 |
4267419250 ps |
| T933 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.449472637 |
|
|
Mar 21 04:07:11 PM PDT 24 |
Mar 21 04:23:26 PM PDT 24 |
6775469716 ps |
| T934 |
/workspace/coverage/default/0.chip_sw_hmac_enc.3977643896 |
|
|
Mar 21 04:01:48 PM PDT 24 |
Mar 21 04:07:25 PM PDT 24 |
2782788450 ps |
| T686 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3957203453 |
|
|
Mar 21 04:32:07 PM PDT 24 |
Mar 21 04:41:42 PM PDT 24 |
6281950952 ps |
| T12 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1010690344 |
|
|
Mar 21 04:14:29 PM PDT 24 |
Mar 21 04:25:10 PM PDT 24 |
4151206080 ps |
| T935 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1845273471 |
|
|
Mar 21 04:22:49 PM PDT 24 |
Mar 21 04:27:15 PM PDT 24 |
3263518568 ps |
| T936 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3515619855 |
|
|
Mar 21 03:57:17 PM PDT 24 |
Mar 21 04:42:29 PM PDT 24 |
22280615793 ps |
| T651 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1069098513 |
|
|
Mar 21 04:28:20 PM PDT 24 |
Mar 21 04:33:43 PM PDT 24 |
3383148444 ps |
| T937 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.993812669 |
|
|
Mar 21 04:05:10 PM PDT 24 |
Mar 21 04:38:49 PM PDT 24 |
8008640860 ps |
| T81 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1771156566 |
|
|
Mar 21 03:58:54 PM PDT 24 |
Mar 21 04:17:07 PM PDT 24 |
9880312178 ps |
| T287 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.3965581193 |
|
|
Mar 21 03:59:39 PM PDT 24 |
Mar 21 04:21:50 PM PDT 24 |
6472877950 ps |
| T938 |
/workspace/coverage/default/2.chip_tap_straps_prod.3179977487 |
|
|
Mar 21 04:18:50 PM PDT 24 |
Mar 21 04:21:50 PM PDT 24 |
3073979308 ps |
| T222 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.162734255 |
|
|
Mar 21 04:18:57 PM PDT 24 |
Mar 21 04:49:51 PM PDT 24 |
23919658000 ps |
| T939 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2717525653 |
|
|
Mar 21 04:01:29 PM PDT 24 |
Mar 21 04:08:11 PM PDT 24 |
7403820700 ps |
| T940 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3319199341 |
|
|
Mar 21 04:31:04 PM PDT 24 |
Mar 21 04:36:09 PM PDT 24 |
4236803648 ps |
| T941 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1041524108 |
|
|
Mar 21 04:05:36 PM PDT 24 |
Mar 21 04:15:56 PM PDT 24 |
3668016376 ps |
| T699 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3840068639 |
|
|
Mar 21 04:30:16 PM PDT 24 |
Mar 21 04:42:34 PM PDT 24 |
5937793020 ps |
| T942 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1036372902 |
|
|
Mar 21 04:17:35 PM PDT 24 |
Mar 21 04:26:49 PM PDT 24 |
3555853304 ps |
| T943 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1328902646 |
|
|
Mar 21 04:23:35 PM PDT 24 |
Mar 21 04:31:49 PM PDT 24 |
6401471070 ps |
| T153 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.797114257 |
|
|
Mar 21 04:19:31 PM PDT 24 |
Mar 21 05:00:19 PM PDT 24 |
16064647443 ps |
| T944 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2021415909 |
|
|
Mar 21 04:14:57 PM PDT 24 |
Mar 21 04:25:15 PM PDT 24 |
4602113066 ps |
| T945 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.1942934610 |
|
|
Mar 21 04:22:55 PM PDT 24 |
Mar 21 04:40:38 PM PDT 24 |
5681663075 ps |
| T946 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.2858240485 |
|
|
Mar 21 04:00:50 PM PDT 24 |
Mar 21 04:09:39 PM PDT 24 |
4551393620 ps |
| T947 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.4223488557 |
|
|
Mar 21 04:26:40 PM PDT 24 |
Mar 21 04:38:58 PM PDT 24 |
5570846430 ps |
| T204 |
/workspace/coverage/default/0.chip_jtag_csr_rw.857526968 |
|
|
Mar 21 03:50:59 PM PDT 24 |
Mar 21 04:14:21 PM PDT 24 |
12293523885 ps |
| T948 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.302761443 |
|
|
Mar 21 04:18:16 PM PDT 24 |
Mar 21 04:23:04 PM PDT 24 |
2436862292 ps |
| T600 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.647569116 |
|
|
Mar 21 04:02:10 PM PDT 24 |
Mar 21 04:04:24 PM PDT 24 |
3945119177 ps |
| T949 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.3827693713 |
|
|
Mar 21 04:01:15 PM PDT 24 |
Mar 21 04:05:01 PM PDT 24 |
2977754298 ps |
| T50 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1891753165 |
|
|
Mar 21 04:13:54 PM PDT 24 |
Mar 21 04:23:28 PM PDT 24 |
5964518216 ps |
| T950 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.646322933 |
|
|
Mar 21 03:59:32 PM PDT 24 |
Mar 21 04:05:20 PM PDT 24 |
2704368464 ps |
| T339 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.1490473402 |
|
|
Mar 21 04:07:37 PM PDT 24 |
Mar 21 04:16:41 PM PDT 24 |
3425995656 ps |
| T340 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.187413294 |
|
|
Mar 21 03:57:55 PM PDT 24 |
Mar 21 04:07:54 PM PDT 24 |
2550801816 ps |
| T263 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2823350868 |
|
|
Mar 21 04:10:32 PM PDT 24 |
Mar 21 04:19:00 PM PDT 24 |
4343960654 ps |
| T951 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3575646807 |
|
|
Mar 21 04:13:21 PM PDT 24 |
Mar 21 04:27:41 PM PDT 24 |
9704467483 ps |
| T294 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3450795455 |
|
|
Mar 21 03:58:46 PM PDT 24 |
Mar 21 04:16:00 PM PDT 24 |
5673851440 ps |
| T714 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1431583394 |
|
|
Mar 21 04:28:48 PM PDT 24 |
Mar 21 04:34:04 PM PDT 24 |
3550967528 ps |
| T667 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2418299471 |
|
|
Mar 21 04:27:38 PM PDT 24 |
Mar 21 04:37:26 PM PDT 24 |
5893730492 ps |
| T952 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1098062161 |
|
|
Mar 21 04:10:57 PM PDT 24 |
Mar 21 04:19:13 PM PDT 24 |
4733225879 ps |
| T953 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2778384394 |
|
|
Mar 21 04:05:51 PM PDT 24 |
Mar 21 04:11:53 PM PDT 24 |
3607221539 ps |
| T954 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1038539482 |
|
|
Mar 21 03:57:51 PM PDT 24 |
Mar 21 04:07:56 PM PDT 24 |
4117636020 ps |
| T718 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3092675166 |
|
|
Mar 21 04:30:35 PM PDT 24 |
Mar 21 04:40:40 PM PDT 24 |
4972002264 ps |
| T955 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.1057024491 |
|
|
Mar 21 04:16:04 PM PDT 24 |
Mar 21 04:45:49 PM PDT 24 |
9122961923 ps |
| T665 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2308840127 |
|
|
Mar 21 04:23:23 PM PDT 24 |
Mar 21 04:29:12 PM PDT 24 |
3648826884 ps |
| T728 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3407753424 |
|
|
Mar 21 04:24:29 PM PDT 24 |
Mar 21 04:29:46 PM PDT 24 |
3132905000 ps |
| T652 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.1847044511 |
|
|
Mar 21 04:27:19 PM PDT 24 |
Mar 21 04:39:46 PM PDT 24 |
5684989944 ps |