| T693 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1754371790 |
|
|
Mar 21 04:24:12 PM PDT 24 |
Mar 21 04:31:39 PM PDT 24 |
3756969400 ps |
| T956 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.481885993 |
|
|
Mar 21 04:23:42 PM PDT 24 |
Mar 21 04:37:46 PM PDT 24 |
9787265150 ps |
| T722 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.748638212 |
|
|
Mar 21 04:28:03 PM PDT 24 |
Mar 21 04:39:52 PM PDT 24 |
5987973360 ps |
| T957 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3971247089 |
|
|
Mar 21 04:04:47 PM PDT 24 |
Mar 21 04:24:15 PM PDT 24 |
8310598136 ps |
| T958 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1655461986 |
|
|
Mar 21 04:26:53 PM PDT 24 |
Mar 21 04:33:09 PM PDT 24 |
3921932608 ps |
| T959 |
/workspace/coverage/default/2.chip_sw_edn_kat.2652372505 |
|
|
Mar 21 04:22:26 PM PDT 24 |
Mar 21 04:32:35 PM PDT 24 |
3634515400 ps |
| T337 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2274149896 |
|
|
Mar 21 04:27:44 PM PDT 24 |
Mar 21 04:34:33 PM PDT 24 |
3346421400 ps |
| T960 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1835984551 |
|
|
Mar 21 04:13:42 PM PDT 24 |
Mar 21 04:33:02 PM PDT 24 |
8599401372 ps |
| T961 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.165363020 |
|
|
Mar 21 04:04:12 PM PDT 24 |
Mar 21 04:09:26 PM PDT 24 |
3210487912 ps |
| T962 |
/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.227380536 |
|
|
Mar 21 04:07:31 PM PDT 24 |
Mar 21 04:49:02 PM PDT 24 |
9442018092 ps |
| T345 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2187984940 |
|
|
Mar 21 04:06:46 PM PDT 24 |
Mar 21 04:54:09 PM PDT 24 |
12096404346 ps |
| T963 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.461523180 |
|
|
Mar 21 04:00:14 PM PDT 24 |
Mar 21 04:19:31 PM PDT 24 |
6029164920 ps |
| T964 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.237267709 |
|
|
Mar 21 04:14:00 PM PDT 24 |
Mar 21 04:19:18 PM PDT 24 |
2881527036 ps |
| T965 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1049625890 |
|
|
Mar 21 04:15:24 PM PDT 24 |
Mar 21 04:59:55 PM PDT 24 |
37727086160 ps |
| T966 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3707732809 |
|
|
Mar 21 04:19:15 PM PDT 24 |
Mar 21 04:42:27 PM PDT 24 |
5585859432 ps |
| T967 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2730906896 |
|
|
Mar 21 04:06:12 PM PDT 24 |
Mar 21 04:47:05 PM PDT 24 |
9220438540 ps |
| T968 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.314460831 |
|
|
Mar 21 04:12:50 PM PDT 24 |
Mar 21 04:37:12 PM PDT 24 |
8047191568 ps |
| T969 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1365630464 |
|
|
Mar 21 04:07:35 PM PDT 24 |
Mar 21 04:39:55 PM PDT 24 |
8277738036 ps |
| T970 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1526195256 |
|
|
Mar 21 04:23:43 PM PDT 24 |
Mar 21 05:02:53 PM PDT 24 |
11204069596 ps |
| T971 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3183612311 |
|
|
Mar 21 04:12:58 PM PDT 24 |
Mar 21 07:04:16 PM PDT 24 |
58039548776 ps |
| T972 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1020434023 |
|
|
Mar 21 04:17:43 PM PDT 24 |
Mar 21 04:24:45 PM PDT 24 |
4996863730 ps |
| T387 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2363931812 |
|
|
Mar 21 04:22:35 PM PDT 24 |
Mar 21 04:28:06 PM PDT 24 |
3622439150 ps |
| T710 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3099720164 |
|
|
Mar 21 04:29:58 PM PDT 24 |
Mar 21 04:36:10 PM PDT 24 |
4141630608 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2031185046 |
|
|
Mar 21 04:15:22 PM PDT 24 |
Mar 21 04:25:24 PM PDT 24 |
6830254190 ps |
| T974 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.992313707 |
|
|
Mar 21 04:05:48 PM PDT 24 |
Mar 21 04:13:52 PM PDT 24 |
5693459920 ps |
| T647 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2379847010 |
|
|
Mar 21 04:26:21 PM PDT 24 |
Mar 21 04:32:41 PM PDT 24 |
3579019488 ps |
| T690 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2180040583 |
|
|
Mar 21 04:30:18 PM PDT 24 |
Mar 21 04:41:26 PM PDT 24 |
5517785060 ps |
| T975 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2117514313 |
|
|
Mar 21 04:16:00 PM PDT 24 |
Mar 21 04:27:45 PM PDT 24 |
4453978630 ps |
| T976 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.633982570 |
|
|
Mar 21 04:07:24 PM PDT 24 |
Mar 21 04:12:15 PM PDT 24 |
2216151378 ps |
| T977 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1428082292 |
|
|
Mar 21 04:02:55 PM PDT 24 |
Mar 21 04:13:29 PM PDT 24 |
6246643923 ps |
| T978 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3272384467 |
|
|
Mar 21 04:05:01 PM PDT 24 |
Mar 21 04:11:41 PM PDT 24 |
6831263936 ps |
| T979 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.485564365 |
|
|
Mar 21 04:17:09 PM PDT 24 |
Mar 21 04:25:57 PM PDT 24 |
4329121024 ps |
| T980 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2894924765 |
|
|
Mar 21 04:13:38 PM PDT 24 |
Mar 21 04:18:39 PM PDT 24 |
5603938272 ps |
| T981 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.103532985 |
|
|
Mar 21 03:58:53 PM PDT 24 |
Mar 21 04:05:31 PM PDT 24 |
3576715532 ps |
| T711 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.4011877012 |
|
|
Mar 21 04:26:26 PM PDT 24 |
Mar 21 04:33:44 PM PDT 24 |
3899203620 ps |
| T982 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1811371972 |
|
|
Mar 21 04:07:22 PM PDT 24 |
Mar 21 04:28:02 PM PDT 24 |
12116511804 ps |
| T983 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1305318094 |
|
|
Mar 21 03:57:41 PM PDT 24 |
Mar 21 04:10:56 PM PDT 24 |
4291808916 ps |
| T984 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2977907929 |
|
|
Mar 21 04:20:23 PM PDT 24 |
Mar 21 04:30:17 PM PDT 24 |
5738439275 ps |
| T985 |
/workspace/coverage/default/1.chip_sw_example_concurrency.3065586292 |
|
|
Mar 21 04:02:44 PM PDT 24 |
Mar 21 04:06:01 PM PDT 24 |
2532915512 ps |
| T986 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.482867424 |
|
|
Mar 21 04:15:28 PM PDT 24 |
Mar 21 04:21:40 PM PDT 24 |
2828372266 ps |
| T51 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.770691821 |
|
|
Mar 21 04:10:48 PM PDT 24 |
Mar 21 04:35:54 PM PDT 24 |
19046325000 ps |
| T297 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.3054567339 |
|
|
Mar 21 04:17:30 PM PDT 24 |
Mar 21 04:30:35 PM PDT 24 |
4425477464 ps |
| T987 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.2309802370 |
|
|
Mar 21 04:19:45 PM PDT 24 |
Mar 21 04:29:15 PM PDT 24 |
5404671112 ps |
| T304 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1927115189 |
|
|
Mar 21 04:23:46 PM PDT 24 |
Mar 21 04:34:05 PM PDT 24 |
4141124261 ps |
| T114 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.2141271214 |
|
|
Mar 21 04:19:25 PM PDT 24 |
Mar 21 04:29:31 PM PDT 24 |
3516996130 ps |
| T988 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.2322785459 |
|
|
Mar 21 04:01:57 PM PDT 24 |
Mar 21 04:06:08 PM PDT 24 |
3233196080 ps |
| T989 |
/workspace/coverage/default/1.chip_sw_kmac_idle.3138031731 |
|
|
Mar 21 04:07:01 PM PDT 24 |
Mar 21 04:11:13 PM PDT 24 |
2561444342 ps |
| T675 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2567622884 |
|
|
Mar 21 04:29:13 PM PDT 24 |
Mar 21 04:41:51 PM PDT 24 |
5895031624 ps |
| T990 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2853325572 |
|
|
Mar 21 04:00:18 PM PDT 24 |
Mar 21 04:05:36 PM PDT 24 |
3255373400 ps |
| T649 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1914251579 |
|
|
Mar 21 04:24:21 PM PDT 24 |
Mar 21 04:30:49 PM PDT 24 |
3950069796 ps |
| T991 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1550311738 |
|
|
Mar 21 03:58:23 PM PDT 24 |
Mar 21 04:44:32 PM PDT 24 |
32450763494 ps |
| T992 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1140455654 |
|
|
Mar 21 04:16:51 PM PDT 24 |
Mar 21 04:21:38 PM PDT 24 |
2819918346 ps |
| T993 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1810695327 |
|
|
Mar 21 03:58:57 PM PDT 24 |
Mar 21 04:30:58 PM PDT 24 |
17430365452 ps |
| T994 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.137113197 |
|
|
Mar 21 04:15:52 PM PDT 24 |
Mar 21 04:39:41 PM PDT 24 |
6774945070 ps |
| T995 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.556024894 |
|
|
Mar 21 04:03:48 PM PDT 24 |
Mar 21 04:13:57 PM PDT 24 |
5400706188 ps |
| T996 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.717319281 |
|
|
Mar 21 04:21:45 PM PDT 24 |
Mar 21 04:29:04 PM PDT 24 |
5931444477 ps |
| T712 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.3173553489 |
|
|
Mar 21 04:22:57 PM PDT 24 |
Mar 21 04:31:48 PM PDT 24 |
5268511780 ps |
| T997 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1132971119 |
|
|
Mar 21 04:16:23 PM PDT 24 |
Mar 21 04:20:01 PM PDT 24 |
3134678803 ps |
| T998 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.94886901 |
|
|
Mar 21 04:22:17 PM PDT 24 |
Mar 21 04:36:54 PM PDT 24 |
5286588327 ps |
| T999 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3018335683 |
|
|
Mar 21 04:16:07 PM PDT 24 |
Mar 21 04:39:39 PM PDT 24 |
9061827892 ps |
| T286 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.486082458 |
|
|
Mar 21 04:14:30 PM PDT 24 |
Mar 21 04:48:11 PM PDT 24 |
12405664156 ps |
| T28 |
/workspace/coverage/default/2.chip_sw_gpio.1222493350 |
|
|
Mar 21 04:12:59 PM PDT 24 |
Mar 21 04:20:25 PM PDT 24 |
3550108114 ps |
| T732 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.359757794 |
|
|
Mar 21 04:28:50 PM PDT 24 |
Mar 21 04:35:37 PM PDT 24 |
4266889248 ps |
| T1000 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1239241051 |
|
|
Mar 21 04:17:05 PM PDT 24 |
Mar 21 04:31:55 PM PDT 24 |
5816489800 ps |
| T1001 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3914350072 |
|
|
Mar 21 04:08:28 PM PDT 24 |
Mar 21 04:44:31 PM PDT 24 |
8710584472 ps |
| T402 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2627025575 |
|
|
Mar 21 04:14:58 PM PDT 24 |
Mar 21 04:29:17 PM PDT 24 |
5071569460 ps |
| T601 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3497302364 |
|
|
Mar 21 04:16:20 PM PDT 24 |
Mar 21 04:18:04 PM PDT 24 |
2186525553 ps |
| T1002 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3628522540 |
|
|
Mar 21 04:20:28 PM PDT 24 |
Mar 21 04:29:07 PM PDT 24 |
3032954152 ps |
| T1003 |
/workspace/coverage/default/0.rom_keymgr_functest.3591786277 |
|
|
Mar 21 04:03:21 PM PDT 24 |
Mar 21 04:12:17 PM PDT 24 |
5231498264 ps |
| T1004 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.3259576743 |
|
|
Mar 21 04:10:37 PM PDT 24 |
Mar 21 04:21:10 PM PDT 24 |
4058115400 ps |
| T1005 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.528801944 |
|
|
Mar 21 04:19:46 PM PDT 24 |
Mar 21 04:23:44 PM PDT 24 |
3169542680 ps |
| T119 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2218108277 |
|
|
Mar 21 04:07:09 PM PDT 24 |
Mar 21 04:29:35 PM PDT 24 |
10484864802 ps |
| T1006 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3060800029 |
|
|
Mar 21 04:19:45 PM PDT 24 |
Mar 21 04:24:18 PM PDT 24 |
2784233981 ps |
| T1007 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1466185782 |
|
|
Mar 21 04:06:13 PM PDT 24 |
Mar 21 04:11:04 PM PDT 24 |
3054091640 ps |
| T1008 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.204306952 |
|
|
Mar 21 04:00:05 PM PDT 24 |
Mar 21 04:08:13 PM PDT 24 |
4961041943 ps |
| T127 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1431522960 |
|
|
Mar 21 03:57:30 PM PDT 24 |
Mar 21 04:07:08 PM PDT 24 |
4996170824 ps |
| T1009 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2351925905 |
|
|
Mar 21 04:05:10 PM PDT 24 |
Mar 21 04:59:42 PM PDT 24 |
31738491764 ps |
| T1010 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.2546086320 |
|
|
Mar 21 04:24:01 PM PDT 24 |
Mar 21 04:28:53 PM PDT 24 |
2736651316 ps |
| T1011 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3894048675 |
|
|
Mar 21 04:31:13 PM PDT 24 |
Mar 21 04:41:05 PM PDT 24 |
4618912000 ps |
| T1012 |
/workspace/coverage/default/4.chip_tap_straps_dev.1612104812 |
|
|
Mar 21 04:22:13 PM PDT 24 |
Mar 21 04:35:08 PM PDT 24 |
7735836321 ps |
| T672 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2152444395 |
|
|
Mar 21 04:26:17 PM PDT 24 |
Mar 21 04:33:04 PM PDT 24 |
3505390532 ps |
| T668 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3466754861 |
|
|
Mar 21 04:28:09 PM PDT 24 |
Mar 21 04:33:19 PM PDT 24 |
4221166184 ps |
| T1013 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.4028014813 |
|
|
Mar 21 04:15:13 PM PDT 24 |
Mar 21 04:21:11 PM PDT 24 |
3387436776 ps |
| T1014 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2955876271 |
|
|
Mar 21 04:07:26 PM PDT 24 |
Mar 21 04:16:02 PM PDT 24 |
4988706342 ps |
| T1015 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3612622787 |
|
|
Mar 21 04:29:15 PM PDT 24 |
Mar 21 04:35:08 PM PDT 24 |
4109727880 ps |
| T1016 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.2101473326 |
|
|
Mar 21 04:03:21 PM PDT 24 |
Mar 21 04:06:38 PM PDT 24 |
3041071322 ps |
| T307 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4206155448 |
|
|
Mar 21 04:14:28 PM PDT 24 |
Mar 21 04:27:12 PM PDT 24 |
4422991320 ps |
| T39 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.589711417 |
|
|
Mar 21 04:14:10 PM PDT 24 |
Mar 21 04:20:46 PM PDT 24 |
3253984451 ps |
| T1017 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3147426437 |
|
|
Mar 21 04:05:33 PM PDT 24 |
Mar 21 04:44:00 PM PDT 24 |
8809601370 ps |
| T1018 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2779140870 |
|
|
Mar 21 04:05:35 PM PDT 24 |
Mar 21 04:51:41 PM PDT 24 |
11992668842 ps |
| T664 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2698629128 |
|
|
Mar 21 04:31:04 PM PDT 24 |
Mar 21 04:37:07 PM PDT 24 |
3629173144 ps |
| T1019 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3819537704 |
|
|
Mar 21 04:14:27 PM PDT 24 |
Mar 21 04:32:52 PM PDT 24 |
6417309711 ps |
| T1020 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3174294038 |
|
|
Mar 21 04:11:34 PM PDT 24 |
Mar 21 04:17:50 PM PDT 24 |
3070224600 ps |
| T1021 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.2649075384 |
|
|
Mar 21 03:58:54 PM PDT 24 |
Mar 21 04:04:54 PM PDT 24 |
3088503881 ps |
| T673 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.642242330 |
|
|
Mar 21 04:27:42 PM PDT 24 |
Mar 21 04:37:33 PM PDT 24 |
4553838440 ps |
| T628 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.4085336581 |
|
|
Mar 21 04:15:05 PM PDT 24 |
Mar 21 04:19:50 PM PDT 24 |
3006128750 ps |
| T99 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3046700533 |
|
|
Mar 21 04:09:40 PM PDT 24 |
Mar 21 04:16:17 PM PDT 24 |
7148550924 ps |
| T682 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.2616307913 |
|
|
Mar 21 04:23:06 PM PDT 24 |
Mar 21 04:32:51 PM PDT 24 |
4568915500 ps |
| T648 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.513333039 |
|
|
Mar 21 04:24:31 PM PDT 24 |
Mar 21 04:31:54 PM PDT 24 |
4348420938 ps |
| T1022 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2929853224 |
|
|
Mar 21 04:25:14 PM PDT 24 |
Mar 21 05:17:34 PM PDT 24 |
22906659497 ps |
| T1023 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.63646497 |
|
|
Mar 21 04:20:34 PM PDT 24 |
Mar 21 04:23:42 PM PDT 24 |
2560375230 ps |
| T1024 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4249836890 |
|
|
Mar 21 04:05:29 PM PDT 24 |
Mar 21 04:27:35 PM PDT 24 |
8285814320 ps |
| T1025 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.773075805 |
|
|
Mar 21 03:59:29 PM PDT 24 |
Mar 21 04:03:17 PM PDT 24 |
2770959320 ps |
| T228 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3200238645 |
|
|
Mar 21 04:28:03 PM PDT 24 |
Mar 21 04:34:18 PM PDT 24 |
3568834270 ps |
| T267 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3449467623 |
|
|
Mar 21 04:22:45 PM PDT 24 |
Mar 21 04:28:38 PM PDT 24 |
3939271024 ps |
| T268 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3063394461 |
|
|
Mar 21 04:16:43 PM PDT 24 |
Mar 21 04:27:03 PM PDT 24 |
4919060376 ps |
| T269 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1063717858 |
|
|
Mar 21 03:58:46 PM PDT 24 |
Mar 21 04:25:08 PM PDT 24 |
9499509536 ps |
| T270 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.41974802 |
|
|
Mar 21 04:01:42 PM PDT 24 |
Mar 21 04:05:40 PM PDT 24 |
3091461340 ps |
| T271 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.385523364 |
|
|
Mar 21 04:13:34 PM PDT 24 |
Mar 21 04:19:07 PM PDT 24 |
2482689924 ps |
| T272 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3855357597 |
|
|
Mar 21 04:13:23 PM PDT 24 |
Mar 21 04:18:04 PM PDT 24 |
3384886180 ps |
| T273 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.75704829 |
|
|
Mar 21 04:24:05 PM PDT 24 |
Mar 21 04:40:23 PM PDT 24 |
11808329165 ps |
| T274 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1485017805 |
|
|
Mar 21 04:23:06 PM PDT 24 |
Mar 21 04:35:28 PM PDT 24 |
5455687699 ps |
| T275 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.4211412670 |
|
|
Mar 21 04:20:01 PM PDT 24 |
Mar 21 04:31:29 PM PDT 24 |
9853612674 ps |
| T618 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.1647948710 |
|
|
Mar 21 04:25:43 PM PDT 24 |
Mar 21 04:36:04 PM PDT 24 |
5460769872 ps |
| T1026 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3591448835 |
|
|
Mar 21 04:13:31 PM PDT 24 |
Mar 21 04:27:13 PM PDT 24 |
4927090780 ps |
| T219 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2970924697 |
|
|
Mar 21 03:57:56 PM PDT 24 |
Mar 21 04:33:31 PM PDT 24 |
20543524103 ps |
| T1027 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2877272465 |
|
|
Mar 21 04:10:56 PM PDT 24 |
Mar 21 04:18:35 PM PDT 24 |
3602723092 ps |
| T734 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1006624317 |
|
|
Mar 21 04:27:20 PM PDT 24 |
Mar 21 04:36:01 PM PDT 24 |
4942805276 ps |
| T327 |
/workspace/coverage/default/2.chip_sw_hmac_enc.1216185061 |
|
|
Mar 21 04:17:40 PM PDT 24 |
Mar 21 04:22:05 PM PDT 24 |
2600427168 ps |
| T1028 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1489216672 |
|
|
Mar 21 04:15:43 PM PDT 24 |
Mar 21 04:33:06 PM PDT 24 |
11034118458 ps |
| T1029 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3059267074 |
|
|
Mar 21 04:23:15 PM PDT 24 |
Mar 21 04:30:42 PM PDT 24 |
7615531614 ps |
| T1030 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3817334541 |
|
|
Mar 21 04:14:20 PM PDT 24 |
Mar 21 04:22:19 PM PDT 24 |
4758996227 ps |
| T223 |
/workspace/coverage/default/2.chip_sw_flash_init.1196233552 |
|
|
Mar 21 04:14:36 PM PDT 24 |
Mar 21 04:44:00 PM PDT 24 |
21933298710 ps |
| T316 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2705033608 |
|
|
Mar 21 03:57:37 PM PDT 24 |
Mar 21 04:09:10 PM PDT 24 |
4964497000 ps |
| T1031 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3939389024 |
|
|
Mar 21 04:00:56 PM PDT 24 |
Mar 21 04:12:12 PM PDT 24 |
5117323880 ps |
| T1032 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2719554698 |
|
|
Mar 21 04:04:23 PM PDT 24 |
Mar 21 04:20:33 PM PDT 24 |
6143793198 ps |
| T300 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.1640789650 |
|
|
Mar 21 03:57:59 PM PDT 24 |
Mar 21 04:01:37 PM PDT 24 |
2769353448 ps |
| T1033 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2086641193 |
|
|
Mar 21 03:58:58 PM PDT 24 |
Mar 21 04:44:47 PM PDT 24 |
12009764616 ps |
| T677 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.280251320 |
|
|
Mar 21 04:30:31 PM PDT 24 |
Mar 21 04:37:21 PM PDT 24 |
4654379496 ps |
| T248 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3273015455 |
|
|
Mar 21 04:22:02 PM PDT 24 |
Mar 21 04:34:35 PM PDT 24 |
5482199568 ps |
| T250 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.463973062 |
|
|
Mar 21 04:06:09 PM PDT 24 |
Mar 21 04:29:30 PM PDT 24 |
5795087400 ps |
| T251 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3707209656 |
|
|
Mar 21 04:28:21 PM PDT 24 |
Mar 21 04:37:44 PM PDT 24 |
6162887792 ps |
| T252 |
/workspace/coverage/default/1.chip_sw_hmac_enc.19207584 |
|
|
Mar 21 04:07:33 PM PDT 24 |
Mar 21 04:11:45 PM PDT 24 |
2405195400 ps |
| T253 |
/workspace/coverage/default/1.chip_sw_aes_idle.2798629541 |
|
|
Mar 21 04:05:17 PM PDT 24 |
Mar 21 04:08:58 PM PDT 24 |
2839343688 ps |
| T254 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.3873143007 |
|
|
Mar 21 04:02:21 PM PDT 24 |
Mar 21 04:43:09 PM PDT 24 |
10125262636 ps |
| T255 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2099174306 |
|
|
Mar 21 04:16:19 PM PDT 24 |
Mar 21 05:06:13 PM PDT 24 |
18213124230 ps |
| T256 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.265783220 |
|
|
Mar 21 03:57:52 PM PDT 24 |
Mar 21 04:12:55 PM PDT 24 |
5372753335 ps |
| T257 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3880232564 |
|
|
Mar 21 03:59:24 PM PDT 24 |
Mar 21 04:02:57 PM PDT 24 |
2842088005 ps |
| T258 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878371807 |
|
|
Mar 21 04:26:38 PM PDT 24 |
Mar 21 04:33:20 PM PDT 24 |
3553038040 ps |
| T1034 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.18380315 |
|
|
Mar 21 04:23:37 PM PDT 24 |
Mar 21 04:33:36 PM PDT 24 |
5721736310 ps |
| T1035 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.968077556 |
|
|
Mar 21 04:22:01 PM PDT 24 |
Mar 21 04:29:48 PM PDT 24 |
4893529389 ps |
| T619 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.899021882 |
|
|
Mar 21 04:27:28 PM PDT 24 |
Mar 21 04:37:55 PM PDT 24 |
6486858320 ps |
| T220 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1184549746 |
|
|
Mar 21 03:59:14 PM PDT 24 |
Mar 21 05:31:33 PM PDT 24 |
48149131612 ps |
| T1036 |
/workspace/coverage/default/4.chip_tap_straps_rma.732030318 |
|
|
Mar 21 04:21:37 PM PDT 24 |
Mar 21 04:28:36 PM PDT 24 |
5520702626 ps |
| T671 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.461483697 |
|
|
Mar 21 04:31:04 PM PDT 24 |
Mar 21 04:39:46 PM PDT 24 |
4774835000 ps |
| T100 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2286197794 |
|
|
Mar 21 04:09:41 PM PDT 24 |
Mar 21 04:37:33 PM PDT 24 |
19914564136 ps |
| T1037 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4001282841 |
|
|
Mar 21 04:07:43 PM PDT 24 |
Mar 21 04:14:33 PM PDT 24 |
5057719198 ps |
| T1038 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2505105516 |
|
|
Mar 21 04:23:34 PM PDT 24 |
Mar 21 04:34:55 PM PDT 24 |
4918954293 ps |
| T705 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1228870989 |
|
|
Mar 21 04:28:37 PM PDT 24 |
Mar 21 04:38:32 PM PDT 24 |
4721842900 ps |
| T1039 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3194929625 |
|
|
Mar 21 03:59:13 PM PDT 24 |
Mar 21 04:02:43 PM PDT 24 |
2407694150 ps |
| T1040 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2313037194 |
|
|
Mar 21 04:22:22 PM PDT 24 |
Mar 21 04:31:05 PM PDT 24 |
7283012884 ps |
| T1041 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3333758891 |
|
|
Mar 21 04:23:43 PM PDT 24 |
Mar 21 05:22:48 PM PDT 24 |
22960118469 ps |
| T716 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3417205506 |
|
|
Mar 21 04:31:05 PM PDT 24 |
Mar 21 04:40:02 PM PDT 24 |
5697834024 ps |
| T1042 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1883983167 |
|
|
Mar 21 04:12:45 PM PDT 24 |
Mar 21 04:17:46 PM PDT 24 |
3364030248 ps |
| T1043 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2952909077 |
|
|
Mar 21 04:29:00 PM PDT 24 |
Mar 21 04:35:56 PM PDT 24 |
3489774058 ps |
| T217 |
/workspace/coverage/default/1.chip_sw_flash_init.456392797 |
|
|
Mar 21 04:04:43 PM PDT 24 |
Mar 21 04:30:52 PM PDT 24 |
22093404200 ps |
| T328 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1278767517 |
|
|
Mar 21 04:11:25 PM PDT 24 |
Mar 21 04:16:34 PM PDT 24 |
2862995490 ps |
| T1044 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2948084233 |
|
|
Mar 21 04:01:48 PM PDT 24 |
Mar 21 04:21:00 PM PDT 24 |
5386596972 ps |
| T1045 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.4071551609 |
|
|
Mar 21 04:26:29 PM PDT 24 |
Mar 21 04:33:13 PM PDT 24 |
4001844938 ps |
| T704 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2707849653 |
|
|
Mar 21 04:22:54 PM PDT 24 |
Mar 21 04:29:08 PM PDT 24 |
3430659128 ps |
| T1046 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.1750965193 |
|
|
Mar 21 03:57:45 PM PDT 24 |
Mar 21 04:01:57 PM PDT 24 |
2717282646 ps |
| T643 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.1310997311 |
|
|
Mar 21 04:22:09 PM PDT 24 |
Mar 21 04:32:49 PM PDT 24 |
5443552600 ps |
| T1047 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.3269016590 |
|
|
Mar 21 04:07:42 PM PDT 24 |
Mar 21 04:12:16 PM PDT 24 |
2941332062 ps |
| T708 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.649378310 |
|
|
Mar 21 04:27:17 PM PDT 24 |
Mar 21 04:37:05 PM PDT 24 |
4912227672 ps |
| T1048 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.2048159946 |
|
|
Mar 21 04:02:01 PM PDT 24 |
Mar 21 07:07:34 PM PDT 24 |
65611299173 ps |
| T1049 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1839470750 |
|
|
Mar 21 04:17:05 PM PDT 24 |
Mar 21 04:25:46 PM PDT 24 |
9768450628 ps |
| T1050 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.212842845 |
|
|
Mar 21 04:22:17 PM PDT 24 |
Mar 21 04:27:12 PM PDT 24 |
3195760160 ps |
| T1051 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.177006449 |
|
|
Mar 21 04:22:12 PM PDT 24 |
Mar 21 04:29:01 PM PDT 24 |
5856456662 ps |
| T1052 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3988587745 |
|
|
Mar 21 04:05:36 PM PDT 24 |
Mar 21 05:04:32 PM PDT 24 |
16689407420 ps |
| T1053 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1964378089 |
|
|
Mar 21 03:57:26 PM PDT 24 |
Mar 21 04:09:42 PM PDT 24 |
6747517753 ps |
| T1054 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.852889214 |
|
|
Mar 21 03:58:57 PM PDT 24 |
Mar 21 04:07:51 PM PDT 24 |
3920919276 ps |
| T229 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.930780382 |
|
|
Mar 21 04:26:22 PM PDT 24 |
Mar 21 04:32:41 PM PDT 24 |
3338326120 ps |
| T1055 |
/workspace/coverage/default/2.chip_sw_kmac_idle.714727052 |
|
|
Mar 21 04:16:37 PM PDT 24 |
Mar 21 04:21:20 PM PDT 24 |
3144704048 ps |
| T1056 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2765800057 |
|
|
Mar 21 04:01:27 PM PDT 24 |
Mar 21 04:06:39 PM PDT 24 |
2660129140 ps |
| T1057 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.683322986 |
|
|
Mar 21 04:07:49 PM PDT 24 |
Mar 21 04:39:17 PM PDT 24 |
9012768472 ps |
| T602 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.3077557185 |
|
|
Mar 21 04:13:13 PM PDT 24 |
Mar 21 04:15:23 PM PDT 24 |
3095120595 ps |
| T346 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2720930568 |
|
|
Mar 21 04:19:54 PM PDT 24 |
Mar 21 04:22:30 PM PDT 24 |
2249724500 ps |
| T308 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.3488647014 |
|
|
Mar 21 04:02:14 PM PDT 24 |
Mar 21 04:05:46 PM PDT 24 |
3041900098 ps |
| T52 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.4174037996 |
|
|
Mar 21 04:12:55 PM PDT 24 |
Mar 21 04:18:19 PM PDT 24 |
3978147152 ps |
| T700 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.1184132329 |
|
|
Mar 21 04:23:48 PM PDT 24 |
Mar 21 04:32:06 PM PDT 24 |
5494705400 ps |
| T290 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3325351267 |
|
|
Mar 21 04:13:52 PM PDT 24 |
Mar 21 04:22:59 PM PDT 24 |
3604420880 ps |
| T88 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.883679099 |
|
|
Mar 21 04:31:09 PM PDT 24 |
Mar 21 04:36:16 PM PDT 24 |
3448972764 ps |
| T1058 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.905137613 |
|
|
Mar 21 04:09:47 PM PDT 24 |
Mar 21 04:19:15 PM PDT 24 |
4717491128 ps |
| T641 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3445430722 |
|
|
Mar 21 04:27:27 PM PDT 24 |
Mar 21 04:34:42 PM PDT 24 |
3629104120 ps |
| T1059 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3306559849 |
|
|
Mar 21 04:04:39 PM PDT 24 |
Mar 21 04:41:13 PM PDT 24 |
21608562859 ps |
| T292 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1051915609 |
|
|
Mar 21 03:57:41 PM PDT 24 |
Mar 21 04:32:32 PM PDT 24 |
7800322908 ps |
| T709 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1214159171 |
|
|
Mar 21 04:25:21 PM PDT 24 |
Mar 21 04:32:54 PM PDT 24 |
2987863304 ps |
| T1060 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2921166548 |
|
|
Mar 21 03:58:08 PM PDT 24 |
Mar 21 04:05:57 PM PDT 24 |
3636057078 ps |
| T1061 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.3602154016 |
|
|
Mar 21 04:17:10 PM PDT 24 |
Mar 21 04:23:39 PM PDT 24 |
2777515048 ps |
| T1062 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2600993925 |
|
|
Mar 21 04:05:01 PM PDT 24 |
Mar 21 05:00:15 PM PDT 24 |
18126685669 ps |
| T1063 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2203708637 |
|
|
Mar 21 04:13:01 PM PDT 24 |
Mar 21 04:16:52 PM PDT 24 |
2336496640 ps |
| T276 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2907810475 |
|
|
Mar 21 04:10:00 PM PDT 24 |
Mar 21 04:14:50 PM PDT 24 |
2926553597 ps |
| T1064 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1021875095 |
|
|
Mar 21 04:28:46 PM PDT 24 |
Mar 21 04:35:10 PM PDT 24 |
3656418790 ps |
| T1065 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.576099827 |
|
|
Mar 21 04:17:29 PM PDT 24 |
Mar 21 04:39:44 PM PDT 24 |
7904093304 ps |
| T1066 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4171878415 |
|
|
Mar 21 04:03:45 PM PDT 24 |
Mar 21 04:07:17 PM PDT 24 |
3507501048 ps |
| T731 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2134184866 |
|
|
Mar 21 04:25:39 PM PDT 24 |
Mar 21 04:31:59 PM PDT 24 |
3699139512 ps |
| T218 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2371387096 |
|
|
Mar 21 04:05:43 PM PDT 24 |
Mar 21 05:31:37 PM PDT 24 |
46720665160 ps |
| T706 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1702790979 |
|
|
Mar 21 04:25:54 PM PDT 24 |
Mar 21 04:30:35 PM PDT 24 |
3391079544 ps |
| T317 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.1721776280 |
|
|
Mar 21 04:13:15 PM PDT 24 |
Mar 21 04:18:09 PM PDT 24 |
2488565438 ps |
| T1067 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3459185927 |
|
|
Mar 21 04:14:33 PM PDT 24 |
Mar 21 04:35:21 PM PDT 24 |
13707969870 ps |
| T1068 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3288818195 |
|
|
Mar 21 04:02:10 PM PDT 24 |
Mar 21 04:12:16 PM PDT 24 |
3834868268 ps |
| T1069 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1065506931 |
|
|
Mar 21 04:23:44 PM PDT 24 |
Mar 21 04:33:18 PM PDT 24 |
6353799371 ps |
| T1070 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1434801213 |
|
|
Mar 21 04:13:53 PM PDT 24 |
Mar 21 04:23:28 PM PDT 24 |
3729985724 ps |
| T183 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.3972999681 |
|
|
Mar 21 03:56:56 PM PDT 24 |
Mar 21 04:06:04 PM PDT 24 |
4247849344 ps |
| T1071 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.688277388 |
|
|
Mar 21 04:08:47 PM PDT 24 |
Mar 21 04:17:19 PM PDT 24 |
5441057890 ps |
| T1072 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3675332672 |
|
|
Mar 21 03:55:50 PM PDT 24 |
Mar 21 04:04:18 PM PDT 24 |
4080111599 ps |
| T1073 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.300224776 |
|
|
Mar 21 04:05:26 PM PDT 24 |
Mar 21 04:13:34 PM PDT 24 |
5593887108 ps |
| T1074 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1732094343 |
|
|
Mar 21 04:04:09 PM PDT 24 |
Mar 21 04:27:25 PM PDT 24 |
13879226216 ps |
| T1075 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2782685046 |
|
|
Mar 21 04:00:21 PM PDT 24 |
Mar 21 04:08:18 PM PDT 24 |
3558094984 ps |
| T322 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2706931738 |
|
|
Mar 21 03:59:02 PM PDT 24 |
Mar 21 04:07:17 PM PDT 24 |
18209266446 ps |
| T173 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1462150226 |
|
|
Mar 21 04:07:34 PM PDT 24 |
Mar 21 04:14:10 PM PDT 24 |
4976787640 ps |
| T1076 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.4262202481 |
|
|
Mar 21 03:58:38 PM PDT 24 |
Mar 21 04:52:49 PM PDT 24 |
12320860744 ps |
| T325 |
/workspace/coverage/default/0.chip_sival_flash_info_access.2571086934 |
|
|
Mar 21 03:58:24 PM PDT 24 |
Mar 21 04:03:31 PM PDT 24 |
2852281304 ps |
| T1077 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.1850825849 |
|
|
Mar 21 04:20:06 PM PDT 24 |
Mar 21 04:25:55 PM PDT 24 |
3109544376 ps |
| T1078 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3137419675 |
|
|
Mar 21 04:29:42 PM PDT 24 |
Mar 21 04:38:45 PM PDT 24 |
5441163368 ps |
| T388 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1013567904 |
|
|
Mar 21 04:27:19 PM PDT 24 |
Mar 21 04:36:18 PM PDT 24 |
5073066660 ps |
| T1079 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1014805269 |
|
|
Mar 21 03:59:53 PM PDT 24 |
Mar 21 04:51:50 PM PDT 24 |
25773033964 ps |
| T1080 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.4212316265 |
|
|
Mar 21 04:07:05 PM PDT 24 |
Mar 21 04:42:12 PM PDT 24 |
6315002100 ps |
| T1081 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1062687839 |
|
|
Mar 21 04:06:00 PM PDT 24 |
Mar 21 04:10:41 PM PDT 24 |
2780807402 ps |
| T670 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.741427237 |
|
|
Mar 21 04:29:58 PM PDT 24 |
Mar 21 04:37:51 PM PDT 24 |
5123080792 ps |
| T227 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3231260787 |
|
|
Mar 21 04:03:28 PM PDT 24 |
Mar 21 04:18:28 PM PDT 24 |
6563090176 ps |
| T72 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.4077695708 |
|
|
Mar 21 03:56:56 PM PDT 24 |
Mar 21 04:02:52 PM PDT 24 |
3038689512 ps |
| T249 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.327262653 |
|
|
Mar 21 04:22:03 PM PDT 24 |
Mar 21 04:32:32 PM PDT 24 |
6173362608 ps |
| T1082 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.2718258089 |
|
|
Mar 21 04:26:41 PM PDT 24 |
Mar 21 04:35:18 PM PDT 24 |
5381977650 ps |
| T733 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1828303731 |
|
|
Mar 21 04:28:18 PM PDT 24 |
Mar 21 04:35:59 PM PDT 24 |
4054774600 ps |
| T1083 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1553717895 |
|
|
Mar 21 04:04:32 PM PDT 24 |
Mar 21 04:15:21 PM PDT 24 |
5772835832 ps |
| T1084 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3738430281 |
|
|
Mar 21 04:13:32 PM PDT 24 |
Mar 21 04:17:36 PM PDT 24 |
2599613000 ps |
| T1085 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1352572483 |
|
|
Mar 21 03:59:09 PM PDT 24 |
Mar 21 04:05:38 PM PDT 24 |
5733678552 ps |
| T1086 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2427757364 |
|
|
Mar 21 03:57:32 PM PDT 24 |
Mar 21 04:12:17 PM PDT 24 |
5750602140 ps |
| T1087 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3700274633 |
|
|
Mar 21 03:59:28 PM PDT 24 |
Mar 21 07:34:03 PM PDT 24 |
255017208342 ps |
| T1088 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.525794073 |
|
|
Mar 21 04:14:30 PM PDT 24 |
Mar 21 04:32:37 PM PDT 24 |
10712850997 ps |
| T389 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1375472907 |
|
|
Mar 21 04:27:05 PM PDT 24 |
Mar 21 04:33:31 PM PDT 24 |
3421144240 ps |
| T1089 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2249890155 |
|
|
Mar 21 04:13:56 PM PDT 24 |
Mar 21 04:24:29 PM PDT 24 |
3787538318 ps |
| T620 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2086704596 |
|
|
Mar 21 04:31:46 PM PDT 24 |
Mar 21 04:41:13 PM PDT 24 |
5975708772 ps |
| T1090 |
/workspace/coverage/default/2.chip_sival_flash_info_access.969244828 |
|
|
Mar 21 04:16:05 PM PDT 24 |
Mar 21 04:22:19 PM PDT 24 |
2555210150 ps |
| T1091 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.397455468 |
|
|
Mar 21 04:06:39 PM PDT 24 |
Mar 21 05:00:47 PM PDT 24 |
15290207476 ps |
| T1092 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2253819759 |
|
|
Mar 21 04:24:25 PM PDT 24 |
Mar 21 04:35:37 PM PDT 24 |
5068546676 ps |
| T1093 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1443644523 |
|
|
Mar 21 04:15:28 PM PDT 24 |
Mar 21 04:24:25 PM PDT 24 |
5036338000 ps |
| T1094 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.1469689263 |
|
|
Mar 21 04:24:08 PM PDT 24 |
Mar 21 04:48:05 PM PDT 24 |
8826872549 ps |
| T698 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1994123928 |
|
|
Mar 21 04:28:39 PM PDT 24 |
Mar 21 04:37:54 PM PDT 24 |
5586282760 ps |
| T1095 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.4251254572 |
|
|
Mar 21 03:57:50 PM PDT 24 |
Mar 21 04:06:25 PM PDT 24 |
6003891830 ps |
| T1096 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3816514621 |
|
|
Mar 21 04:04:17 PM PDT 24 |
Mar 21 04:13:30 PM PDT 24 |
6178415170 ps |
| T101 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3996303525 |
|
|
Mar 21 04:19:11 PM PDT 24 |
Mar 21 04:44:21 PM PDT 24 |
19585148600 ps |
| T603 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.2361339020 |
|
|
Mar 21 04:21:34 PM PDT 24 |
Mar 21 04:23:14 PM PDT 24 |
2465126527 ps |
| T719 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3726955323 |
|
|
Mar 21 04:29:40 PM PDT 24 |
Mar 21 04:37:06 PM PDT 24 |
3617383060 ps |
| T723 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.1485702585 |
|
|
Mar 21 04:28:11 PM PDT 24 |
Mar 21 04:37:28 PM PDT 24 |
4676169454 ps |
| T1097 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1736447707 |
|
|
Mar 21 04:07:56 PM PDT 24 |
Mar 21 04:23:02 PM PDT 24 |
8570067940 ps |
| T1098 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3579259610 |
|
|
Mar 21 04:09:16 PM PDT 24 |
Mar 21 04:12:21 PM PDT 24 |
2516913244 ps |
| T1099 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.277067783 |
|
|
Mar 21 03:58:06 PM PDT 24 |
Mar 21 04:34:26 PM PDT 24 |
9930923368 ps |
| T1100 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2445982598 |
|
|
Mar 21 04:18:36 PM PDT 24 |
Mar 21 04:30:23 PM PDT 24 |
8869708720 ps |