| T1101 |
/workspace/coverage/default/0.chip_sw_aes_idle.446008023 |
|
|
Mar 21 04:01:03 PM PDT 24 |
Mar 21 04:05:38 PM PDT 24 |
2209435384 ps |
| T481 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2785287689 |
|
|
Mar 21 03:59:05 PM PDT 24 |
Mar 21 04:14:28 PM PDT 24 |
5045924092 ps |
| T1102 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2685363109 |
|
|
Mar 21 04:17:16 PM PDT 24 |
Mar 21 04:26:43 PM PDT 24 |
5981008941 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3822310123 |
|
|
Mar 21 03:56:26 PM PDT 24 |
Mar 21 04:01:53 PM PDT 24 |
2922261936 ps |
| T1103 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2355540682 |
|
|
Mar 21 04:20:31 PM PDT 24 |
Mar 21 04:25:04 PM PDT 24 |
3468486245 ps |
| T1104 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1356810989 |
|
|
Mar 21 04:16:00 PM PDT 24 |
Mar 21 04:24:09 PM PDT 24 |
7427005856 ps |
| T1105 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.703877929 |
|
|
Mar 21 04:17:50 PM PDT 24 |
Mar 21 04:26:12 PM PDT 24 |
4565339612 ps |
| T1106 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.1682566043 |
|
|
Mar 21 04:25:25 PM PDT 24 |
Mar 21 04:34:12 PM PDT 24 |
5266671000 ps |
| T1107 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3524766732 |
|
|
Mar 21 04:04:58 PM PDT 24 |
Mar 21 04:13:48 PM PDT 24 |
3672136440 ps |
| T235 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.4268918521 |
|
|
Mar 21 04:14:31 PM PDT 24 |
Mar 21 04:22:21 PM PDT 24 |
5908696120 ps |
| T1108 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.611033524 |
|
|
Mar 21 04:26:57 PM PDT 24 |
Mar 21 04:55:33 PM PDT 24 |
13293521336 ps |
| T1109 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3760561385 |
|
|
Mar 21 03:59:03 PM PDT 24 |
Mar 21 05:36:21 PM PDT 24 |
47875476310 ps |
| T178 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1285865971 |
|
|
Mar 21 04:15:08 PM PDT 24 |
Mar 21 04:24:14 PM PDT 24 |
7578378816 ps |
| T1110 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1532312687 |
|
|
Mar 21 04:06:08 PM PDT 24 |
Mar 21 04:42:24 PM PDT 24 |
8533437276 ps |
| T293 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.1392568159 |
|
|
Mar 21 04:15:54 PM PDT 24 |
Mar 21 04:38:43 PM PDT 24 |
6593881980 ps |
| T1111 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1159209673 |
|
|
Mar 21 03:59:40 PM PDT 24 |
Mar 21 04:09:50 PM PDT 24 |
3633257502 ps |
| T1112 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2686516473 |
|
|
Mar 21 04:16:43 PM PDT 24 |
Mar 21 04:21:59 PM PDT 24 |
2583930150 ps |
| T697 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.4188171636 |
|
|
Mar 21 04:29:07 PM PDT 24 |
Mar 21 04:38:12 PM PDT 24 |
4484282436 ps |
| T1113 |
/workspace/coverage/default/0.chip_sw_edn_kat.1448095312 |
|
|
Mar 21 03:59:19 PM PDT 24 |
Mar 21 04:10:24 PM PDT 24 |
3635296808 ps |
| T1114 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.674450877 |
|
|
Mar 21 04:21:01 PM PDT 24 |
Mar 21 04:27:00 PM PDT 24 |
4304536935 ps |
| T715 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1936578896 |
|
|
Mar 21 04:29:41 PM PDT 24 |
Mar 21 04:36:52 PM PDT 24 |
3323832456 ps |
| T89 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1944487375 |
|
|
Mar 21 04:33:14 PM PDT 24 |
Mar 21 04:40:00 PM PDT 24 |
4578056992 ps |
| T1115 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2370608682 |
|
|
Mar 21 03:57:30 PM PDT 24 |
Mar 21 04:09:43 PM PDT 24 |
4344067662 ps |
| T725 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3853038374 |
|
|
Mar 21 04:29:16 PM PDT 24 |
Mar 21 04:34:33 PM PDT 24 |
3556917216 ps |
| T36 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2155123312 |
|
|
Mar 21 04:04:22 PM PDT 24 |
Mar 21 04:09:37 PM PDT 24 |
2976448432 ps |
| T1116 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3906087106 |
|
|
Mar 21 03:58:32 PM PDT 24 |
Mar 21 04:01:18 PM PDT 24 |
2715242568 ps |
| T56 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2768877233 |
|
|
Mar 21 04:02:19 PM PDT 24 |
Mar 21 04:06:56 PM PDT 24 |
2706500840 ps |
| T1117 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.4160080632 |
|
|
Mar 21 03:58:41 PM PDT 24 |
Mar 21 04:05:26 PM PDT 24 |
3807723000 ps |
| T1118 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.204175685 |
|
|
Mar 21 04:18:38 PM PDT 24 |
Mar 21 04:32:34 PM PDT 24 |
4808532480 ps |
| T1119 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1967691384 |
|
|
Mar 21 04:22:41 PM PDT 24 |
Mar 21 04:38:16 PM PDT 24 |
5191558573 ps |
| T1120 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3735670649 |
|
|
Mar 21 04:27:42 PM PDT 24 |
Mar 21 04:36:14 PM PDT 24 |
5754416068 ps |
| T1121 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.946093242 |
|
|
Mar 21 04:07:08 PM PDT 24 |
Mar 21 04:37:59 PM PDT 24 |
7230763300 ps |
| T1122 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1755082749 |
|
|
Mar 21 04:21:34 PM PDT 24 |
Mar 21 04:26:34 PM PDT 24 |
3046997728 ps |
| T1123 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.772998000 |
|
|
Mar 21 04:02:23 PM PDT 24 |
Mar 21 04:18:43 PM PDT 24 |
5121112740 ps |
| T1124 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.2181285295 |
|
|
Mar 21 04:19:12 PM PDT 24 |
Mar 21 04:22:52 PM PDT 24 |
2043370342 ps |
| T604 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2684916265 |
|
|
Mar 21 03:58:13 PM PDT 24 |
Mar 21 04:00:50 PM PDT 24 |
2425509415 ps |
| T348 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.4032078088 |
|
|
Mar 21 04:29:18 PM PDT 24 |
Mar 21 04:39:05 PM PDT 24 |
5863408500 ps |
| T236 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3258044165 |
|
|
Mar 21 04:26:51 PM PDT 24 |
Mar 21 04:35:17 PM PDT 24 |
4548423880 ps |
| T1125 |
/workspace/coverage/default/0.chip_sw_aes_enc.3836805737 |
|
|
Mar 21 03:59:03 PM PDT 24 |
Mar 21 04:02:58 PM PDT 24 |
3181594384 ps |
| T1126 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2758046848 |
|
|
Mar 21 04:23:01 PM PDT 24 |
Mar 21 04:29:12 PM PDT 24 |
3209178256 ps |
| T1127 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3684711856 |
|
|
Mar 21 04:13:54 PM PDT 24 |
Mar 21 04:18:59 PM PDT 24 |
2952892390 ps |
| T1128 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.373983696 |
|
|
Mar 21 04:21:13 PM PDT 24 |
Mar 21 04:31:35 PM PDT 24 |
4194488300 ps |
| T1129 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1111678249 |
|
|
Mar 21 03:57:58 PM PDT 24 |
Mar 21 04:23:52 PM PDT 24 |
6791302546 ps |
| T598 |
/workspace/coverage/default/1.chip_tap_straps_dev.1036814659 |
|
|
Mar 21 04:09:23 PM PDT 24 |
Mar 21 04:23:47 PM PDT 24 |
7698160301 ps |
| T1130 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.213773052 |
|
|
Mar 21 04:10:23 PM PDT 24 |
Mar 21 04:49:04 PM PDT 24 |
10270127768 ps |
| T694 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1745534951 |
|
|
Mar 21 04:30:22 PM PDT 24 |
Mar 21 04:35:52 PM PDT 24 |
3630407992 ps |
| T1131 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4197703836 |
|
|
Mar 21 04:05:15 PM PDT 24 |
Mar 21 04:13:46 PM PDT 24 |
2988783940 ps |
| T1132 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.976375505 |
|
|
Mar 21 04:00:31 PM PDT 24 |
Mar 21 04:10:04 PM PDT 24 |
4743338360 ps |
| T179 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3659281405 |
|
|
Mar 21 04:03:47 PM PDT 24 |
Mar 21 04:11:22 PM PDT 24 |
6923089112 ps |
| T596 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1729715351 |
|
|
Mar 21 04:01:47 PM PDT 24 |
Mar 21 04:09:57 PM PDT 24 |
5386944858 ps |
| T591 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3193336810 |
|
|
Mar 21 04:01:38 PM PDT 24 |
Mar 21 04:56:58 PM PDT 24 |
25283069342 ps |
| T1133 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3406300163 |
|
|
Mar 21 04:04:15 PM PDT 24 |
Mar 21 06:58:13 PM PDT 24 |
255088108030 ps |
| T1134 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.504866521 |
|
|
Mar 21 04:20:29 PM PDT 24 |
Mar 21 04:31:57 PM PDT 24 |
4729518832 ps |
| T53 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2922082184 |
|
|
Mar 21 04:05:07 PM PDT 24 |
Mar 21 04:10:24 PM PDT 24 |
3449093400 ps |
| T1135 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3957349232 |
|
|
Mar 21 04:00:17 PM PDT 24 |
Mar 21 04:10:21 PM PDT 24 |
5038258004 ps |
| T349 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3840982091 |
|
|
Mar 21 04:28:08 PM PDT 24 |
Mar 21 04:33:19 PM PDT 24 |
4003088240 ps |
| T726 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3591566071 |
|
|
Mar 21 04:26:56 PM PDT 24 |
Mar 21 04:34:13 PM PDT 24 |
3922138890 ps |
| T1136 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.2788993284 |
|
|
Mar 21 04:05:15 PM PDT 24 |
Mar 21 04:09:57 PM PDT 24 |
3350503944 ps |
| T368 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1172157820 |
|
|
Mar 21 04:19:37 PM PDT 24 |
Mar 21 04:41:12 PM PDT 24 |
20936422968 ps |
| T1137 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.771533494 |
|
|
Mar 21 04:19:36 PM PDT 24 |
Mar 21 04:28:22 PM PDT 24 |
5210065977 ps |
| T123 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2781655071 |
|
|
Mar 21 04:02:50 PM PDT 24 |
Mar 21 04:05:59 PM PDT 24 |
2626002591 ps |
| T1138 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1032023244 |
|
|
Mar 21 03:57:47 PM PDT 24 |
Mar 21 04:05:12 PM PDT 24 |
4424997286 ps |
| T1139 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.2081774359 |
|
|
Mar 21 04:24:47 PM PDT 24 |
Mar 21 04:34:38 PM PDT 24 |
5697810332 ps |
| T678 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.643578675 |
|
|
Mar 21 04:28:27 PM PDT 24 |
Mar 21 04:36:57 PM PDT 24 |
5015214432 ps |
| T1140 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2785001382 |
|
|
Mar 21 03:57:10 PM PDT 24 |
Mar 21 03:58:55 PM PDT 24 |
2210850863 ps |
| T1141 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3199864298 |
|
|
Mar 21 04:24:28 PM PDT 24 |
Mar 21 04:31:39 PM PDT 24 |
3622737662 ps |
| T645 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.2847553860 |
|
|
Mar 21 04:26:17 PM PDT 24 |
Mar 21 04:37:09 PM PDT 24 |
4936578824 ps |
| T1142 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1373890429 |
|
|
Mar 21 03:57:52 PM PDT 24 |
Mar 21 04:08:41 PM PDT 24 |
8441861848 ps |
| T277 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.33122118 |
|
|
Mar 21 03:59:21 PM PDT 24 |
Mar 21 04:03:56 PM PDT 24 |
2990304794 ps |
| T1143 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4097399513 |
|
|
Mar 21 04:13:04 PM PDT 24 |
Mar 21 04:28:16 PM PDT 24 |
5749240834 ps |
| T1144 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.268285259 |
|
|
Mar 21 04:22:38 PM PDT 24 |
Mar 21 04:40:46 PM PDT 24 |
13144805521 ps |
| T312 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.582832458 |
|
|
Mar 21 04:07:27 PM PDT 24 |
Mar 21 04:11:56 PM PDT 24 |
2500621581 ps |
| T1145 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3272340534 |
|
|
Mar 21 04:14:47 PM PDT 24 |
Mar 21 04:23:56 PM PDT 24 |
5069215650 ps |
| T639 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1287448875 |
|
|
Mar 21 04:00:34 PM PDT 24 |
Mar 21 04:57:06 PM PDT 24 |
20597544666 ps |
| T1146 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1295983766 |
|
|
Mar 21 04:04:27 PM PDT 24 |
Mar 21 04:23:18 PM PDT 24 |
4668474151 ps |
| T1147 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3599736767 |
|
|
Mar 21 04:03:19 PM PDT 24 |
Mar 21 04:09:15 PM PDT 24 |
3678497585 ps |
| T1148 |
/workspace/coverage/default/0.rom_e2e_smoke.1152159479 |
|
|
Mar 21 04:02:56 PM PDT 24 |
Mar 21 04:38:29 PM PDT 24 |
8931813516 ps |
| T1149 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2070947683 |
|
|
Mar 21 03:59:15 PM PDT 24 |
Mar 21 04:11:19 PM PDT 24 |
4839507676 ps |
| T1150 |
/workspace/coverage/default/1.chip_sw_power_idle_load.2195557913 |
|
|
Mar 21 04:10:09 PM PDT 24 |
Mar 21 04:19:22 PM PDT 24 |
3706193904 ps |
| T1151 |
/workspace/coverage/default/0.chip_tap_straps_rma.854599897 |
|
|
Mar 21 04:00:25 PM PDT 24 |
Mar 21 04:03:18 PM PDT 24 |
2543478380 ps |
| T237 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.4291403650 |
|
|
Mar 21 04:02:36 PM PDT 24 |
Mar 21 04:13:44 PM PDT 24 |
5969441814 ps |
| T1152 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2565333995 |
|
|
Mar 21 04:06:33 PM PDT 24 |
Mar 21 04:14:15 PM PDT 24 |
3971296360 ps |
| T115 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.3861541143 |
|
|
Mar 21 03:58:39 PM PDT 24 |
Mar 21 04:06:43 PM PDT 24 |
4118030760 ps |
| T1153 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1270663399 |
|
|
Mar 21 04:26:26 PM PDT 24 |
Mar 21 04:34:13 PM PDT 24 |
4003396260 ps |
| T1154 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2629168276 |
|
|
Mar 21 04:14:45 PM PDT 24 |
Mar 21 05:39:51 PM PDT 24 |
50468965072 ps |
| T58 |
/workspace/coverage/default/0.chip_sw_alert_test.1456051568 |
|
|
Mar 21 03:58:09 PM PDT 24 |
Mar 21 04:04:39 PM PDT 24 |
3073530378 ps |
| T684 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.662914715 |
|
|
Mar 21 04:25:54 PM PDT 24 |
Mar 21 04:31:09 PM PDT 24 |
3509060150 ps |
| T1155 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1606070908 |
|
|
Mar 21 03:57:21 PM PDT 24 |
Mar 21 04:06:40 PM PDT 24 |
4296870799 ps |
| T1156 |
/workspace/coverage/default/3.chip_tap_straps_rma.69792125 |
|
|
Mar 21 04:20:44 PM PDT 24 |
Mar 21 04:35:31 PM PDT 24 |
8288350608 ps |
| T205 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1234001813 |
|
|
Mar 21 04:05:35 PM PDT 24 |
Mar 21 04:14:19 PM PDT 24 |
4142488112 ps |
| T1157 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.862344045 |
|
|
Mar 21 04:18:26 PM PDT 24 |
Mar 21 04:35:08 PM PDT 24 |
7527302514 ps |
| T1158 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3976754600 |
|
|
Mar 21 04:30:23 PM PDT 24 |
Mar 21 05:01:27 PM PDT 24 |
8526056102 ps |
| T1159 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.291310063 |
|
|
Mar 21 04:12:04 PM PDT 24 |
Mar 21 04:16:14 PM PDT 24 |
3517079895 ps |
| T1160 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1726308676 |
|
|
Mar 21 04:08:12 PM PDT 24 |
Mar 21 04:15:23 PM PDT 24 |
4077618670 ps |
| T1161 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2725633114 |
|
|
Mar 21 03:57:16 PM PDT 24 |
Mar 21 03:59:47 PM PDT 24 |
3091427619 ps |
| T1162 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3950016042 |
|
|
Mar 21 04:19:44 PM PDT 24 |
Mar 21 04:31:34 PM PDT 24 |
8448928040 ps |
| T1163 |
/workspace/coverage/default/2.chip_sw_aes_idle.2020447556 |
|
|
Mar 21 04:20:01 PM PDT 24 |
Mar 21 04:24:59 PM PDT 24 |
3207529100 ps |
| T1164 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2769432622 |
|
|
Mar 21 04:04:35 PM PDT 24 |
Mar 21 04:23:14 PM PDT 24 |
6097452784 ps |
| T1165 |
/workspace/coverage/default/0.rom_e2e_static_critical.4053063618 |
|
|
Mar 21 04:06:05 PM PDT 24 |
Mar 21 04:53:39 PM PDT 24 |
10560911000 ps |
| T1166 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3631074858 |
|
|
Mar 21 03:57:46 PM PDT 24 |
Mar 21 04:04:58 PM PDT 24 |
4771985568 ps |
| T341 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.320938017 |
|
|
Mar 21 04:22:37 PM PDT 24 |
Mar 21 04:32:52 PM PDT 24 |
3244354488 ps |
| T90 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.3200709699 |
|
|
Mar 21 04:24:53 PM PDT 24 |
Mar 21 04:37:07 PM PDT 24 |
6346329544 ps |
| T1167 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2996042461 |
|
|
Mar 21 04:02:44 PM PDT 24 |
Mar 21 04:04:47 PM PDT 24 |
1951282159 ps |
| T1168 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1203622732 |
|
|
Mar 21 04:05:41 PM PDT 24 |
Mar 21 04:07:34 PM PDT 24 |
2499098732 ps |
| T1169 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3782423532 |
|
|
Mar 21 04:05:02 PM PDT 24 |
Mar 21 04:14:25 PM PDT 24 |
5558554814 ps |
| T1170 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.162572429 |
|
|
Mar 21 04:23:12 PM PDT 24 |
Mar 21 04:30:37 PM PDT 24 |
4905415412 ps |
| T701 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.3401224701 |
|
|
Mar 21 04:22:56 PM PDT 24 |
Mar 21 04:32:00 PM PDT 24 |
5608726528 ps |
| T1171 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3434609564 |
|
|
Mar 21 04:04:18 PM PDT 24 |
Mar 21 04:23:32 PM PDT 24 |
5380329124 ps |
| T1172 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1911842454 |
|
|
Mar 21 04:17:26 PM PDT 24 |
Mar 21 04:27:12 PM PDT 24 |
4796061608 ps |
| T1173 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.3382079916 |
|
|
Mar 21 04:12:34 PM PDT 24 |
Mar 21 04:16:27 PM PDT 24 |
2119351555 ps |
| T1174 |
/workspace/coverage/default/1.chip_sival_flash_info_access.3568354204 |
|
|
Mar 21 04:02:20 PM PDT 24 |
Mar 21 04:07:39 PM PDT 24 |
3200949584 ps |
| T1175 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3849528242 |
|
|
Mar 21 04:05:57 PM PDT 24 |
Mar 21 04:51:38 PM PDT 24 |
11854387619 ps |
| T691 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.1187737673 |
|
|
Mar 21 04:26:23 PM PDT 24 |
Mar 21 04:37:48 PM PDT 24 |
5221800780 ps |
| T1176 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1392025788 |
|
|
Mar 21 04:19:58 PM PDT 24 |
Mar 21 04:28:30 PM PDT 24 |
6119060500 ps |
| T707 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1882497680 |
|
|
Mar 21 04:27:20 PM PDT 24 |
Mar 21 04:34:23 PM PDT 24 |
3340042308 ps |
| T221 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2110756270 |
|
|
Mar 21 04:14:44 PM PDT 24 |
Mar 21 05:38:12 PM PDT 24 |
46141539652 ps |
| T640 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.935774490 |
|
|
Mar 21 04:16:20 PM PDT 24 |
Mar 21 05:04:04 PM PDT 24 |
20934405304 ps |
| T1177 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.125417519 |
|
|
Mar 21 04:21:47 PM PDT 24 |
Mar 21 04:35:49 PM PDT 24 |
5403235444 ps |
| T1178 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1548355414 |
|
|
Mar 21 04:16:22 PM PDT 24 |
Mar 21 05:13:00 PM PDT 24 |
17469681082 ps |
| T1179 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.907617948 |
|
|
Mar 21 04:05:23 PM PDT 24 |
Mar 21 04:28:48 PM PDT 24 |
7030973706 ps |
| T1180 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1922817763 |
|
|
Mar 21 04:01:55 PM PDT 24 |
Mar 21 04:13:14 PM PDT 24 |
6603829039 ps |
| T1181 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.3598004686 |
|
|
Mar 21 04:15:42 PM PDT 24 |
Mar 21 04:46:32 PM PDT 24 |
8540418112 ps |
| T1182 |
/workspace/coverage/default/2.rom_e2e_smoke.4023075825 |
|
|
Mar 21 04:26:52 PM PDT 24 |
Mar 21 04:57:48 PM PDT 24 |
8735365736 ps |
| T1183 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.257397405 |
|
|
Mar 21 04:15:22 PM PDT 24 |
Mar 21 04:34:16 PM PDT 24 |
9783325460 ps |
| T1184 |
/workspace/coverage/default/1.rom_e2e_static_critical.3721912951 |
|
|
Mar 21 04:15:38 PM PDT 24 |
Mar 21 04:59:33 PM PDT 24 |
10965254336 ps |
| T1185 |
/workspace/coverage/default/4.chip_tap_straps_prod.2862874614 |
|
|
Mar 21 04:22:34 PM PDT 24 |
Mar 21 04:33:53 PM PDT 24 |
7130596248 ps |
| T288 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.621233992 |
|
|
Mar 21 04:12:50 PM PDT 24 |
Mar 21 04:34:32 PM PDT 24 |
5987181470 ps |
| T1186 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.3199811906 |
|
|
Mar 21 04:12:51 PM PDT 24 |
Mar 21 04:16:48 PM PDT 24 |
2663676954 ps |
| T1187 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.103183492 |
|
|
Mar 21 04:17:34 PM PDT 24 |
Mar 21 04:22:47 PM PDT 24 |
3525190680 ps |
| T209 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2098039752 |
|
|
Mar 21 04:00:42 PM PDT 24 |
Mar 21 04:09:32 PM PDT 24 |
5106593184 ps |
| T1188 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3116956301 |
|
|
Mar 21 04:00:58 PM PDT 24 |
Mar 21 04:12:08 PM PDT 24 |
4394156350 ps |
| T636 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2867719676 |
|
|
Mar 21 04:04:05 PM PDT 24 |
Mar 21 04:19:58 PM PDT 24 |
5442748860 ps |
| T702 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.13670511 |
|
|
Mar 21 04:28:24 PM PDT 24 |
Mar 21 04:34:24 PM PDT 24 |
4324140544 ps |
| T1189 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.978611736 |
|
|
Mar 21 04:19:17 PM PDT 24 |
Mar 21 04:32:05 PM PDT 24 |
5913226397 ps |
| T200 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3040248625 |
|
|
Mar 21 04:19:17 PM PDT 24 |
Mar 21 04:26:19 PM PDT 24 |
4546299312 ps |
| T1190 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1606703004 |
|
|
Mar 21 04:13:53 PM PDT 24 |
Mar 21 04:23:51 PM PDT 24 |
4264540784 ps |
| T1191 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3857096179 |
|
|
Mar 21 04:16:33 PM PDT 24 |
Mar 21 04:18:34 PM PDT 24 |
2214913627 ps |
| T1192 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1935335810 |
|
|
Mar 21 04:07:43 PM PDT 24 |
Mar 21 04:19:37 PM PDT 24 |
4693636842 ps |
| T1193 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2222805724 |
|
|
Mar 21 04:08:07 PM PDT 24 |
Mar 21 04:15:53 PM PDT 24 |
4050845058 ps |
| T1194 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.976894191 |
|
|
Mar 21 04:12:26 PM PDT 24 |
Mar 21 04:21:13 PM PDT 24 |
4096820630 ps |
| T116 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.1763807193 |
|
|
Mar 21 04:10:27 PM PDT 24 |
Mar 21 04:19:51 PM PDT 24 |
4054011478 ps |
| T1195 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.448125179 |
|
|
Mar 21 04:15:17 PM PDT 24 |
Mar 21 04:41:19 PM PDT 24 |
22375073540 ps |
| T1196 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.191654927 |
|
|
Mar 21 04:23:13 PM PDT 24 |
Mar 21 04:31:31 PM PDT 24 |
4600456700 ps |
| T1197 |
/workspace/coverage/default/2.chip_tap_straps_rma.1694788007 |
|
|
Mar 21 04:20:06 PM PDT 24 |
Mar 21 04:33:20 PM PDT 24 |
7841231722 ps |
| T1198 |
/workspace/coverage/default/2.chip_sw_example_flash.931472231 |
|
|
Mar 21 04:14:17 PM PDT 24 |
Mar 21 04:18:17 PM PDT 24 |
2636884688 ps |
| T1199 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.1803572597 |
|
|
Mar 21 04:20:24 PM PDT 24 |
Mar 21 04:26:37 PM PDT 24 |
3270776176 ps |
| T1200 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.583640886 |
|
|
Mar 21 04:27:58 PM PDT 24 |
Mar 21 04:34:07 PM PDT 24 |
3587553984 ps |
| T729 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2108492786 |
|
|
Mar 21 04:30:44 PM PDT 24 |
Mar 21 04:39:35 PM PDT 24 |
5026793672 ps |
| T688 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2070247000 |
|
|
Mar 21 04:30:41 PM PDT 24 |
Mar 21 04:37:02 PM PDT 24 |
3652844836 ps |
| T1201 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2756068041 |
|
|
Mar 21 04:06:46 PM PDT 24 |
Mar 21 04:51:25 PM PDT 24 |
12033459020 ps |
| T1202 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1801980565 |
|
|
Mar 21 03:59:39 PM PDT 24 |
Mar 21 04:05:45 PM PDT 24 |
3695536390 ps |
| T347 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.115013451 |
|
|
Mar 21 04:20:57 PM PDT 24 |
Mar 21 04:36:17 PM PDT 24 |
9165888460 ps |
| T1203 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.418914663 |
|
|
Mar 21 04:16:53 PM PDT 24 |
Mar 21 04:22:05 PM PDT 24 |
3121525485 ps |
| T1204 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3691315183 |
|
|
Mar 21 04:15:48 PM PDT 24 |
Mar 21 04:20:05 PM PDT 24 |
2818900360 ps |
| T1205 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2870394583 |
|
|
Mar 21 04:28:18 PM PDT 24 |
Mar 21 04:37:30 PM PDT 24 |
4460154704 ps |
| T326 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3615101623 |
|
|
Mar 21 04:02:35 PM PDT 24 |
Mar 21 04:13:19 PM PDT 24 |
3899325905 ps |
| T1206 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.2634491610 |
|
|
Mar 21 04:25:28 PM PDT 24 |
Mar 21 05:13:24 PM PDT 24 |
23606900828 ps |
| T1207 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2371125830 |
|
|
Mar 21 04:00:40 PM PDT 24 |
Mar 21 04:19:39 PM PDT 24 |
11894277310 ps |
| T1208 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2950543862 |
|
|
Mar 21 04:00:46 PM PDT 24 |
Mar 21 04:05:53 PM PDT 24 |
2971394202 ps |
| T278 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1247116062 |
|
|
Mar 21 04:09:21 PM PDT 24 |
Mar 21 04:14:23 PM PDT 24 |
3352477152 ps |
| T1209 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3484660600 |
|
|
Mar 21 04:03:42 PM PDT 24 |
Mar 21 04:15:35 PM PDT 24 |
6642087224 ps |
| T54 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1669503188 |
|
|
Mar 21 03:58:51 PM PDT 24 |
Mar 21 04:05:44 PM PDT 24 |
5033551144 ps |
| T59 |
/workspace/coverage/default/1.chip_sw_alert_test.1173946121 |
|
|
Mar 21 04:06:54 PM PDT 24 |
Mar 21 04:12:17 PM PDT 24 |
2849343700 ps |
| T55 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1092404239 |
|
|
Mar 21 03:56:13 PM PDT 24 |
Mar 21 04:00:49 PM PDT 24 |
3305062792 ps |
| T1210 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.691642599 |
|
|
Mar 21 04:02:05 PM PDT 24 |
Mar 21 04:13:11 PM PDT 24 |
7504555240 ps |
| T1211 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2794260673 |
|
|
Mar 21 04:03:29 PM PDT 24 |
Mar 21 04:08:52 PM PDT 24 |
3051224280 ps |
| T49 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2855595637 |
|
|
Mar 21 04:19:20 PM PDT 24 |
Mar 21 04:24:43 PM PDT 24 |
3821930540 ps |
| T1212 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3669246636 |
|
|
Mar 21 04:09:56 PM PDT 24 |
Mar 21 04:23:01 PM PDT 24 |
4697591604 ps |
| T1213 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.200226249 |
|
|
Mar 21 04:14:34 PM PDT 24 |
Mar 21 05:52:16 PM PDT 24 |
47632285448 ps |
| T1214 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1908998562 |
|
|
Mar 21 04:26:36 PM PDT 24 |
Mar 21 04:35:10 PM PDT 24 |
5584570160 ps |
| T1215 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.758379072 |
|
|
Mar 21 04:29:56 PM PDT 24 |
Mar 21 04:39:45 PM PDT 24 |
5476638364 ps |
| T1216 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.2664765136 |
|
|
Mar 21 03:59:58 PM PDT 24 |
Mar 21 04:07:14 PM PDT 24 |
9565904100 ps |
| T1217 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.692181317 |
|
|
Mar 21 04:06:41 PM PDT 24 |
Mar 21 04:10:58 PM PDT 24 |
3333038002 ps |
| T1218 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2723153209 |
|
|
Mar 21 04:02:12 PM PDT 24 |
Mar 21 04:09:22 PM PDT 24 |
3837768020 ps |
| T74 |
/workspace/coverage/cover_reg_top/3.xbar_stress_all.2982434431 |
|
|
Mar 21 03:31:56 PM PDT 24 |
Mar 21 03:33:05 PM PDT 24 |
1875666470 ps |
| T75 |
/workspace/coverage/cover_reg_top/87.xbar_random_large_delays.1914536300 |
|
|
Mar 21 03:47:22 PM PDT 24 |
Mar 21 03:48:28 PM PDT 24 |
5940596979 ps |
| T76 |
/workspace/coverage/cover_reg_top/66.xbar_error_random.2492248093 |
|
|
Mar 21 03:43:18 PM PDT 24 |
Mar 21 03:44:09 PM PDT 24 |
572872822 ps |
| T77 |
/workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2153561928 |
|
|
Mar 21 03:34:08 PM PDT 24 |
Mar 21 03:34:35 PM PDT 24 |
271050967 ps |
| T230 |
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.3849174255 |
|
|
Mar 21 03:33:18 PM PDT 24 |
Mar 21 03:34:23 PM PDT 24 |
3502592601 ps |
| T398 |
/workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.1207034321 |
|
|
Mar 21 03:43:16 PM PDT 24 |
Mar 21 03:47:08 PM PDT 24 |
13443548379 ps |
| T399 |
/workspace/coverage/cover_reg_top/84.xbar_random.2926607491 |
|
|
Mar 21 03:46:31 PM PDT 24 |
Mar 21 03:46:48 PM PDT 24 |
215398028 ps |
| T400 |
/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.569942003 |
|
|
Mar 21 03:37:19 PM PDT 24 |
Mar 21 03:39:23 PM PDT 24 |
404229693 ps |
| T489 |
/workspace/coverage/cover_reg_top/55.xbar_random.2547918874 |
|
|
Mar 21 03:41:06 PM PDT 24 |
Mar 21 03:41:19 PM PDT 24 |
246356143 ps |
| T484 |
/workspace/coverage/cover_reg_top/38.xbar_error_random.2933086758 |
|
|
Mar 21 03:38:08 PM PDT 24 |
Mar 21 03:38:32 PM PDT 24 |
307111053 ps |
| T492 |
/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1071658245 |
|
|
Mar 21 03:43:17 PM PDT 24 |
Mar 21 03:43:34 PM PDT 24 |
56840823 ps |
| T401 |
/workspace/coverage/cover_reg_top/7.xbar_stress_all.2965784578 |
|
|
Mar 21 03:32:17 PM PDT 24 |
Mar 21 03:42:56 PM PDT 24 |
15448893487 ps |
| T483 |
/workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.210234902 |
|
|
Mar 21 03:35:41 PM PDT 24 |
Mar 21 03:36:00 PM PDT 24 |
172475825 ps |
| T486 |
/workspace/coverage/cover_reg_top/95.xbar_stress_all.720453426 |
|
|
Mar 21 03:48:29 PM PDT 24 |
Mar 21 03:49:22 PM PDT 24 |
528156728 ps |
| T485 |
/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2594270566 |
|
|
Mar 21 03:43:32 PM PDT 24 |
Mar 21 03:48:59 PM PDT 24 |
1428821651 ps |
| T487 |
/workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.937014578 |
|
|
Mar 21 03:48:39 PM PDT 24 |
Mar 21 04:24:46 PM PDT 24 |
113197868127 ps |
| T457 |
/workspace/coverage/cover_reg_top/9.xbar_random.2310391180 |
|
|
Mar 21 03:32:31 PM PDT 24 |
Mar 21 03:32:54 PM PDT 24 |
258184259 ps |
| T377 |
/workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.1317377784 |
|
|
Mar 21 03:47:37 PM PDT 24 |
Mar 21 03:48:14 PM PDT 24 |
429693438 ps |
| T493 |
/workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.3371395172 |
|
|
Mar 21 03:37:41 PM PDT 24 |
Mar 21 03:38:10 PM PDT 24 |
286020664 ps |
| T488 |
/workspace/coverage/cover_reg_top/13.chip_tl_errors.2311474232 |
|
|
Mar 21 03:32:39 PM PDT 24 |
Mar 21 03:36:55 PM PDT 24 |
3223972876 ps |
| T576 |
/workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1235625196 |
|
|
Mar 21 03:39:54 PM PDT 24 |
Mar 21 03:41:29 PM PDT 24 |
9021085689 ps |
| T503 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3724685594 |
|
|
Mar 21 03:32:36 PM PDT 24 |
Mar 21 03:34:10 PM PDT 24 |
8954229285 ps |
| T557 |
/workspace/coverage/cover_reg_top/10.xbar_smoke.2158058481 |
|
|
Mar 21 03:32:35 PM PDT 24 |
Mar 21 03:32:43 PM PDT 24 |
152412306 ps |
| T663 |
/workspace/coverage/cover_reg_top/18.xbar_smoke.872841501 |
|
|
Mar 21 03:33:54 PM PDT 24 |
Mar 21 03:34:01 PM PDT 24 |
148302228 ps |
| T491 |
/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3649631794 |
|
|
Mar 21 03:42:22 PM PDT 24 |
Mar 21 03:49:19 PM PDT 24 |
2918119131 ps |
| T1219 |
/workspace/coverage/cover_reg_top/92.xbar_smoke.3002609323 |
|
|
Mar 21 03:47:46 PM PDT 24 |
Mar 21 03:47:53 PM PDT 24 |
36954180 ps |
| T738 |
/workspace/coverage/cover_reg_top/26.xbar_access_same_device.2547904564 |
|
|
Mar 21 03:35:42 PM PDT 24 |
Mar 21 03:36:27 PM PDT 24 |
521364151 ps |
| T1220 |
/workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.2829183298 |
|
|
Mar 21 03:40:24 PM PDT 24 |
Mar 21 03:40:30 PM PDT 24 |
45866369 ps |
| T579 |
/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.2669076066 |
|
|
Mar 21 03:44:43 PM PDT 24 |
Mar 21 03:46:20 PM PDT 24 |
2597094104 ps |
| T490 |
/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.990921160 |
|
|
Mar 21 03:34:51 PM PDT 24 |
Mar 21 03:37:26 PM PDT 24 |
1748103015 ps |
| T506 |
/workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.1142422411 |
|
|
Mar 21 03:43:29 PM PDT 24 |
Mar 21 04:02:06 PM PDT 24 |
58784679155 ps |
| T542 |
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2768014134 |
|
|
Mar 21 03:31:50 PM PDT 24 |
Mar 21 03:32:40 PM PDT 24 |
2903501994 ps |
| T621 |
/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.16198246 |
|
|
Mar 21 03:41:59 PM PDT 24 |
Mar 21 03:58:25 PM PDT 24 |
57886314760 ps |
| T378 |
/workspace/coverage/cover_reg_top/42.xbar_stress_all.182409771 |
|
|
Mar 21 03:38:52 PM PDT 24 |
Mar 21 03:43:44 PM PDT 24 |
3632360624 ps |
| T403 |
/workspace/coverage/cover_reg_top/55.xbar_access_same_device.1508224583 |
|
|
Mar 21 03:41:29 PM PDT 24 |
Mar 21 03:43:25 PM PDT 24 |
3224110219 ps |
| T174 |
/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1062466118 |
|
|
Mar 21 03:31:52 PM PDT 24 |
Mar 21 03:36:05 PM PDT 24 |
4677049668 ps |
| T552 |
/workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.797564434 |
|
|
Mar 21 03:36:52 PM PDT 24 |
Mar 21 03:37:58 PM PDT 24 |
5482454850 ps |
| T528 |
/workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.2640002942 |
|
|
Mar 21 03:40:52 PM PDT 24 |
Mar 21 03:42:16 PM PDT 24 |
4951405111 ps |
| T380 |
/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1256334675 |
|
|
Mar 21 03:38:41 PM PDT 24 |
Mar 21 03:44:26 PM PDT 24 |
3143010399 ps |
| T529 |
/workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.1720088264 |
|
|
Mar 21 03:34:15 PM PDT 24 |
Mar 21 03:34:50 PM PDT 24 |
405915196 ps |
| T742 |
/workspace/coverage/cover_reg_top/48.xbar_access_same_device.1594198023 |
|
|
Mar 21 03:39:54 PM PDT 24 |
Mar 21 03:41:09 PM PDT 24 |
1708104934 ps |
| T181 |
/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.4292075971 |
|
|
Mar 21 03:31:41 PM PDT 24 |
Mar 21 04:38:46 PM PDT 24 |
28283303244 ps |
| T1221 |
/workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.1678045683 |
|
|
Mar 21 03:38:08 PM PDT 24 |
Mar 21 03:39:23 PM PDT 24 |
7274204562 ps |
| T570 |
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.3150142788 |
|
|
Mar 21 03:33:31 PM PDT 24 |
Mar 21 03:33:44 PM PDT 24 |
92368051 ps |
| T1222 |
/workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2568588358 |
|
|
Mar 21 03:42:04 PM PDT 24 |
Mar 21 03:42:49 PM PDT 24 |
1084548449 ps |
| T417 |
/workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.723605837 |
|
|
Mar 21 03:32:16 PM PDT 24 |
Mar 21 03:39:42 PM PDT 24 |
24597889732 ps |
| T635 |
/workspace/coverage/cover_reg_top/97.xbar_smoke.3496293568 |
|
|
Mar 21 03:48:42 PM PDT 24 |
Mar 21 03:48:52 PM PDT 24 |
229777639 ps |
| T182 |
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1165835431 |
|
|
Mar 21 03:31:50 PM PDT 24 |
Mar 21 04:13:18 PM PDT 24 |
16074052626 ps |
| T443 |
/workspace/coverage/cover_reg_top/55.xbar_stress_all.1004911124 |
|
|
Mar 21 03:41:28 PM PDT 24 |
Mar 21 03:47:01 PM PDT 24 |
8285493220 ps |
| T1223 |
/workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.69983045 |
|
|
Mar 21 03:35:12 PM PDT 24 |
Mar 21 03:35:25 PM PDT 24 |
246619560 ps |
| T589 |
/workspace/coverage/cover_reg_top/23.xbar_error_random.2737679082 |
|
|
Mar 21 03:35:09 PM PDT 24 |
Mar 21 03:35:54 PM PDT 24 |
1218645382 ps |
| T563 |
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2379049397 |
|
|
Mar 21 03:31:51 PM PDT 24 |
Mar 21 03:42:16 PM PDT 24 |
35282723065 ps |
| T507 |
/workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.4206213127 |
|
|
Mar 21 03:37:05 PM PDT 24 |
Mar 21 03:56:04 PM PDT 24 |
64772267922 ps |
| T739 |
/workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3407026385 |
|
|
Mar 21 03:47:57 PM PDT 24 |
Mar 21 04:30:42 PM PDT 24 |
134767426433 ps |
| T1224 |
/workspace/coverage/cover_reg_top/35.xbar_error_random.1707203842 |
|
|
Mar 21 03:37:31 PM PDT 24 |
Mar 21 03:38:07 PM PDT 24 |
432330534 ps |
| T1225 |
/workspace/coverage/cover_reg_top/4.xbar_error_random.308086936 |
|
|
Mar 21 03:31:58 PM PDT 24 |
Mar 21 03:32:37 PM PDT 24 |
1123611470 ps |
| T537 |
/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.1370288829 |
|
|
Mar 21 03:33:43 PM PDT 24 |
Mar 21 03:51:15 PM PDT 24 |
106477014793 ps |
| T1226 |
/workspace/coverage/cover_reg_top/86.xbar_error_random.3346328226 |
|
|
Mar 21 03:46:58 PM PDT 24 |
Mar 21 03:47:16 PM PDT 24 |
160711092 ps |
| T1227 |
/workspace/coverage/cover_reg_top/37.xbar_error_random.430624018 |
|
|
Mar 21 03:37:57 PM PDT 24 |
Mar 21 03:38:15 PM PDT 24 |
180578415 ps |
| T404 |
/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2810569409 |
|
|
Mar 21 03:38:40 PM PDT 24 |
Mar 21 03:49:26 PM PDT 24 |
5453783912 ps |
| T405 |
/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1271919171 |
|
|
Mar 21 03:31:59 PM PDT 24 |
Mar 21 03:39:49 PM PDT 24 |
7473763617 ps |
| T502 |
/workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.3032009800 |
|
|
Mar 21 03:45:59 PM PDT 24 |
Mar 21 03:59:49 PM PDT 24 |
49554047006 ps |
| T1228 |
/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.3753948131 |
|
|
Mar 21 03:46:19 PM PDT 24 |
Mar 21 03:47:47 PM PDT 24 |
2572644800 ps |
| T1229 |
/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.2213765778 |
|
|
Mar 21 03:42:36 PM PDT 24 |
Mar 21 03:43:03 PM PDT 24 |
649659691 ps |
| T748 |
/workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.385496359 |
|
|
Mar 21 03:47:55 PM PDT 24 |
Mar 21 03:51:25 PM PDT 24 |
12705895027 ps |
| T516 |
/workspace/coverage/cover_reg_top/22.xbar_random_large_delays.144734476 |
|
|
Mar 21 03:34:52 PM PDT 24 |
Mar 21 03:47:53 PM PDT 24 |
78356414281 ps |
| T560 |
/workspace/coverage/cover_reg_top/89.xbar_random.307259801 |
|
|
Mar 21 03:47:12 PM PDT 24 |
Mar 21 03:47:33 PM PDT 24 |
235855339 ps |
| T1230 |
/workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.4055982948 |
|
|
Mar 21 03:39:46 PM PDT 24 |
Mar 21 03:41:19 PM PDT 24 |
8435636350 ps |
| T543 |
/workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.3460120463 |
|
|
Mar 21 03:46:42 PM PDT 24 |
Mar 21 03:47:04 PM PDT 24 |
234462537 ps |
| T558 |
/workspace/coverage/cover_reg_top/75.xbar_same_source.2799073110 |
|
|
Mar 21 03:44:51 PM PDT 24 |
Mar 21 03:45:49 PM PDT 24 |
2060525916 ps |
| T735 |
/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.445497685 |
|
|
Mar 21 03:34:50 PM PDT 24 |
Mar 21 03:38:56 PM PDT 24 |
4203075646 ps |
| T1231 |
/workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.3882039758 |
|
|
Mar 21 03:42:52 PM PDT 24 |
Mar 21 03:42:58 PM PDT 24 |
42127834 ps |
| T744 |
/workspace/coverage/cover_reg_top/62.xbar_access_same_device.3988735047 |
|
|
Mar 21 03:42:35 PM PDT 24 |
Mar 21 03:44:29 PM PDT 24 |
2951062738 ps |
| T331 |
/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.161419000 |
|
|
Mar 21 03:33:54 PM PDT 24 |
Mar 21 04:11:16 PM PDT 24 |
14136043201 ps |
| T534 |
/workspace/coverage/cover_reg_top/72.xbar_random.1909148499 |
|
|
Mar 21 03:44:16 PM PDT 24 |
Mar 21 03:44:37 PM PDT 24 |
268189831 ps |
| T511 |
/workspace/coverage/cover_reg_top/25.xbar_same_source.3499728249 |
|
|
Mar 21 03:35:41 PM PDT 24 |
Mar 21 03:36:39 PM PDT 24 |
1648334264 ps |