CHIP Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.006m	2.637ms	3	3	100.00
		chip_sw_example_rom	2.324m	2.789ms	3	3	100.00
		chip_sw_example_manufacturer	3.952m	2.664ms	3	3	100.00
		chip_sw_example_concurrency	4.920m	3.081ms	3	3	100.00
		chip_sw_uart_smoketest_signed	41.499m	9.442ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	4.755m	5.072ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.001m	5.908ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.383h	45.918ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.981h	66.601ms	3	5	60.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.952m	2.640ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.981h	66.601ms	3	5	60.00
		chip_csr_rw	11.001m	5.908ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.830s	268.415us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.564m	4.334ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.564m	4.334ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.564m	4.334ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	17.703m	5.682ms	3	5	60.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	17.703m	5.682ms	3	5	60.00
		chip_sw_uart_tx_rx_idx1	15.316m	5.224ms	2	5	40.00
		chip_sw_uart_tx_rx_idx2	15.933m	5.551ms	4	5	80.00
		chip_sw_uart_tx_rx_idx3	16.165m	6.144ms	3	5	60.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	59.067m	22.960ms	15	20	75.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	33.724m	13.455ms	4	5	80.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	43.300m	22.913ms	3	5	60.00
V1		TOTAL			185	223	82.96
V2	chip_pin_mux	chip_padctrl_attributes	5.247m	4.307ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.247m	4.307ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	4.839m	2.828ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	9.542m	5.965ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.853m	5.034ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	22.875m	14.222ms	5	5	100.00
		chip_tap_straps_testunlock0	12.790m	5.913ms	5	5	100.00
		chip_tap_straps_rma	14.772m	8.288ms	5	5	100.00
		chip_tap_straps_prod	11.319m	7.131ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.891m	2.489ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.404m	7.643ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.952m	5.070ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.952m	5.070ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.837m	7.171ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.226m	4.292ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.417m	5.623ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.020h	18.735ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.305m	2.184ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.897m	5.576ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.163m	2.828ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.435m	5.981ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.521m	2.806ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.800m	4.187ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.012m	2.864ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.529m	3.021ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	15.879m	7.425ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.126m	5.962ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.128m	2.971ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.126m	5.962ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	5.360m	2.558ms	3	3	100.00
		chip_sw_aes_smoketest	5.305m	2.882ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.272m	3.307ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.561m	2.483ms	3	3	100.00
		chip_sw_csrng_smoketest	3.776m	2.873ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.357m	4.194ms	3	3	100.00
		chip_sw_gpio_smoketest	5.278m	3.324ms	3	3	100.00
		chip_sw_hmac_smoketest	6.426m	2.767ms	3	3	100.00
		chip_sw_kmac_smoketest	5.824m	3.110ms	3	3	100.00
		chip_sw_otbn_smoketest	40.786m	10.125ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.462m	3.274ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.341m	5.943ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.434m	4.391ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.198m	2.660ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.048m	2.948ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.962m	3.047ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.070m	2.600ms	3	3	100.00
		chip_sw_uart_smoketest	4.901m	2.970ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.212m	4.672ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	41.499m	9.442ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.719h	78.094ms	1	3	33.33
V2	chip_sw_secure_boot	rom_e2e_smoke	35.553m	8.932ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	35.707m	15.460ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	11.911m	4.640ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	11.450m	9.854ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.054h	57.184ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.092h	65.611ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	7.601m	4.980ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	7.601m	4.980ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.981h	66.601ms	3	5	60.00
		chip_same_csr_outstanding	1.225h	29.605ms	20	20	100.00
		chip_csr_hw_reset	4.755m	5.072ms	5	5	100.00
		chip_csr_rw	11.001m	5.908ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.981h	66.601ms	3	5	60.00
		chip_same_csr_outstanding	1.225h	29.605ms	20	20	100.00
		chip_csr_hw_reset	4.755m	5.072ms	5	5	100.00
		chip_csr_rw	11.001m	5.908ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.495m	2.507ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.610s	60.473us	100	100	100.00
		xbar_smoke_large_delays	1.967m	11.747ms	100	100	100.00
		xbar_smoke_slow_rsp	2.069m	6.751ms	100	100	100.00
		xbar_random_zero_delays	57.560s	612.714us	100	100	100.00
		xbar_random_large_delays	22.625m	110.667ms	100	100	100.00
		xbar_random_slow_rsp	23.692m	70.129ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.024m	1.341ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.029m	1.498ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.564m	2.687ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.029m	1.498ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.619m	3.539ms	100	100	100.00
		xbar_access_same_device_slow_rsp	55.498m	174.351ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.472m	2.737ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	10.656m	15.449ms	100	100	100.00
		xbar_stress_all_with_error	11.030m	17.916ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	16.630m	8.827ms	100	100	100.00
		xbar_stress_all_with_reset_error	14.892m	19.337ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	35.553m	8.932ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	47.927m	23.607ms	2	3	66.67
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	36.924m	8.161ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	23.864m	7.471ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	36.038m	8.711ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	34.915m	8.598ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	32.452m	9.475ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	31.344m	8.885ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	23.415m	7.031ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	36.377m	8.803ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	38.434m	8.810ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	36.019m	8.750ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	34.380m	8.470ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	38.661m	10.270ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	47.385m	12.096ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	46.086m	11.993ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	53.119m	11.168ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	45.594m	12.105ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	39.871m	9.920ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	46.369m	11.817ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	44.926m	11.303ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	44.613m	12.033ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	45.691m	11.854ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.363m	7.535ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	31.622m	8.774ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	31.449m	9.013ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	33.624m	8.009ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	30.010m	8.571ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	28.505m	7.158ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	32.321m	8.278ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	31.919m	8.009ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	40.570m	8.647ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	40.864m	9.220ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	30.844m	7.231ms	3	3	100.00
		rom_e2e_asm_init_dev	34.564m	9.429ms	3	3	100.00
		rom_e2e_asm_init_prod	35.114m	8.490ms	3	3	100.00
		rom_e2e_asm_init_prod_end	36.250m	8.533ms	3	3	100.00
		rom_e2e_asm_init_rma	32.981m	9.318ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	47.549m	10.561ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.836m	2.539ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.305m	2.184ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.330m	2.889ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.956m	3.208ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	8.813m	5.107ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.566m	19.120ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.566m	19.120ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.599m	4.460ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.341m	5.943ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.599m	4.460ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.645m	9.268ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.645m	9.268ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.037m	6.830ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.057m	4.840ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	19.283m	6.029ms	3	3	100.00
		chip_sw_aes_idle	4.956m	3.208ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.486m	2.778ms	3	3	100.00
		chip_sw_kmac_idle	4.834m	3.064ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.268m	4.635ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.738m	4.097ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.369m	4.565ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	7.790m	4.477ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	21.950m	10.497ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.342m	3.990ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.939m	4.809ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.905m	4.694ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.727m	4.724ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.553m	4.249ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.028m	5.252ms	3	3	100.00
		chip_sw_ast_clk_outputs	16.837m	7.171ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.292m	11.755ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.905m	4.694ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.727m	4.724ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.226m	4.292ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.417m	5.623ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.020h	18.735ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.305m	2.184ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.897m	5.576ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.163m	2.828ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.435m	5.981ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.521m	2.806ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.800m	4.187ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.012m	2.864ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.655m	2.855ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	11.263m	5.117ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	21.305m	6.794ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.210h	24.791ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.970m	3.556ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.137m	2.863ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.753m	5.210ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	6.286m	3.467ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	9.882m	5.738ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	35.566m	20.544ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	57.335m	16.355ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.837m	7.171ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.078m	4.698ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.629m	3.603ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	13.192m	5.670ms	98	100	98.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	36.338m	9.931ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	34.839m	7.800ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	9.692m	10.010ms	0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	14.531m	20.010ms	0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.563m	2.941ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	19.458m	7.519ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	31.821m	21.056ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	7.374m	3.102ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	43.000s	10.200us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	9.814m	4.527ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	31.821m	21.056ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	31.821m	21.056ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	56.502m	20.598ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	56.502m	20.598ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	7.181m	4.772ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.566m	19.120ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	54.126m	15.290ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.851m	3.054ms	3	3	100.00
		chip_sw_edn_entropy_reqs	13.767m	4.939ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.851m	3.054ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	34.839m	7.800ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.428m	3.264ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	30.508m	20.212ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	17.987m	5.628ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.417m	5.623ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	10.561m	4.441ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	13.226m	4.292ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	8.413m	10.010ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	30.508m	20.212ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.616m	3.577ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	11.562m	4.304ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.255m	3.841ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	8.413m	10.010ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.255m	3.841ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.255m	3.841ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	8.255m	3.841ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.255m	3.841ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	13.192m	5.670ms	98	100	98.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	8.293m	10.232ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	18.844m	4.668ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	10.541m	4.058ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	10.541m	4.058ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.619m	2.783ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.163m	2.828ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.486m	2.778ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	12.740m	4.423ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	17.216m	5.674ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	17.726m	6.013ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.320m	3.668ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	11.562m	4.304ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.435m	5.981ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	10.617m	4.503ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	8.813m	5.107ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.180h	17.195ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.795m	2.704ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.124m	2.997ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.521m	2.806ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	11.562m	4.304ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	16.417m	11.475ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.837m	2.216ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.489m	2.950ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.834m	3.064ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.231m	5.114ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	22.875m	14.222ms	5	5	100.00
		chip_tap_straps_rma	14.772m	8.288ms	5	5	100.00
		chip_tap_straps_prod	11.319m	7.131ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.376m	3.051ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	16.417m	11.475ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	16.417m	11.475ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	16.417m	11.475ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	7.800m	4.812ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	8.255m	3.841ms	3	3	100.00
		chip_sw_flash_rma_unlocked	8.413m	10.010ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.463m	3.987ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.743m	7.916ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.359m	9.500ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	22.777m	8.659ms	3	3	100.00
		chip_sw_lc_ctrl_transition	16.417m	11.475ms	15	15	100.00
		chip_sw_keymgr_key_derivation	11.562m	4.304ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	13.528m	8.797ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	9.748m	10.021ms	0	3	0.00
		chip_prim_tl_access	8.293m	10.232ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.292m	11.755ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.342m	3.990ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.939m	4.809ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.905m	4.694ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.727m	4.724ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.553m	4.249ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.028m	5.252ms	3	3	100.00
		chip_tap_straps_dev	22.875m	14.222ms	5	5	100.00
		chip_tap_straps_rma	14.772m	8.288ms	5	5	100.00
		chip_tap_straps_prod	11.319m	7.131ms	5	5	100.00
		chip_rv_dm_lc_disabled	4.897m	7.842ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.507m	3.091ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.583m	2.426ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.789m	3.469ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.420m	3.708ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	46.125m	32.451ms	3	3	100.00
		chip_rv_dm_lc_disabled	4.897m	7.842ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.596h	47.845ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.628h	47.632ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	17.396m	8.027ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.538h	48.149ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	46.125m	32.451ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.035m	1.951ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.098m	2.642ms	3	3	100.00
		rom_volatile_raw_unlock	2.179m	3.095ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	16.417m	11.475ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	30.508m	20.212ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.692m	3.789ms	3	3	100.00
		chip_sw_keymgr_key_derivation	11.562m	4.304ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.812m	5.770ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.817m	2.927ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	30.508m	20.212ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.692m	3.789ms	3	3	100.00
		chip_sw_keymgr_key_derivation	11.562m	4.304ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.812m	5.770ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.817m	2.927ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	16.417m	11.475ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	14.686m	14.635ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.376m	3.051ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.463m	3.987ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.743m	7.916ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.359m	9.500ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	22.777m	8.659ms	3	3	100.00
		chip_sw_lc_ctrl_transition	16.417m	11.475ms	15	15	100.00
		chip_prim_tl_access	8.293m	10.232ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.293m	10.232ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	11.098m	7.505ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	25.148m	19.585ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	6.605m	7.149ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	10.271m	8.218ms	1	3	33.33
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	11.625m	16.618ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	27.864m	19.915ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	32.005m	17.430ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	14.645m	9.268ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	20.657m	12.117ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.972m	5.517ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	11.098m	7.505ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	7.972m	4.759ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	54.527m	31.738ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.130m	7.427ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.145m	5.069ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.182m	22.281ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	19.458m	7.519ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	27.906m	13.662ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	51.928m	25.773ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.739m	3.006ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	13.192m	5.670ms	98	100	98.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	13.528m	8.797ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	13.528m	8.797ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	27.906m	13.662ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.182m	22.281ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	11.972m	5.517ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.341m	5.943ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.386m	4.478ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	14.993m	6.563ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	10.334m	4.919ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	33.667m	12.406ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.219m	3.210ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	13.192m	5.670ms	98	100	98.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	35.110m	6.315ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	24.001m	6.301ms	3	3	100.00
		chip_plic_all_irqs_10	10.106m	3.517ms	3	3	100.00
		chip_plic_all_irqs_20	15.856m	5.026ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.380m	3.079ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.141m	3.242ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	35.553m	8.932ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.715m	6.202ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	10.681m	4.151ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.851m	3.540ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.423m	2.922ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.812m	5.770ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.800m	4.187ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	15.086m	8.570ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	13.596m	6.313ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.748m	10.021ms	0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	13.192m	5.670ms	98	100	98.00
		chip_sw_data_integrity_escalation	14.952m	5.070ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.436m	3.299ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.921m	3.039ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.183m	3.636ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.126m	4.248ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	35.319m	8.259ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.853h	31.208ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	54.186m	12.321ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.482m	3.074ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.231m	5.114ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	13.192m	5.670ms	98	100	98.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.199m	3.122ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	33.667m	12.406ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.815m	5.773ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.453m	3.936ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	22.433m	10.485ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	36.338m	9.931ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	35.110m	6.315ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.576h	255.017ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	23.343m	12.294ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	27.995m	12.690ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.386m	4.478ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	7.894m	5.012ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.377m	3.733ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	14.772m	8.288ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.897m	7.842ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2581	2657	97.14
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.203m	3.271ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.622h	50.374ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.590m	5.911ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.002m	2.251ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.967m	2.564ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.706m	1.854ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.129h	39.664ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.096h	39.793ms	0	1	0.00
		rom_e2e_jtag_inject_rma	54.608m	39.913ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	34.746m	9.325ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.204m	3.556ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.226m	3.244ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	33.763m	7.280ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	35.962m	9.725ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.072m	3.635ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	23.185m	5.586ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.500m	3.388ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	9.609m	4.996ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.183m	23.117ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	10.077m	4.118ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	27.906m	13.662ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	13.192m	5.670ms	98	100	98.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	17.703m	5.682ms	3	5	60.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.032h	19.439ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.002m	2.251ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.967m	2.564ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.706m	1.854ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.442m	5.445ms	3	3	100.00
V3		TOTAL			30	48	62.50
	Unmapped tests	chip_sival_flash_info_access	6.226m	2.555ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	10.065m	5.430ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.178h	17.409ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	18.646m	6.097ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.882m	5.443ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.721m	5.717ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.044m	3.302ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.726m	2.799ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2823	2958	95.44

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	10	52.63
V2	290	276	248	85.52
V2S	1	1	1	100.00
V3	91	22	12	13.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.10	95.47	94.22	95.06	--	94.93	97.38	99.53

Failure Buckets

• Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

  • Test chip_sw_flash_ctrl_write_clear has 3 failures.

    • 0.chip_sw_flash_ctrl_write_clear.93205012161374136533739004384084807304764946218726263721524634414456639767761
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

        (15:52:00) Loading:
        (15:52:01) Loading:
        (15:52:01) Loading: 4 packages loaded
        (15:52:01) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (15:52:01) WARNING: Target pattern parsing failed.
        (15:52:01) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (15:52:02) INFO: Elapsed time: 35.458s
        (15:52:02) INFO: 0 processes.
        (15:52:02) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_flash_ctrl_write_clear.15966648428844170922744938342321798745295698542736669435724415168226732781853
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

        (16:03:21) Loading:
        (16:03:22) Loading:
        (16:03:22) Loading: 4 packages loaded
        (16:03:22) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (16:03:22) WARNING: Target pattern parsing failed.
        (16:03:22) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (16:03:23) INFO: Elapsed time: 31.659s
        (16:03:23) INFO: 0 processes.
        (16:03:23) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_meas.109897558858528573838892806983026554661464962699175083145376932391709231979146
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

        (15:53:12) Loading:
        (15:53:12) Loading:
        (15:53:12) Loading: 4 packages loaded
        (15:53:12) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:53:12) WARNING: Target pattern parsing failed.
        (15:53:12) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:53:12) INFO: Elapsed time: 18.284s
        (15:53:12) INFO: 0 processes.
        (15:53:12) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_meas.48955908098063998740729929896205109743633524490963312327274130667676240946698
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

        (16:04:37) Loading:
        (16:04:37) Loading:
        (16:04:37) Loading: 4 packages loaded
        (16:04:38) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:04:38) WARNING: Target pattern parsing failed.
        (16:04:38) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:04:38) INFO: Elapsed time: 19.883s
        (16:04:38) INFO: 0 processes.
        (16:04:38) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_no_meas.81701131519377160515710261914048497682005772516483359029072993744860021254780
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

        (15:53:25) Loading:
        (15:53:26) Loading:
        (15:53:26) Loading: 4 packages loaded
        (15:53:26) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:53:26) WARNING: Target pattern parsing failed.
        (15:53:26) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:53:26) INFO: Elapsed time: 29.689s
        (15:53:26) INFO: 0 processes.
        (15:53:26) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_no_meas.113448196957351801627747583385043735198271100470536918273538119028858738997079
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

        (16:04:34) Loading:
        (16:04:34) Loading:
        (16:04:34) Loading: 4 packages loaded
        (16:04:35) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:04:35) WARNING: Target pattern parsing failed.
        (16:04:35) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:04:35) INFO: Elapsed time: 17.842s
        (16:04:35) INFO: 0 processes.
        (16:04:35) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_invalid_meas.85588152551404587685607910605909923281780020947411477651705907802964360161059
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

        (15:53:23) Loading:
        (15:53:24) Loading:
        (15:53:24) Loading: 4 packages loaded
        (15:53:24) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:53:24) WARNING: Target pattern parsing failed.
        (15:53:24) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:53:24) INFO: Elapsed time: 19.687s
        (15:53:24) INFO: 0 processes.
        (15:53:24) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_invalid_meas.7028415879371062164280563689837969026704961325706004360580500978895262014982
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

        (16:04:45) Loading:
        (16:04:46) Loading:
        (16:04:46) Loading: 4 packages loaded
        (16:04:46) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:04:46) WARNING: Target pattern parsing failed.
        (16:04:46) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:04:46) INFO: Elapsed time: 26.093s
        (16:04:46) INFO: 0 processes.
        (16:04:46) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

    • 0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.98127178648974674922765497765356201492844943803389081137605159131400975911970
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

        (15:53:38) Loading:
        (15:53:39) Loading:
        (15:53:39) Loading: 4 packages loaded
        (15:53:39) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:53:39) WARNING: Target pattern parsing failed.
        (15:53:39) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:53:39) INFO: Elapsed time: 22.610s
        (15:53:39) INFO: 0 processes.
        (15:53:39) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.20788762716006473095751000270158180509164436325833349730451061081680887098235
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

        (16:04:35) Loading:
        (16:04:36) Loading:
        (16:04:36) Loading: 4 packages loaded
        (16:04:36) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (16:04:36) WARNING: Target pattern parsing failed.
        (16:04:36) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (16:04:36) INFO: Elapsed time: 18.528s
        (16:04:36) INFO: 0 processes.
        (16:04:36) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • ... and 9 more tests.

• UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test chip_csr_mem_rw_with_rand_reset has 20 failures.

    • 0.chip_csr_mem_rw_with_rand_reset.8632747960185055511721432078082334655316997129013178421179127881347631355506
      Line 409, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2648.584813 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2648.584813 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_csr_mem_rw_with_rand_reset.63760623039111643072814490601027406203719650195037169463363390412500436824658
      Line 381, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2301.031965 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2301.031965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt has 17 failures:

  • Test chip_sw_uart_tx_rx has 2 failures.

    • 0.chip_sw_uart_tx_rx.37321104362897456507073206030635486531410528498947518990375422393375997933988
      Line 792, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

        UVM_ERROR @ 5180.296412 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
        UVM_INFO @ 5180.296412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.chip_sw_uart_tx_rx.112286859026117966636070637271170246537286170268005003982577339152158534052928
      Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx/latest/run.log

        UVM_ERROR @ 5200.952556 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
        UVM_INFO @ 5200.952556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_uart_tx_rx_idx1 has 3 failures.

    • 0.chip_sw_uart_tx_rx_idx1.45799560074454817182943723355138767270739409616275450901212658844853245480562
      Line 817, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx1/latest/run.log

        UVM_ERROR @ 4678.583276 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
        UVM_INFO @ 4678.583276 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_uart_tx_rx_idx1.32378804101291051492634667450626245788065305764046625798429804614767664974135
      Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx1/latest/run.log

        UVM_ERROR @ 5224.407690 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
        UVM_INFO @ 5224.407690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test chip_sw_uart_tx_rx_idx3 has 2 failures.

    • 0.chip_sw_uart_tx_rx_idx3.2948751233046525979352021909623927938635640196756111831492932387940711714912
      Line 771, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx3/latest/run.log

        UVM_ERROR @ 4751.381280 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
        UVM_INFO @ 4751.381280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.chip_sw_uart_tx_rx_idx3.24106420076891270674859238551240871762708043509424371875378426878143424443910
      Line 812, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx3/latest/run.log

        UVM_ERROR @ 4449.786928 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
        UVM_INFO @ 4449.786928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_uart_tx_rx_bootstrap has 1 failures.

    • 1.chip_sw_uart_tx_rx_bootstrap.98107342110887289640746165427112704357184809651315085873723441895444507534692
      Line 844, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log

        UVM_ERROR @ 78094.476173 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
        UVM_INFO @ 78094.476173 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_uart_rand_baudrate has 5 failures.

    • 1.chip_sw_uart_rand_baudrate.55320763210189717981750080674592935536719301368460562655326749036854581960074
      Line 747, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_rand_baudrate/latest/run.log

        UVM_ERROR @ 5013.481162 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
        UVM_INFO @ 5013.481162 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.chip_sw_uart_rand_baudrate.53045318000513717318996291034886882872196688848388144514368527840083108110923
      Line 796, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest/run.log

        UVM_ERROR @ 18359.258632 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
        UVM_INFO @ 18359.258632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

  • ... and 3 more tests.

• Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:

  • Test chip_sw_uart_tx_rx_bootstrap has 1 failures.

    • 0.chip_sw_uart_tx_rx_bootstrap.55046598194703108752092767342450971309634161621685680198113660086166776066976
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log

        Job ID: smart:1a68f639-6178-4f64-8b09-5bfb6e2c5a79
      

  • Test chip_sw_rv_timer_systick_test has 3 failures.

    • 0.chip_sw_rv_timer_systick_test.64756388251089870102616225892104772706729842190060692566390748321758195436947
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:3e5bdd56-8013-4613-ac57-d40556323afc
      

    • 1.chip_sw_rv_timer_systick_test.68661187956078526483167999589887349015666264780388422211663734806398216737719
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:b9fa870a-a24e-4ae5-9f6f-e3e2e0e38e77
      

    • ... and 1 more failures.

  • Test chip_sw_ast_clk_rst_inputs has 3 failures.

    • 0.chip_sw_ast_clk_rst_inputs.33108439579316055766157522359215873050328106901877081421638834240365846354198
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log

        Job ID: smart:1fa65750-1f6c-4087-8572-f11c0828b5d2
      

    • 1.chip_sw_ast_clk_rst_inputs.91371786075200130498969010639144727656721133612825790514996103855592817857934
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log

        Job ID: smart:62c95fae-12f7-4c35-a322-0312408d5b86
      

    • ... and 1 more failures.

  • Test chip_sw_power_virus has 1 failures.

    • 2.chip_sw_power_virus.74411263551191414585927151570454231059164037804535804918270381152116189585808
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log

        Job ID: smart:ea2e9743-22e0-47a6-8dad-df1810e4414d
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

  • Test chip_sw_pwrmgr_deep_sleep_por_reset has 2 failures.

    • 0.chip_sw_pwrmgr_deep_sleep_por_reset.60078581360383248548433731850681427634158436105238303255876963029126534531545
      Line 766, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

        UVM_ERROR @ 16019.131989 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 16019.131989 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 2.chip_sw_pwrmgr_deep_sleep_por_reset.65302172376287656550333052455799206087159474044664090140035602530035735885435
      Line 802, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

        UVM_ERROR @ 16652.741102 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 16652.741102 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_pwrmgr_normal_sleep_por_reset has 2 failures.

    • 0.chip_sw_pwrmgr_normal_sleep_por_reset.40878798791146120874807981516615566306704424611925516054673998553571192978176
      Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

        UVM_ERROR @ 16617.967546 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 16617.967546 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 2.chip_sw_pwrmgr_normal_sleep_por_reset.63789958101780935638820832630400550746679571791575973340260625769540864963335
      Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

        UVM_ERROR @ 17335.684666 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 17335.684666 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (chip_sw_flash_rma_unlocked_vseq.sv:159) [chip_sw_flash_rma_unlocked_vseq] wait timeout occurred! has 3 failures:

  • Test chip_sw_flash_rma_unlocked has 3 failures.

    • 0.chip_sw_flash_rma_unlocked.78620214779736782323292648187372316552299375375655242540778945963383978221156
      Line 723, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log

        UVM_FATAL @ 10010.140001 us: (chip_sw_flash_rma_unlocked_vseq.sv:159) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
        UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_flash_rma_unlocked.78357728418345593132397067017660636301210441189555478762338791211351923496008
      Line 799, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log

        UVM_FATAL @ 10010.260001 us: (chip_sw_flash_rma_unlocked_vseq.sv:159) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
        UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:

  • Test chip_sw_sysrst_ctrl_outputs has 3 failures.

    • 0.chip_sw_sysrst_ctrl_outputs.48193540621411618836071451110142091351043835334697081431967359854094581093014
      Line 751, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_sysrst_ctrl_outputs.76595391952738677907214224846845250877180328874407506795790648476104636183214
      Line 741, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:57) [chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress has 3 failures:

  • Test chip_sw_csrng_lc_hw_debug_en_test has 3 failures.

    • 0.chip_sw_csrng_lc_hw_debug_en_test.33839626733933236164648081892331732050263270650966402000110703229457884980223
      Line 786, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log

        UVM_FATAL @ 20010.160001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
        UVM_INFO @ 20010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_csrng_lc_hw_debug_en_test.41966126231698505996615833595160799159592582964412468258895925560366848526292
      Line 814, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log

        UVM_FATAL @ 20010.160001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
        UVM_INFO @ 20010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_entropy_src_fuse_vseq.sv:34) [chip_sw_entropy_src_fuse_vseq] *- has 3 failures:

  • Test chip_sw_csrng_fuse_en_sw_app_read_test has 3 failures.

    • 0.chip_sw_csrng_fuse_en_sw_app_read_test.83915967670311198477815624691779718774402700095491879896920310143931635288863
      Line 859, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log

        UVM_FATAL @ 10010.140001 us: (chip_sw_entropy_src_fuse_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
        UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_csrng_fuse_en_sw_app_read_test.81344996220827390455988805809680893558968290829525967174941695190467776949786
      Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log

        UVM_FATAL @ 10010.400001 us: (chip_sw_entropy_src_fuse_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
        UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_sram_ctrl_execution_main_vseq.sv:33) [chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred! has 3 failures:

  • Test chip_sw_sram_ctrl_execution_main has 3 failures.

    • 0.chip_sw_sram_ctrl_execution_main.8834535242197749667749796049990762293591289335748518428756429538840701364231
      Line 891, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log

        UVM_FATAL @ 10020.500001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
        UVM_INFO @ 10020.500001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_sram_ctrl_execution_main.22275240515712876185967333998467856113578781892533923102365928871235594862947
      Line 750, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/run.log

        UVM_FATAL @ 10020.420001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
        UVM_INFO @ 10020.420001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

  • Test chip_sw_lc_ctrl_program_error has 3 failures.

    • 0.chip_sw_lc_ctrl_program_error.107024834065574899978159280882110550753426538291758420131818914855033676220613
      Line 830, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 14634.954098 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 14634.954098 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.chip_sw_lc_ctrl_program_error.19933497578801809999893517298678468910977314288442710270861602923296944905993
      Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 14764.566664 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 14764.566664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:

  • Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.

    • 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.23835279438120427353643471751654064647358776518956602032620480059387339580904
      Line 811, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log

        UVM_FATAL @ 22635.516318 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
        UVM_INFO @ 22635.516318 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.86176923456144530699426316882212377487672696588977474393996381705697840150595
      Line 782, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log

        UVM_FATAL @ 23117.144926 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
        UVM_INFO @ 23117.144926 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:

  • Test chip_sw_rv_dm_access_after_wakeup has 3 failures.

    • 0.chip_sw_rv_dm_access_after_wakeup.21221833558110998908958612987482986965696024611724572465911498197675352087808
      Line 843, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log

        UVM_FATAL @ 3732.929663 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
        UVM_INFO @ 3732.929663 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_rv_dm_access_after_wakeup.71168487279525966220813686730089687893612687316404977805817715360899787037637
      Line 793, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log

        UVM_FATAL @ 3601.051903 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
        UVM_INFO @ 3601.051903 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:

  • Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_debug_test_unlocked0.7125204129028016644926878031246021593327786369783597385499073148473791970895
      Line 742, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log

        UVM_FATAL @ 2250.741500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2250.741500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_dev has 1 failures.

    • 0.rom_e2e_jtag_debug_dev.84735883650470791970485323014520093526708444011818054134792925094297033606687
      Line 784, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log

        UVM_FATAL @ 2563.816000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2563.816000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_rma has 1 failures.

    • 0.rom_e2e_jtag_debug_rma.63380305912343668348479303234230087400474068851794403145315514605343782862908
      Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log

        UVM_FATAL @ 1853.546500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 1853.546500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:

  • Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_inject_test_unlocked0.1119076196462966357925026528713582479574161055910695886617233761860533830562
      Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log

        UVM_FATAL @ 39664.460307 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 39664.460307 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_inject_dev has 1 failures.

    • 0.rom_e2e_jtag_inject_dev.6952162158655732517927667913537531082726814796673386684094593830079382667455
      Line 809, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log

        UVM_FATAL @ 39793.235012 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 39793.235012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_inject_rma has 1 failures.

    • 0.rom_e2e_jtag_inject_rma.55373657312462075343997468434036794171057635993724732902330300545929407223870
      Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log

        UVM_FATAL @ 39912.588590 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 39912.588590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns * has 3 failures:

  • Test rom_e2e_self_hash has 3 failures.

    • 0.rom_e2e_self_hash.38696133523507483563590038567898048613661606020708487748830156461151623755479
      Line 816, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

        UVM_ERROR @ 9324.622290 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
        UVM_INFO @ 9324.622290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_e2e_self_hash.102260039084688449230920314840292083049129783400630686363862417506291328444098
      Line 766, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

        UVM_ERROR @ 9451.780968 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
        UVM_INFO @ 9451.780968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test chip_csr_aliasing has 2 failures.

    • 0.chip_csr_aliasing.74055677093676665689237049442079679385404725484347196736958075804126236273187
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

        Job ID: smart:6040c602-e5ec-49eb-91b6-8762ecfe41b4
      

    • 3.chip_csr_aliasing.17549843654232968278134373256241872814533346926607865727621249840130243763260
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_csr_aliasing/latest/run.log

        Job ID: smart:e443dcfd-d29a-4c2d-acfc-e03fceb2c574
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:

  • Test chip_sw_all_escalation_resets has 2 failures.

    • 0.chip_sw_all_escalation_resets.32745273458207729634897234003052284862455178936497614372360629087246860032319
      Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 2768.753660 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
        UVM_INFO @ 2768.753660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 79.chip_sw_all_escalation_resets.19659320470778186088917232003684065914220790321595710696768478925252872267350
      Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 3420.081440 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
        UVM_INFO @ 3420.081440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 2 failures:

  • Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 2 failures.

    • 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.26468160832703903015764922295421736936845085404662326246959146577784259900272
      Line 861, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 6101.225150 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
        UVM_INFO @ 6101.225150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.79759337981204344459070522523199779673477835393104005195944867191782169322249
      Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 6740.023938 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
        UVM_INFO @ 6740.023938 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 2 failures:

  • Test chip_sw_power_virus has 2 failures.

    • 0.chip_sw_power_virus.10281047508887675798616728220390771997173039350901030606965895103925771616000
      Line 1028, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log

        UVM_ERROR @ 5910.866229 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 5910.866229 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_power_virus.54894934781161084857774191898275394504520085176424598166245900587046896187930
      Line 983, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log

        UVM_ERROR @ 4387.919281 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 4387.919281 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.

    • 50.chip_sw_alert_handler_lpg_sleep_mode_alerts.97633545045930051424015476816331272836514890638235557721299553278768859869381
      Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 3062.561272 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
        UVM_INFO @ 3062.561272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 85.chip_sw_alert_handler_lpg_sleep_mode_alerts.57520778196488321244726906573697515252963763300935996038546472567521185911687
      Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 3632.473174 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
        UVM_INFO @ 3632.473174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:

  • Test rom_e2e_shutdown_output has 1 failures.

    • 0.rom_e2e_shutdown_output.90469562150684081686381468582360394881840165671530394288061277109037192191943
      Line 986, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log

            Offending '(pend_req[h2d.a_source].pend == 0)'
        UVM_ERROR @ 11588.754073 us: (tlul_assert.sv:263) [ASSERT FAILED] pendingReqPerSrc_M
        UVM_INFO @ 11588.754073 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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