CHIP Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.340m	2.902ms	3	3	100.00
		chip_sw_example_rom	2.165m	2.164ms	3	3	100.00
		chip_sw_example_manufacturer	3.736m	2.787ms	3	3	100.00
		chip_sw_example_concurrency	4.214m	2.174ms	3	3	100.00
		chip_sw_uart_smoketest_signed	37.940m	8.588ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset			0	5	0.00
V1	csr_rw	chip_csr_rw			0	20	0.00
V1	csr_bit_bash	chip_csr_bit_bash			0	5	0.00
V1	csr_aliasing	chip_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	5	0.00
		chip_csr_rw			0	20	0.00
V1	xbar_smoke	xbar_smoke			0	100	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	10.973m	4.124ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	10.973m	4.124ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	10.973m	4.124ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	16.495m	5.530ms	3	5	60.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	16.495m	5.530ms	3	5	60.00
		chip_sw_uart_tx_rx_idx1	15.346m	5.757ms	4	5	80.00
		chip_sw_uart_tx_rx_idx2	16.351m	5.625ms	4	5	80.00
		chip_sw_uart_tx_rx_idx3	14.569m	5.507ms	3	5	60.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	49.388m	22.679ms	15	20	75.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	56.640m	22.947ms	3	5	60.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	37.374m	22.731ms	3	5	60.00
V1		TOTAL			53	223	23.77
V2	chip_pin_mux	chip_padctrl_attributes	7.024m	4.845ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	7.024m	4.845ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	6.117m	2.958ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.104m	4.863ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.298m	4.074ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	24.081m	11.582ms	5	5	100.00
		chip_tap_straps_testunlock0	10.056m	6.423ms	5	5	100.00
		chip_tap_straps_rma	6.478m	4.433ms	5	5	100.00
		chip_tap_straps_prod	18.428m	12.991ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.351m	3.120ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.516m	8.426ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	16.059m	5.759ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	16.059m	5.759ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	21.590m	7.054ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.448m	4.592ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.546m	6.346ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.021h	18.050ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.465m	3.101ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	15.151m	5.161ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.787m	3.188ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.384m	4.692ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	7.518m	2.773ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.729m	4.366ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.710m	2.465ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.253m	2.820ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	16.716m	6.892ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.533m	5.368ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.571m	2.811ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.533m	5.368ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.636m	2.294ms	3	3	100.00
		chip_sw_aes_smoketest	5.279m	3.132ms	3	3	100.00
		chip_sw_aon_timer_smoketest	7.094m	3.367ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.281m	2.439ms	3	3	100.00
		chip_sw_csrng_smoketest	4.632m	2.398ms	3	3	100.00
		chip_sw_entropy_src_smoketest	8.798m	3.419ms	3	3	100.00
		chip_sw_gpio_smoketest	5.236m	3.445ms	3	3	100.00
		chip_sw_hmac_smoketest	6.528m	2.753ms	3	3	100.00
		chip_sw_kmac_smoketest	6.309m	3.441ms	3	3	100.00
		chip_sw_otbn_smoketest	20.955m	6.266ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.742m	3.739ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.567m	6.006ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	9.049m	5.035ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.916m	2.690ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.703m	3.533ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.476m	2.199ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.688m	3.214ms	3	3	100.00
		chip_sw_uart_smoketest	5.127m	3.586ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.172m	5.040ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	37.940m	8.588ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.702h	78.754ms	1	3	33.33
V2	chip_sw_secure_boot	rom_e2e_smoke	34.453m	9.348ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	35.879m	14.420ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	14.117m	4.581ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	10.951m	10.414ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.959h	59.574ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.164h	65.027ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors			0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors			0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	tl_d_partial_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	xbar_base_random_sequence	xbar_random			0	100	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays			0	100	0.00
		xbar_smoke_large_delays			0	100	0.00
		xbar_smoke_slow_rsp			0	100	0.00
		xbar_random_zero_delays			0	100	0.00
		xbar_random_large_delays			0	100	0.00
		xbar_random_slow_rsp			0	100	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_error_cases	xbar_error_random			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_all_access_same_device	xbar_access_same_device			0	100	0.00
		xbar_access_same_device_slow_rsp			0	100	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source			0	100	0.00
V2	xbar_stress_all	xbar_stress_all			0	100	0.00
		xbar_stress_all_with_error			0	100	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset			0	100	0.00
		xbar_stress_all_with_reset_error			0	100	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	34.453m	9.348ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	48.119m	25.810ms	2	3	66.67
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	34.893m	8.745ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	30.290m	6.431ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	31.334m	8.702ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.630m	8.525ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	35.521m	9.079ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	33.438m	9.329ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.605m	7.146ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	37.199m	8.821ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	34.612m	9.398ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	30.888m	8.306ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	34.155m	8.455ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	41.785m	9.823ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	48.563m	12.008ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.014h	11.618ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	52.580m	11.823ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	50.489m	11.493ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	46.013m	10.003ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	56.252m	11.420ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	46.092m	12.194ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	50.127m	11.151ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	47.203m	11.412ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	27.285m	6.807ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	30.963m	9.027ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	31.736m	8.371ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	40.520m	8.672ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	38.024m	8.208ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	30.297m	6.720ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	33.420m	8.603ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	35.240m	8.207ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	35.676m	8.770ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	35.076m	8.212ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	25.890m	7.469ms	3	3	100.00
		rom_e2e_asm_init_dev	35.379m	8.651ms	3	3	100.00
		rom_e2e_asm_init_prod	40.553m	8.991ms	3	3	100.00
		rom_e2e_asm_init_prod_end	36.413m	8.594ms	3	3	100.00
		rom_e2e_asm_init_rma	31.887m	8.990ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.641m	10.261ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.623m	2.606ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.465m	3.101ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.367m	2.884ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.739m	2.763ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	11.323m	5.462ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.574m	19.307ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.574m	19.307ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.817m	4.186ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	9.567m	6.006ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.817m	4.186ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.470m	9.471ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.470m	9.471ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.006m	6.875ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.842m	4.838ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	18.394m	5.911ms	3	3	100.00
		chip_sw_aes_idle	3.739m	2.763ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.764m	3.079ms	3	3	100.00
		chip_sw_kmac_idle	5.385m	2.791ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	7.819m	5.041ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	10.236m	5.723ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	9.050m	5.309ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	10.959m	5.289ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	27.016m	11.875ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.242m	3.956ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.340m	4.705ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.249m	4.265ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.729m	5.174ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.470m	4.284ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.426m	5.187ms	3	3	100.00
		chip_sw_ast_clk_outputs	21.590m	7.054ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	18.974m	9.945ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.249m	4.265ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.729m	5.174ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.448m	4.592ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.546m	6.346ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.021h	18.050ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.465m	3.101ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	15.151m	5.161ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.787m	3.188ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.384m	4.692ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	7.518m	2.773ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.729m	4.366ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.710m	2.465ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.108m	2.886ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	14.358m	4.790ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	20.927m	7.635ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.172h	24.767ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.091m	2.692ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.963m	3.624ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.709m	5.349ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.761m	3.672ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	13.615m	5.314ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	35.196m	22.892ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.027h	18.558ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	21.590m	7.054ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.081m	4.497ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.755m	3.536ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	13.953m	6.073ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	39.485m	9.659ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	30.974m	8.083ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.886m	5.524ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	11.721m	5.492ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.638m	2.912ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	23.043m	6.939ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	31.838m	20.990ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	7.995m	3.425ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	40.640s	10.400us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	10.408m	4.254ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	31.838m	20.990ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	31.838m	20.990ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	57.226m	20.873ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	57.226m	20.873ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.679m	4.791ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.574m	19.307ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.312h	20.748ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.751m	3.168ms	3	3	100.00
		chip_sw_edn_entropy_reqs	19.713m	4.863ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.751m	3.168ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	30.974m	8.083ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.868m	3.009ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	37.344m	23.853ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	20.256m	5.678ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.546m	6.346ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.632m	3.946ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	13.448m	4.592ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.406h	43.204ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	37.344m	23.853ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	5.686m	3.716ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	8.146m	3.670ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.603m	5.049ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.406h	43.204ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.603m	5.049ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.603m	5.049ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	8.603m	5.049ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.603m	5.049ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	13.953m	6.073ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	19.628m	6.003ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	12.748m	5.786ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	12.748m	5.786ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.589m	2.832ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.787m	3.188ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.764m	3.079ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	18.997m	5.868ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	12.629m	5.705ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	15.568m	5.821ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	8.152m	3.782ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	8.146m	3.670ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.384m	4.692ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	8.495m	4.102ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	11.323m	5.462ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.152h	15.342ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.219m	2.671ms	3	3	100.00
		chip_sw_kmac_mode_kmac	4.946m	2.466ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	7.518m	2.773ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	8.146m	3.670ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	20.402m	13.310ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.686m	2.666ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.204m	2.933ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.385m	2.791ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.069m	6.184ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	24.081m	11.582ms	5	5	100.00
		chip_tap_straps_rma	6.478m	4.433ms	5	5	100.00
		chip_tap_straps_prod	18.428m	12.991ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.794m	3.616ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	20.402m	13.310ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	20.402m	13.310ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	20.402m	13.310ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.788m	4.388ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	8.603m	5.049ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.406h	43.204ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.509m	3.897ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	21.135m	7.525ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	23.266m	8.094ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	26.451m	8.090ms	3	3	100.00
		chip_sw_lc_ctrl_transition	20.402m	13.310ms	15	15	100.00
		chip_sw_keymgr_key_derivation	8.146m	3.670ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	9.285m	9.094ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	15.793m	10.186ms	3	3	100.00
		chip_prim_tl_access			0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	18.974m	9.945ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.242m	3.956ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.340m	4.705ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.249m	4.265ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.729m	5.174ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.470m	4.284ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.426m	5.187ms	3	3	100.00
		chip_tap_straps_dev	24.081m	11.582ms	5	5	100.00
		chip_tap_straps_rma	6.478m	4.433ms	5	5	100.00
		chip_tap_straps_prod	18.428m	12.991ms	5	5	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.485m	2.482ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.157m	3.104ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.359m	3.072ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.267m	3.802ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	35.089m	27.446ms	3	3	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.508h	51.880ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.660h	50.176ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	18.627m	7.807ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.630h	45.781ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	35.089m	27.446ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.004m	2.988ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.047m	2.434ms	3	3	100.00
		rom_volatile_raw_unlock	1.897m	1.908ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	20.402m	13.310ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	37.344m	23.853ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.874m	3.448ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.146m	3.670ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	14.048m	5.276ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.238m	3.127ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	37.344m	23.853ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.874m	3.448ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.146m	3.670ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	14.048m	5.276ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.238m	3.127ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	20.402m	13.310ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	17.488m	15.214ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.794m	3.616ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.509m	3.897ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	21.135m	7.525ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	23.266m	8.094ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	26.451m	8.090ms	3	3	100.00
		chip_sw_lc_ctrl_transition	20.402m	13.310ms	15	15	100.00
		chip_prim_tl_access			0	3	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.977m	7.100ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	32.991m	18.934ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	8.247m	7.177ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	11.613m	17.476ms	0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	14.933m	5.687ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	28.651m	22.388ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	23.334m	15.623ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.470m	9.471ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	28.825m	14.244ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.908m	5.093ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.977m	7.100ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	6.597m	3.801ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.108h	38.617ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.397m	7.029ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.980m	5.235ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.085m	19.847ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	23.043m	6.939ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	23.892m	12.222ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	49.352m	29.095ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.248m	2.686ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	13.953m	6.073ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.285m	9.094ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.285m	9.094ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	23.892m	12.222ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.085m	19.847ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	10.908m	5.093ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.567m	6.006ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.239m	4.946ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	11.524m	6.082ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.470m	4.823ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	30.177m	10.835ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.424m	2.556ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	13.953m	6.073ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	32.212m	8.102ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	22.209m	6.555ms	3	3	100.00
		chip_plic_all_irqs_10	11.896m	4.136ms	3	3	100.00
		chip_plic_all_irqs_20	14.752m	4.961ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.588m	3.062ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.881m	2.363ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	34.453m	9.348ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.648m	7.432ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	11.828m	4.773ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.070m	3.378ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.096m	3.105ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	14.048m	5.276ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.729m	4.366ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	15.107m	6.883ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	12.854m	7.861ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	15.793m	10.186ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	13.953m	6.073ms	97	100	97.00
		chip_sw_data_integrity_escalation	16.059m	5.759ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.395m	3.207ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.481m	3.246ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	6.936m	3.393ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.224m	3.921ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	32.811m	8.001ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.828h	31.656ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	48.420m	12.331ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.545m	3.106ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.069m	6.184ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	13.953m	6.073ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.350m	3.333ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	30.177m	10.835ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.221m	5.056ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.562m	3.602ms	89	90	98.89
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	28.352m	11.366ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	39.485m	9.659ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	32.212m	8.102ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.265h	255.278ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	34.714m	17.365ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	28.197m	13.403ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.239m	4.946ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9.794m	3.845ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.669m	3.987ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.478m	4.433ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			839	2657	31.58
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.679m	2.351ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.844h	51.179ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.988m	5.860ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.941m	2.126ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.485m	1.879ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.885m	2.400ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.049h	39.780ms	0	1	0.00
		rom_e2e_jtag_inject_dev	55.555m	39.814ms	0	1	0.00
		rom_e2e_jtag_inject_rma	50.177m	41.194ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	34.368m	8.982ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.433m	3.822ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.973m	3.337ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	21.238m	6.656ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	41.383m	11.220ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	14.255m	2.929ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	20.702m	5.275ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.895m	2.387ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.818m	6.036ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	6.613m	22.660ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.658m	4.893ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	23.892m	12.222ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	13.953m	6.073ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	16.495m	5.530ms	3	5	60.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.157h	18.954ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.941m	2.126ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.485m	1.879ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.885m	2.400ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.218m	4.237ms	3	3	100.00
V3		TOTAL			30	48	62.50
	Unmapped tests	chip_sival_flash_info_access	4.938m	3.325ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	12.177m	5.555ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.043h	17.174ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	16.899m	5.492ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	16.507m	4.667ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.758m	5.894ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.860m	3.480ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.341m	2.473ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			949	2958	32.08

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	6	31.58
V2	290	276	232	80.00
V2S	1	1	1	100.00
V3	91	22	12	13.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.44	90.58	80.18	89.51	--	92.51	80.56	85.31

Failure Buckets

launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.61589067212914215312657122687381988672212282992295536791572172592520716865199
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
  - 2.chip_csr_bit_bash.63425159165331406781937479219297231403000293801468432547622644460764368446513
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.59894930617992663088846456322747893210835579212373766209922983663868202887316
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
  - 2.chip_same_csr_outstanding.5923141309368496476387616923999584953938241291210368782654292041316210226276
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log
  - ... and 1 more failures.
- Test chip_prim_tl_access has 2 failures.
  - 0.chip_prim_tl_access.24172300449104718778632631199045346942764200736656332962484112804600057299678
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
  - 2.chip_prim_tl_access.107664714484921279418631223582470609302279270970216596056705447884047821262449
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log
- Test xbar_smoke has 8 failures.
  - 0.xbar_smoke.65846940260171443313403237400859370822304105729828249297352609159957161726976
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log
  - 2.xbar_smoke.83516237188523737183083980608066442739201289376103566834728255871740026501650
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log
  - ... and 6 more failures.
- Test xbar_smoke_large_delays has 8 failures.
  - 0.xbar_smoke_large_delays.89123125495246273436365945480111663854148646843345201058994370291711621347845
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log
  - 2.xbar_smoke_large_delays.47174847974748807947334505802316016055464830332379408600884150181476855959672
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log
  - ... and 6 more failures.
- ... and 22 more tests.
Job killed most likely because its dependent job failed. has 955 failures:
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.114423771445139520169948508106005534405341396031357873600467355170922085030264
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
  - 2.chip_csr_aliasing.45365367943594493932305457327628572959112480114889817643772431329755020728947
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
  - ... and 1 more failures.
- Test chip_tl_errors has 8 failures.
  - 0.chip_tl_errors.89154406948918769852103002987929834806118197288465264841293928245966462060552
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
  - 2.chip_tl_errors.11387337625613667985101542197453378393781983228191467647086506743644942324166
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log
  - ... and 6 more failures.
- Test chip_rv_dm_lc_disabled has 2 failures.
  - 0.chip_rv_dm_lc_disabled.8805355043870341050658388174059562069056263717751914446852125468768880882951
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
  - 2.chip_rv_dm_lc_disabled.31360353266254009532359776323727929873934768338958199918340383783689822477133
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
- Test xbar_smoke_zero_delays has 8 failures.
  - 0.xbar_smoke_zero_delays.21710865522667920276916431711553917026569305705705845923203632383025834663448
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log
  - 2.xbar_smoke_zero_delays.5106745426566883088600501953798611619592679304096620204274344485623226042682
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log
  - ... and 6 more failures.
- Test xbar_smoke_slow_rsp has 8 failures.
  - 0.xbar_smoke_slow_rsp.114814693081699551332591675064246911417279116227906970500789400437292171935492
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log
  - 2.xbar_smoke_slow_rsp.32747149312800416215273277288066183590603840665048759507032290326091988891524
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log
  - ... and 6 more failures.
- ... and 22 more tests.

Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.62218281677512832296692200674183081267493314829911678619383234536250669574371
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:14:54) Loading:
  (15:14:55) Loading:
  (15:14:55) Loading: 4 packages loaded
  (15:14:55) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:14:55) WARNING: Target pattern parsing failed.
  (15:14:55) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:14:55) INFO: Elapsed time: 25.614s
  (15:14:55) INFO: 0 processes.
  (15:14:55) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.62747575909495387075628874555118868893829729804499220384389306535999334702538
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:29:53) Loading:
  (15:29:54) Loading:
  (15:29:54) Loading: 4 packages loaded
  (15:29:54) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:29:54) WARNING: Target pattern parsing failed.
  (15:29:54) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:29:54) INFO: Elapsed time: 38.119s
  (15:29:54) INFO: 0 processes.
  (15:29:54) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.60894789404039935035820830418914878739946608791635593254023279809811397355592
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:18:21) Loading:
  (15:18:22) Loading:
  (15:18:22) Loading: 4 packages loaded
  (15:18:22) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:18:22) WARNING: Target pattern parsing failed.
  (15:18:22) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:18:22) INFO: Elapsed time: 25.924s
  (15:18:22) INFO: 0 processes.
  (15:18:22) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.77181875154912889776478973156585252023708832155623574951172430030720891906006
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:30:18) Loading:
  (15:30:19) Loading:
  (15:30:19) Loading: 4 packages loaded
  (15:30:19) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:30:19) WARNING: Target pattern parsing failed.
  (15:30:19) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:30:19) INFO: Elapsed time: 19.321s
  (15:30:19) INFO: 0 processes.
  (15:30:19) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.31251307655291581288796070153067425315934205469287295488632896985046335007027
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:18:46) Loading:
  (15:18:47) Loading:
  (15:18:47) Loading: 4 packages loaded
  (15:18:47) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:18:47) WARNING: Target pattern parsing failed.
  (15:18:47) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:18:47) INFO: Elapsed time: 24.542s
  (15:18:47) INFO: 0 processes.
  (15:18:47) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.44023531888423379884759158942903764670466124825856985717002280582308983735868
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:30:13) Loading:
  (15:30:14) Loading:
  (15:30:14) Loading: 4 packages loaded
  (15:30:14) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:30:14) WARNING: Target pattern parsing failed.
  (15:30:14) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:30:14) INFO: Elapsed time: 17.065s
  (15:30:14) INFO: 0 processes.
  (15:30:14) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.64633110195802196800790009602792005180901672585514463519290043754230940538225
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:18:21) Loading:
  (15:18:22) Loading:
  (15:18:22) Loading: 4 packages loaded
  (15:18:22) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:18:22) WARNING: Target pattern parsing failed.
  (15:18:22) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:18:22) INFO: Elapsed time: 19.808s
  (15:18:22) INFO: 0 processes.
  (15:18:22) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.59765551104217128952589775432289613306448995961268597392567453968512707128337
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:30:44) Loading:
  (15:30:45) Loading:
  (15:30:45) Loading: 4 packages loaded
  (15:30:45) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:30:45) WARNING: Target pattern parsing failed.
  (15:30:45) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:30:45) INFO: Elapsed time: 38.579s
  (15:30:45) INFO: 0 processes.
  (15:30:45) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.18139878596156008679433898007323441159962208215490967142166298963484876106968
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:18:23) Loading:
  (15:18:24) Loading:
  (15:18:24) Loading: 4 packages loaded
  (15:18:24) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:18:24) WARNING: Target pattern parsing failed.
  (15:18:24) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:18:24) INFO: Elapsed time: 20.622s
  (15:18:24) INFO: 0 processes.
  (15:18:24) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.10901689944835140024111634634107897853948074070818950658891576096936902526832
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:30:25) Loading:
  (15:30:25) Loading:
  (15:30:25) Loading: 4 packages loaded
  (15:30:26) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:30:26) WARNING: Target pattern parsing failed.
  (15:30:26) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:30:26) INFO: Elapsed time: 20.282s
  (15:30:26) INFO: 0 processes.
  (15:30:26) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 9 more tests.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt has 15 failures:
- Test chip_sw_uart_tx_rx_alt_clk_freq has 2 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq.4699166502631311971955136932108494917314495170187099701668126660470611305941
    Line 828, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log
```
  UVM_ERROR @ 10628.501894 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 10628.501894 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_uart_tx_rx_alt_clk_freq.12519656123920636629319014151566364331477584906253337555281576588709553017133
    Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log
```
  UVM_ERROR @ 18401.062819 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 18401.062819 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_alt_clk_freq_low_speed has 2 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.112183370978628506834667775829150062975515049046741825265400622808862367282040
    Line 826, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest/run.log
```
  UVM_ERROR @ 4721.039526 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 4721.039526 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.70011709233095921142435587201062654149902535086815365431734398117534021664187
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest/run.log
```
  UVM_ERROR @ 11610.407566 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 11610.407566 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_idx1 has 1 failures.
  - 1.chip_sw_uart_tx_rx_idx1.78881538104377544801022489160963806489067443564686199235101289694754529528221
    Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx1/latest/run.log
```
  UVM_ERROR @ 4560.691570 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 4560.691570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_rand_baudrate has 5 failures.
  - 2.chip_sw_uart_rand_baudrate.109716280830967224589836950793397173196376995282685753332583607234900116259533
    Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_rand_baudrate/latest/run.log
```
  UVM_ERROR @ 3771.806994 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 3771.806994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.chip_sw_uart_rand_baudrate.106508404656470720758295638796553440828933949281951241024118395531654351764364
    Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest/run.log
```
  UVM_ERROR @ 10834.198232 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 10834.198232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
- Test chip_sw_uart_tx_rx has 2 failures.
  - 3.chip_sw_uart_tx_rx.48434886000088288471339360966664427368373352157621684757460106358434841886269
    Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx/latest/run.log
```
  UVM_ERROR @ 4348.012672 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 4348.012672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.chip_sw_uart_tx_rx.2666949741074729716468569066774458881667077516396658090104982760490049140452
    Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx/latest/run.log
```
  UVM_ERROR @ 5463.259072 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 5463.259072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 2 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test chip_sw_uart_tx_rx_bootstrap has 2 failures.
  - 0.chip_sw_uart_tx_rx_bootstrap.75115291666439522356766746706338543074351105765620333348367497362049137509310
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:370e1644-e201-4ed0-9480-4f5b57d1e1cd
```
  - 1.chip_sw_uart_tx_rx_bootstrap.7519850263388415311710090667719607976130807688894705982108525854309804230015
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:70d38b5b-1c7c-4f35-b3a4-2c0a59655ecc
```
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.9983014099841641926813089168746847166339483741873197727126083845661378151020
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:f058a8ca-9be3-4e87-9e79-2e2a599d81d1
```
  - 1.chip_sw_rv_timer_systick_test.78353277017283402055032245543212976218074336935963464893696167903672706580941
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:6df72f18-2211-4c91-b4e7-69aa5b6eafaa
```
  - ... and 1 more failures.
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.110104944466867842820944808604889430774447642319065947359890312940855043755473
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:61f25130-5dfe-4a20-ba28-66956de011de
```
  - 1.chip_sw_ast_clk_rst_inputs.107455299584229617265808435840716672149930575398062513454874685643993016270420
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:03f7e34f-f430-41f9-9c92-77969979fbf4
```
  - ... and 1 more failures.
- Test chip_sw_power_virus has 2 failures.
  - 0.chip_sw_power_virus.85339376183898123140486976212085327446793535178264578207574864791795127551777
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:56f85482-748e-46ce-a028-d9b22144b542
```
  - 2.chip_sw_power_virus.88583722061991443711215419171977599566663128376029559906949568226744715104552
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:6cb146ac-3c32-439d-a5c6-e4cb0ca7045c
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 3 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.13147994794079622185633743701123683684773654983130815601820033772694610555122
    Line 842, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 16379.264463 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 16379.264463 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_pwrmgr_deep_sleep_por_reset.66478923148916934142165078220717499614347337130846685955982977990972574116724
    Line 807, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 17310.127231 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17310.127231 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.84379841952343254374004754868523286877468223875028081608692649910481436427812
    Line 921, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.43748113930800518225233413345347681271722936703941562916986105701410108525101
    Line 724, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.73395095971539962016576813347295722922375159205816022442802579643131533067878
    Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15214.171232 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15214.171232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.95521940488209561714461369495739722252164041646928541309457876222132206422630
    Line 921, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14735.204568 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14735.204568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.78493017820772468033155874891391061610145451102446195624704265603124231561305
    Line 869, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 22659.627920 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 22659.627920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.88743388371910649515145647441872994766763799700185205052487435678949004118840
    Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23750.674916 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23750.674916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.93903764129283884005431033748412239789779426395086185464270270247264653156082
    Line 728, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 4311.000521 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 4311.000521 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.4418590369839213358911011053013629262581364192062083018106177771668855913216
    Line 771, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3986.952070 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3986.952070 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.76608946905153475773798864103854830552507413869038813353308737156240751141993
    Line 729, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2125.752500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2125.752500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.31861961318346722024434898962579857563675691892923692246727510965278763622366
    Line 710, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 1878.767500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1878.767500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.79525072966351995509688413123050415620859650812121835558136718631865045580072
    Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2400.226000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2400.226000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.108312577700878692407133717595425715603450652165177391990444051038677854731210
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 39779.598960 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 39779.598960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.60484561795036564673713644013467499927459935120831755680852396664603962234122
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 39813.793215 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 39813.793215 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.90309138236279651965746951506756904112731408274438594162303351674387878380989
    Line 778, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 41194.280325 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 41194.280325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns * has 3 failures:
- Test rom_e2e_self_hash has 3 failures.
  - 0.rom_e2e_self_hash.40027758246736744467922403890199406326612825016879313654966514789529857246287
    Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log
```
  UVM_ERROR @ 8714.543630 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
  UVM_INFO @ 8714.543630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_e2e_self_hash.17111000950547936338258493691771599182968985819336547346588005050084962269920
    Line 802, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log
```
  UVM_ERROR @ 8981.503018 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
  UVM_INFO @ 8981.503018 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 59.chip_sw_all_escalation_resets.68030526661492062807523477781765919163920626076897743101280670843706515516666
    Line 801, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2817.570420 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2817.570420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 84.chip_sw_all_escalation_resets.9927075368711305128305567652737376130657094593451704994891640978468989338298
    Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2728.941780 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2728.941780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 1 failures.
  - 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.55785690909932991824628754541611743179143695907335443642117472873585883999128
    Line 910, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6204.325584 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6204.325584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 1.chip_sw_power_virus.30567535980867335740855433948592528712035902354353847286099102995352862321208
    Line 1001, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5859.826913 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 5859.826913 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test rom_e2e_shutdown_output has 1 failures.
  - 1.rom_e2e_shutdown_output.101428474150482482362566807856775365240264451365911825605342777234063678471874
    Line 999, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 21919.449818 us: (tlul_assert.sv:263) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 21919.449818 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 83.chip_sw_alert_handler_lpg_sleep_mode_alerts.36066411597199684510311553708207123410024665157977528606850811472444360117799
    Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3384.939104 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3384.939104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```