Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.63			85.63

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	85.47			85.47
tb.dut.top_earlgrey.u_i2c1	85.55			85.55
tb.dut.top_earlgrey.u_i2c2	85.55			85.55

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.47			85.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.47			85.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.77	90.32		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.55			85.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.55			85.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.77	90.32		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.55			85.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.55			85.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.77	90.32		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	52	40	76.92
Total Bits	348	298	85.63
Total Bits 0->1	174	149	85.63
Total Bits 1->0	174	149	85.63

Ports	52	40	76.92
Port Bits	348	298	85.63
Port Bits 0->1	174	149	85.63
Port Bits 1->0	174	149	85.63

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T30,T4	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T56,*T57	Yes	T54,T56,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T56,*T57,*T79	Yes	T56,T57,T79	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	INPUT
tl_o.a_ready	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,T65,*T225	Yes	T177,T223,T224	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T65,*T66,*T177	Yes	T65,T66,T177	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T65,T225	Yes	T177,T223,T224	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T177,*T223,*T224	Yes	T177,T223,T224	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T226,T63	Yes	T62,T226,T63	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T226,T63	Yes	T62,T226,T63	OUTPUT
cio_scl_i	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	OUTPUT
cio_sda_i	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	OUTPUT
intr_rx_threshold_o	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	OUTPUT
intr_acq_threshold_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_rx_overflow_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_nak_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_scl_interference_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_sda_interference_o	Yes	Yes	T216,T65,T217	Yes	T216,T65,T217	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_sda_unstable_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_cmd_complete_o	Yes	Yes	T177,T223,T224	Yes	T177,T223,T224	OUTPUT
intr_tx_stretch_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_tx_threshold_o	Yes	Yes	T216,T65,T217	Yes	T216,T65,T217	OUTPUT
intr_acq_full_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_unexp_stop_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_host_timeout_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	52	40	76.92
Total Bits	344	294	85.47
Total Bits 0->1	172	147	85.47
Total Bits 1->0	172	147	85.47

Ports	52	40	76.92
Port Bits	344	294	85.47
Port Bits 0->1	172	147	85.47
Port Bits 1->0	172	147	85.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T30,T4	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T223,T227,T216	Yes	T223,T227,T216	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T223,T227,T216	Yes	T223,T227,T216	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T56,*T57	Yes	T54,T56,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T56,*T57,*T79	Yes	T56,T57,T79	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T223,T227,T92	Yes	T223,T227,T92	INPUT
tl_o.a_ready	Yes	Yes	T223,T227,T92	Yes	T223,T227,T92	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T223,T227,T216	Yes	T223,T227,T216	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T223,T227,T92	Yes	T223,T227,T92	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,T65,*T225	Yes	T223,T227,T92	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T223,T227,T92	Yes	T223,T227,T92	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T65,*T66,*T223	Yes	T65,T66,T223	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T65,T225	Yes	T223,T227,T92	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T223,*T227,*T216	Yes	T223,T227,T216	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T223,T227,T92	Yes	T223,T227,T92	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T226,T63	Yes	T62,T226,T63	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T63,T64	Yes	T62,T64,T194	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T64,T194	Yes	T62,T63,T64	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T226,T63	Yes	T62,T226,T63	OUTPUT
cio_scl_i	Yes	Yes	T223,T227,T228	Yes	T223,T227,T228	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T223,T65,T229	Yes	T223,T65,T229	OUTPUT
cio_sda_i	Yes	Yes	T223,T227,T228	Yes	T223,T227,T228	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T223,T227,T228	Yes	T223,T227,T228	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T223,T216,T65	Yes	T223,T216,T65	OUTPUT
intr_rx_threshold_o	Yes	Yes	T223,T216,T217	Yes	T223,T216,T217	OUTPUT
intr_acq_threshold_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_rx_overflow_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_nak_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_scl_interference_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_sda_interference_o	Yes	Yes	T216,T65,T217	Yes	T216,T65,T217	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_sda_unstable_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_cmd_complete_o	Yes	Yes	T223,T227,T216	Yes	T223,T227,T216	OUTPUT
intr_tx_stretch_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_tx_threshold_o	Yes	Yes	T216,T65,T217	Yes	T216,T65,T217	OUTPUT
intr_acq_full_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_unexp_stop_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_host_timeout_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	52	40	76.92
Total Bits	346	296	85.55
Total Bits 0->1	173	148	85.55
Total Bits 1->0	173	148	85.55

Ports	52	40	76.92
Port Bits	346	296	85.55
Port Bits 0->1	173	148	85.55
Port Bits 1->0	173	148	85.55

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T30,T4	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T177,T230,T216	Yes	T177,T230,T216	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T177,T230,T216	Yes	T177,T230,T216	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T56,*T57	Yes	T54,T56,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T56,*T57,*T79	Yes	T56,T57,T79	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T177,T230,T92	Yes	T177,T230,T92	INPUT
tl_o.a_ready	Yes	Yes	T177,T230,T92	Yes	T177,T230,T92	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T177,T230,T216	Yes	T177,T230,T216	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T177,T230,T92	Yes	T177,T230,T92	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,T65,*T225	Yes	T177,T230,T92	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T177,T230,T92	Yes	T177,T230,T92	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T65,*T66,*T177	Yes	T65,T66,T177	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T65,T225	Yes	T177,T230,T92	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T177,*T230,*T216	Yes	T177,T230,T216	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T177,T230,T92	Yes	T177,T230,T92	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
cio_scl_i	Yes	Yes	T177,T230,T231	Yes	T177,T230,T231	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T177,T230,T65	Yes	T177,T230,T65	OUTPUT
cio_sda_i	Yes	Yes	T177,T230,T231	Yes	T177,T230,T231	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T177,T230,T65	Yes	T177,T230,T65	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T177,T230,T216	Yes	T177,T230,T216	OUTPUT
intr_rx_threshold_o	Yes	Yes	T177,T230,T216	Yes	T177,T230,T216	OUTPUT
intr_acq_threshold_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_rx_overflow_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_nak_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_scl_interference_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_sda_interference_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_sda_unstable_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_cmd_complete_o	Yes	Yes	T177,T230,T216	Yes	T177,T230,T216	OUTPUT
intr_tx_stretch_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_tx_threshold_o	Yes	Yes	T216,T65,T217	Yes	T216,T65,T217	OUTPUT
intr_acq_full_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_unexp_stop_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_host_timeout_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	52	40	76.92
Total Bits	346	296	85.55
Total Bits 0->1	173	148	85.55
Total Bits 1->0	173	148	85.55

Ports	52	40	76.92
Port Bits	346	296	85.55
Port Bits 0->1	173	148	85.55
Port Bits 1->0	173	148	85.55

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T30,T4	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T224,T232,T216	Yes	T224,T232,T216	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T224,T232,T216	Yes	T224,T232,T216	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T56,*T57	Yes	T54,T56,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T56,*T57,*T79	Yes	T56,T57,T79	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T224,T92,T232	Yes	T224,T92,T232	INPUT
tl_o.a_ready	Yes	Yes	T224,T92,T232	Yes	T224,T92,T232	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T224,T232,T216	Yes	T224,T232,T216	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T224,T92,T232	Yes	T224,T92,T232	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,T65,*T225	Yes	T224,T92,T232	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T224,T92,T232	Yes	T224,T92,T232	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T65,*T66,*T224	Yes	T65,T66,T224	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T65,T225	Yes	T224,T92,T232	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T224,*T232,*T216	Yes	T224,T232,T216	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T224,T92,T232	Yes	T224,T92,T232	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
cio_scl_i	Yes	Yes	T224,T232,T233	Yes	T224,T232,T233	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T224,T232,T65	Yes	T224,T232,T65	OUTPUT
cio_sda_i	Yes	Yes	T224,T232,T233	Yes	T224,T232,T233	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T224,T232,T233	Yes	T224,T232,T233	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T224,T232,T216	Yes	T224,T232,T216	OUTPUT
intr_rx_threshold_o	Yes	Yes	T224,T232,T216	Yes	T224,T232,T216	OUTPUT
intr_acq_threshold_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_rx_overflow_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_nak_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_scl_interference_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_sda_interference_o	Yes	Yes	T216,T65,T217	Yes	T216,T65,T217	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_sda_unstable_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_cmd_complete_o	Yes	Yes	T224,T232,T216	Yes	T224,T232,T216	OUTPUT
intr_tx_stretch_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_tx_threshold_o	Yes	Yes	T216,T65,T217	Yes	T216,T65,T217	OUTPUT
intr_acq_full_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_unexp_stop_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_host_timeout_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT

*Tests covering at least one bit in the range