Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : adc_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.12 90.12

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_adc_ctrl_aon 90.12 90.12



Module Instance : tb.dut.top_earlgrey.u_adc_ctrl_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.12 90.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.12 90.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.77 90.32 90.98 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : adc_ctrl
TotalCoveredPercent
Totals 37 29 78.38
Total Bits 324 292 90.12
Total Bits 0->1 162 146 90.12
Total Bits 1->0 162 146 90.12

Ports 37 29 78.38
Port Bits 324 292 90.12
Port Bits 0->1 162 146 90.12
Port Bits 1->0 162 146 90.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T46,T17,T44 Yes T46,T17,T44 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T46,T17,T44 Yes T46,T17,T44 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[17:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[21:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T54,*T56,*T57 Yes T54,T56,T57 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T27,T28,T29 Yes T27,T28,T29 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T56,*T57,*T79 Yes T56,T57,T79 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T46,T17,T44 Yes T46,T17,T44 INPUT
tl_o.a_ready Yes Yes T46,T17,T44 Yes T46,T17,T44 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T17,T44,T122 Yes T46,T17,T44 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T46,T17,T44 Yes T46,T17,T44 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T46,T47,*T48 Yes T46,T17,T44 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T46,T17,T44 Yes T46,T17,T44 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T17,*T44,*T122 Yes T46,T17,T44 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T46,T47,T48 Yes T46,T17,T44 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T17,*T44,*T122 Yes T46,T17,T44 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T46,T17,T44 Yes T46,T17,T44 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T62,T63,T332 Yes T62,T63,T332 INPUT
alert_rx_i[0].ping_n Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[0].ping_p Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T62,T63,T332 Yes T62,T63,T332 OUTPUT
adc_o.pd Yes Yes T17,T44,T122 Yes T17,T44,T122 OUTPUT
adc_o.channel_sel[1:0] Yes Yes T17,T44,T122 Yes T17,T44,T122 OUTPUT
adc_i.data_valid Yes Yes T17,T44,T122 Yes T17,T44,T122 INPUT
adc_i.data[9:0] Yes Yes T17,T44,T122 Yes T17,T44,T122 INPUT
intr_match_pending_o Yes Yes T122,T216,T126 Yes T122,T216,T126 OUTPUT
wkup_req_o Yes Yes T17,T44,T126 Yes T17,T44,T122 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%