Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart2	89.47			89.47
tb.dut.top_earlgrey.u_uart3	89.54			89.54
tb.dut.top_earlgrey.u_uart0	90.07			90.07
tb.dut.top_earlgrey.u_uart1	90.13			90.13

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.77	90.32		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.77	90.32		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.77	90.32		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.77	90.32		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T30,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T39,T40,T43	Yes	T39,T40,T43	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T39,T40,T43	Yes	T39,T40,T43	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T56,*T57	Yes	T54,T56,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T56,*T57,*T79	Yes	T56,T57,T79	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T39,T40,T43	Yes	T39,T40,T43	INPUT
tl_o.a_ready	Yes	Yes	T39,T40,T139	Yes	T39,T40,T139	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T40,T139,T109	Yes	T40,T139,T109	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T40,T139,*T109	Yes	T39,T40,T139	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T152,T157,T160	Yes	T39,T40,T139	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T40,T139,T109	Yes	T39,T40,T139	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T59,*T39,*T40	Yes	T59,T39,T40	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T152,T157,T160	Yes	T39,T40,T139	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T40,*T139,*T109	Yes	T40,T139,T109	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T39,T40,T139	Yes	T39,T40,T139	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T333,T265,T62	Yes	T333,T265,T62	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T333,T265,T62	Yes	T333,T265,T62	OUTPUT
cio_rx_i	Yes	Yes	T2,T30,T4	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T139,T120,T235	Yes	T139,T120,T235	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T139,T109,T152	Yes	T139,T109,T152	OUTPUT
intr_rx_watermark_o	Yes	Yes	T139,T109,T120	Yes	T139,T109,T120	OUTPUT
intr_tx_empty_o	Yes	Yes	T139,T109,T120	Yes	T139,T109,T120	OUTPUT
intr_rx_overflow_o	Yes	Yes	T139,T109,T120	Yes	T139,T109,T120	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_break_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_timeout_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	272	89.47
Total Bits 0->1	152	136	89.47
Total Bits 1->0	152	136	89.47

Ports	39	31	79.49
Port Bits	304	272	89.47
Port Bits 0->1	152	136	89.47
Port Bits 1->0	152	136	89.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T30,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T139,T109,T162	Yes	T139,T109,T162	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T139,T109,T162	Yes	T139,T109,T162	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T56,*T57	Yes	T54,T56,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T56,*T57,*T79	Yes	T56,T57,T79	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T139,T109,T162	Yes	T139,T109,T162	INPUT
tl_o.a_ready	Yes	Yes	T139,T109,T162	Yes	T139,T109,T162	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T139,T109,T162	Yes	T139,T109,T162	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T139,T109,T162	Yes	T139,T109,T162	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,*T225,*T325	Yes	T139,T109,T162	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T139,T109,T162	Yes	T139,T109,T162	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T139,*T109,*T162	Yes	T139,T109,T162	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T225,T325	Yes	T139,T109,T162	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T139,*T109,*T162	Yes	T139,T109,T162	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T139,T109,T162	Yes	T139,T109,T162	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
cio_rx_i	Yes	Yes	T139,T109,T334	Yes	T139,T109,T334	INPUT
cio_tx_o	Yes	Yes	T139,T109,T334	Yes	T139,T109,T334	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T139,T109,T162	Yes	T139,T109,T162	OUTPUT
intr_rx_watermark_o	Yes	Yes	T139,T109,T162	Yes	T139,T109,T162	OUTPUT
intr_tx_empty_o	Yes	Yes	T139,T109,T162	Yes	T139,T109,T162	OUTPUT
intr_rx_overflow_o	Yes	Yes	T139,T109,T162	Yes	T139,T109,T162	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_break_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_timeout_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	274	89.54
Total Bits 0->1	153	137	89.54
Total Bits 1->0	153	137	89.54

Ports	39	31	79.49
Port Bits	306	274	89.54
Port Bits 0->1	153	137	89.54
Port Bits 1->0	153	137	89.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T30,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T162	Yes	T14,T15,T162	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T15,T162	Yes	T14,T15,T162	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T56,*T57	Yes	T54,T56,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T56,*T57,*T79	Yes	T56,T57,T79	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T14,T15,T162	Yes	T14,T15,T162	INPUT
tl_o.a_ready	Yes	Yes	T14,T15,T162	Yes	T14,T15,T162	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T162	Yes	T14,T15,T162	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T14,T15,T162	Yes	T14,T15,T162	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,*T225,*T325	Yes	T14,T15,T162	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T15,T162	Yes	T14,T15,T162	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T14,*T15,*T162	Yes	T14,T15,T162	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T225,T325	Yes	T14,T15,T162	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T15,*T162	Yes	T14,T15,T162	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T15,T162	Yes	T14,T15,T162	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T63,T335	Yes	T62,T63,T335	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T63,T335	Yes	T62,T63,T335	OUTPUT
cio_rx_i	Yes	Yes	T14,T15,T336	Yes	T14,T15,T336	INPUT
cio_tx_o	Yes	Yes	T14,T15,T336	Yes	T14,T15,T336	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T14,T15,T162	Yes	T14,T15,T162	OUTPUT
intr_rx_watermark_o	Yes	Yes	T14,T15,T162	Yes	T14,T15,T162	OUTPUT
intr_tx_empty_o	Yes	Yes	T14,T15,T162	Yes	T14,T15,T162	OUTPUT
intr_rx_overflow_o	Yes	Yes	T14,T15,T162	Yes	T14,T15,T162	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_break_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_timeout_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	302	272	90.07
Total Bits 0->1	151	136	90.07
Total Bits 1->0	151	136	90.07

Ports	39	31	79.49
Port Bits	302	272	90.07
Port Bits 0->1	151	136	90.07
Port Bits 1->0	151	136	90.07

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T30,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T39,T40,T43	Yes	T39,T40,T43	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T39,T40,T43	Yes	T39,T40,T43	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T56,*T57	Yes	T54,T56,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T56,*T57,*T79	Yes	T56,T57,T79	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T39,T40,T43	Yes	T39,T40,T43	INPUT
tl_o.a_ready	Yes	Yes	T39,T40,T152	Yes	T39,T40,T152	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T40,T152,T120	Yes	T40,T152,T120	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T40,T152,T120	Yes	T39,T40,T152	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T152,T157,T160	Yes	T39,T40,T152	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T40,T152,T120	Yes	T39,T40,T152	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T59,*T39,*T40	Yes	T59,T39,T40	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T152,T157,T160	Yes	T39,T40,T152	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T40,*T152,*T120	Yes	T40,T152,T120	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T39,T40,T152	Yes	T39,T40,T152	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T333,T62,T63	Yes	T333,T62,T63	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T333,T62,T63	Yes	T333,T62,T63	OUTPUT
cio_rx_i	Yes	Yes	T2,T30,T4	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T120,T238,T36	Yes	T120,T238,T36	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T152,T120,T162	Yes	T152,T120,T162	OUTPUT
intr_rx_watermark_o	Yes	Yes	T120,T162,T238	Yes	T120,T162,T238	OUTPUT
intr_tx_empty_o	Yes	Yes	T120,T102,T162	Yes	T120,T102,T162	OUTPUT
intr_rx_overflow_o	Yes	Yes	T120,T102,T162	Yes	T120,T102,T162	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_break_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_timeout_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T30,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T162,T235,T236	Yes	T162,T235,T236	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T162,T235,T236	Yes	T162,T235,T236	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T56,*T57	Yes	T54,T56,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T56,*T57,*T79	Yes	T56,T57,T79	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T162,T235,T236	Yes	T162,T235,T236	INPUT
tl_o.a_ready	Yes	Yes	T162,T235,T236	Yes	T162,T235,T236	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T162,T235,T236	Yes	T162,T235,T236	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T162,T235,T236	Yes	T162,T235,T236	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,*T225,*T325	Yes	T162,T235,T236	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T162,T235,T236	Yes	T162,T235,T236	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T59,*T162,*T235	Yes	T59,T162,T235	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T225,T325	Yes	T162,T235,T236	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T162,*T235,*T236	Yes	T162,T235,T236	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T162,T235,T236	Yes	T162,T235,T236	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T265,T62,T144	Yes	T265,T62,T144	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T265,T62,T144	Yes	T265,T62,T144	OUTPUT
cio_rx_i	Yes	Yes	T235,T236,T237	Yes	T11,T235,T236	INPUT
cio_tx_o	Yes	Yes	T235,T236,T237	Yes	T235,T236,T237	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T162,T235,T236	Yes	T162,T235,T236	OUTPUT
intr_rx_watermark_o	Yes	Yes	T162,T235,T236	Yes	T162,T235,T236	OUTPUT
intr_tx_empty_o	Yes	Yes	T162,T235,T236	Yes	T162,T235,T236	OUTPUT
intr_rx_overflow_o	Yes	Yes	T162,T235,T236	Yes	T162,T235,T236	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_break_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_timeout_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T162,T188,T189	Yes	T162,T188,T189	OUTPUT

*Tests covering at least one bit in the range