Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : pwrmgr
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.04 93.04

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pwrmgr_aon 93.04 93.04


Module Instance : tb.dut.top_earlgrey.u_pwrmgr_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.04 93.04


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.04 93.04


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.77 90.32 90.98 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : pwrmgr
TotalCoveredPercent
Totals 83 75 90.36
Total Bits 460 428 93.04
Total Bits 0->1 230 214 93.04
Total Bits 1->0 230 214 93.04

Ports 83 75 90.36
Port Bits 460 428 93.04
Port Bits 0->1 230 214 93.04
Port Bits 1->0 230 214 93.04

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_slow_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_slow_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
rst_main_ni Yes Yes T30,T4,T5 Yes T1,T2,T3 INPUT
clk_lc_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_lc_ni Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
clk_esc_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_esc_ni Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T2,T30,T83 Yes T2,T30,T83 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T2,T30,T83 Yes T2,T30,T83 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[21:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T54,*T56,*T57 Yes T54,T56,T57 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T27,T28,T29 Yes T27,T28,T29 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T56,*T57,*T79 Yes T56,T57,T79 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T2,T30,T83 Yes T2,T30,T83 INPUT
tl_o.a_ready Yes Yes T2,T30,T83 Yes T2,T30,T83 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T2,T30,T83 Yes T2,T30,T83 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T2,T30,T83 Yes T2,T30,T83 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T222,*T327,*T36 Yes T2,T30,T83 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T2,T30,T83 Yes T2,T30,T83 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T2,*T30,*T83 Yes T2,T30,T83 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T222,T327,T36 Yes T2,T30,T83 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T2,*T30,*T83 Yes T2,T30,T83 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T2,T30,T83 Yes T2,T30,T83 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T2,T116,T62 Yes T2,T116,T62 INPUT
alert_rx_i[0].ping_n Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_rx_i[0].ping_p Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T2,T116,T385 Yes T2,T116,T385 OUTPUT
pwr_ast_i.main_pok Yes Yes T30,T4,T5 Yes T1,T2,T3 INPUT
pwr_ast_i.usb_clk_val Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
pwr_ast_i.io_clk_val Yes Yes T30,T4,T83 Yes T1,T2,T3 INPUT
pwr_ast_i.core_clk_val Yes Yes T30,T4,T83 Yes T1,T2,T3 INPUT
pwr_ast_i.slow_clk_val Yes Yes T111,T120,T121 Yes T1,T2,T3 INPUT
pwr_ast_o.usb_clk_en Yes Yes T2,T30,T4 Yes T1,T2,T3 OUTPUT
pwr_ast_o.io_clk_en Yes Yes T30,T4,T83 Yes T1,T2,T3 OUTPUT
pwr_ast_o.core_clk_en Yes Yes T30,T4,T83 Yes T1,T2,T3 OUTPUT
pwr_ast_o.slow_clk_en Unreachable Unreachable Unreachable OUTPUT
pwr_ast_o.pwr_clamp Yes Yes T1,T2,T3 Yes T30,T4,T5 OUTPUT
pwr_ast_o.pwr_clamp_env Yes Yes T1,T2,T3 Yes T30,T4,T5 OUTPUT
pwr_ast_o.main_pd_n Yes Yes T30,T113,T114 Yes T30,T113,T114 OUTPUT
pwr_rst_i.rst_sys_src_n[1:0] Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
pwr_rst_i.rst_lc_src_n[1:0] Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
pwr_rst_o.reset_cause[1:0] Yes Yes T1,T2,T3 Yes T2,T30,T4 OUTPUT
pwr_rst_o.rstreqs[4:0] Yes Yes T2,T222,T19 Yes T2,T222,T19 OUTPUT
pwr_rst_o.rst_sys_req[1:0] Yes Yes T1,T2,T3 Yes T2,T30,T4 OUTPUT
pwr_rst_o.rst_lc_req[1:0] Yes Yes T1,T2,T3 Yes T2,T30,T4 OUTPUT
pwr_clk_o.usb_ip_clk_en Yes Yes T2,T30,T4 Yes T1,T2,T3 OUTPUT
pwr_clk_o.io_ip_clk_en Yes Yes T2,T30,T4 Yes T1,T2,T3 OUTPUT
pwr_clk_o.main_ip_clk_en Yes Yes T2,T30,T4 Yes T1,T2,T3 OUTPUT
pwr_clk_i.usb_status Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
pwr_clk_i.io_status Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
pwr_clk_i.main_status Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
pwr_otp_i.otp_idle Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
pwr_otp_i.otp_done Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
pwr_otp_o.otp_init Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
pwr_lc_i.lc_idle Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
pwr_lc_i.lc_done Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
pwr_lc_o.lc_init Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
pwr_flash_i.flash_idle Yes Yes T1,T4,T109 Yes T1,T4,T109 INPUT
pwr_cpu_i.core_sleeping Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
fetch_en_o[3:0] Yes Yes T2,T30,T4 Yes T1,T2,T3 OUTPUT
lc_hw_debug_en_i[3:0] Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
lc_dft_en_i[3:0] Yes Yes T2,T30,T4 Yes T1,T2,T3 INPUT
wakeups_i[5:0] Yes Yes T2,T222,T19 Yes T2,T222,T19 INPUT
rstreqs_i[1:0] Yes Yes T2,T222,T19 Yes T2,T222,T19 INPUT
ndmreset_req_i Yes Yes T46,T54,T55 Yes T46,T54,T55 INPUT
strap_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
low_power_o Yes Yes T1,T2,T3 Yes T2,T30,T4 OUTPUT
rom_ctrl_i.good[3:0] Yes Yes T1,T2,T3 Yes T2,T30,T4 INPUT
rom_ctrl_i.done[3:0] Yes Yes T1,T2,T3 Yes T2,T30,T4 INPUT
sw_rst_req_i[3:0] Yes Yes T2,T4,T206 Yes T2,T4,T206 INPUT
esc_rst_tx_i.esc_n Yes Yes T2,T81,T43 Yes T2,T81,T43 INPUT
esc_rst_tx_i.esc_p Yes Yes T2,T81,T43 Yes T2,T81,T43 INPUT
esc_rst_rx_o.resp_n Yes Yes T2,T81,T43 Yes T2,T81,T43 OUTPUT
esc_rst_rx_o.resp_p Yes Yes T2,T81,T43 Yes T2,T81,T43 OUTPUT
intr_wakeup_o Yes Yes T30,T83,T195 Yes T30,T83,T195 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%